Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. A method includes forming a shallow trench isolation region alongside a protruding fin. The protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure. A doping process is performed to dope dopants into a top portion of the shallow trench isolation region to form a protective layer. The method further includes forming a dummy gate stack over the protruding fin; removing the sacrificial layer in the protruding fins to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; a disposable interposer is formed in the space. The dummy gate stack is then removed, followed by an etch process to remove the disposable interposer using an etchant. In the etching process, the protective layer is exposed to an etchant. A replacement gate stack is then formed, where a portion of the replacement gate stack is filled in the space.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and methods of fabricating the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising: forming a shallow trench isolation region next to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into a top portion of the shallow trench isolation region to form a protective layer; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interlayer in the space; removing the dummy gate stack; performing an etching process to remove the disposable interlayer using an etchant, wherein the protective layer is exposed to the etchant during the etching process; and forming a replacement gate stack, wherein a portion of the replacement gate stack is filled in the space.

[0005] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor strip; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack comprising a first portion and a second portion, wherein the first portion is located between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack comprises a gate dielectric and a gate electrode located above the gate dielectric; and a protective layer located between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer comprises a dielectric material different from a material of the shallow trench isolation region and the gate dielectric.

[0006] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and in contact with the shallow trench isolation region to serve as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack located above and surrounding the semiconductor layer; a source / drain region located next to the gate stack; and a dielectric protection layer located above and in contact with the shallow trench isolation region, wherein the dielectric protection layer includes a first portion located directly below the gate stack and a second portion located directly below the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 、 Figure 2 、 Figure 3A 、 Figures 3B to 16A 、 Figure 16B and Figure 16C A diagram illustrating an intermediate stage in the formation of a transistor and STI protection layer, according to some embodiments.

[0009] Figure 17 Schematic distribution curves of dopants according to some embodiments are shown.

[0010] Figure 18 A process flow for forming a transistor according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. In order to simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially relative terms (e.g., "below," "beneath," "lower," "overlying," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be similarly interpreted accordingly.

[0013] Provided are a gate-all-around (GAA) transistor, a protective layer for protecting a shallow trench isolation region, and a method for forming the same. According to some embodiments of the present disclosure, the formation of the GAA transistor adopts a disposable oxide interposing (DOI) process, which includes forming and removing a sacrificial layer including an oxide. Since the sacrificial layer does not have sufficient etching selectivity relative to the shallow trench isolation (STI) region, the STI region may be undesirably recessed, resulting in an undesirable increase in the effective capacitance Ceff between the conductive features, and an undesirable increase in the peripheral capacitance. Therefore, a protective layer (also referred to as a hard mask) is formed by implantation and / or directional plasma treatment to prevent the STI region from being recessed during the removal of the sacrificial layer.

[0014] The purpose of the embodiments discussed herein is to provide examples to enable making or using the subject matter of the present disclosure, and those skilled in the art will readily appreciate the modifications that can be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, like reference numerals are used to represent like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 16A 、 Figure 16B and Figure 16C 1 shows a cross-sectional view of an intermediate stage in the formation of a GAA transistor according to some embodiments of the present disclosure. Figure 18 The process flow 200 shown schematically also reflects the corresponding process.

[0016] refer to Figure 1, a perspective view of wafer 10 is shown. Wafer 10 includes a multilayer structure including a multilayer stack 22 on a substrate 20. According to some embodiments, substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon germanium (SiGe) substrate, etc., although other substrates and / or structures may be used, such as semiconductor on insulator (SOI), strained SOI, silicon germanium on insulator, etc. Substrate 20 may be doped as a p-type semiconductor, but in other embodiments, it may be doped as an n-type semiconductor.

[0017] According to some embodiments, the multilayer stack 22 is formed by a series of deposition processes for depositing alternating materials. Figure 18 The illustrated process flow 200 is shown as process 202. According to some embodiments, the multilayer stack 22 includes a first layer 22A formed of a first semiconductor material and a second layer 22B formed of a second semiconductor material that is different from the first semiconductor material.

[0018] According to some embodiments, the first semiconductor material of the first layer 22A is formed of or includes the following: SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, etc. According to some embodiments, the deposition of the first layer 22A (e.g., SiGe) is performed by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), etc. According to some embodiments, the first layer 22A is formed to have a thickness of about 100 nm. peace treaty However, any suitable thickness may be used while remaining within the scope of the embodiments.

[0019] Once first layer 22A is deposited on substrate 20, second layer 22B is deposited on first layer 22A. According to some embodiments, second layer 22B is formed of or includes a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GasB, InAlAs, InGaAs, GasB, GaAsSB, and combinations thereof, and is different from the first semiconductor material of first layer 22A. For example, according to some embodiments in which first layer 22A is silicon germanium, second layer 22B can be formed of silicon, and vice versa. It should be understood that any suitable material combination can be used for first layer 22A and second layer 22B.

[0020] According to some embodiments, the second layer 22B is epitaxially grown on the first layer 22A using a deposition technique similar to that used to form the first layer 22A. According to some embodiments, the second layer 22B is formed to have a thickness similar to that of the first layer 22A. The second layer 22B may also be formed to have a thickness different from that of the first layer 22A. According to some embodiments, for example, the second layer 22B may be formed to have a thickness between about peace treaty A second thickness within a range between.

[0021] Once the second layer 22B is formed on the first layer 22A, the deposition process is repeated to form the remaining layers in the multilayer stack 22 until the desired topmost layer of the multilayer stack 22 is formed. According to some embodiments, the first layers 22A have the same or similar thickness as each other, and the second layers 22B have the same or similar thickness as each other. The first layer 22A may also have the same or different thickness as the second layer 22B. According to some embodiments, the first layer 22A is removed in a subsequent process and is alternatively referred to as a sacrificial layer 22A in the specification. According to an alternative embodiment, the second layer 22B is sacrificial and removed in a subsequent process.

[0022] According to some embodiments, a mask layer 25 is formed. According to some embodiments, the mask layer 25 includes a pad oxide layer 25A ( Figure 1 Not shown, see Figure 3B ) and hard mask layer(s) 25B. According to some embodiments, pad oxide layer 25A includes silicon oxide and hard mask layer 25B includes silicon nitride, although other materials may be used.

[0023] According to some embodiments, a well implantation process may be performed to form a well region 21, which may be of p-type or n-type. The well region 21 has a substantially uniform polarity with the subsequently formed source / drain regions 48 ( Figure 16A and Figure 16C ) of the opposite conductivity type. According to an alternative embodiment, the conductive type of the conductive type may be changed in a later process (e.g., when forming the conductive type of ... Figure 3A A well implantation process is performed after the structure shown.

[0024] refer to Figure 2 , the multilayer stack 22 and a portion of the underlying substrate 20 are patterned in (one or more) etching processes so that the trench 23 is formed. Figure 18This is shown as process 204 in the illustrated process flow 200. The formation of trench 23 may include forming a patterned etch mask (e.g., a patterned photoresist) and etching hard mask layer 25B to define a pattern in hard mask layer 25B. Patterned hard mask layer 25B may then be used to etch the underlying pad oxide layer 25A, multilayer stack 22, and substrate 20 to form trench 23.

[0025] Trench 23 extends into substrate 20. The remaining portion of the multilayer stack is hereinafter referred to as multilayer stack 22'. Below multilayer stack 22', portions of substrate 20 are left, and these portions are hereinafter referred to as substrate strip 20'. Multilayer stack 22' includes semiconductor layer 22A and semiconductor layer 22B. Hereinafter, semiconductor layer 22A is alternatively referred to as a sacrificial layer, while semiconductor layer 22B is alternatively referred to as a nanostructure. Multilayer stack 22' and the portions of substrate strip 20' below are collectively referred to as semiconductor strip 24.

[0026] In the above-described embodiments, the GAA transistor structure can be patterned by any suitable method. For example, one or more photolithography processes (including double patterning processes or multi-patterning processes) can be used to pattern these structures. Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the creation of patterns having, for example, a smaller spacing than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers are then used to pattern the GAA structure.

[0027] Figure 3A The formation of the isolation region 26 is shown, and the isolation region 26 is also referred to as the shallow trench isolation (STI) region in the specification. Figure 18 This is shown as process 206 in the illustrated process flow 200. The STI regions 26 may include a liner oxide (not shown), which may be a thermal oxide formed by thermally oxidizing a surface layer of the substrate 20, or may be deposited. The liner oxide may also be a deposited silicon oxide layer formed using, for example, ALD, high-density plasma chemical vapor deposition (HDPCVD), CVD, or the like.

[0028] STI regions 26 may further include a dielectric material over the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, HDPVCD, etc. A planarization process (e.g., a chemical mechanical polishing (CMP) process or a mechanical grinding process) may then be performed to level the top surface of the dielectric material, with the remaining portion of the dielectric material being the STI regions 26 .

[0029] STI regions 26 are then recessed so that the top portion of semiconductor strip 24 protrudes above the top surface 26T of the remaining portion of STI regions 26 to form protruding fins 28. Protruding fins 28 include the top portion of substrate strip 20' and multilayer stack 22'. The recessing of STI regions 26 can be performed by a dry etching process, wherein, for example, NF3 and NH3 are used as etching gases. During the etching process, a plasma can be generated. Argon gas can also be included. According to an alternative embodiment of the present disclosure, the recessing of STI regions 26 is performed by a wet etching process. For example, the etching chemical can include HF.

[0030] Figure 3B Shown Figure 3A The cross section A1-A1 in the figure. Figure 3B As shown, STI region 26 may include a plurality of dielectric liners, such as dielectric liners 26A, 26B, and 26C, and dielectric region 26D on dielectric liner 26C. In some embodiments, dielectric liner 26A is formed of or includes silicon oxide, which may be formed by a thermal oxidation process or a deposition process. Dielectric liners 26B and 26C may be formed of, for example, silicon nitride, although other materials may be used.

[0031] Dielectric region 26D may be formed of or include silicon oxide. Dielectric region 26D may have a lower density and a higher etch rate than dielectric liners 26A, 26B, and 26C. For example, when dielectric region 26D is formed by FCVD or spin coating, it may have a lower density than dielectric liners 26A, 26B, and 26C. Dielectric region 26D may also be formed by other deposition processes (e.g., ALD, CVD, etc.).

[0032] refer to Figure 4 , perform doping process 124. The corresponding process is Figure 18 This is shown as process 208 in the process flow 200. The doped elements (substances) may include nitrogen, carbon, oxygen, etc. For example, N2, N2O, CO2, or a combination of N2 and N2O may be used for doping. Inert gases such as Ar, He, etc. may also be used.

[0033] According to alternative embodiments, the dopant may be a p-type dopant (e.g., boron and / or indium) or an n-type dopant (e.g., phosphorus, arsenic, antimony, or a combination thereof). The conductivity type of the p-type or n-type dopant may be the same as the conductivity type of the dopant used to form the well region 21 and may be opposite to the conductivity type of the source / drain region of the corresponding transistor. For example, when the subsequently formed source / drain regions 48 ( Figure 16A and Figure 16C ) is a p-type source / drain region, the dopant introduced by the doping process 124 is n-type. Conversely, when the subsequently formed source / drain region 48 ( Figure 16A and Figure 16C ) is an n-type source / drain region, the dopant introduced by the doping process 124 is p-type.

[0034] According to alternative embodiments, the p-type or n-type dopant introduced by doping process 124 has a conductivity type opposite to the conductivity type of well region 21 and, therefore, has the same conductivity type as the conductivity type of subsequently formed source / drain regions 48. According to these embodiments, the concentration of the dopant is lower than the doping concentration in well region 21 so that the conductivity type of well region 21 is not offset.

[0035] According to some embodiments, the doping process 124 may be performed through a vertical implantation process and / or a plasma treatment process. The plasma treatment may be performed using plasma generated from the above-described gases.

[0036] As a result of doping process 124, the top portion of STI region 26 is converted into protective layer 126, which has a higher concentration (and atomic percentage) of dopants (e.g., carbon, nitrogen, oxygen, and / or inert gas) than before the implantation process. The concentration and atomic percentage are also higher than those in the unimplanted portion of STI region 26 (e.g., the bottom portion of STI region 26). Depending on the implanted species, protective layer 126 may include SiOC, SiON, SiOCN, etc., and may incorporate other elements such as He, Ar, etc. The thickness of protective layer 126 may range from about 1 nm to about 20 nm.

[0037] According to some embodiments employing implantation, the implantation energy is controlled so that all or a majority of the implanted dopant is in mask layer 25 and not in underlying nanostructures 22B. According to some embodiments, nanostructures 22B may be free of dopants introduced by doping process 124. According to alternative embodiments, nanostructures 22B may include a low concentration of dopant. The concentration (atomic percentage) of the dopant is sufficiently low so that the properties of nanostructures 22B are not adversely altered.

[0038] According to some embodiments, the dopant may be implanted at an energy in a range between about 1 keV and about 20 keV. The dose of each of the substances listed above and / or the total dose of the implanted substances may be about 5E13 / cm 2 and 1E16 / cm 2 The concentration of the dopant in the protective layer 126 may be in the range of about 1E20 / cm 3 and about 3E22 / cm 3 within the range between.

[0039] When performing the plasma treatment, a low bias power may be provided so that the dopant is directional and can diffuse vertically to a desired depth without diffusing horizontally from the sidewalls of the multilayer stack 22' too deep into the multilayer stack 22'. According to some embodiments, the bias power may be in a range between about 20 eV and about 120 eV.

[0040] According to some embodiments, when the doping process 124 is performed, the sidewalls of the multilayer stack 22' are exposed. According to alternative embodiments, before the doping process 124, the sidewalls of the multilayer stack 22' may be exposed. Figure 4 A conformal sacrificial layer is formed on the structure shown. After doping process 124, the conformal sacrificial layer is removed along with the dopants that laterally diffused into the vertical portions of the conformal sacrificial layer. Thus, the vertical portions of the conformal sacrificial layer located on the sidewalls of multilayer stack 22' serve as a sacrificial layer to reduce the amount of dopants that diffuse into multilayer stack 22' in the lateral direction. The conformal sacrificial layer can be formed of or include a dielectric material that is different from the materials of STI regions 26 and multilayer stack 22', and can include SiC, SiCN, etc.

[0041] According to some embodiments, doping process 124 may be performed at room temperature (e.g., in a range between about 18° C. and about 22° C.) According to alternative embodiments, doping process 124 may be performed at an elevated temperature (e.g., in a range between about 18° C. and about 500° C.).

[0042] Then remove the mask layer 25. The corresponding process is Figure 18 The process flow 200 is shown as process 210 . Figure 5 The resulting structure is shown in . The multilayer stack 22 ′ and the protective layer 126 are exposed.

[0043] In subsequent processes, dummy gate stacks and gate spacers are formed. Figure 6The formation of dummy gate dielectric layer 32, dummy gate electrode layer 34, and hard mask layer 36 is shown. Dummy gate dielectric layer 32 can be formed by oxidizing a surface portion of protruding fin 28 to form an oxide layer, or by depositing a dielectric layer such as a silicon oxide layer. For example, dummy gate electrode layer 34 can be formed by depositing polycrystalline silicon or amorphous silicon, and other materials such as amorphous carbon can also be used. A planarization process can be performed to level the top surface of dummy gate electrode layer 34.

[0044] The hard mask layer 36 may be formed by deposition on the gate electrode layer 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon carbonitride, silicon oxycarbonitride, or a multilayer thereof. A patterning process(es) is then performed to pattern the hard mask layer 36, the dummy gate electrode layer 34, and the dummy gate dielectric layer 32, thereby forming a plurality of dummy gate stacks 30 (e.g., Figure 7A As shown, Figure 7A The corresponding process is shown in FIG. Figure 18 This is shown in the illustrated process flow 200 as process 212 .

[0045] Next, as Figure 7A As shown, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. According to some embodiments of the present disclosure, the gate spacers 38 are formed of a dielectric material (e.g., silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), etc.) and may have a single-layer structure or a multi-layer structure including multiple dielectric layers. The formation process of the gate spacers 38 may include: depositing one or more dielectric layers, and then performing one or more anisotropic etching processes on the (one or more) dielectric layers. The remaining portion of the (one or more) dielectric layers is the gate spacer 38.

[0046] like Figure 7A As shown, the protection layer 126 includes a first portion directly below and overlapping the dummy gate stack 30, and a second portion not directly below the dummy gate stack 30 (and laterally offset relative to the dummy gate stack 30). The thickness of the first portion can be the same as that of the second portion. Figure 7B Shown as Figure 7A A cross-sectional view of the cross section BB is shown.

[0047] Figure 8 The source / drain recess process is shown in FIG. Figure 18This is shown as process 214 in the illustrated process flow 200. The protruding fins 28 that are not directly under the dummy gate stack 30 and the gate spacers 38 are etched in an anisotropic etching process, thereby forming source / drain recesses 42.

[0048] Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B The sacrificial layer 22A is shown replaced with a disposable interposer 29. Figure 9A and Figure 9B , Figure 9A and Figure 9B Shown respectively Figure 7A In the cross sections BB and A2-A2, the sacrificial layer 22A is first removed to form openings 27 between the nanostructures 22B. Figure 18 This is shown in the illustrated process flow 200 as process 216 .

[0049] refer to Figure 10A and Figure 10B , forming a disposable intermediary layer 29 between the nanostructures 22B. The corresponding process is Figure 18 This is shown as process 218 in the illustrated process flow 200. According to some embodiments, the disposable interposer 29 includes an oxide such as silicon oxide, and thus may also be referred to as a disposable oxide interposer (DOI) 29. According to other embodiments, the disposable interposer 29 may include other types of dielectric materials, such as AlO, SiON, SiC, SiCN, etc.

[0050] The formation of disposable interposer 29 may include depositing a dielectric layer using a conformal deposition process such that the dielectric layer includes portions that fill openings 27 and other portions that are located outside openings 27. A trimming process (which may include an isotropic etching process or an anisotropic etching process followed by an isotropic etching process) is then performed to etch and remove the portions of the dielectric layer that are located outside openings 27. Thus, the remaining portion of the dielectric layer is disposable interposer 29.

[0051] refer to Figure 11A and Figure 11B , the disposable interposer 29 is laterally recessed and filled to form the inner spacer 44 ( Figure 11A ). The corresponding process is Figure 18This is shown as process 220 in the illustrated process flow 200. The lateral recessing of the disposable interposer 29 can be achieved by a wet etching process or a dry etching process. The wet etching process can be performed using a dipping process, a spraying process, a spin coating process, etc. The nanostructure 22B is not etched.

[0052] Internal spacers 44 are then formed. According to some embodiments, forming internal spacers 44 includes depositing a conformal dielectric layer that extends into the lateral recess. Next, an etching process (also referred to as a spacer trimming process) is performed to trim portions of the dielectric layer outside the lateral recess, thereby leaving portions of the dielectric layer within the lateral recess. The remaining portions of the dielectric layer are referred to as internal spacers 44.

[0053] refer to Figure 12A and Figure 12B , Figure 12A and Figure 12B Shown respectively with Figure 7A The cross section A1-A1 in FIG. 1 is the same as the cross section BB, and the epitaxial source / drain region 48 is formed in the recess 42 by selective epitaxy. The corresponding process is Figure 18 This is shown as process 222 in the illustrated process flow 200. Depending on whether the resulting transistor is a p-type transistor or an n-type transistor, p-type or n-type dopants may be in-situ doped as the epitaxy proceeds. For example, when the resulting transistor is a p-type transistor, silicon germanium boron (SiGeb), silicon boron (SiB), etc. may be grown. Conversely, when the resulting transistor is an n-type transistor, silicon phosphide (SiP), silicon arsenic (SiAs), silicon carbon phosphide (SiCP), etc. may be grown.

[0054] Figure 13A and Figure 13B FIG shows a cross-sectional view of the structure after forming a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52. Figure 18 This is shown in the illustrated process flow 200 as process 224 . Figure 13A and Figure 13B Shown respectively Figure 7A 1 and 2. The CESL 50 may be formed of silicon oxide, silicon nitride, silicon carbonitride, or the like, and may be formed using CVD, ALD, or the like. The ILD 52 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or any other suitable deposition method. The ILD 52 may be formed of an oxygen-containing dielectric material, which may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0055] CESL 50 and ILD 52 are planarized by a planarization process (eg, a CMP process or a mechanical grinding process). According to some embodiments, the planarization process may result in the removal of hard mask 36 to expose dummy gate electrode 34, such as Figure 13A and Figure 13B According to alternative embodiments, the planarization process may expose hard mask 36 and stop at hard mask 36. According to some embodiments, after the planarization process, the top surfaces of dummy gate electrode 34 (or hard mask 36), gate spacers 38, and ILD 52 are flush within process variations.

[0056] Next, the dummy gate electrode 34 and the dummy gate dielectric 32 (and the hard mask 36, if remaining) are removed in one or more etching processes, thereby forming the recess 58, as shown in FIG. Figure 14A and Figure 14B The corresponding process is shown in Figure 18 This is shown as process 226 in the illustrated process flow 200. According to some embodiments, the dummy gate electrode 34 and the dummy gate dielectric 32 are removed by an anisotropic dry etching process(es). For example, the etching process may be performed using a reactive gas(es) that selectively etches the dummy gate electrode 34 and the dummy gate dielectric 32 at a faster rate than etching the ILD 52. Each recess 58 exposes and / or overlies portions of the multilayer stack 22' that comprise future channel regions in a subsequently completed transistor.

[0057] The disposable interposer 29 is then removed to leave the recess 58 extending between the nanostructures 22B. Figure 18 This is shown as process 228 in the illustrated process flow 200. The disposable interposer 29 can be removed by performing an isotropic etching process (e.g., a wet etching process or a dry etching process) using an etchant that is selective to the material of the disposable interposer 29, while the nanostructures 22B and the substrate 20 remain relatively unetched compared to the disposable interposer 29. According to some embodiments in which the disposable interposer 29 comprises, for example, silicon oxide, a mixture of NF3 and NH3, a mixture of HF and NH3, or HF can be used to remove the disposable interposer 29.

[0058] In etching the disposable interposer 29 (e.g. Figure 14B As shown in FIG. 1 , the STI region 26 is protected by the protective layer 126 from the etching chemicals used to remove the disposable interposer 29. Therefore, due to the high etching selectivity, the STI region 26 is not etched (or substantially not etched, for example, the loss is less than about ), the etch selectivity is the ratio of the etch rate of the disposable interposer 29 to the etch rate of the protective layer 126. For example, the etch selectivity may be greater than about 5, greater than about 10, greater than about 20, or higher.

[0059] refer to Figure 15A and Figure 15B , forming a gate dielectric 62 and a gate electrode 68, thereby forming a replacement gate stack 70. The corresponding process is Figure 18 The process flow 200 is shown as process 230. According to some embodiments, each gate dielectric 62 includes an interfacial layer and a high-k dielectric layer above the interfacial layer. The interfacial layer can be formed of or include silicon oxide, which can be deposited by a conformal deposition process (e.g., ALD or CVD) or formed by an oxidation process (or formed by thermal oxidation). According to some embodiments, the high-k dielectric layer includes one or more high-k dielectric layers. For example, the (one or more) high-k dielectric layers can include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0060] When the interface layer is formed by deposition, the top surface of protective layer 126 contacts the bottom surface of the interface layer to form an interface. When the interface layer is formed by thermal oxidation, the top surface of protective layer 126 contacts the bottom surface of the high-k dielectric layer to form an interface.

[0061] Gate electrode 68 is also formed. In the formation process, a conductive layer is first formed on the high-k dielectric layer and fills the remaining portion of recess 58. Gate electrode 68 can include a metal-containing material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multiple layers thereof. For example, gate electrode 68 can include any number of layers, any number of work function layers, and may include a filler material. Gate dielectric 62 and gate electrode 68 also fill the space between adjacent nanostructures 22B and the space between the bottom nanostructure 22B and the underlying substrate strip 20'.

[0062] After filling recess 58, a planarization process (e.g., a CMP process or a mechanical grinding process) may be performed to remove excess portions of gate dielectric 62 and gate electrode 68 above the top surface of ILD 52. Gate electrode 68 and gate dielectric 62 are collectively referred to as a gate stack 70 of the resulting transistor.

[0063] exist Figure 16A 、 Figure 16B and Figure 16CIn the illustrated process, gate stack 70 is recessed so that recesses are formed directly above gate stack 70 and between opposing portions of gate spacers 38. A gate mask 74 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in each of these recesses, and a planarization process is then performed to remove excess portions of the dielectric material that extend over ILD 52.

[0064] like Figure 16A 、 Figure 16B and Figure 16C As further shown, ILD 76 is deposited over ILD 52 and gate mask 74. An etch stop layer (not shown) may (or may not) be deposited prior to the formation of ILD 76. According to some embodiments, ILD 76 is formed by FCVD, CVD, PECVD, or the like. ILD 76 is formed of a dielectric material that may be selected from silicon oxide, PSG, BSG, BPSG, USG, or the like.

[0065] ILD 76, ILD 52, CESL 50, and gate mask 74 are then etched to form recesses (occupied by contact plugs 80A and 80B) that expose the surface of source / drain regions 48 and / or gate stack 70. Figure 16A The contact plugs 80A and 80B are shown in the same cross-section, but in various embodiments, the contact plugs 80A and 80B may be formed in different cross-sections, thereby reducing the risk of shorting to each other.

[0066] After the recess is formed, a silicide region 78 is formed on the epitaxial source / drain region 48. A contact plug 80B is then formed on the silicide region 78. In addition, a contact 80A (also referred to as a gate contact plug) is formed in the recess and is above and in contact with the gate electrode 68. A corresponding structure is also formed in FIG. Figure 16A As shown in FIG. , transistor 82 is thus formed.

[0067] Figure 17 shows a doping process 124 ( Figure 4 ) are some example profiles of the concentration (or atomic percentage) of the dopant introduced by the implantation process 124. The dopant profiles represent profiles resulting from the implantation process 124, whereby the implanted dopant has a distribution (e.g., a Gaussian distribution) in which some ions / atoms of the dopant are implanted deeper than others. It should be understood that the concentrations shown reflect trends, not actual concentrations.

[0068] The figure above shows that the dopant is Figure 16BThe figure below shows the concentration (or atomic percentage) of the dopant along the path indicated by arrow 84A. Figure 16B ) represents the concentration (or atomic percentage) of the path. The positions in the upper figure correspond to the corresponding positions in the lower figure. Each of the upper and lower figures shows the concentration (or atomic percentage) of the dopant according to the position along arrows 84A and 84B.

[0069] As shown in the above figure, since dopants may be injected into the sacrificial layer 22A ( Figure 4 ) (the sacrificial layer 22A is then removed and replaced by the gate stack 70 ( Figure 16B ) is replaced), so gate stack 70 has a dopant concentration that is abruptly lower than that of the corresponding upper and lower semiconductor strips 20'. Upper nanostructure 22B has a higher concentration than the corresponding lower nanostructure 22B. In addition, the concentration profile within nanostructure 22B can be fitted with a curve. The peak concentration can be within top nanostructure 22B and can be close to the top surface of top nanostructure 22B.

[0070] The lower graph shows that the peak concentration of the dopant is in the protective layer 126 and may be near the top surface of the protective layer 126 or midway between the top and bottom surfaces of the protective layer 126 .

[0071] Embodiments of the present disclosure have several advantageous features. According to some embodiments, by forming a protective layer on top of the STI region, the protective layer protects the STI region from recessing during the removal of the disposable interposer, thereby reducing the undesirable increase in parasitic capacitance between the gate electrode and the semiconductor strip.

[0072] According to some embodiments of the present disclosure, a method includes: forming a shallow trench isolation region next to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into a top portion of the shallow trench isolation region to form a protective layer; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interposer in the space; removing the dummy gate stack; performing an etching process to remove the disposable interposer using an etchant, wherein the protective layer is exposed to the etchant during the etching process; and forming a replacement gate stack, wherein a portion of the replacement gate stack is filled in the space.

[0073] In one embodiment, during the doping process, the shallow trench isolation region is exposed. In one embodiment, the method further comprises: forming a hard mask over the protruding fin, wherein the hard mask is doped with a dopant during the doping process. In one embodiment, the method further comprises: removing the hard mask after the doping process. In one embodiment, the doping process comprises doping with nitrogen. In one embodiment, the doping process is performed using a process gas comprising N2, N2O, or a combination thereof.

[0074] In an embodiment, the dopant comprises an n-type dopant or a p-type dopant. In an embodiment, the method further comprises: forming a source / drain region adjacent to the dummy gate stack, wherein the dopant has a conductivity type opposite to that of the source / drain region. In an embodiment, the doping process comprises an implantation process. In an embodiment, the doping process comprises a plasma treatment process. In an embodiment, the doping process is performed at a temperature above room temperature. In an embodiment, the doping process is performed before forming the dummy gate stack.

[0075] According to some embodiments of the present disclosure, a structure includes: a semiconductor strip; a first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack including a first portion and a second portion, wherein the first portion is located between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack includes a gate dielectric and a gate electrode above the gate dielectric; and a protective layer located between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer includes a dielectric material different from a material of the shallow trench isolation region and the gate dielectric.

[0076] In an embodiment, the protective layer includes a dopant, and the dopant concentration of a lower portion of the protective layer is lower than the dopant concentration of a corresponding upper portion of the protective layer. In an embodiment, the bottom portion of the shallow trench isolation region includes silicon oxide, and the protective layer includes silicon oxynitride. In an embodiment, the bottom portion of the shallow trench isolation region includes silicon oxide, and the protective layer includes silicon carbonitride. In an embodiment, the protective layer includes an n-type dopant or a p-type dopant.

[0077] According to some embodiments of the present disclosure, a structure includes: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and in contact with the shallow trench isolation region to serve as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack located above and surrounding the semiconductor layer; a source / drain region located next to the gate stack; and a dielectric protection layer located above and in contact with the shallow trench isolation region, wherein the dielectric protection layer includes a first portion located directly below the gate stack and a second portion located directly below the source / drain region.

[0078] In an embodiment, the dielectric protection layer contacts a gate dielectric of the gate stack. In an embodiment, the dielectric protection layer comprises a dopant, and wherein a first concentration of a lower portion of the dielectric protection layer is lower than a second concentration of an upper portion of the dielectric protection layer.

[0079] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0080] Example 1. A method for manufacturing a semiconductor structure, comprising: forming a shallow trench isolation region next to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into a top portion of the shallow trench isolation region to form a protective layer; forming a dummy gate stack above the protruding fin; removing a sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable interposer in the space; removing the dummy gate stack; performing an etching process to remove the disposable interposer using an etchant, wherein, in the etching process, the protective layer is exposed to the etchant; and forming a replacement gate stack, wherein a portion of the replacement gate stack is filled in the space.

[0081] Example 2. The method of Example 1, wherein the shallow trench isolation region is exposed during the doping process.

[0082] Example 3. The method of Example 1, further comprising: forming a hard mask over the protruding fin, wherein the hard mask is doped with the dopant during the doping process.

[0083] Example 4. The method according to Example 3 further includes: removing the hard mask after the doping process.

[0084] Example 5. The method of Example 1, wherein the doping process includes doping with nitrogen.

[0085] Example 6. The method of Example 5, wherein the doping process is performed using a process gas comprising N2, N2O, or a combination thereof.

[0086] Example 7. The method of Example 1, wherein the dopant comprises an n-type dopant or a p-type dopant.

[0087] Example 8. The method of Example 7, further comprising: forming a source / drain region adjacent to the dummy gate stack, wherein the dopant has a conductivity type opposite to a conductivity type of the source / drain region.

[0088] Example 9. The method of Example 1, wherein the doping process comprises an implantation process.

[0089] Example 10. The method of Example 1, wherein the doping process comprises a plasma treatment process.

[0090] Example 11. The method of Example 1, wherein the doping process is performed at a temperature above room temperature.

[0091] Example 12. The method of Example 1, wherein the doping process is performed before forming the dummy gate stack.

[0092] Example 13. A semiconductor structure comprising: a semiconductor strip; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack comprising a first portion and a second portion, wherein the first portion is located between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack includes a gate dielectric and a gate electrode located above the gate dielectric; and a protective layer located between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer includes a dielectric material different from the material of the shallow trench isolation region and the gate dielectric.

[0093] Example 14. The structure of Example 13, wherein the protective layer includes a dopant, and a lower portion of the protective layer has a dopant concentration that is lower than a dopant concentration of a corresponding upper portion of the protective layer.

[0094] Example 15. The structure of Example 13, wherein a bottom portion of the shallow trench isolation region comprises silicon oxide, and the protective layer comprises silicon oxynitride.

[0095] Example 16. The structure of Example 13, wherein a bottom portion of the shallow trench isolation region comprises silicon oxide and the protective layer comprises silicon carbonitride.

[0096] Example 17. The structure of Example 13, wherein the protective layer comprises an n-type dopant or a p-type dopant.

[0097] Example 18. A semiconductor structure comprising: a semiconductor substrate; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located next to and in contact with the shallow trench isolation region to serve as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack located above and surrounding the semiconductor layer; a source / drain region located next to the gate stack; and a dielectric protection layer located above and in contact with the shallow trench isolation region, wherein the dielectric protection layer includes a first portion located directly below the gate stack and a second portion located directly below the source / drain region.

[0098] Example 19. The structure of Example 18, wherein the dielectric protection layer contacts a gate dielectric of the gate stack.

[0099] Example 20. The structure of Example 18, wherein the dielectric protection layer includes a dopant, and wherein a first concentration in a lower portion of the dielectric protection layer is lower than a second concentration in an upper portion of the dielectric protection layer.

Claims

1. A method for manufacturing a semiconductor structure, comprising: forming a shallow trench isolation region adjacent to a protruding fin, wherein the protruding fin includes a first semiconductor nanostructure and a second semiconductor nanostructure; performing a doping process to dope a dopant into a top portion of the shallow trench isolation region to form a protection layer; forming a dummy gate stack on the protruding fin; removing the sacrificial layer in the protruding fin to leave a space between the first semiconductor nanostructure and the second semiconductor nanostructure; forming a disposable intermediary layer in the space; removing the dummy gate stack; performing an etching process to remove the disposable interposer using an etchant, wherein the protective layer is exposed to the etchant during the etching process; and A replacement gate stack is formed, wherein a portion of the replacement gate stack fills the space.

2. The method according to claim 1, wherein During the doping process, the shallow trench isolation region is exposed.

3. The method according to claim 1, further comprising: A hard mask is formed over the protruding fin, wherein the hard mask is doped with the dopant during the doping process.

4. The method according to claim 3, further comprising: After the doping process, the hard mask is removed.

5. The method according to claim 1, wherein The doping process includes doping nitrogen.

6. The method according to claim 5, wherein: The doping process is performed using a process gas including N 2 , N 2 O, or a combination thereof.

7. The method according to claim 1, wherein The dopant includes an n-type dopant or a p-type dopant.

8. The method according to claim 7, further comprising: Source / drain regions are formed adjacent to the dummy gate stack, wherein the dopant has a conductivity type opposite to that of the source / drain regions.

9. A semiconductor structure comprising: semiconductor strips; a first semiconductor nanostructure, the first semiconductor nanostructure overlapping and spaced apart from the semiconductor strip; a shallow trench isolation region contacting an edge of the semiconductor strip; a gate stack comprising a first portion and a second portion, wherein the first portion is located between the first semiconductor nanostructure and the semiconductor strip, and wherein the gate stack comprises a gate dielectric and a gate electrode located over the gate dielectric; and A protective layer is located between the shallow trench isolation region and the second portion of the gate stack, wherein the protective layer includes a dielectric material different from a material of the shallow trench isolation region and the gate dielectric.

10. A semiconductor structure comprising: semiconductor substrates; a shallow trench isolation region in the semiconductor substrate, wherein a portion of the semiconductor substrate is located adjacent to and in contact with the shallow trench isolation region to serve as a semiconductor strip; a semiconductor layer overlapping the semiconductor strip; a gate stack located above and surrounding the semiconductor layer; a source / drain region adjacent to the gate stack; and A dielectric protection layer is located above the shallow trench isolation region and contacts the shallow trench isolation region, wherein the dielectric protection layer includes a first portion located directly below the gate stack and a second portion located directly below the source / drain region.

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