Preparation method of semiconductor device
By forming sidewall structures with different dielectric constants and chemical-mechanical properties on the semiconductor substrate, the problem of electrical performance fluctuations caused by changes in sidewall thickness is solved, the stability and performance consistency of semiconductor devices are improved, and RC delay is reduced.
Patent Information
- Application Number
- CN202410284023.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-13
- Publication Date
- 2025-09-19
AI Technical Summary
During the semiconductor manufacturing process, electrical performance fluctuations caused by changes in sidewall thickness are difficult to control, especially during multiple photolithography rework processes, which affects the stability and performance consistency of semiconductor devices.
First and second sidewall structures with different dielectric constants are sequentially formed on a semiconductor substrate. The second sidewall structure with excellent chemical mechanical properties is used to resist etching and cleaning in the photoresist layer rework process to ensure the consistency of the sidewall thickness. The second sidewall structure is then removed, leaving only the first sidewall structure with a lower dielectric constant to reduce dielectric loss.
By controlling the thickness and chemical mechanical properties of the sidewall structure, the electrical performance fluctuation of the semiconductor device is reduced, the stability and speed uniformity of the device are improved, and the RC delay is reduced.
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Figure CN120676701A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art
[0002] When semiconductor manufacturing technology develops to lower nodes, in order to reduce the peak electric field strength in the channel region and alleviate the hot carrier effect, the sidewall process is gradually introduced into the semiconductor transistor manufacturing process. At relatively lower process nodes, a sidewall is formed on the side of the gate structure after the gate structure is formed. The thickness of the sidewall defines the distance between the lightly doped ion region injected in the subsequent lightly doped source and drain process (LDD) and the channel, as well as the boundary of the subsequent source and drain structure, and protects the integrity of the gate structure morphology during the lightly doped source and drain process and the formation of the source and drain structure.
[0003] Among them, each lightly doped source and drain process usually requires a patterned mask layer (such as a patterned photoresist layer) to define the injection area that requires the lightly doped source and drain process. In the actual production process, each wafer will go through more than ten lightly doped source and drain processes, so it is inevitable that the patterned mask layer needs to be reworked (photolithography rework). However, the photolithography rework will cause changes in the thickness of the sidewalls. The changes in the sidewall thickness will affect the distance between the lightly doped ion region and the channel in the lightly doped source and drain process and the boundary of the subsequent source and drain structure, thereby causing fluctuations (instability) in the electrical performance of the semiconductor device. Summary of the Invention
[0004] An object of the present invention is to provide a method for preparing a semiconductor device, which is used to reduce the electrical performance fluctuation of the semiconductor device caused by the sidewall spacer.
[0005] To solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising:
[0006] Providing a semiconductor substrate comprising a gate structure and source and drain regions located on both sides of the gate structure;
[0007] forming a first spacer structure and a second spacer structure in sequence on the semiconductor substrate, wherein the first spacer structure and the second spacer structure both include a spacer portion located on a sidewall of the gate structure, the dielectric constant of the spacer portion of the first spacer structure being smaller than the dielectric constant of the second spacer structure, and the chemical mechanical properties of the spacer portion of the second spacer structure being better than those of the spacer portion of the first spacer structure;
[0008] Performing a lightly doped source / drain process using the first spacer structure and the second spacer structure;
[0009] The second spacer structure is removed, and a source-drain structure is formed in the source-drain region using the first spacer structure.
[0010] Optionally, both the first spacer structure and the second spacer structure include an extension portion covering the surface of the source and drain regions.
[0011] Optionally, the step of forming the first sidewall structure includes:
[0012] forming a first oxide layer conformally covering the outer wall of the gate structure and the surface of the source and drain regions;
[0013] forming a first nitrogen-containing dielectric layer conformally covering the first oxide layer;
[0014] The first nitrogen-containing dielectric layer on the surface of the source and drain regions is removed, and the remaining first oxide layer on the surface of the source and drain regions is used as an extension of the first sidewall structure, and the first nitrogen-containing dielectric layer and the first oxide layer on the sidewall of the gate structure are used as the sidewall portion of the first sidewall structure.
[0015] Optionally, the step of forming the second sidewall structure includes:
[0016] forming a second oxide layer conformally covering the first sidewall structure;
[0017] forming a second nitrogen-containing dielectric layer conformally covering the second oxide layer, wherein the dielectric constant of the second nitrogen-containing dielectric layer is greater than the dielectric constant of the first nitrogen-containing dielectric layer;
[0018] The second nitrogen-containing dielectric layer on the source / drain region is removed, and the remaining second oxide layer on the source / drain region is used as an extension of the second spacer structure. The second nitrogen-containing dielectric layer and the second oxide layer on the sidewall of the gate structure are used as the sidewall portion of the second spacer structure.
[0019] Optionally, the second nitrogen-containing dielectric layer includes silicon nitride, and the first nitrogen-containing dielectric layer includes silicon carbide.
[0020] Optionally, dry etching is used to remove the first nitrogen-containing dielectric layer and the second nitrogen-containing dielectric layer on the source / drain region.
[0021] Optionally, a wet process is used to remove the second oxide layer and the second nitrogen-containing dielectric layer located on the second oxide layer, so as to remove the second sidewall structure.
[0022] Optionally, after forming the second spacer structure and before performing the lightly doped source / drain process, the second spacer structure and the extension portion of a portion of the thickness of the first spacer structure are further removed.
[0023] Optionally, the source / drain region includes a P-type source / drain region, and the step of forming a P-type source / drain structure in the P-type source / drain region includes:
[0024] Using the first sidewall structure, a source-drain trench is formed in the semiconductor substrate in the P-type source-drain region;
[0025] A silicon-germanium structure is epitaxially formed in the source-drain trench to serve as the P-type source-drain structure.
[0026] Optionally, the source / drain region includes an N-type source / drain region, and source / drain ion implantation is performed using the first sidewall structure to form an N-type source / drain structure in the N-type source / drain region.
[0027] In summary, in the present invention, a first spacer structure and a second spacer structure are sequentially formed on a semiconductor structure having a gate structure and a source / drain region. The first spacer structure and the second spacer structure both include a spacer portion located on the sidewall of the gate structure. The dielectric constant of the sidewall portion of the first spacer structure is less than that of the second spacer structure, and the chemical mechanical properties of the sidewall portion of the second spacer structure are better than those of the sidewall portion of the first spacer structure. A lightly doped source / drain process is performed using the first and second spacer structures. The second spacer structure is removed, and a source / drain structure is formed in the source / drain region using the first spacer structure. During the lightly doped source / drain process, the strong chemical mechanical properties of the sidewall portion of the second spacer structure can be utilized to better resist etching and cleaning in the photoresist rework process, so that the second spacer structure that has not undergone the photoresist rework process and the second spacer structure that has undergone the photoresist rework process have as similar thickness as possible, thereby ensuring that the lightly doped source / drain regions of transistors on the same semiconductor substrate and the same batch are as close as possible to the channel, thereby reducing electrical performance fluctuations of each transistor caused by the sidewall thickness. After performing the light source and drain doping process, the second spacer structure is removed, leaving only the sidewall portion of the first spacer structure between the gate structures. The sidewall portion of the retained first spacer structure, which has a relatively low dielectric constant and is thinner than the first and second spacers, can be used to reduce dielectric loss between the gate structures, thereby reducing RC delay within the semiconductor device. Furthermore, the fabrication method of this embodiment employs a unified treatment method for both regions that have undergone photoresist rework and those that have not undergone photoresist rework, as well as for the semiconductor substrate. This simple and easy treatment method provides high practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0029] Figure 1 is a flow chart of a method for manufacturing a semiconductor device provided in this embodiment;
[0030] Figure 2a ˉ Figure 2g This is a schematic structural diagram corresponding to the corresponding steps of the method for manufacturing a semiconductor device provided in this embodiment.
[0031] In the attached figure:
[0032] 10-semiconductor substrate; AA-first region; BB-second region; 21a-first gate structure; 21b-first source-drain region; 22a-second gate structure; 22b-second source-drain region; 23a-first oxide layer; 23b-first nitrogen-containing dielectric layer; 24a-extension of the first sidewall structure; 24b-sidewall portion of the first sidewall structure; 23-first sidewall structure; 25a-second oxide layer; 25b-second nitrogen-containing dielectric layer; 26a-extension of the second sidewall structure; 26b-sidewall portion of the second sidewall structure; 25-second sidewall structure; 31-lightly doped source-drain structure. DETAILED DESCRIPTION
[0033] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.
[0034] As used in the present invention, the singular forms "a", "an", and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0035] This embodiment provides a method for manufacturing a semiconductor device.
[0036] Figure 1 This is a flow chart of a method for manufacturing a semiconductor device provided in this embodiment.
[0037] like Figure 1 As shown, the method for preparing a semiconductor device provided in this embodiment includes:
[0038] S01: Providing a semiconductor substrate, which includes a gate structure and source and drain regions located on both sides of the gate structure;
[0039] S02: sequentially forming a first spacer structure and a second spacer structure on the semiconductor substrate, wherein the first spacer structure and the second spacer structure each include a spacer portion located on a sidewall of the gate structure, the dielectric constant of the spacer portion of the first spacer structure is smaller than the dielectric constant of the second spacer structure, and the chemical mechanical properties of the spacer portion of the second spacer structure are better than those of the spacer portion of the first spacer structure;
[0040] S03: performing a lightly doped source / drain process using the first spacer structure and the second spacer structure;
[0041] S04: removing the second spacer structure, and forming a source-drain structure in the source-drain region using the first spacer structure.
[0042] Figure 2a ˉ Figure 2g The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the semiconductor device provided in this embodiment is shown below. Figure 2a ˉ Figure 2g The preparation method of the semiconductor device is described in detail.
[0043] First, please refer to Figure 2a , performing step S01 to provide a semiconductor substrate 10 including a gate structure and source and drain regions located on both sides of the gate structure.
[0044] The material of the semiconductor substrate 10 may include any suitable silicon base material known to those skilled in the art, for example, may be at least one of the following materials: silicon, silicon germanium, silicon on insulator, etc.
[0045] The semiconductor substrate 10 may include several different regions for forming transistors with different electrical properties and performance, such as a first region AA and a second region BB. The first region AA is provided with a first gate structure 21a and a first source / drain region 21b, with the first source / drain region 21b disposed on either side of the first gate structure 21a. The second region BB is provided with a second gate structure 22a and a second source / drain region 22b, with the second source / drain region 22b disposed on either side of the second gate structure 22a. In this embodiment, the first region AA may be used to form a PMOS transistor in the core region, and the second region BB may be used to form an NMOS transistor in the core region. Of course, the second region BB may also be used to form other transistors, such as an NMOS transistor in the IO region and a PMOS transistor in the IO region.
[0046] The first gate structure 21a and the second gate structure 22a may each include a gate dielectric layer located on the semiconductor substrate 10, a gate conductive material layer located on the gate dielectric layer, and a hard material layer located on the gate conductive material layer. The semiconductor substrate 10 below the first gate structure 21a and the second gate structure 22a may serve as corresponding channels. In some examples, the first gate structure 21a and the second gate structure 22a may serve as actual gate structures. In other examples, the first gate structure 21a and the second gate structure 22a may serve as dummy gate structures for forming metal gates.
[0047] Next, step S02 is executed to sequentially form a first spacer structure 23 and a second spacer structure 25 on the semiconductor substrate 10. The first spacer structure 23 and the second spacer structure 25 both include a spacer portion located on the sidewall of the gate structure. The dielectric constant of the spacer portion 24b of the first spacer structure 23 is smaller than the dielectric constant of the second spacer structure 25, and the chemical mechanical properties of the spacer portion 26b of the second spacer structure 25 are better than the chemical mechanical properties of the spacer portion 24b of the first spacer structure 23.
[0048] Specifically, the first sidewall structure 23 may be formed, and the process may include, for example: Figure 2b , a first oxide layer 23a and a first nitrogen-containing dielectric layer 23b are sequentially formed. The first oxide layer 23a conformally covers the outer wall of the first gate structure 21a, the outer wall of the second gate structure 22a, the first source / drain region 21b, and the second source / drain region 22b. The first nitrogen-containing dielectric layer 23b conformally covers the surface of the first oxide layer 23a. In practice, the formed first oxide layer 23a conformally covers the entire surface of the semiconductor substrate 10. The material of the first oxide layer 23a may include silicon oxide, and its thickness may be, for example, but not limited to, 10 angstroms to 100 angstroms. The dielectric constant of the first nitrogen-containing dielectric layer 23b may be lower than that of common hard material layers (such as silicon nitride), but the chemical and mechanical properties of the first nitrogen-containing dielectric layer 23b (including strength and corrosion resistance) may be greater than those of silicon oxide, and it can be used to support other structures. In this embodiment, the material of the first nitrogen-containing dielectric layer 23b may preferably be silicon carbide nitride, and its thickness may be, for example, but not limited to, 10 angstroms to 100 angstroms.
[0049] Please refer to Figure 2cThe first nitrogen-containing dielectric layer 23b on the surfaces of the first source / drain region 21b and the second source / drain region 22b is removed, and the remaining first oxide layer 23a and the first nitrogen-containing dielectric layer 23b serve as the first spacer 23. The remaining first oxide layer 23a on the surfaces of the first source / drain region 21b and the second source / drain region 22b serves as the extension 24a of the first spacer 23. The first nitrogen-containing dielectric layer 23b and the first oxide layer 23a on the sidewalls of the first gate structure 21a and the second gate structure 22a serve as the spacer portion 24b of the first spacer 23. Dry etching perpendicular to the surface of the semiconductor substrate 10 can be used to remove the first nitrogen-containing dielectric layer 23b on the surfaces of the first source / drain region 21b and the second source / drain region 22b. Of course, the first nitrogen-containing dielectric layer 23b located on the top (top wall) of the first gate structure 21a and the second gate structure 22a can also be partially or completely removed. In addition, a certain amount of over-etching can be performed in the above process, that is, removing a portion of the thickness of the first oxide layer 23a on the surface of the first source and drain regions 21b and the second source and drain regions 22b to ensure that the first nitrogen-containing dielectric layer 23b on the surface of the first source and drain regions 21b and the second source and drain regions 22b is completely removed.
[0050] Next, the second sidewall structure 25 may be formed, and the process may include, for example: Figure 2d , a second oxide layer 25a and a second nitrogen-containing dielectric layer 25b are formed in sequence. The second oxide layer 25a conformally covers the surface of the first sidewall structure 23, and the second nitrogen-containing dielectric layer 25b conformally covers the surface of the second oxide layer 25a. The material and thickness of the second oxide layer 25a can refer to the material and thickness of the first oxide layer 23a. The chemical mechanical properties of the second nitrogen-containing dielectric layer 25b can be better than those of the first nitrogen-containing dielectric layer 23b, and it can have strong resistance to etching and cleaning in the photoresist layer rework process. In this embodiment, the material of the second nitrogen-containing dielectric layer 25b can be preferably silicon nitride, and its thickness can be, for example, but not limited to, 10 angstroms to 100 angstroms.
[0051] Please refer to Figure 2e , remove the second nitrogen-containing dielectric layer 25b on the surface of the first source / drain region 21b and the second source / drain region 22b, and use the remaining second oxide layer 25a and the second nitrogen-containing dielectric layer 25b as the second spacer structure 25, the remaining second oxide layer 25a on the surface of the first source / drain region 21b and the second source / drain region 22b as the extension 26a of the second spacer structure 25, and the second nitrogen-containing dielectric layer 25b and the second oxide layer 25a on the sidewalls of the first gate structure 21a and the second gate structure 22a as the sidewall portion 26b of the second spacer structure 25.
[0052] The second nitrogen-containing dielectric layer 25b on the surfaces of the first source / drain region 21b and the second source / drain region 22b can be removed by dry etching perpendicular to the surface of the semiconductor substrate 10. Of course, the second nitrogen-containing dielectric layer 25b located on the top (top wall) of the first gate structure 21a and the second gate structure 22a can also be partially or completely removed. Furthermore, a certain amount of overetching can be performed during the above process, i.e., a portion of the thickness of the second oxide layer 25a on the surfaces of the first source / drain region 21b and the second source / drain region 22b can be removed to ensure that the second nitrogen-containing dielectric layer 25b on the surfaces of the first source / drain region 21b and the second source / drain region 22b is completely removed.
[0053] Next, please refer to Figure 2f , executing step S03, performing a lightly doped source / drain process using the first spacer structure 23 and the second spacer structure 25.
[0054] Before performing the lightly doped source and drain process, the thickness of the oxide layer (extension portion) on the surface of the source and drain regions (the first source and drain regions 21b and the second source and drain regions 22b) can also be adjusted to avoid ion tunneling during the ion implantation process, that is, the second oxide layer 25a of part thickness on the source and drain regions or part thickness of the second oxide layer 25a and the first oxide layer 23a can be removed, and a wet process can preferably be used to remove the above-mentioned partial thickness of the oxide layer.
[0055] Specifically, the steps of performing the lightly doped source and drain process may include: forming a patterned mask layer (e.g., a patterned photoresist layer) covering the surface of the semiconductor substrate 10, the openings of the patterned mask layer exposing the corresponding source and drain regions, performing various tests (e.g., appearance, thickness, etc.) on the patterned mask layer to determine whether it is qualified, and if so, performing corresponding lightly doped ion implantation on the exposed source and drain regions to form corresponding lightly doped source and drain regions (including pocket structures), and if not, performing a rework process on the patterned mask layer, i.e., a rework process on the patterned photoresist layer, and then re-performing various tests on it. The openings of the patterned mask layer are bounded by the sidewall portion 26b of the second sidewall structure 25 corresponding to the source and drain regions, i.e., the thickness of the sidewall portions of the first sidewall structure 23 and the second sidewall structure 25 is used to define the distance between the lightly doped source and drain regions formed after the lightly doped ion implantation and the channel under the gate structure. In this embodiment, the sidewall portion 26b of the second sidewall structure 25 can be utilized to have stronger chemical mechanical properties, which can better resist etching and cleaning in the photoresist layer rework process, so that the second sidewall structure 25 that has not undergone the photoresist rework process and the second sidewall structure 25 that has undergone the photoresist rework process have as similar thickness as possible, so that the source and drain lightly doped regions of the transistors of the same batch of semiconductor substrates 10 have their respective corresponding close distances from the channel, thereby reducing the electrical performance fluctuations of each transistor caused by the sidewall thickness.
[0056] It is understandable that transistors of various electrical properties and functions on the semiconductor substrate 10 may have lightly doped source and drain regions with different electrical properties and different concentrations. Therefore, more than ten lightly doped source and drain processes may be performed on the semiconductor substrate 10, that is, more than ten photoresist layer photolithography processes. For a batch of semiconductor substrates 10, some of them may undergo at least one photoresist layer rework process. The removal of the photoresist layer and the cleaning process in the photoresist layer rework process will cause erosion of the exposed sidewall thickness, causing the distance between the edge of the sidewall and the channel under the gate structure to change, thereby affecting the electrical performance of the transistor.
[0057] Next, step S04 is performed to remove the second spacer structure 25 and form a source-drain structure in the source-drain region using the first spacer structure 23 .
[0058] For details, please refer to Figure 2g , remove the second sidewall spacer 25, and expose and retain the first sidewall spacer 23. When removing the second nitrogen-containing dielectric layer 25b and the second oxide layer 25a, a wet process targeting the second oxide layer 25a can be preferably used to remove the second nitrogen-containing dielectric layer 25b located on the second oxide layer 25a while removing the second oxide layer 25a. The etchant of the above-mentioned wet process can be a silicon oxide buffered etchant or hydrofluoric acid. The etchant also has a high etching selectivity ratio (less etching) for the sidewall portion 24b of the first sidewall spacer 23, so as to minimize the corrosion of the sidewall portion 24b of the first sidewall spacer 23. Of course, in the above-mentioned process, it is also feasible to partially remove the extension portion 24a (first oxide layer 23a) of the first sidewall spacer 23.
[0059] Among them, the first source and drain region 21b can be used to form a PMOS transistor in the core area, and the step of forming the first source and drain structure in the first source and drain region 21b may include: forming a patterned mask layer, the opening of the patterned mask layer exposes the corresponding first source and drain region 21b, the above-mentioned exposed first source and drain region 21b can use the side wall portion 24b of the first side wall structure 23 as a boundary, then, using the patterned mask layer, performing a dry etching process to form source and drain trenches in the first source and drain region 21b to expose the silicon in the semiconductor substrate 10, then, performing a germanium silicon epitaxial process to form a germanium silicon epitaxial structure in the above-mentioned source and drain trenches as the first source and drain structure. The second source-drain region 22b can be used to form an NMOS transistor. The step of forming a second source-drain structure in the second source-drain region 22b may include: forming a patterned mask layer, the opening of the patterned mask layer exposing the corresponding second source-drain region 22b, the above-mentioned exposed second source-drain region 22b can use the sidewall portion 24b of the first sidewall structure 23 as a boundary, and then, using the patterned mask layer, performing source-drain ion implantation to form a second source-drain structure in the second source-drain region 22b.
[0060] Thus, the first source-drain structure and the second source-drain structure formed above both use the sidewall portion of the first sidewall structure as their boundary close to the channel, and the first sidewall structure itself also has chemical mechanical properties superior to silicon oxide, so that it can maintain a relatively fixed thickness. Therefore, regardless of whether the transistor undergoes a photoresist layer rework process, the lightly doped source-drain structure and the source-drain structure of the transistor each have a fixed distance relative to the channel, thereby reducing the electrical performance fluctuations of each transistor caused by the sidewall thickness (i.e., improving the uniformity of the speed of each transistor). Moreover, the sidewall portion of the retained first sidewall structure also has a relatively low dielectric constant and is relatively thin, which can reduce the dielectric loss between each gate structure, thereby reducing the RC delay within the semiconductor device.
[0061] In summary, in the present invention, a first spacer structure and a second spacer structure are sequentially formed on a semiconductor structure having a gate structure and a source / drain region. The first spacer structure and the second spacer structure both include a spacer portion located on the sidewall of the gate structure. The dielectric constant of the sidewall portion of the first spacer structure is less than that of the second spacer structure, and the chemical mechanical properties of the sidewall portion of the second spacer structure are better than those of the sidewall portion of the first spacer structure. A lightly doped source / drain process is performed using the first and second spacer structures. The second spacer structure is removed, and a source / drain structure is formed in the source / drain region using the first spacer structure. During the lightly doped source / drain process, the strong chemical mechanical properties of the sidewall portion of the second spacer structure can be utilized to better resist etching and cleaning in the photoresist rework process, so that the second spacer structure that has not undergone the photoresist rework process and the second spacer structure that has undergone the photoresist rework process have as similar thickness as possible, thereby ensuring that the lightly doped source / drain regions of transistors on the same semiconductor substrate and the same batch are as close as possible to the channel, thereby reducing electrical performance fluctuations of each transistor caused by the sidewall thickness. After performing the light source and drain doping process, the second spacer structure is removed, leaving only the sidewall portion of the first spacer structure between the gate structures. The sidewall portion of the retained first spacer structure, which has a relatively low dielectric constant and is thinner than the first and second spacers, can be used to reduce dielectric loss between the gate structures, thereby reducing RC delay within the semiconductor device. Furthermore, the fabrication method of this embodiment employs a unified treatment method for both regions that have undergone photoresist rework and those that have not undergone photoresist rework, as well as for the semiconductor substrate. This simple and easy treatment method provides high practicality.
[0062] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate comprising a gate structure and source and drain regions located on both sides of the gate structure; forming a first spacer structure and a second spacer structure in sequence on the semiconductor substrate, wherein the first spacer structure and the second spacer structure both include a spacer portion located on a sidewall of the gate structure, the dielectric constant of the spacer portion of the first spacer structure being smaller than the dielectric constant of the second spacer structure, and the chemical mechanical properties of the spacer portion of the second spacer structure being better than those of the spacer portion of the first spacer structure; Performing a lightly doped source / drain process using the first spacer structure and the second spacer structure; The second spacer structure is removed, and a source-drain structure is formed in the source-drain region using the first spacer structure.
2. The method for preparing a semiconductor device according to claim 1, wherein: The first spacer structure and the second spacer structure both include an extension portion covering the surface of the source and drain regions.
3. The method for preparing a semiconductor device according to claim 2, wherein: The step of forming the first sidewall structure includes: forming a first oxide layer conformally covering the outer wall of the gate structure and the surface of the source and drain regions; forming a first nitrogen-containing dielectric layer conformally covering the first oxide layer; The first nitrogen-containing dielectric layer on the surface of the source and drain regions is removed, and the remaining first oxide layer on the surface of the source and drain regions is used as an extension of the first sidewall structure, and the first nitrogen-containing dielectric layer and the first oxide layer on the sidewall of the gate structure are used as the sidewall portion of the first sidewall structure.
4. The method for preparing a semiconductor device according to claim 3, wherein: The step of forming the second sidewall structure includes: forming a second oxide layer conformally covering the first sidewall structure; forming a second nitrogen-containing dielectric layer conformally covering the second oxide layer, wherein the dielectric constant of the second nitrogen-containing dielectric layer is greater than the dielectric constant of the first nitrogen-containing dielectric layer; The second nitrogen-containing dielectric layer on the source / drain region is removed, and the remaining second oxide layer on the source / drain region is used as an extension of the second spacer structure. The second nitrogen-containing dielectric layer and the second oxide layer on the sidewall of the gate structure are used as the sidewall portion of the second spacer structure.
5. The method for preparing a semiconductor device according to claim 4, wherein: The second nitrogen-containing dielectric layer includes silicon nitride, and the first nitrogen-containing dielectric layer includes silicon carbide.
6. The method for preparing a semiconductor device according to claim 4, wherein: The first nitrogen-containing dielectric layer and the second nitrogen-containing dielectric layer on the source / drain region are removed by dry etching.
7. The method for preparing a semiconductor device according to claim 4, wherein: The second oxide layer and the second nitrogen-containing dielectric layer on the second oxide layer are removed by a wet process to remove the second sidewall structure.
8. The method for preparing a semiconductor device according to claim 2, wherein: After forming the second spacer structure and before performing the lightly doped source / drain process, the second spacer structure and a portion of the extension of the first spacer structure are removed.
9. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: The source-drain region includes a P-type source-drain region, and the step of forming a P-type source-drain structure in the P-type source-drain region includes: Using the first sidewall structure, a source-drain trench is formed in the semiconductor substrate in the P-type source-drain region; A silicon-germanium structure is epitaxially formed in the source-drain trench to serve as the P-type source-drain structure.
10. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: The source / drain region includes an N-type source / drain region, and source / drain ion implantation is performed using the first sidewall structure to form an N-type source / drain structure in the N-type source / drain region.