Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and aims to solve the problems of performance reduction and serious saturation current degradation when some transistors are insufficient in driving. A double-layer gate oxide layer formed by stacking a first gate oxide layer and a second gate oxide layer in the prior art is replaced by a third gate oxide layer which is thinner and more compact in quality. And the polycrystalline silicon gates of the transistors continuously extend from the third gate oxide layer of the channel region to the double-layer gate oxide layer above the partial region of the LDD region, so that the thickness of the gate oxide layer above the channel region of the transistors is reduced, and meanwhile, the gate oxide layers of the transistors generate height difference on the LDD region; therefore, the electric field intensity of the overlapped region of the LDD region and the polycrystalline silicon gate can be effectively reduced, hot carriers in the region are reduced, the reliability of the hot carrier effect and the like of the device is not influenced, and the saturation current and the performance of the transistor can be improved under the condition that the transistors are insufficient in driving.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Current semiconductor devices typically include high voltage (HV) transistors (whose conventional operating voltage is 20 to 50 V), medium voltage (MV) transistors (whose conventional operating voltage is 2 V to 10 V), and low voltage (LV) transistors (whose conventional operating voltage is, for example, 0.6 to 2 V) with different operating voltages formed on a semiconductor substrate (e.g., silicon).

[0003] An existing method for manufacturing a semiconductor device having a medium voltage transistor and a low voltage transistor generally includes the following steps:

[0004] First, please refer to Figure 1 In (A), a device isolation structure 101 is formed in the substrate 100 (for defining a first transistor region I and a second transistor region II, the first transistor region I is used to manufacture a medium-voltage transistor, and the second transistor region II is used to manufacture a low-voltage transistor) and well implantation and LDD implantation are performed (forming a lightly doped region 100a). Then, a first gate oxide layer 102a and a second gate oxide layer 102b (i.e., a double-layer gate oxide layer) are stacked in sequence on the substrate 100.

[0005] Then, please refer to Figure 1 In (A) and (B), a patterned photoresist layer 103 is formed on the second gate oxide layer 102b by a photolithography process, and the patterned photoresist layer 103 is used as a mask to only etch away the second gate oxide layer 102b and the first gate oxide layer 102a on the second transistor region II. The first gate oxide layer 102a and the second gate oxide layer 102b on other regions including the first transistor region I are retained because they are masked by the patterned photoresist layer 103.

[0006] Next, please refer to Figure 1 In step (C), the patterned photoresist layer 103 is removed, and a thinner third gate oxide layer 102c is regrown on the substrate of the second transistor region II.

[0007] Afterwards, please refer to Figure 1 In step (D), a polysilicon layer 104 is deposited and the polysilicon layer and the second gate oxide layer 102b are etched to form the required polysilicon gates on the first transistor region I and the second transistor region II. Further, sidewalls 105 are formed on the sidewalls of each polysilicon gate, and corresponding source and drain ion implantation is performed to form source and drain regions 100b of the first transistor region I and source and drain regions 100c of the second transistor region II.

[0008] In order to save energy, reduce power consumption, and increase standby time to improve market competitiveness, medium-voltage transistors are usually driven at a voltage lower than the normal operating voltage of the medium-voltage transistors. In other words, the medium-voltage transistors are driven at a low voltage. This results in underdrive of the medium-voltage transistors, resulting in reduced performance of the medium-voltage transistors and a phenomenon in which the saturation current Idsat is too small. Figure 2 As shown, the function of the circuit where the medium voltage transistor is located is limited, thereby reducing the yield of the entire semiconductor integrated circuit device.

[0009] In the prior art, in order to improve the performance and saturation current (Idsat) of the medium voltage transistor when the medium voltage transistor is underdriven, the overlap (OVL) between the lightly doped region (i.e., MVLDD region) and the polysilicon gate (poly gate) of the medium voltage transistor is usually increased, i.e., Figure 1 As shown by the dotted arrow in (D), the lightly doped region (i.e., MVLDD region) 100a of the medium voltage transistor is retracted into the channel to reduce the effective channel length L, thereby increasing the saturation current of the medium voltage transistor. However, this method has the following problems:

[0010] 1. The increased overlap between the lightly doped region and the polysilicon gate of the medium-voltage transistor may lead to gate-induced drain leakage (GIDL);

[0011] 2. For medium-voltage transistors with a relatively high doping concentration in the lightly doped region, reducing the effective channel length may result in a risk of device punch-through in the medium-voltage transistor. Summary of the Invention

[0012] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can improve the performance and saturation current of a medium-voltage transistor when the corresponding medium-voltage transistor is underdriven.

[0013] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0014] Providing a substrate having a first transistor region and a second transistor region, wherein the first transistor region and the second transistor region have different conventional operating voltages;

[0015] forming a first gate oxide layer and a second gate oxide layer stacked sequentially on the substrate;

[0016] forming a patterned mask layer on the second gate oxide layer to open the channel region of the first transistor region and the second transistor region and mask the remaining regions;

[0017] Using the patterned mask layer as a mask, etching and removing the second gate oxide layer and the first gate oxide layer exposed by the patterned mask layer to expose the channel region of the first transistor region and the substrate surface of the second transistor region;

[0018] forming a third gate oxide layer on the exposed surface of the substrate, wherein the thickness of the third gate oxide layer is less than the stacking thickness of the first gate oxide layer and the second gate oxide layer;

[0019] A polysilicon layer is deposited and the polysilicon layer and the second gate oxide layer are etched to form a polysilicon gate on the first transistor region and the second transistor region, wherein the polysilicon gate of the first transistor region covers the surface of the third gate oxide layer in the channel region and continuously extends to the surface of the second gate oxide layer retained outside the channel region.

[0020] Optionally, the manufacturing method further forms a lightly doped region in the substrate outside the channel region of the first transistor region before forming the first gate oxide layer or after forming the polysilicon gate, and the first gate oxide layer and the second gate oxide layer are sandwiched between the polysilicon gate and the lightly doped region.

[0021] Optionally, the manufacturing method, after forming the polysilicon gate, further comprises:

[0022] forming sidewall spacers on sidewalls of each of the polysilicon gates;

[0023] The source and drain regions of the first transistor region and the second transistor region are formed together or successively, wherein the source and drain regions of the first transistor region are formed in a surface layer of the lightly doped region.

[0024] Optionally, the step of providing a substrate having a first transistor region and a second transistor region includes:

[0025] Providing a substrate, and performing deep well implantation in the substrate to form a deep well;

[0026] forming a device isolation structure in the deep well to define a first transistor region and a second transistor region;

[0027] forming a first well in the deep well surface layer of the first transistor region, and forming a second well in the deep well surface layer of the second transistor region;

[0028] The channel region and the lightly doped regions on both sides thereof are laterally distributed in a surface layer of the first well, and the source and drain regions of the second transistor region are formed in a surface layer of the second well.

[0029] Optionally, the third gate oxide layer has higher density than the first gate oxide layer and the second gate oxide layer.

[0030] Optionally, the manufacturing method further includes at least one of the following parameters:

[0031] (1) The thickness of the third gate oxide layer is thinner than the thickness of the first gate oxide layer;

[0032] (2) the thickness of the second gate oxide layer is thicker than the thickness of the first gate oxide layer;

[0033] (3) The normal operating voltage of the first transistor region is higher than the normal operating voltage of the second transistor region;

[0034] (4) The thickness of the first gate oxide layer is

[0035] (5) The thickness of the second gate oxide layer is

[0036] (6) The thickness of the third gate oxide layer is

[0037] (7) The first transistor region is used to form a medium-voltage transistor, and the second transistor region is used to form a low-voltage transistor. The normal operating voltage of the medium-voltage transistor is 2V to 10V, and the normal operating voltage of the low-voltage transistor is 0.6V to 2V.

[0038] (8) The processes for forming the first gate oxide layer and the third gate oxide layer are respectively selected from furnace thermal oxidation, rapid thermal annealing oxidation, in-situ water vapor oxidation, atomic layer deposition or chemical vapor deposition, and the process for forming the second gate oxide layer is selected from atomic layer deposition or chemical vapor deposition.

[0039] Based on the same inventive concept, the present invention further provides a semiconductor device comprising:

[0040] a substrate having a first transistor region and a second transistor region, wherein the first transistor region and the second transistor region have different conventional operating voltages;

[0041] a first gate oxide layer and a third gate oxide layer, wherein the third gate oxide layer covers a surface of a channel region of the first transistor region and a surface of a substrate of the second transistor region, and the first gate oxide layer covers a surface of the substrate exposed by the third gate oxide layer;

[0042] A polysilicon gate and a second gate oxide layer, wherein the polysilicon gate of the second transistor region is formed on a portion of the surface of the third gate oxide layer of the second transistor region, and the polysilicon gate of the first transistor region covers the surface of the third gate oxide layer of the first transistor region and continuously extends onto a portion of the first gate oxide layer outside the channel region of the first transistor region, with the second gate oxide layer sandwiched between the polysilicon gate of the first transistor region and the first gate oxide layer outside the channel region of the first transistor region.

[0043] Optionally, the semiconductor device further includes:

[0044] A lightly doped region is formed in the substrate on both sides of the channel region of the first transistor region, and the second gate oxide layer is formed on top of a side of the lightly doped region close to the channel region;

[0045] Sidewall spacers formed on side walls of each of the polysilicon gates;

[0046] a source and drain region formed in a surface layer of the lightly doped region of the first transistor region;

[0047] forming a source and drain region in the substrate of the second transistor region;

[0048] A device isolation structure is formed at a junction of the first transistor region and the second transistor region.

[0049] Optionally, the semiconductor device further includes:

[0050] A deep well is formed in the substrate, and the device isolation structure is formed in the deep well to define the first transistor region and the second transistor region;

[0051] a first well formed in a deep well surface layer of the first transistor region;

[0052] a second well formed in a deep well surface layer of the second transistor region;

[0053] The channel region and the lightly doped regions on both sides thereof are laterally distributed in a surface layer of the first well, and the source and drain regions of the second transistor region are formed in a surface layer of the second well.

[0054] Optionally, the semiconductor device further includes at least one of the following parameters:

[0055] (1) The thickness of the third gate oxide layer is thinner than the thickness of the first gate oxide layer;

[0056] (2) the thickness of the second gate oxide layer is thicker than the thickness of the first gate oxide layer;

[0057] (3) The normal operating voltage of the first transistor region is higher than the normal operating voltage of the second transistor region;

[0058] (4) The thickness of the first gate oxide layer is

[0059] (5) The thickness of the second gate oxide layer is

[0060] (6) The thickness of the third gate oxide layer is

[0061] (7) The first transistor region is used to form a medium-voltage transistor, and the second transistor region is used to form a low-voltage transistor. The normal operating voltage of the medium-voltage transistor is 2V to 10V, and the normal operating voltage of the low-voltage transistor is 0.6V to 2V.

[0062] (8) The third gate oxide layer has a higher density than the first gate oxide layer and the second gate oxide layer.

[0063] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0064] 1. To address the performance degradation and severe saturation current degradation of certain transistors (such as medium-voltage transistors) when underdriven (underdrive), the gate oxide layer on the channel region of these transistors is replaced from the original double-layer gate oxide layer with a thinner and denser gate oxide layer. The polysilicon gate of these transistors is continuously extended from the channel region to the double-layer gate oxide layer on both sides of the channel region (i.e., extending above part of the LDD region). This not only reduces the thickness of the gate oxide layer above the channel region of these transistors, but also retains the original thickness of the gate oxide layer above other areas of the LDD region of these transistors (i.e., the gate oxide layer of these transistors has a height difference above the LDD region). This can effectively reduce the electric field strength in the overlapping area of ​​the LDD region and the polysilicon gate (poly), reducing hot carriers in this area, ensuring that reliability such as the heat-carried injection effect (HCI) is not affected. Therefore, the saturation current Idsat of these transistors can be increased when these transistors are underdriven, avoiding the risk of increased gate-induced drain leakage current and transistor punch-through.

[0065] 2. In the manufacturing method of the present invention, by modifying the corresponding mask, the double-layer gate oxide layer in the second transistor region can be etched away while the double-layer gate oxide layer on the channel region of the first transistor region is also etched away at the same time, and the double-layer gate oxide layer on part of the lightly doped region of the first transistor region is retained. Subsequently, a thinner and denser third gate oxide layer is grown on the first transistor region and the second transistor region together. There is no need to add additional masks, etching processes and oxidation processes. The process is simple, easy to implement and low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0067] Figure 1 This is a schematic diagram of a device cross-sectional structure in an existing method for manufacturing a semiconductor device.

[0068] Figure 2 This is a schematic diagram of the saturation current of an existing medium-voltage transistor when it is normally driven and underdriven.

[0069] Figure 3 It is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0070] Figure 4 It is a schematic diagram of a cross-sectional structure of a device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0071] Figure 5 1 is a schematic diagram of saturation current curves of the first transistor under two simulated third gate oxide layer thicknesses in one embodiment of the present invention.

[0072] Figure 6 1 is a schematic diagram of the saturation current of the first transistor under five simulated third gate oxide layer thicknesses in one embodiment of the present invention. DETAILED DESCRIPTION

[0073] In the following description, a large number of specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, some technical features known in the art are not described to avoid confusion with the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. The same reference numerals throughout represent the same elements. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly connected to" another element, there are no intervening elements. When used herein, the singular forms "a," "an," and "said / the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of certain features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] The technical solutions proposed by the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0075] Please refer to Figure 3 An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps:

[0076] S1, providing a substrate having a first transistor region and a second transistor region, wherein the first transistor region and the second transistor region have different conventional operating voltages;

[0077] S2, forming a first gate oxide layer and a second gate oxide layer stacked in sequence on the substrate;

[0078] S3, forming a patterned mask layer on the second gate oxide layer to open the channel region of the first transistor region and the second transistor region and mask the remaining regions;

[0079] S4, using the patterned mask layer as a mask, etching and removing the second gate oxide layer and the first gate oxide layer exposed by the patterned mask layer to expose the channel region of the first transistor region and the substrate surface of the second transistor region;

[0080] S5, forming a third gate oxide layer on the exposed surface of the substrate, wherein the thickness of the third gate oxide layer is less than the stacking thickness of the first gate oxide layer and the second gate oxide layer;

[0081] S6, depositing a polysilicon layer and etching the polysilicon layer and the second gate oxide layer to form a polysilicon gate on the first transistor region and the second transistor region, wherein the polysilicon gate of the first transistor region covers the surface of the third gate oxide layer in the channel region and continuously extends to the surface of the second gate oxide layer retained outside the channel region.

[0082] In step S1, please refer to Figure 4 In step (A), first, a substrate 200 is provided, which can be any suitable semiconductor substrate in the art, such as silicon (Si), silicon-on-insulator (SOI), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide, etc. Next, a deep well implantation is performed on the substrate 200 to form a deep well 200a in the substrate 200. For example, the substrate 200 is made of p-type single crystal silicon, and any suitable one or more n-type ions such as arsenic (As) ions, phosphorus (P) ions, antimony (Sb) ions, etc. are used to form an n-type deep well 200a. Next, a device isolation structure 201 can be formed in the substrate 200 using a shallow trench isolation (STI) process or a local isolation (LOCOS) process to define at least one first transistor region I and at least one second transistor region II. The conventional operating voltages of the transistors subsequently formed based on the first transistor region I and the second transistor region II are different. Then, a first well 200b is formed in the deep well surface layer of the first transistor region I, and a second well 200c is formed in the deep well surface layer of the second transistor region II, through a photolithography process combined with a well ion implantation process. When the desired conductivity types of the first well 200b and the second well 200c are opposite (i.e., one is a p-type well and the other is an n-type well), two different photomasks and different well ion implantation processes are required to form the first well 200b and the second well 200c, respectively. Furthermore, when there are multiple first transistor regions I, the conductivity types of the first wells 200b in different first transistor regions I can be the same or different; and when there are multiple second transistor regions II, the conductivity types of the second wells 200c in different second transistor regions II can be the same or different. For each transistor region, the first well in the first transistor region I for forming an n-type transistor and the second well in the second transistor region II are both p-type wells, and the first well in the first transistor region I for forming a p-type transistor and the second well in the second transistor region II are both n-type wells.

[0083] As an example, at least one p-type dopant ion such as boron (B) ions, boron fluoride ions, indium ions, gallium ions, etc. is injected into the surface layer of the deep well 200a of the corresponding first transistor region I to form a p-type well as the first well 200b, and at least one n-type dopant ion such as phosphorus (P), arsenic (As) ions, antimony (Sb) ions is injected into the surface layer of the deep well 200a of the corresponding second transistor region II to form an n-type well as the second well 200c.

[0084] In other embodiments of the present invention, at least one p-type dopant ion, such as boron (B) ions, boron fluoride ions, indium ions, and gallium ions, may be implanted into the surface layer of the deep well 200a of the corresponding second transistor region II to form a p-type well as the second well 200c. Alternatively, at least one n-type dopant ion, such as phosphorus (P), arsenic (As), and antimony (Sb) ions, may be implanted into the surface layer of the deep well 200a of the corresponding first transistor region I to form an n-type well as the first well 200b.

[0085] Optionally, the normal operating voltage of the first transistor region I is higher than the normal operating voltage of the second transistor region II. As an example, the first transistor region I defined in step S1 is used to form a medium-voltage transistor, and the second transistor region II is used to form a low-voltage transistor (which can be used as a logic transistor). The normal operating voltage of the medium-voltage transistor is 2V to 10V (for example, 8V), and the normal operating voltage of the low-voltage transistor is 0.6V to 2V (for example, 1.1V).

[0086] As an example, in step S1, after forming the first well 200b and the second well 200c, a photolithography process may be used to mask the portion of the first well 200b serving as the channel region and the second well 200c, exposing the first well 200b regions on both sides of the channel region. Ion implantation is then performed on the exposed first well 200b regions using a lightly doped drain (LDD) ion implantation process to form lightly doped regions (i.e., LDD regions) 200d in the surface layer of the first well 200b on both sides of the channel region of the first transistor region I. The conductivity type of the lightly doped regions 200d is opposite to that of the first well 200b. For example, when the first well 200b is a p-type well, the lightly doped regions 200d are n-type doped regions. The first well 200b between the lightly doped regions 200d is a channel region (not labeled), i.e., the channel region and the lightly doped regions 200d on both sides thereof are laterally distributed in the surface layer of the first well 200b.

[0087] It should be understood that the formation nodes of the lightly doped regions 200d are not limited to this example. In other examples of the present invention, after the polysilicon layer is subsequently etched to form a polysilicon gate, a lightly doped drain ion implantation process can be used to implant ions into the first well 200b regions on both sides of the polysilicon gate (the first well 200b region covered by the polysilicon gate serves as the channel region of the first transistor region I), thereby forming lightly doped regions (i.e., LDD regions) 200d in the surface layer of the first well 200b on both sides of the channel region of the first transistor region I. In this case, due to the masking of the polysilicon gate, a photomask can be omitted, and the LDD ion implantation process is a self-aligned ion implantation process.

[0088] In one example, in step S2, please continue to refer to Figure 4 In (A), first, a first gate oxide layer 202a can be formed on the substrate 200 by any suitable process such as furnace thermal oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), atomic layer deposition or chemical vapor deposition; then, a second gate oxide layer 202b can be formed on the first gate oxide layer 202a by any suitable deposition process such as atomic layer deposition or chemical vapor deposition.

[0089] In another example, in step S2, please continue to refer to Figure 4 In step (A), a second gate oxide layer 202b can be first formed on the substrate 200 by any suitable process such as furnace thermal oxidation, rapid thermal annealing oxidation (RTO), in-situ steam oxidation (ISSG), high-temperature oxidation (e.g., process temperature greater than 700°C), atomic layer deposition, chemical vapor deposition, etc.; and then a first gate oxide layer 202a is formed between the substrate 200 and the second gate oxide layer 202b by any suitable oxidation process such as furnace thermal oxidation, rapid thermal annealing oxidation (RTO), or in-situ steam oxidation (ISSG). The first gate oxide layer 202a is used to reduce interface defects between the substrate 200 and the gate oxide layer in a corresponding region (e.g., the region where the LDD region of the medium-voltage transistor overlaps with the gate), and the second gate oxide layer 202b is used to ensure that the thickness of the gate oxide layer in the corresponding region (e.g., the region where the LDD region of the medium-voltage transistor overlaps with the gate) meets the requirements.

[0090] Optionally, the thickness of the second gate oxide layer 202 b is greater than the thickness of the first gate oxide layer 202 a .

[0091] Optionally, the formation processes of the first gate oxide layer 202a and the second gate oxide layer 202b are different, so that the first gate oxide layer 202a and the second gate oxide layer 202b have a higher selectivity in the subsequent process of etching the second gate oxide layer 202b, so as to avoid unnecessary damage to the first gate oxide layer 202a caused by the subsequent process of etching the second gate oxide layer 202b.

[0092] In one example, the surface of the substrate 200 is oxidized by furnace thermal oxidation, rapid thermal annealing oxidation, or in-situ steam oxidation to form a first gate oxide layer 202a. The thickness of the first gate oxide layer 202a is between For example, wait.

[0093] In one example, a high temperature oxide layer (HTO) is formed by any suitable process such as high temperature oxidation (e.g., oxidation temperature above 700° C.), atomic layer deposition, low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or atmospheric pressure chemical vapor deposition, and post-deposition annealing (to eliminate dangling bonds in the HTO layer) is performed to form a second gate oxide layer 202 b. The thickness of the second gate oxide layer 202 b is between For example, wait.

[0094] In one example, in step S3, please continue to refer to Figure 4 In (A), a patterned mask layer 203 (i.e., it can be a patterned photoresist layer) is formed on the second gate oxide layer 202b by performing a series of photolithography operations such as coating, exposure, and development on the second gate oxide layer 202b. The patterned mask layer 203 has a first opening 203a and a second opening 203b. The first opening 203a exposes the second gate oxide layer 202b on the channel region of the first transistor region I (i.e., the first opening 203a is used to open the region of the first well 200b used as the channel region), and the second opening 203b exposes the second transistor region II (i.e., the second opening 203b is used to open the second well 200c). The patterned mask layer 203 also masks the remaining regions.

[0095] In another example, in step S3, please continue to refer to Figure 4 In (A), a patterned mask layer 203 (i.e., a hard mask layer such as silicon nitride) is formed on the second gate oxide layer 202b by performing a series of photolithography operations such as hard mask layer (e.g., silicon nitride) deposition, photolithography, hard mask layer etching, and desmearing on the second gate oxide layer 202b. The patterned mask layer 203 also has a first opening 203a and a second opening 203b.

[0096] It should be understood that, compared to the prior art, step S3 can be implemented by modifying the corresponding mask without modifying the process flow, so there is no need to add additional masks and etching processes. The process is simple, easy to implement, and low-cost.

[0097] Please continue to refer to Figure 4In step (B), in step S4, the patterned mask layer 203 is used as a mask and any suitable etching process, such as a dry etching process or a wet etching process, is used to etch away the second gate oxide layer 202b and the first gate oxide layer 202a exposed by the patterned mask layer 203 (i.e., the second gate oxide layer 202b and the first gate oxide layer 202a at the bottom of the first opening 203a and the second opening 203b are etched away), thereby exposing the channel region of the first transistor region I (i.e., the surface of a portion of the first well 200b) and the substrate surface of the second transistor region II (i.e., the surface of the second well 200c). The patterned mask layer 203 can then be removed or retained as needed.

[0098] In step S5, please refer to Figure 4 In (C), any suitable process such as furnace thermal oxidation, rapid thermal annealing oxidation, in-situ water vapor oxidation, atomic layer deposition, chemical vapor deposition, etc. can be used to form a third gate oxide layer 202c on the surface of the substrate 200 of the first transistor region I and the second transistor region II exposed by the second gate oxide layer 202b, and the thickness of the third gate oxide layer 202c is less than the stacking thickness of the first gate oxide layer 202a and the second gate oxide layer 202b.

[0099] Optionally, the third gate oxide layer 202c has a higher density than the first gate oxide layer 202a and the second gate oxide layer 202b, and the third gate oxide layer 202c is thinner than the first gate oxide layer 202a and the second gate oxide layer 202b.

[0100] At this time, in the first transistor region I, the gate oxide layer on the LDD region 200d is a double-layer oxide layer structure formed by stacking the first gate oxide layer 202a and the second gate oxide layer 202b (that is, the original thickness of the gate oxide layer is retained), and the gate oxide layer on the channel region between the LDD regions 200d is a relatively thinner and denser third gate oxide layer 202c, that is, the gate oxide layer in the first transistor region I is a non-uniform structure, and the gate oxide layer on the side of the LDD region 200d close to the channel region will form a step (that is, a height difference is formed), and the gate oxide layer (gate OX) above the channel region is thinner than the physical thickness of the gate oxide layer above the LDD region, thereby ensuring that the reliability of the hot carrier effect (Heat Carried Injection Effect, HCI) is not affected, and when these transistors are underdriven, the saturation current Idsat of these transistors is increased, avoiding the risk of increased gate-induced drain leakage current and transistor punch-through.

[0101] Optionally, the thickness of the third gate oxide layer 202c is less than that of the first gate oxide layer 202a. In one example, the thickness of the third gate oxide layer 202c is between For example, wait.

[0102] It is worth noting that in step S5, a third gate oxide layer can be formed on the channel region of the first transistor region I and the second transistor region II through the same gate oxide process. Therefore, there is no need to add an additional mask, nor is there a need to add an additional oxidation process or deposition process. The process is simple, easy to implement, and low cost.

[0103] In step S6, please refer to Figure 4 In step (D), a polysilicon layer can first be deposited on the surfaces of the second gate oxide layer 202b, the third gate oxide layer 202c, and the exposed device isolation structure 201 by any suitable chemical vapor deposition process, such as low-temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), or atomic layer deposition. Then, the polysilicon layer and the second gate oxide layer 202b are etched by a photolithography process combined with an etching process to form a polysilicon gate 204a on the first transistor region I and a polysilicon gate 204b on the second transistor region II. In this etching of the polysilicon layer, not only the polysilicon layer on the channel region is retained in the first transistor region I, but also the polysilicon layer on the steps of the gate oxide layer at the edges of the LDD region 200d on both sides of the channel region is retained. Therefore, after the etching of the polysilicon layer is completed, the second gate oxide layer 202b exposed by the remaining polysilicon layer is further etched away in a self-aligned manner using the remaining polysilicon layer as a mask. The remaining polysilicon layer in the first transistor region I is the polysilicon gate 204a of the first transistor region I, and the polysilicon gate 204b is further removed. 4a not only covers the third gate oxide layer 202c in the channel region, but also continuously extends to the partial surface of the second gate oxide layer 202b on the edges of the LDD regions 200d on both sides of the channel region. Therefore, the gate oxide layer in the overlapping area of ​​the polysilicon gate 204a and the LDD region 200d is a thicker double-layer structure formed by stacking the second gate oxide layer 202b and the first gate oxide layer 202a. The gate oxide layer on the channel region between the LDD regions 200d is composed of the thinner and denser third gate oxide layer 202c.

[0104] Optionally, for the manufacturing method of this embodiment, please refer to Figure 4 (D) in the embodiment further includes, after forming the polysilicon gates 204a and 204b and etching the second gate oxide layer 202b:

[0105] First, dielectric material deposition and etching processes are used to form sidewall spacers 205 on the sidewalls of each polysilicon gate 204a, 204b. The sidewall spacers 205 may be a single-layer structure or a multi-layer structure (e.g., a double-layer sidewall formed of silicon oxide and silicon nitride, or a triple-layer sidewall formed of silicon oxide, silicon nitride, and silicon oxide). In other embodiments of the present invention, the sidewall spacers 205 on the polysilicon gate 204a may further extend downward to cover the exposed sidewalls of the second gate oxide layer 202b, and the sidewall spacers 205 on the polysilicon gate 204b may further extend downward to cover the exposed sidewalls of the third gate oxide layer 202c.

[0106] Next, the source and drain regions 200e of the first transistor region I and the source and drain regions 200f of the second transistor region II are formed one by one or successively, wherein the source and drain regions 200e of the first transistor region I are formed in the surface layer of the lightly doped region 200d, and the source and drain regions 200f of the second transistor region II are formed in the surface layer of the second well 200c.

[0107] Please refer to Figure 5 and Figure 6 With all other conditions remaining the same as those in the prior art, the overlap between the polysilicon gate and the LDD region of the first transistor region I is maintained unchanged (i.e., the channel length between the LDD regions is maintained unchanged), as is the thickness of the gate oxide layer in the overlapping region between the polysilicon gate and the LDD region of the first transistor region I. Simulation tests of the technical solution of the present invention are conducted by varying only the thickness of the gate oxide layer between the LDD regions of the first transistor region I (i.e., the third gate oxide layer on the channel region of the first transistor region I). The results indicate that a reduction in the thickness of the gate oxide layer between the LDD regions of the first transistor region I (i.e., a step difference is formed between the LDD region and the gate oxide layer on the channel region of the first transistor region I) effectively increases the saturation current Idsat of the transistor having the LDD region and gate oxide layer co-formed in the first transistor region I. This is because: for the transistor formed in the first transistor region I, when it is necessary to turn on the transistor, after applying a corresponding voltage to the polysilicon gate, a corresponding conductive channel will be formed in the channel region below the polysilicon gate, allowing current to flow. During this period, the gate oxide layer is used to control the electric field distribution in the channel region, thereby changing the charge density in the channel region and controlling the flow of current. Therefore, the thickness of the gate oxide layer will affect the conductive channel length and electric field distribution at the bottom of the polysilicon gate. The smaller the thickness of the gate oxide layer, the lower the threshold voltage and the greater the saturation current. In this embodiment, the thickness of the gate oxide layer between the LDD regions (i.e., the channel region) is thinned to make the electric field distribution more concentrated, thereby increasing the saturation current. This can improve the saturation current Idsat and performance of the transistor formed in the first transistor region when the transistor is underdriven, thereby improving the device yield.

[0108] In addition, in this embodiment, the gate oxide layer in the overlapping area between the bottom of the polysilicon gate and the LDD region (i.e., a double-layer gate oxide layer stacked by the first gate oxide layer and the second gate oxide layer) is thicker than the gate oxide layer in the channel region (i.e., a single-layer gate oxide layer composed of the third gate oxide layer), forming a height difference of the gate oxide layer, which can effectively reduce the electric field strength in the overlapping area of ​​the LDD region and the polysilicon gate (poly), reduce the hot carriers in this area, and ensure that the reliability performance of the device, such as the hot carrier injection effect (HCI), is not affected, thereby increasing the saturation current Idsat of these transistors when these transistors are insufficiently driven, avoiding the risk of increased gate-induced drain leakage current and transistor punch-through.

[0109] In addition, the manufacturing method of the semiconductor device of this embodiment first forms a double-layer gate oxide layer consisting of a first gate oxide layer and a second gate oxide layer stacked together, and then removes the double-layer gate oxide layer in the second transistor region and forms a thinner and denser third gate oxide layer. At the same time, the double-layer gate oxide layer on the channel region of the first transistor region is removed and the third gate oxide layer is formed on the channel region. No additional masks and processes are added, and the method is easy to implement and low in cost.

[0110] Based on the same invention concept, please refer to Figure 4 (D) in the figure, an embodiment of the present invention further provides a semiconductor device, which can be manufactured using the manufacturing method of the semiconductor device of the present invention, or using any other suitable manufacturing method, and the semiconductor device includes a substrate 200, a first gate oxide layer 202a, a second gate oxide layer 202b, a third gate oxide layer 202c, a polysilicon gate 204a and a polysilicon gate 204b, and a sidewall 205.

[0111] A deep well 200a is also formed in the substrate 200, and a device isolation structure 201 is formed in the deep well 200a to define a first transistor region I and a second transistor region II. A first well 200b is formed in the surface layer of the deep well 200a of the first transistor region I, and a second well 200c is formed in the surface layer of the deep well 200a of the second transistor region II. The surface layer of the first well 200b is also formed with lightly doped regions 200d arranged laterally at intervals. The first well 200b between the lightly doped regions 200d serves as the channel region of the first transistor region I (not labeled, i.e., the channel region and the lightly doped regions 200d on both sides are laterally distributed in the surface layer of the first well 200b). The first transistor region I and the second transistor region II have different normal operating voltages.

[0112] The third gate oxide layer 202c covers the surface of the channel region of the first transistor region I (i.e., the surface of the first well 200b between the lightly doped regions 200d) and the substrate surface of the second transistor region II (i.e., the surface of the second well 200c); the first gate oxide layer 202a covers the substrate surface exposed by the third gate oxide layer 202c (including the surface of the lightly doped region 200d); the second gate oxide layer 202b covers the surface of the first gate oxide layer 202a in the edge area of ​​the lightly doped region 200d close to the channel region.

[0113] Optionally, the thickness of the second gate oxide layer 202 b is greater than the thickness of the first gate oxide layer 202 a .

[0114] Optionally, the thickness of the third gate oxide layer 202c is at least thinner than the stacked thickness of the first gate oxide layer 202a and the second gate oxide layer 202b on the lightly doped region 200d. For example, the thickness of the third gate oxide layer 202c is thinner than the thickness of the first gate oxide layer 202a.

[0115] For example, the thickness of the first gate oxide layer 202a is The thickness of the second gate oxide layer 202b is The thickness of the third gate oxide layer 202c is

[0116] The polysilicon gate 204b of the second transistor region II is formed on a portion of the surface of the third gate oxide layer of the second transistor region II. The polysilicon gate 204a of the first transistor region I covers the surface of the third gate oxide layer 202c and the surface of the second gate oxide layer 202b of the first transistor region I. That is, the polysilicon gate 204a of the first transistor region I extends continuously from the third gate oxide layer 202c on the channel region of the first transistor region I to portions of the first gate oxide layer 202a on both sides of the channel region of the first transistor region II, with the second gate oxide layer 202b sandwiched between the polysilicon gate 204a and the first gate oxide layer 202a on both sides of the channel region of the first transistor region I.

[0117] Spacers 205 are formed on sidewalls of the polysilicon gates 204 a and 204 b .

[0118] Source and drain regions 200e are further formed in the surface layer of the lightly doped region 200d of the first transistor region I on both sides of the polysilicon gate 204a; source and drain regions 200f are further formed in the surface layer of the second well 200c of the second transistor region II on both sides of the polysilicon gate 204b.

[0119] The source / drain region 200e and the source / drain region 200f may have opposite or same conductivity types, as long as the device design requirements are met. The present invention does not impose any specific limitation on this.

[0120] In this embodiment, the number of the first transistor area I and the second transistor area II and the type of transistor to be formed are not specifically limited. Any suitable transistor can be manufactured. For example, the first transistor area I is used to form a medium-voltage transistor, and the second transistor area II is used to form a low-voltage transistor. The conventional operating voltage of the medium-voltage transistor is 2V~10V (for example, 8V), and the conventional operating voltage of the low-voltage transistor is 0.6V~2V (for example, 1.1V).

[0121] It should be understood that the parameters such as materials of various structures of the semiconductor device of this embodiment can refer to the corresponding contents in the above-mentioned method for manufacturing the semiconductor device, and will not be repeated here.

[0122] In the semiconductor device of this embodiment, in order to solve the problem that the performance of certain transistors (i.e., transistors formed in the first transistor region I, such as medium-voltage transistors) in the semiconductor device is degraded and the saturation current is seriously degraded when underdrive is insufficient, the gate oxide layer on the channel region of these transistors is replaced by the original double-layer gate oxide layer (e.g., the first gate oxide layer formed by the ISSG process and the second gate oxide layer formed by the HTO process) with a thinner and more dense third gate oxide layer, and the polysilicon gate of these transistors is continuously extended from the channel region to the double-layer gate oxide layer on both sides of the channel region (i.e., to the part of the LDD region). This not only reduces the thickness of the gate oxide layer above the channel region of these transistors, but also retains the original thickness of the gate oxide layer above other areas of the LDD region of these transistors (that is, the gate oxide layer of these transistors has a height difference). This can effectively reduce the electric field strength in the overlapping area of ​​the LDD region and the polysilicon gate (poly), reducing the hot carriers in this area to ensure that the reliability of the device, such as the hot carrier effect, is not affected. Therefore, the saturation current Idsat and performance of these transistors can be improved when these transistors are underdriven, avoiding the risk of increased gate-induced drain leakage current and transistor punch-through.

[0123] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate having a first transistor region and a second transistor region, wherein the first transistor region and the second transistor region have different conventional operating voltages; forming a first gate oxide layer and a second gate oxide layer stacked sequentially on the substrate; forming a patterned mask layer on the second gate oxide layer to open the channel region of the first transistor region and the second transistor region and mask the remaining regions; Using the patterned mask layer as a mask, etching and removing the second gate oxide layer and the first gate oxide layer exposed by the patterned mask layer to expose the channel region of the first transistor region and the substrate surface of the second transistor region; forming a third gate oxide layer on the exposed surface of the substrate, wherein the thickness of the third gate oxide layer is less than the stacking thickness of the first gate oxide layer and the second gate oxide layer; A polysilicon layer is deposited and the polysilicon layer and the second gate oxide layer are etched to form a polysilicon gate on the first transistor region and the second transistor region, wherein the polysilicon gate of the first transistor region covers the surface of the third gate oxide layer in the channel region and continuously extends to the surface of the second gate oxide layer retained on both sides outside the channel region.

2. The manufacturing method according to claim 1, wherein Before forming the first gate oxide layer or after forming the polysilicon gate, a lightly doped region is formed in the substrate outside the channel region of the first transistor region, and the first gate oxide layer and the second gate oxide layer are sandwiched between the polysilicon gate and the lightly doped region.

3. The manufacturing method according to claim 2, wherein: After forming the polysilicon gate, the method further includes: forming sidewall spacers on sidewalls of each of the polysilicon gates; The source and drain regions of the first transistor region and the second transistor region are formed together or successively, wherein the source and drain regions of the first transistor region are formed in a surface layer of the lightly doped region.

4. The manufacturing method according to claim 3, wherein: The step of providing a substrate having a first transistor region and a second transistor region comprises: Providing a substrate, and performing deep well implantation in the substrate to form a deep well; forming a device isolation structure in the deep well to define a first transistor region and a second transistor region; forming a first well in the deep well surface layer of the first transistor region, and forming a second well in the deep well surface layer of the second transistor region; The channel region and the lightly doped regions on both sides thereof are laterally distributed in a surface layer of the first well, and the source and drain regions of the second transistor region are formed in a surface layer of the second well.

5. The manufacturing method according to claim 1, wherein: The third gate oxide layer has higher density than the first gate oxide layer and the second gate oxide layer.

6. The manufacturing method according to any one of claims 1 to 5, characterized in that Also includes at least one of the following parameters: (1) The thickness of the third gate oxide layer is thinner than the thickness of the first gate oxide layer; (2) the thickness of the second gate oxide layer is thicker than the thickness of the first gate oxide layer; (3) The normal operating voltage of the first transistor region is higher than the normal operating voltage of the second transistor region; (4) The thickness of the first gate oxide layer is (5) The thickness of the second gate oxide layer is (6) The thickness of the third gate oxide layer is (7) The first transistor region is used to form a medium-voltage transistor, and the second transistor region is used to form a low-voltage transistor. The normal operating voltage of the medium-voltage transistor is 2V to 10V, and the normal operating voltage of the low-voltage transistor is 0.6V to 2V. (8) The processes for forming the first gate oxide layer and the third gate oxide layer are respectively selected from furnace thermal oxidation, rapid thermal annealing oxidation, in-situ water vapor oxidation, atomic layer deposition or chemical vapor deposition, and the process for forming the second gate oxide layer is selected from atomic layer deposition or chemical vapor deposition.

7. A semiconductor device, characterized in that: include: a substrate having a first transistor region and a second transistor region, wherein the first transistor region and the second transistor region have different conventional operating voltages; a first gate oxide layer and a third gate oxide layer, wherein the third gate oxide layer covers a surface of a channel region of the first transistor region and a surface of a substrate of the second transistor region, and the first gate oxide layer covers a surface of the substrate exposed by the third gate oxide layer; A polysilicon gate and a second gate oxide layer, wherein the polysilicon gate of the second transistor region is formed on a portion of the surface of the third gate oxide layer of the second transistor region, and the polysilicon gate of the first transistor region covers the surface of the third gate oxide layer of the first transistor region and continuously extends onto a portion of the first gate oxide layer outside the channel region of the first transistor region, with the second gate oxide layer sandwiched between the polysilicon gate of the first transistor region and the first gate oxide layer outside the channel region of the first transistor region.

8. The semiconductor device according to claim 7, wherein Also includes: A lightly doped region is formed in the substrate on both sides of the channel region of the first transistor region, and the second gate oxide layer is formed on top of a side of the lightly doped region close to the channel region; Sidewall spacers formed on side walls of each of the polysilicon gates; a source and drain region formed in a surface layer of the lightly doped region of the first transistor region; forming a source and drain region in the substrate of the second transistor region; A device isolation structure is formed at a junction of the first transistor region and the second transistor region.

9. The semiconductor device according to claim 8, wherein Also includes: A deep well is formed in the substrate, and the device isolation structure is formed in the deep well to define the first transistor region and the second transistor region; a first well formed in a deep well surface layer of the first transistor region; a second well formed in a deep well surface layer of the second transistor region; The channel region and the lightly doped regions on both sides thereof are laterally distributed in a surface layer of the first well, and the source and drain regions of the second transistor region are formed in a surface layer of the second well.

10. The semiconductor device according to claim 8 or 9, wherein: Also includes at least one of the following parameters: The thickness of the third gate oxide layer is thinner than that of the first gate oxide layer; (2) the thickness of the second gate oxide layer is thicker than the thickness of the first gate oxide layer; (3) The normal operating voltage of the first transistor region is higher than the normal operating voltage of the second transistor region; (4) The thickness of the first gate oxide layer is (5) The thickness of the second gate oxide layer is (6) The thickness of the third gate oxide layer is (7) The first transistor region is used to form a medium-voltage transistor, and the second transistor region is used to form a low-voltage transistor. The normal operating voltage of the medium-voltage transistor is 2 to 10 V, and the normal operating voltage of the low-voltage transistor is 0.6 V to 2 V. (8) The third gate oxide layer has a higher density than the first gate oxide layer and the second gate oxide layer.

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