Semiconductor devices with different threshold voltages in integrated circuits

Abstract

The present disclosure generally relates to semiconductor devices with different threshold voltages in an integrated circuit (IC). In an example, an IC includes a semiconductor substrate (222), a channel layer (226), a barrier layer (428), a first semiconductor device (402), and a second semiconductor device (206). The channel layer (226) is on the semiconductor substrate (222), and the channel layer (226) includes a gallium nitride (GaN) material. The barrier layer (428) is on the channel layer (226). The first semiconductor device (402) is on the semiconductor substrate (222). The first semiconductor device (402) includes a first terminal (248a) over the barrier layer (428), and the first semiconductor device (402) has a first threshold voltage. The second semiconductor device (206) is on the semiconductor substrate (222). The second semiconductor device (206) includes a second terminal (248c) over the barrier layer (428), and the second semiconductor device (206) has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

Description

Technical Field

[0001] The present application relates to semiconductor devices. Background Art

[0002] One type of semiconductor device is a high electron mobility transistor (HEMT). HEMTs typically use different semiconductor materials to form a heterojunction, where a channel can be formed near the heterojunction and between source and drain regions. HEMTs can operate at high speeds, making them attractive for applications such as high-frequency applications. Summary of the Invention

[0003] This summary is provided to introduce a brief selection of the disclosed concepts in a simplified form, which are further described in the detailed description, which includes the accompanying figures. The various disclosed devices and methods can be advantageously applied to semiconductor devices with different threshold voltages in integrated circuits (ICs). Although such embodiments can be expected to achieve improved performance in target applications, no specific results are required unless expressly stated in a particular claim.

[0004] The example described herein is an integrated circuit (IC). The IC includes a semiconductor substrate, a channel layer, a barrier layer, a first semiconductor device, and a second semiconductor device. The channel layer is on the semiconductor substrate and includes a gallium nitride (GaN) material. The barrier layer is on the channel layer. The first semiconductor device is on the semiconductor substrate. The first semiconductor device includes a first terminal above the barrier layer and has a first threshold voltage. The second semiconductor device is on the semiconductor substrate. The second semiconductor device includes a second terminal above the barrier layer and has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

[0005] Another example described herein is an integrated circuit (IC). The IC includes a semiconductor substrate, a first high electron mobility transistor (HEMT), a second HEMT, and a diode. The first HEMT is on the semiconductor substrate. The first HEMT is coupled between a power terminal and a switch terminal. The second HEMT is on the semiconductor substrate. The second HEMT is coupled between the switch terminal and a ground terminal. The diode is on the semiconductor substrate. The diode is coupled between the switch terminal and the ground terminal. The diode has a different threshold voltage than at least one of the first HEMT and the second HEMT.

[0006] Another example described herein is an integrated circuit (IC). The IC includes a semiconductor substrate, a first depletion-mode HEMT, an enhancement-mode HEMT, and a comparator. The first depletion-mode HEMT is on the semiconductor substrate. The first depletion-mode HEMT is coupled between a power terminal and a clamp terminal. The first depletion-mode HEMT has a first threshold voltage. The enhancement-mode HEMT is on the semiconductor substrate. The enhancement-mode HEMT is coupled between the clamp terminal and a ground terminal. The enhancement-mode HEMT has a gate terminal. The comparator has a first comparator input, a second comparator input, and a comparator output. The first comparator input is electrically coupled to the clamp terminal. The second comparator input is electrically coupled to a reference terminal. The comparator output is electrically coupled to the gate terminal. The comparator includes a second depletion-mode HEMT on the semiconductor substrate. The second depletion-mode HEMT has a second threshold voltage different from the first threshold voltage.

[0007] An example method is provided. A channel layer is formed on a semiconductor substrate. The channel layer includes a gallium nitride (GaN) material. A barrier layer is formed on the channel layer. A first semiconductor device is formed on the semiconductor substrate. The first semiconductor device includes a first terminal above the barrier layer and has a first threshold voltage. A second semiconductor device is formed on the semiconductor substrate. The second semiconductor device includes a second terminal above the barrier layer and has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.

[0008] The foregoing summary has generally outlined various features of the examples of the present disclosure so that the following detailed description may be better understood. Additional features and advantages of these examples will be described below. The examples described may be readily used as a basis for modifying or designing other examples within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic diagram of a circuit including semiconductor devices having different threshold voltages according to some examples.

[0010] Figure 1B is a schematic diagram of a circuit including semiconductor devices having different threshold voltages according to some examples.

[0011] Figure 2 、 3 , 4, 5, 6, 7, 8, and 9 are diagrams illustrating cross-sectional views of corresponding integrated circuits (ICs) according to some examples.

[0012] Figure 10 Based on some examples Figure 2Flowchart of the IC method.

[0013] Figure 11 、 12 , 13, 14, 15, 16, 17, 18, 19, 20 and 21 are diagrams according to some examples Figure 2 Schematic diagram of a cross-section of an IC at various fabrication stages.

[0014] Figure 22 Based on some examples Figure 4 Flowchart of the IC method.

[0015] Figure 23 、 24 , 25 and 26 are diagrams according to some examples Figure 4 Schematic diagram of a cross-section of an IC at various fabrication stages.

[0016] Figure 27 Based on some examples Figure 6 Flowchart of the IC method.

[0017] Figure 28 、 29 , 30, 31 and 32 are diagrams according to some examples Figure 6 Schematic diagram of a cross-section of an IC at various fabrication stages.

[0018] Figure 33 Based on some examples Figure 7 Flowchart of the IC method.

[0019] Figure 34 、 35 , 36 and 37 are diagrams according to some examples Figure 7 Schematic diagram of a cross-section of an IC at various fabrication stages.

[0020] Figure 38 is a flow chart of a method of fabricating an IC in which gate layers have different doping concentrations, according to some examples.

[0021] Figure 39 、 40 , 41 , and 42 are schematic diagrams illustrating cross-sectional views of an IC at various stages of fabrication, according to some examples.

[0022] Figure 43 is a flow chart of a method of fabricating an IC in which gate layers have different doping concentrations, according to some examples.

[0023] Figure 44 and 45 is a schematic diagram illustrating cross-sectional views of an IC at various stages of fabrication, according to some examples.

[0024] Figure 46 is a flow chart of a method of fabricating an IC in which gate layers have different doping concentrations, according to some examples.

[0025] Figure 47 、 48 49 are schematic diagrams illustrating cross-sectional views of an IC at various stages of fabrication, according to some examples.

[0026] Figure 50 is a flow chart of a method for manufacturing an IC using a gate first process according to some examples.

[0027] Figure 51 、 52 , 53 , 54 , and 55 are schematic diagrams illustrating cross-sectional views of an IC at various stages of fabrication according to some examples.

[0028] Figure 56 is a flow chart of a method for fabricating an IC using a gate-first process, according to some examples.

[0029] Figure 57 is a diagram illustrating a cross-sectional view of an IC at a stage of fabrication, according to some examples.

[0030] Figure 58 is a flow chart of a method for fabricating an IC using a gate-first process, according to some examples.

[0031] Figure 59 、 60 , 61 , and 62 are schematic diagrams illustrating cross-sectional views of an IC at various stages of fabrication, according to some examples.

[0032] Figure 63 is a graph illustrating threshold voltage of a semiconductor device as a function of gate layer thickness according to some examples.

[0033] Figure 64 is a graph illustrating threshold voltage of a semiconductor device as a function of gate layer dopant concentration, according to some examples.

[0034] Figure 65 is a graph illustrating threshold voltage of a semiconductor device as a function of barrier layer thickness, according to some examples.

[0035] Figure 66 is a graph illustrating threshold voltage of a semiconductor device as a function of gate length, according to some examples.

[0036] Figure 67 is a graph illustrating threshold voltage of a semiconductor device as a function of contact offset length, according to some examples.

[0037] Figure 68 、 69 , 70 , 71 , and 72 are schematic diagrams illustrating cross-sectional views of respective semiconductor devices, illustrating different isolation mechanisms, according to some examples.

[0038] The drawings and accompanying detailed description are provided to facilitate understanding of the features of the various examples and do not limit the scope of the appended claims. The examples shown in the drawings and described in the accompanying detailed description can be readily used as a basis for modifying or designing other examples within the scope of the appended claims. Wherever possible, the same reference numerals are used to represent identical elements that are common to the figures. The figures are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0039] Various features will be described below with reference to the accompanying drawings. The examples shown may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other example, even if not shown or not explicitly described as such. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders with more or fewer operations (e.g., including different serial or parallel executions of various operations).

[0040] The present disclosure relates to semiconductor devices with different threshold voltages in an integrated circuit (IC). In some examples described herein, the semiconductor device may be or include a high electron mobility transistor (HEMT), a HEMT-based device, a diode, or the like. An example HEMT-based device may include a diode-connected HEMT. In some examples, the IC includes two or more semiconductor devices of the same type but with different threshold voltages. The IC may include one or more other semiconductor devices of the same or different types and with the same threshold voltage or different threshold voltages. For example, the IC may include two or more enhancement mode (Emode) HEMTs with different threshold voltages, and may further include one or more depletion mode (Dmode) HEMTs. In another example, the IC may include two or more Dmode HEMTs with different threshold voltages, and may further include one or more Emode HEMTs. In some examples, the IC in which the semiconductor device is formed may include a gallium nitride (GaN) platform, such as indium aluminum gallium nitride (InGaN). i Al j Ga 1-i-j N, where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1) platform.

[0041] According to some examples, an IC includes a semiconductor substrate, a channel layer on the semiconductor substrate, and a barrier layer on the channel layer. A first semiconductor device (e.g., a HEMT) is on the semiconductor substrate and has a first threshold voltage. A second semiconductor device (e.g., a HEMT) is on the semiconductor substrate and has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages can both be corresponding positive voltages or corresponding negative voltages. The first and second semiconductor devices can both be of the same Emode type or Dmode type. Other examples include a method of manufacturing such an IC. The method includes forming a channel layer on the semiconductor substrate, forming a barrier layer on the channel layer, forming the first semiconductor device, and forming the second semiconductor device.

[0042] Different threshold voltages in a semiconductor device can be achieved by one or more techniques. Any number of those techniques can be implemented in any semiconductor device to achieve a target threshold voltage.

[0043] A first technique involves implementing different thicknesses for respective gate layers of a semiconductor device, such as for an Emode HEMT. As described in detail below, a semiconductor device such as an Emode HEMT may include a gate layer, such as a p-doped semiconductor layer, which may further include a gate metal contact that forms a Schottky or ohmic junction with the gate layer. The thickness of the gate layer may affect the Schottky capacitance and hole depletion of the gate metal contact to the gate layer. Therefore, a positive gate voltage may need to be applied to the gate layer before the gate layer begins to modulate the channel. A thinner gate layer may result in a semiconductor device having a larger Schottky capacitance and a lower threshold voltage than a semiconductor device having a thicker gate layer. To form such gate layers having different thicknesses, the gate layer may be patterned, and the patterned gate layer may then be selectively reduced (e.g., by etching while the mask deselects the gate layer).

[0044] Another technique involves implementing different thicknesses of barrier layers for semiconductor devices, such as Emode HEMTs. In some examples, the barrier layer can be aluminum gallium nitride (AlGaN). A higher aluminum (Al) content in the barrier layer at the channel lowers the threshold voltage (e.g., the positive threshold voltage can be reduced to zero, and the negative threshold voltage can be reduced to a more negative voltage). The aluminum content can vary based on different concentrations and / or thicknesses. A greater thickness can result in a higher aluminum content, while a reduced thickness can result in a lower aluminum content. A thicker barrier layer can also result in a higher channel electron density, which is more difficult to deplete by the gate layer, resulting in a lower threshold voltage. The barrier thickness can increase polarization charge and, therefore, can also lower the threshold voltage. Therefore, in some examples, the barrier layer at the channel of a semiconductor device is thinner than the barrier layer at the channel of another semiconductor device. To form barrier layers of varying thickness, in some examples, the barrier layer can be deposited (e.g., epitaxially grown), and a recess can be etched in the channel of the semiconductor device where the thinner barrier layer is to be provided. To form barrier layers having different thicknesses, in some examples, the barrier layer may include a first barrier sublayer that is deposited (e.g., epitaxially grown) and through which an opening is etched at a channel of a semiconductor device where a thinner barrier layer is to be formed. The barrier layer may further include a second barrier sublayer that is deposited (e.g., epitaxially grown) on the first barrier sublayer and in the opening.

[0045] Another technique includes implementing different thicknesses of the channel layer for a semiconductor device, such as an Emode HEMT. In some examples, the channel layer can be on one or more transition layers, which can include one or more doped buffer layers. By having channel layers of different thicknesses, the distance from the doped buffer layer can be varied, which can produce different threshold voltages. The thinner the channel layer, the closer the channel in the channel layer is to the doped buffer layer, and the greater the threshold voltage. Being closer to the doped buffer layer can result in lower electron density, thereby increasing depletion of the channel, which can result in an increase in the threshold voltage. To form channel layers with different thicknesses, in some examples, the channel layer can be deposited (e.g., epitaxially grown), and a recess can be etched in the channel of the semiconductor device to have a thinner channel layer.

[0046] Another technique includes implementing different gate lengths for the gate layer of a semiconductor device (e.g., an Emode HEMT), where the gate length is the length of the gate layer along the axis between the source and drain. For a certain range of gate lengths, the threshold voltage decreases as the gate length increases, and for another range of gate lengths, the threshold voltage increases as the gate length increases. Due to the longer gate length, a longer depletion region may result in a channel region below the gate layer between the source and drain. Therefore, a larger gate voltage may be required to generate enough charge to replenish the depleted charge and form a channel, which may result in a higher threshold voltage. To form gate layers with different gate lengths, in some examples, the mask used to pattern the gate layer can be modified to achieve the gate length.

[0047] Another technique involves implementing different gate contact offset lengths between the gate metal contact and the gate layer of a semiconductor device, such as for an Emode HEMT. The gate contact offset length can be the distance between the sidewall of the gate metal contact (where the gate metal contact contacts the gate layer) and the corresponding sidewall of the gate layer. Increasing the gate contact offset length within a certain range increases the threshold voltage. Due to the gate contact offset, the gate metal is closer to the channel (e.g., directly on the gate layer), and the metal above the gate contact offset length has a passivation layer and gate layer below it. As a result, the channel region directly below the gate metal has a lower threshold voltage and can form a channel, while the channel region within the gate contact offset length has a higher threshold voltage and can form a channel. Increasing the gate contact offset length can reduce the size of the gate contact directly above the channel region and increase the threshold voltage. To achieve different gate contact offset lengths, in some examples, the mask used to form the contact opening to the gate layer (e.g., through one or more dielectric layers) can be modified to achieve the gate contact offset length.

[0048] Another technique involves implementing different dopant concentrations in corresponding gate layers of a semiconductor device, including different uniform concentrations or different concentration gradients, such as for an Emode HEMT. As described in detail below, a semiconductor device such as an Emode HEMT may include a gate layer, such as a p-doped semiconductor layer. Having different concentrations of p-type dopant in a p-doped semiconductor gate layer may result in different numbers of acceptors compared to the p-type dopant amount, thereby resulting in different threshold voltages. A lower number of acceptors in the gate layer may result in less depletion in the semiconductor device channel, which may lower the semiconductor device's threshold voltage. Conversely, a higher number of acceptors in the gate layer may result in greater depletion in the semiconductor device channel, which may increase the semiconductor device's threshold voltage. Therefore, a gate layer with a lower dopant concentration may result in a semiconductor device having a lower threshold voltage than a semiconductor device with a gate layer having a higher threshold voltage. To form such gate layers with different dopant concentrations, in some examples, different gate sublayers may be deposited (e.g., epitaxially grown) with different in-situ doping, where the gate layer is patterned from the different gate sublayers. To form such a gate layer with different dopant concentrations, in other examples, the gate layer can be deposited (e.g., epitaxially grown) with in-situ doping and dopant implanted into some areas to have a higher dopant concentration. To form such a gate layer with different dopant concentrations, in still other examples, the gate layer can be deposited (e.g., epitaxially grown) and dopant implanted into different areas at different concentrations.

[0049] Another technique involves implementing different metal-barrier work functions in semiconductor devices, such as for Emode HEMTs. Different metals can be used as gate metal contacts for different semiconductor devices to achieve different metal-barrier work functions. To form the different gate contact metals, in some examples, multiple processes, each including metal deposition and metal patterning, can be used to form the different gate metal contacts.

[0050] Another technique includes implementing different effective gate-to-channel capacitances for a semiconductor device, for example, for a Dmode HEMT. The semiconductor device may be a Dmode metal-insulator-semiconductor HEMT (MIS-HEMT). The effective gate-to-channel capacitance is a function of the thickness of the dielectric material and the dielectric constant of the dielectric material. Therefore, various examples include modifying the thickness and / or dielectric constant of the dielectric material implemented in the semiconductor device. For example, to implement different effective gate-to-channel capacitances, two dielectric layers may be formed, wherein a second dielectric layer is formed on a first dielectric layer. The second dielectric layer may be a different material than the first dielectric layer, such that the two dielectric layers have different dielectric constants. The second dielectric layer may be removed from the semiconductor device, such that the first and second dielectric layers remain as gate dielectric layers for at least one semiconductor device, and the first dielectric layer remains as the gate dielectric layer for at least one other semiconductor device. Other methods of forming gate dielectric layers with different thicknesses and / or dielectric constants may be implemented.

[0051] Implementing semiconductor devices with different threshold voltages in an IC can provide improved performance for the IC. Combining semiconductor devices in an IC (e.g., in a single die or chip), such as a system on a chip (SoC), can save power, reduce size, lower costs, and reduce parasitic effects, among other benefits and advantages.

[0052] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, the examples may incorporate any combination of the features generally described above (which are described in more detail in the examples below). Various operations and / or processes may be implemented according to the methods of the various examples to achieve various aspects.

[0053] The examples described herein can implement a platform for integrating different semiconductor devices on an IC. Such a platform can allow for the inclusion of E-mode HEMTs (which may include a Schottky junction to the gate layer), D-mode HEMTs (e.g., D-mode MIS-HEMTs), and field-effect rectifiers and / or diodes. In such a monolithic integration, multiple threshold voltages can be achieved, such as low threshold voltages for E-mode HEMTs used in driver circuits, low threshold currents for freewheeling diodes, low threshold voltages for HEMTs used in startup circuits, fine-tuned clamping voltages for high-resolution clamping diode stacks, and high threshold voltages for both low-voltage and high-voltage power HEMTs to avoid false turn-on during rapid switching. Other components and devices, such as resistors, capacitors, and inductors, can be included in the monolithic integration. For example, such monolithic integration can be implemented for high-efficiency power conversion and other applications.

[0054] Figure 1AFIG1 is a circuit schematic diagram of a circuit 100 including a semiconductor device according to some examples. Circuit 100 is an example buck converter circuit. Circuit 100 can be implemented as an IC on a single die or chip, and can further be included on a SoC. Circuit 100 includes a gate driver circuit 102, a first HEMT 104, a second HEMT 106, a diode 108, and a load circuit 110. Load circuit 110 includes an inductor 112, a capacitor 114, and a resistor 116. First HEMT 104 and second HEMT 106 can be Emode HEMTs and can have the same or similar threshold voltages. The threshold voltage of diode 108 (e.g., a diode-connected HEMT) can be different from (e.g., lower than) the threshold voltage of at least one of first HEMT 104 or second HEMT 106. For example, the lower threshold voltage of diode 108 can minimize power loss during dead time. In some examples, diode 108 is integrated with first HEMT 104 and / or second HEMT 106 (eg, implemented on the same semiconductor die) to reduce parasitic effects and the overall size of circuit 100 .

[0055] The first HEMT 104 is electrically coupled between a power terminal (VIN) and a switch terminal (VSW). More specifically, the drain terminal of the first HEMT 104 is electrically coupled to the input terminal (VIN), and the source terminal of the first HEMT 104 is electrically coupled to the switch terminal (VSW). The second HEMT 106 and the diode 108 are electrically coupled between the switch terminal (VSW) and a ground terminal. More specifically, the drain terminal of the second HEMT 106 and the cathode of the diode 108 are electrically coupled to the switch terminal (VSW), and the source terminal of the second HEMT 106 and the anode of the diode 108 are electrically coupled to the ground terminal. The gate terminals of the first and second HEMTs 104, 106 are electrically coupled to respective control terminals of the gate driver circuit 102.

[0056] A first terminal of inductor 112 is electrically coupled to the switch terminal (VSW). A second terminal of inductor 112 is electrically coupled to respective first terminals of capacitor 114 and resistor 116. Respective second terminals of capacitor 114 and resistor 116 are electrically coupled to a ground terminal. Capacitor 114 and resistor 116 are electrically coupled in parallel.

[0057] Figure 1BFIG1 is a circuit schematic diagram of a circuit 130 including a semiconductor device according to some examples. Circuit 130 is an example startup circuit. Circuit 130 can be implemented as an IC on a single die or chip, and can further be included on an SoC. Circuit 130 includes a first HEMT 132, a second HEMT 134, a third HEMT 136, and a comparator 138. Circuit 130 further includes a first capacitor 142, a second capacitor 144, a first resistor 146, a second resistor 148, a third resistor 150, and a fourth resistor 152. The HEMTs in first HEMT 132 and comparator 138 may be D-mode HEMTs and may have different threshold voltages. For example, the magnitude of the threshold voltage (e.g., a negative voltage) of first HEMT 132 may be greater than the magnitude of the threshold voltage (e.g., a negative voltage) of the HEMT in comparator 138. Second HEMT 134 and third HEMT 136 may be E-mode HEMTs. By integrating these devices on a single die / chip, parasitic effects may be reduced and the overall size of the circuit 130 may also be reduced.

[0058] The first HEMT 132 is electrically coupled to the power terminal (V DD ) and the clamp terminal (V CLAMP More specifically, the source terminal of the first HEMT 132 is electrically coupled to the power terminal (V DD ), and the drain terminal of the first HEMT 132 is electrically coupled to the clamping terminal (V CLAMP ). In addition, the first terminal of the first capacitor 142 is electrically coupled to the power terminal (V DD ), and a second terminal of the first capacitor 142 and a gate terminal of the first HEMT 132 are electrically coupled to the ground terminal.

[0059] A first terminal of the first resistor 146 and a source terminal of the second HEMT 134 are electrically coupled to the clamp terminal (V CLAMP ). The second terminal of the first resistor 146 and the gate terminal of the second HEMT 134 are electrically coupled to the drain terminal of the third HEMT 136. The source terminal of the third HEMT 136 is electrically coupled to the ground terminal.

[0060] The drain terminal of the second HEMT 134 is electrically coupled to respective first terminals of the second capacitor 144 and the second resistor 148. The second terminal of the second resistor 148 is electrically coupled to the positive (+) input terminal of the comparator 138 (which serves as the input terminal (V IN ) and respective first terminals of the third resistor 150 and the fourth resistor 152. Respective second terminals of the second capacitor 144 and the third resistor 150 are electrically coupled to the ground terminal. A second terminal of the fourth resistor 152 is electrically coupled to the output terminal (VO ) and the gate terminal of the third HEMT 136. The negative (-) input terminal of the comparator 138 is a reference voltage (V REF ) terminal.

[0061] The comparator 138 includes a fourth HEMT 160, a fifth HEMT 162, a sixth HEMT 164, a seventh HEMT 166, and an eighth HEMT 168. The HEMTs 160-168 in the comparator 138 may be Dmode HEMTs and may have a different threshold voltage than the first HEMT 132. The source terminal of the fourth HEMT 160 is electrically coupled to the power terminal (V DD ), and the gate terminal and the drain terminal of the fourth HEMT 160 are electrically coupled to the output terminal (V O The source terminal of the fifth HEMT 162 is electrically coupled to the output terminal (V O ), and the drain terminal of the fifth HEMT 162 is electrically coupled to the internal node (V X The gate terminal of the fifth HEMT 162 is electrically coupled to the input node (V IN ). The source terminal of the sixth HEMT 164 is electrically coupled to the power terminal (V DD ), and the gate terminal and the drain terminal of the sixth HEMT 164 are electrically coupled to the source terminal of the seventh HEMT 166. The drain terminal of the seventh HEMT 166 is electrically coupled to the internal node (V X ), and the gate terminal of the seventh HEMT 166 is electrically coupled to the reference voltage terminal (V REF ).

[0062] Various examples contemplate circuits implemented on a single die or chip (e.g., on the same semiconductor substrate) that include semiconductor devices of the same Emode or Dmode type but with different threshold voltages. The circuits 100 and 130 described above are merely example circuits that can be implemented on a single die or chip in which semiconductor devices of the same type (e.g., Emode or Dmode) (e.g., HEMT) have different threshold voltages. Furthermore, one or more semiconductor devices of different types (e.g., Emode or Dmode) can be included in the circuit. Other circuits can be implemented according to various examples.

[0063] Examples of various semiconductor devices are provided in the descriptions of the following figures. Some semiconductor devices may be described as being rated for high voltage or low voltage applications. The high or low voltage rating of a semiconductor device does not indicate a high or low threshold voltage of the semiconductor device. A semiconductor device rated for high voltage applications may have a low threshold voltage magnitude. Conversely, a semiconductor device rated for low voltage applications may have a high threshold voltage magnitude. Any combination of a high or low voltage rating may be implemented with a high or low threshold voltage.

[0064] Figure 2 、 3 , 4, 5, 6, 7, 8, and 9 show cross-sectional views of corresponding ICs. Components described with respect to a figure may be common to other figures. Such components are indicated by similar reference numerals in the figures, and for the sake of brevity, the description of such components in subsequent figures may be omitted. In addition, changes between components in different figures may cause certain changes to the components common to those figures. In some cases, for the sake of brevity, the description of such changes may be omitted; however, such changes may be obvious in the figures and do not change the general nature of the components described.

[0065] Figure 2A cross-sectional view of an IC 200 according to some examples is shown. In this example, IC 200 includes a first semiconductor device 202, a second semiconductor device 204, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. In the illustrated example, the first semiconductor device 202, the second semiconductor device 204, and the third semiconductor device 206 are each E-mode HEMTs. The fourth semiconductor device 208 is a diode-connected E-mode HEMT. The fifth semiconductor device 210, the sixth semiconductor device 212, and the seventh semiconductor device 214 are each D-mode HEMTs. More specifically, in some examples, the first semiconductor device 202 may be an E-mode HEMT rated for high-voltage applications (e.g., due in part to a larger lateral distance between the drain and gate). The second semiconductor device 204 may be an E-mode HEMT rated for low-voltage applications (e.g., due in part to a smaller lateral distance between the drain and gate). The low voltage rating is lower than the high voltage rating. The third semiconductor device 206 may be an E-mode HEMT rated for low-voltage applications and may be an analog HEMT. The fourth semiconductor device 208 may be an E-mode HEMT connected in a diode-connected configuration. The fifth semiconductor device 210 may be a D-mode MIS-HEMT rated for high-voltage applications. The sixth semiconductor device 212 may be a D-mode MIS-HEMT rated for low-voltage applications. The seventh semiconductor device 214 may be a D-mode HEMT. Other semiconductor devices may be included in addition to or in place of the illustrated devices. Some examples contemplate that a subset of the illustrated devices may be included in an IC. The illustrated devices are shown for ease of describing various aspects.

[0066] In some examples, the respective magnitudes of the threshold voltages of first semiconductor device 202 and second semiconductor device 204 are greater than each of the magnitudes of the respective threshold voltages of third semiconductor device 206 and fourth semiconductor device 208. As described later, different threshold voltages can be achieved by different thicknesses of the gate layers of the respective semiconductor devices.

[0067] In some examples, the magnitude of the threshold voltage of fifth semiconductor device 210 is smaller than the magnitude of the threshold voltage of sixth semiconductor device 212. As described later, different threshold voltages can be achieved by different thicknesses and / or dielectric constants of the gate insulator layer between the corresponding gate terminals and the channel region.

[0068] Figure 2Shown are a semiconductor substrate 222 and one or more transition layers 224 above and on semiconductor substrate 222. A channel layer 226 is above and on an uppermost transition layer 224. A barrier layer 228 is above and on channel layer 226. In some examples, semiconductor substrate 222, transition layers 224, channel layer 226, and barrier layer 228 can be collectively considered a semiconductor substrate.

[0069] The semiconductor substrate 222 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other suitable substrate. For example, the semiconductor substrate 222 may be or include a bulk silicon wafer. The transition layer 224 may include any number of layers of any material configured to accommodate the lattice mismatch between the semiconductor substrate 222 and the channel layer 226 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 226). For example, the transition layer 224 may have a gradient concentration of one or more elements in a direction perpendicular to the upper surface of the semiconductor substrate 222. Furthermore, one of the transition layers 224 may be a doped buffer layer.

[0070] The channel layer 226 is configured to conduct and confine charge carriers (e.g., electrons) in two dimensions, potentially in conjunction with the barrier layer 228. In some examples, the channel layer 226 is configured to contain a two-dimensional electron gas (2DEG), in various examples. The 2DEG can be formed by band bending caused by the barrier layer 228 above and on the channel layer 226. In some examples, the channel layer 226 can be part of a semiconductor substrate (e.g., without a transition layer), and / or the semiconductor substrate 222 with the transition layer 224 and the channel layer 226 can be considered a semiconductor substrate. In some examples, the channel layer 226 includes a gallium nitride (GaN) layer and, in such examples, can be referred to as a GaN channel layer. In some examples, the material of the channel layer 226 is or includes an unintentionally doped material, such as a material doped by diffusion of dopants from another layer, or is or includes an intrinsic material. In some examples, the barrier layer 228 can be or include an aluminum gallium nitride (AlGaN) layer and, in such examples, can be referred to as an AlGaN barrier layer. In some examples, the channel layer 226 may be or include Indium Aluminum Gallium Nitride (InGaN). i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1), and the barrier layer 228 may be or include indium aluminum gallium nitride (InGaN). k Al l Ga 1-k-l N) (wherein 0≤k≤1, 0≤l≤1, and 0≤k+l≤1). Other materials may be implemented for the channel layer 226 and / or the barrier layer 228.

[0071] Isolation structure 230 extends through barrier layer 228 and channel layer 226 into transition layer 224. Isolation structure 230 may be or include shallow trench isolation (STI), deep trench isolation (DTI), a doped region, an implanted region (e.g., undoped to amorphize), or other isolation structures. Isolation structure 230 is laterally positioned between adjacent semiconductor devices 204-214 and may provide electrical isolation between semiconductor devices 204-214. Other isolation techniques that may be implemented are described below.

[0072] Gate layers 232a, 232b, 232c, 232d are above and on the upper surface of barrier layer 228. In some examples, gate layers 232a, 232b, 232c, 232d are or include semiconductor layers of a semiconductor material. Furthermore, in some examples, gate layers 232a-232d are doped with a dopant. In some examples, gate layers 232a-232d are doped with a p-type dopant. In some examples, gate layers 232a-232d may be or include gallium nitride (GaN) layers, such as indium aluminum gallium nitride (InGaN). m Al n Ga 1-m-n N) (where 0≤m<1, 0≤n<1, and 0≤m+n≤1), and the dopant doped with the gate layers 232a-232d is a p-type dopant, which may be or include magnesium (Mg), carbon (C), zinc (Zn), etc., or a combination thereof. In an example where the gate layers 232a-232d are gallium nitride (GaN) doped with a p-type dopant, the gate layer 232 may be referred to as a p-doped GaN (pGaN) layer. In addition, in an example where the gate layers 232a-232d are gallium nitride (GaN) doped with magnesium, the gate layers 232a-232d may be referred to as magnesium-doped gallium nitride (GaN:Mg) layers. In some examples, the dopant concentration in the electrically active gate layers 232a-232d is equal to or greater than 1×10 17 cm -3 In some examples, the concentration is equal to or greater than 1×10 18 cm -3 In some examples, the dopant in gate layers 232a-232d may have a uniform concentration, which may be equal or different between gate layers 232a-232d. In some examples, the dopant in gate layers 232a-232d may have a gradient concentration, which may be the same or different between gate layers 232a-232d. Other materials, dopants, and / or concentrations may be implemented in other examples.

[0073] Implant layer 234 is above and on the upper surface of barrier layer 228. Implant layer 234 can be or include the same material as gate layers 232a-232d, including being similarly doped as one or more of gate layers 232a-232d.

[0074] A first dielectric layer 236 is disposed above and on the upper surface of barrier layer 228, on and along the sidewalls of gate layers 232a-232b, and above and on the upper surfaces of gate layers 232a, 232b and implant layer 234. In some examples, first dielectric layer 236 may be or include silicon oxide, silicon nitride, or the like. A second dielectric layer 238 is disposed above and on first dielectric layer 236 within the region of fifth semiconductor device 210. The material of second dielectric layer 238 is different from the material of first dielectric layer 236. The dielectric constant of second dielectric layer 238 may be different from the dielectric constant of first dielectric layer 236. In some examples, second dielectric layer 238 may be or include silicon nitride, or the like.

[0075] Third dielectric layer 240 may be a pre-metal dielectric layer (PMD) that is above and on first dielectric layer 236 and second dielectric layer 238. In some examples, third dielectric layer 240 is or includes silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), or aluminum oxide (Al2O3), but in other examples, third dielectric layer 240 may be or include one or more other dielectric materials.

[0076] Drain metal contacts 242a, 242b, 242c, 242d, 242e, 242f, 242g and source metal contacts 244a, 244b, 244c, 244d, 244e, 244f, 244g pass through the third dielectric layer 240 and the first dielectric layer 236 and contact the barrier layer 228. In some examples, the metal contacts 242a-242g, 244a-244g may extend into the barrier layer 228. In yet other examples, the metal contacts 242a-242g, 244a-244g may pass through the barrier layer 228 and contact the channel layer 226. The metal contacts 242a-242g, 244a-244g may be or include a metal such as titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), etc., or a combination thereof.

[0077] A fourth dielectric layer 246 is disposed above and over the third dielectric layer 240 and the metal contacts 242a-242g, 244a-244g. In some examples, the fourth dielectric layer 246 is or includes a nitride, such as silicon nitride (SiN), but in other examples, the fourth dielectric layer 246 may be or include one or more other dielectric materials.

[0078] Gate metal contacts 248a, 248b, 248c, 248d, 248e, 248f, and 248g, and implant metal contact 250, pass through fourth dielectric layer 246 and third dielectric layer 240. Gate metal contact 248a also passes through first dielectric layer 236 and contacts gate layer 232a. Implant metal contact 250 also passes through first dielectric layer 236 and contacts implant layer 234. Gate metal contact 248b also passes through first dielectric layer 236 and contacts gate layer 232b. Gate metal contact 248c contacts gate layer 232c. Gate metal contact 248d contacts gate layer 232d. Gate metal contact 248e contacts second dielectric layer 238. Gate metal contact 248f contacts first dielectric layer 236. Gate metal contact 248g also passes through first dielectric layer 236 and contacts barrier layer 228. As shown, the metal contacts 248a-248g, 250 may be a layer conformally following a surface defining the respective openings in which the metal contacts 248a-248g, 250 are formed. In other examples, the metal contacts 248a-248g, 250 may fill the openings in which the metal contacts 248a-248g, 250 are formed.

[0079] Metal contacts 248a-248g, 250 may include or be any suitable metal. In some semiconductor devices, the gate metal contact may form a Schottky junction with the gate layer. By way of example, when the gate layer is magnesium-doped gallium nitride (GaN:Mg), the metal that may form a Schottky junction with the gate layer may be or include titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), or alloys thereof. By way of example, when the gate layer is magnesium-doped gallium nitride (GaN:Mg), the metal that may form an ohmic junction with the gate layer may be or include gold (Au), aluminum (Al), or alloys thereof, such alloys including titanium tungsten aluminum (TiWAl) and titanium aluminum nitride (TiAlN).

[0080] A fifth dielectric layer 252, which may be an interlayer dielectric layer (ILD), is disposed above and on the fourth dielectric layer 246 and the metal contacts 248a-248g, 250. The fifth dielectric layer 252 may be a single dielectric layer or may include multiple dielectric layers of the same dielectric material or different dielectric materials. For example, the fifth dielectric layer 252 may include silicon nitride, a silicon oxide-based material (e.g., phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide), polytetrafluoroethylene, and the like.

[0081] Metal vias 254a through 254v penetrate the fifth dielectric layer 252. Metal via 254a also penetrates the fourth dielectric layer 246 and contacts the drain metal contact 242a. Metal via 254b contacts the implant metal contact 250. Metal via 254c contacts the gate metal contact 248a. Metal via 254d also penetrates the fourth dielectric layer 246 and contacts the source metal contact 244a. Metal via 254e also penetrates the fourth dielectric layer 246 and contacts the drain metal contact 242b. Metal via 254f contacts the gate metal contact 248b. Metal via 254g also penetrates the fourth dielectric layer 246 and contacts the source metal contact 244b. Metal via 254h also penetrates the fourth dielectric layer 246 and contacts the drain metal contact 242c. Metal via 254i contacts the gate metal contact 248c. Metal via 254j also passes through the fourth dielectric layer 246 and contacts the source metal contact 244c. Metal via 254k also passes through the fourth dielectric layer 246 and contacts the drain metal contact 242d. Metal via 254l contacts the gate metal contact 248d. Metal via 254m also passes through the fourth dielectric layer 246 and contacts the source metal contact 244d. Metal via 254n also passes through the fourth dielectric layer 246 and contacts the drain metal contact 242e. Metal via 254o contacts the gate metal contact 248e. Metal via 254p also passes through the fourth dielectric layer 246 and contacts the source metal contact 244e. Metal via 254q also passes through the fourth dielectric layer 246 and contacts the drain metal contact 242f. Metal via 254r contacts the gate metal contact 248f. Metal via 254s also passes through the fourth dielectric layer 246 and contacts the source metal contact 244f. Metal via 254t also passes through the fourth dielectric layer 246 and contacts the drain metal contact 242g. Metal via 254u contacts the gate metal contact 248g. Metal via 254v also passes through the fourth dielectric layer 246 and contacts the source metal contact 244g.

[0082] Metal lines 256a through 256t are above and on fifth dielectric layer 252. Metal line 256a is also above and on (and electrically coupled to) metal vias 254a and 254b. Metal lines 256b-256j are also above and on (and electrically coupled to) metal vias 254c-254k, respectively. Metal line 256k is also above and on (and electrically coupled to) metal vias 254l and 254m. Metal lines 256l-256t are also above and on (and electrically coupled to) metal vias 254n-254v, respectively. Each of metal vias 254a-254v may include: (i) one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) conformally located in corresponding openings through fifth dielectric layer 252 and, if applicable, fourth dielectric layer 246, and (ii) a filler metal (e.g., aluminum (Al), copper (Cu), tungsten (W), etc., or a combination thereof) above and / or on the metal-barrier and / or adhesion layers. Each of metal lines 256a-256t may include one or more metal-barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) and bulk metal (e.g., aluminum (Al), copper (Cu), etc., or a combination thereof) above and / or on the metal-barrier and / or adhesion layers. In some examples, some of metal lines 256a-256t may implement or include corresponding field plates for semiconductor device electric field management.

[0083] The first semiconductor device 202 includes a first source terminal Sa, a first channel region Ca, a first drain terminal Da, and a first gate terminal Ga. The first gate terminal Ga is or includes a gate layer 232a. The first channel region Ca is located in the channel layer 226 below the first gate terminal Ga. The first channel region Ca is laterally located between the first drain terminal Da and the first source terminal Sa, both located in the channel layer 226. The drain metal contact 242a is electrically coupled to the first drain terminal Da, and the source metal contact 244a is electrically coupled to the first source terminal Sa. The gate metal contact 248a is electrically coupled to the first gate terminal Ga (e.g., the gate layer 232a). The first gate terminal Ga and the gate metal contact 248a are laterally located between the drain metal contact 242a and the source metal contact 244a. In addition, the injection layer 234 is laterally located between the gate layer 232a and the drain metal contact 242a. The implant layer 234 is electrically coupled to the drain metal contact 242a through the implant metal contact 250, metal vias 254a, 254b, and metal line 256a. The implant layer 234 electrically coupled to the drain metal contact 242a forms a hybrid drain.

[0084] The second semiconductor device 204 includes a second source terminal Sb, a second channel region Cb, a second drain terminal Db, and a second gate terminal Gb. The second gate terminal Gb is or includes a gate layer 232b. The second channel region Cb underlies the second gate terminal Gb in the channel layer 226. The second channel region Cb is laterally located between the second drain terminal Db and the second source terminal Sb, also in the channel layer 226. The drain metal contact 242b is electrically coupled to the second drain terminal Db, and the source metal contact 244b is electrically coupled to the second source terminal Sb. The gate metal contact 248b is electrically coupled to the second gate terminal Gb (e.g., the gate layer 232b). The second gate terminal Gb and the gate metal contact 248b are laterally located between the drain metal contact 242b and the source metal contact 244b.

[0085] The third semiconductor device 206 includes a third source terminal Sc, a third channel region Cc, a third drain terminal Dc, and a third gate terminal Gc. The third gate terminal Gc is or includes a gate layer 232c. The third channel region Cc underlies the third gate terminal Gc in the channel layer 226. The third channel region Cc is laterally located between the third drain terminal Dc and the third source terminal Sc, both also in the channel layer 226. A drain metal contact 242c is electrically coupled to the third drain terminal Dc, and a source metal contact 244c is electrically coupled to the third source terminal Sc. A gate metal contact 248c is electrically coupled to the third gate terminal Gc (e.g., gate layer 232c). The third gate terminal Gc and the gate metal contact 248c are laterally located between the drain metal contact 242c and the source metal contact 244c.

[0086] The fourth semiconductor device 208 includes a fourth source terminal Sd, a fourth channel region Cd, a fourth drain terminal Dd, and a fourth gate terminal Gd. The fourth gate terminal Gd is or includes a gate layer 232d. The fourth channel region Cd underlies the fourth gate terminal Gd in the channel layer 226. The fourth channel region Cd is laterally located between the fourth drain terminal Dd and the fourth source terminal Sd, both located in the channel layer 226. A drain metal contact 242d is electrically coupled to the fourth drain terminal Dd, and a source metal contact 244d is electrically coupled to the fourth source terminal Sd. A gate metal contact 248d is electrically coupled to the fourth gate terminal Gd (e.g., gate layer 232d). The fourth gate terminal Gd and the gate metal contact 248d are laterally located between the drain metal contact 242d and the source metal contact 244d. The fourth gate terminal Gd is electrically coupled to the fourth source terminal Sd through the gate metal contact 248d, metal vias 2541, 254m, metal line 256k, and source metal contact 244d. Thus, the fourth semiconductor device 208 is electrically connected in a diode-connected configuration.

[0087] The fifth semiconductor device 210 includes a fifth source terminal Se, a fifth channel region Ce, a fifth drain terminal De, and a fifth gate terminal Ge. The fifth gate terminal Ge is or includes a gate metal contact 248e. The fifth channel region Ce underlies the fifth gate terminal Ge in the channel layer 226. A gate insulator or gate dielectric layer (e.g., first dielectric layer 236 and second dielectric layer 238) is vertically located between the fifth gate terminal Ge (e.g., gate metal contact 248e) and the fifth channel region Ce, and more specifically, between the gate metal contact 248e and the barrier layer 228. The fifth channel region Ce is laterally located between a fifth drain terminal De and a fifth source terminal Se, also in the channel layer 226. The drain metal contact 242e is electrically coupled to the fifth drain terminal De, and the source metal contact 244e is electrically coupled to the fifth source terminal Se. A fifth gate terminal Ge (eg, gate metal contact 248e) is laterally located between the drain metal contact 242e and the source metal contact 244e.

[0088] The sixth semiconductor device 212 includes a sixth source terminal Sf, a sixth channel region Cf, a sixth drain terminal Df, and a sixth gate terminal Gf. The sixth gate terminal Gf is or includes a gate metal contact 248f. The sixth channel region Cf underlies the sixth gate terminal Gf in the channel layer 226. A gate insulator or gate dielectric layer (e.g., first dielectric layer 236) is vertically located between the sixth gate terminal Gf (e.g., gate metal contact 248f) and the sixth channel region Cf, and more specifically, between the gate metal contact 248f and the barrier layer 228. The sixth channel region Cf is laterally located between a sixth drain terminal Df and a sixth source terminal Sf, also in the channel layer 226. The drain metal contact 242f is electrically coupled to the sixth drain terminal Df, and the source metal contact 244f is electrically coupled to the sixth source terminal Sf. A sixth gate terminal Gf (eg, gate metal contact 248f) is laterally located between the drain metal contact 242f and the source metal contact 244f.

[0089] The seventh semiconductor device 214 includes a seventh source terminal Sg, a seventh channel region Cg, a seventh drain terminal Dg, and a seventh gate terminal Gg. The seventh gate terminal Gg is or includes a gate metal contact 248g. The seventh channel region Cg underlies the seventh gate terminal Gg in the channel layer 226. The seventh channel region Cg is laterally located between the seventh drain terminal Dg and the seventh source terminal Sg, also in the channel layer 226. The drain metal contact 242g is electrically coupled to the seventh drain terminal Dg, and the source metal contact 244g is electrically coupled to the seventh source terminal Sg. The seventh gate terminal Gg (e.g., gate metal contact 248g) is laterally located between the drain metal contact 242g and the source metal contact 244g.

[0090] The gate layer 232a of the first semiconductor device 202 has a thickness / height 260a (e.g., in a direction perpendicular to the upper surface of the barrier layer 228 and between the upper surface of the barrier layer 228 and the metal contact 248a). The gate layer 232b of the second semiconductor device 204 has a thickness 260b (e.g., between the upper surface of the barrier layer 228 and the metal contact 248b). Thickness 260b may be equal to thickness 260a. The gate layer 232c of the third semiconductor device 206 has a thickness 260c (e.g., between the upper surface of the barrier layer 228 and the metal contact 248c). The gate layer 232d of the fourth semiconductor device 208 has a thickness 260d. Thickness 260d may be equal to thickness 260c. Thickness 260a and thickness 260b are each greater than thickness 260c and thickness 260d.

[0091] The difference in thickness causes the magnitude of the threshold voltage of the first semiconductor device 202 to be different from (e.g., greater than) each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The difference in thickness / height causes the magnitude of the threshold voltage of the second semiconductor device 204 to be greater than each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The threshold voltages of the first semiconductor device 202 and the second semiconductor device 204 can be equal, and the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208 can be equal. The threshold voltages of the semiconductor devices 202-208 can be positive voltages.

[0092] The gate insulator or gate dielectric layer (e.g., first dielectric layer 236 and second dielectric layer 238) of the fifth semiconductor device 210 has a thickness / height 262e (e.g., in a direction perpendicular to the upper surface of the barrier layer 228 and between the upper surface of the barrier layer 228 and the metal contact 248e). The gate insulator (e.g., first dielectric layer 236) of the sixth semiconductor device 212 has a thickness 262f (e.g., between the upper surface of the barrier layer 228 and the metal contact 248f). Thickness 262f is less than thickness 262e. The seventh semiconductor device 214 does not include a gate insulator or gate dielectric layer between the seventh gate terminal Gg and the seventh channel region Cg.

[0093] The difference in effective gate-to-channel capacitance causes the magnitude of the threshold voltage of the fifth semiconductor device 210 to be greater than each of the corresponding magnitudes of the threshold voltages of the sixth semiconductor device 212 and the seventh semiconductor device 214. The difference in effective gate-to-channel capacitance causes the magnitude of the threshold voltage of the sixth semiconductor device 212 to be greater than the magnitude of the threshold voltage of the seventh semiconductor device 214. The difference in effective gate-to-channel capacitance can be achieved by differences in the thickness and / or absence of gate insulators or gate dielectric layers and / or differences in the effective dielectric constants of the gate insulators or gate dielectric layers. The threshold voltages of the semiconductor devices 210-214 can be negative voltages.

[0094] Figure 3 FIG3 shows a cross-sectional view of an IC 300 according to some examples. In this example, the IC 300 includes a first semiconductor device 202, a second semiconductor device 204, a third semiconductor device 306, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 202, 204, 208, 210, 212, 214 are as described above with respect to FIG3 . Figure 2 As described. Figure 3 In the example shown, the third semiconductor device 306 is a two-terminal diode. Other semiconductor devices may be included in addition to or in place of the devices shown. Some examples contemplate that a subset of the devices shown may be included in an IC. The devices shown are shown for ease of describing various aspects.

[0095] Anode layer 332c is above and on the upper surface of barrier layer 228. Anode layer 332c may have a structure and / or material similar to gate layer 232c described above. Cathode metal contact 342c passes through third dielectric layer 240 and first dielectric layer 236 and contacts barrier layer 228. Cathode metal contact 342c may have a structure and / or material similar to drain metal contact 242c described above. Anode metal contact 348c passes through fourth dielectric layer 246 and third dielectric layer 240. Anode metal contact 348c contacts anode layer 332c. Anode metal contact 348c may have a structure and / or material similar to gate metal contact 248c described above. Anode metal contact 348c may form an ohmic junction with anode layer 332c.

[0096] The third semiconductor device 306 includes a cathode terminal Hc and an anode terminal Ac. The anode terminal Ac is or includes an anode layer 332c. The cathode terminal Hc is laterally spaced apart from the anode terminal Ac in the channel layer 226. The cathode metal contact 342c is electrically coupled to the cathode terminal Hc. The anode metal contact 348c is electrically coupled to the anode terminal Ac (e.g., the anode layer 332c).

[0097] Anode layer 332c of third semiconductor device 306 has thickness 360c. Thickness 260d (of gate layer 232d) can be equal to thickness 360c (e.g., between the upper surface of barrier layer 228 and metal contact 348c). Thickness 260a (of gate layer 232a) and thickness 260b (of gate layer 232b) are each greater than thickness 360c. This difference in thickness causes the magnitude of the threshold voltages of first and second semiconductor devices 202 to be greater than the magnitude of the threshold voltage of third semiconductor device 306. The threshold voltages of third and fourth semiconductor devices 306 and 208 can be equal. The threshold voltages of semiconductor devices 202, 204, 306, and 208 can be positive voltages.

[0098] Although not shown in subsequent figures, the third semiconductor device 306 may be included in other example ICs. The third semiconductor device 306 may be included in addition to or instead of other semiconductor devices described with respect to various examples.

[0099] Figure 4 FIG4 shows a cross-sectional view of an IC 400 according to some examples. In this example, the IC 400 includes a first semiconductor device 402, a second semiconductor device 404, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 206, 208, 210, 212, 214 are as described above with respect to FIG4. Figure 2 As described. In the illustrated example, the first semiconductor device 402 and the second semiconductor device 404 are each an E-mode HEMT. More specifically, in some examples, the first semiconductor device 402 may be an E-mode HEMT rated for high voltage applications and may be a power HEMT. The second semiconductor device 404 may be an E-mode HEMT rated for low voltage applications and may be a power HEMT. Other semiconductor devices may be included in addition to or in place of the illustrated devices. Some examples contemplate that a subset of the illustrated devices may be included in an IC. The illustrated devices are shown for ease of describing various aspects.

[0100] In some examples, the respective magnitudes of the threshold voltages of the first semiconductor device 402 and the second semiconductor device 404 are greater than the magnitudes of the respective threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. As described later, the different threshold voltages can be achieved by different thicknesses of the barrier layers of the semiconductor devices. Although described in the context of the first semiconductor device 402 and the second semiconductor device 404 compared to the third semiconductor device 206 and the fourth semiconductor device 208, at least one of the fifth semiconductor device 210, the sixth semiconductor device 212, and the seventh semiconductor device 214 can also have a different threshold voltage than another of the fifth semiconductor device 210, the sixth semiconductor device 212, and the seventh semiconductor device 214 due to different thicknesses of the barrier layers of the respective semiconductor devices.

[0101] A barrier layer 428 is located above and on the channel layer 226. Gate recesses 422a and 422b are located within barrier layer 428. Barrier layer 428 may be the material described above with respect to barrier layer 228. Gate layers 432a and 432b are at least partially located within gate recesses 422a and 422b, respectively, and may also be partially located above and on the upper surface of barrier layer 428. An implant layer 434 is located above and on the upper surface of barrier layer 428. Gate layers 432a and 432b may be the materials described above with respect to gate layers 232a and 232b. Similarly, implant layer 434 may be the material described above with respect to implant layer 234.

[0102] The first semiconductor device 402 includes a first source terminal Sa, a first channel region Ca, a first drain terminal Da, and a first gate terminal Ga. The first gate terminal Ga is or includes a gate layer 432a. The first channel region Ca is located in the channel layer 226 below the first gate terminal Ga and below the gate recess 422a in which the gate layer 432a is at least partially disposed. The first channel region Ca is laterally located between the first drain terminal Da and the first source terminal Sa, also in the channel layer 226. The metal contacts 242a, 244a, 248a are similar to those described above with respect to Figure 2 In addition, the injection layer 434 is laterally located between the gate layer 432a and the drain metal contact 242a. The injection layer 434 is electrically coupled in a manner similar to that described above with respect to Figure 2 The described manner is electrically coupled to the drain metal contact 242a. The implantation layer 434 electrically coupled to the drain metal contact 242a forms a hybrid drain.

[0103] The second semiconductor device 404 includes a second source terminal Sb, a second channel region Cb, a second drain terminal Db, and a second gate terminal Gb. The second gate terminal Gb is or includes a gate layer 432b. The second channel region Cb is located in the channel layer 226 below the second gate terminal Gb and below the gate recess 422b in which the gate layer 432b is at least partially disposed. The second channel region Cb is laterally located between the second drain terminal Db and the second source terminal Sb, also in the channel layer 226. The metal contacts 242b, 244b, and 248b are arranged in a manner similar to that described above with respect to the embodiment of the present invention. Figure 2 Electrical coupling as described.

[0104] The barrier layer 428 in the first semiconductor device 402 has a thickness 460a (e.g., in a direction perpendicular to the upper surface of the barrier layer 428) at the gate recess 422a (e.g., from the bottom surface of the gate recess 422a to the bottom surface of the barrier layer 428, and between the gate layer 432a and the channel layer 226). The barrier layer 428 in the second semiconductor device 404 has a thickness 460b at the gate recess 422b (e.g., between the gate layer 432b and the channel layer 226). Thickness 460b may be equal to thickness 460a. The barrier layer 428 in the third semiconductor device 206 has a thickness 460c (e.g., between the gate layer 232c and the channel layer 226). The barrier layer 428 in the fourth semiconductor device 208 has a thickness 460d (e.g., between the gate layer 232d and the channel layer 226). Thickness 460d may be equal to thickness 460c. Thickness 460a and thickness 460b are each smaller than each of thickness 460c and thickness 460d.

[0105] The thickness difference causes the magnitude of the threshold voltage of the first semiconductor device 402 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The thickness difference causes the magnitude of the threshold voltage of the second semiconductor device 404 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The threshold voltages of the first semiconductor device 402 and the second semiconductor device 404 may be equal, and the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208 may be equal. The threshold voltages of the semiconductor devices 202-208 may be positive voltages.

[0106] Figure 5FIG5 shows a cross-sectional view of an IC 500 according to some examples. In this example, the IC 500 includes a first semiconductor device 502, a second semiconductor device 404, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 404, 206, 208, 210, 212, 214 are as described above with respect to FIG5 . Figure 2 and 4 As described. In the illustrated example, the first semiconductor device 402 is an E-mode HEMT. More specifically, in some examples, the first semiconductor device 402 may be an E-mode HEMT rated for high voltage applications and may be a power HEMT. Other semiconductor devices may be included in addition to or in place of the illustrated device. Some examples contemplate that a subset of the illustrated devices may be included in an IC. The illustrated device is shown for ease of describing various aspects.

[0107] In some examples, the respective magnitudes of the threshold voltages of first semiconductor device 502 and second semiconductor device 404 are greater than each of the magnitudes of the respective threshold voltages of third semiconductor device 206 and fourth semiconductor device 208. As previously described, the different threshold voltages can be achieved by different thicknesses of the barrier layers of the semiconductor devices.

[0108] The barrier layer 528 is above and on the channel layer 226. The barrier layer 528 is similar to Figure 4 4. The barrier layer 428 is formed in the barrier layer 428 and has an implantation recess 524 therein. The implantation layer 534 is at least partially in the implantation recess 524 and may further be partially above and on the upper surface of the barrier layer 428. The implantation layer 534 may be the material described above with respect to the implantation layer 234.

[0109] The first semiconductor device 502 includes a first source terminal Sa, a first channel region Ca, a first drain terminal Da, and a first gate terminal Ga. The first gate terminal Ga is or includes a gate layer 432a. The first channel region Ca is located in the channel layer 226 below the first gate terminal Ga and below the gate recess 422a in which the gate layer 432a is at least partially disposed. The first channel region Ca is laterally located between the first drain terminal Da and the first source terminal Sa, also in the channel layer 226. The metal contacts 242a, 244a, 248a are arranged in a manner similar to that described above with respect to Figure 2 Furthermore, the injection layer 534 and the injection recess 524 (in which the injection layer 534 is at least partially located) are laterally located between the gate layer 432a and the drain metal contact 242a. The injection layer 534 is electrically coupled in a manner similar to that described above with respect to Figure 2The described manner is electrically coupled to the drain metal contact 242a. The implantation layer 534 electrically coupled to the drain metal contact 242a forms a hybrid drain.

[0110] refer to Figure 4 , the barrier layer 428 has a thickness 462 at the injection layer 434, and with reference to Figure 5 , the barrier layer 528 has a thickness 562 at the injection layer 434 that is less than the thickness 462. The varying thickness of the barrier layer at the injection layer, such as shown by thicknesses 462 and 562, can change the drain-to-source on-resistance (Rdson). A larger thickness, such as thickness 462, can result in a lower Rdson, while a smaller thickness, such as thickness 562, can result in a higher Rdson.

[0111] Although the subsequent figures show Figure 4 (eg, where the injection layer 434 does not have an injection recess in the barrier layer), but the various examples described and shown in the figures below may be modified to include Figure 5 A hybrid drain is shown (eg, where the implant layer 534 has an implant recess 524 in the barrier layer).

[0112] Figure 6 FIG6 shows a cross-sectional view of an IC 600 according to some examples. In this example, the IC 600 includes a first semiconductor device 402, a second semiconductor device 404, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 402, 404, 206, 208, 210, 212, 214 are as described above with respect to FIG6. Figure 2 and 4 As described. Other semiconductor devices may be included in addition to or instead of the devices shown. Some examples contemplate that a subset of the devices shown may be included in an IC. The devices shown are shown for ease of description of various aspects.

[0113] In some examples, the respective magnitudes of the threshold voltages of first semiconductor device 402 and second semiconductor device 404 are greater than each of the magnitudes of the respective threshold voltages of third semiconductor device 206 and fourth semiconductor device 208. As described later, the different threshold voltages can be achieved by different thicknesses of the barrier layers of the semiconductor devices.

[0114] The barrier layer in semiconductor devices 402, 404, 206, 208, 210, 212, and 214 includes a first blocking sublayer 612 and a second blocking sublayer 614. The first blocking sublayer 612 is above and on the channel layer 226. Openings 622a and 622b extend through the first blocking sublayer 612. The second blocking sublayer 614 is conformally above and on the first blocking sublayer 612. The second blocking sublayer 614 conformally defines the respective openings 622a and 622b in the sidewall surfaces of the first blocking sublayer 612 and the upper surface of the channel layer 226. The conformality of the second blocking sublayer 614 in the openings 622a and 622b forms gate recesses 422a and 422b, respectively. Each of the blocking sublayers 612 and 614 can be the materials described above for the blocking layer 228. As previously described, gate layers 432 a , 432 b are at least partially within gate recesses 422 a , 422 b , respectively, and may also be partially above and on an upper surface of barrier layer 228 .

[0115] The barrier layer (including the blocking sublayers 612 and 614) in the first semiconductor device 402 has a thickness 460a (e.g., in a direction perpendicular to the upper surface of the barrier layer 228) at the gate recess 422a (e.g., from the bottom surface of the gate recess 422a to the bottom surface of the barrier layer). The barrier layer (including the blocking sublayers 612 and 614) in the second semiconductor device 404 has a thickness 460b at the gate recess 422b. The barrier layer in the third semiconductor device 206 has a thickness 460c. The barrier layer in the fourth semiconductor device 208 has a thickness 460d. The thicknesses 460a, 460b, 460c, and 460d may be as described above with respect to Figure 4 As described above, the threshold voltages of the semiconductor devices 402, 404, 206, and 208 are different in magnitude, as shown in FIG. Figure 4 described.

[0116] Figure 7 A cross-sectional view of an IC 700 according to some examples is shown. In this example, the IC 700 includes a first semiconductor device 702, a second semiconductor device 704, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. In the example shown, the first semiconductor device 702 and the second semiconductor device 204 are each an Emode HEMT. More specifically, in some examples, the first semiconductor device 702 can be an Emode HEMT rated for high voltage applications and can be a power HEMT. The second semiconductor device 704 can be an Emode HEMT rated for low voltage applications and can be a power HEMT. The semiconductor devices 206, 208, 210, 212, 214 are described above with respect to FIG. Figure 2As described. Other semiconductor devices may be included in addition to or instead of the devices shown. Some examples contemplate that a subset of the devices shown may be included in an IC. The devices shown are shown for ease of description of various aspects.

[0117] In some examples, the respective magnitudes of the threshold voltages of the first semiconductor device 702 and the second semiconductor device 704 are greater than each of the magnitudes of the respective threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. As described later, the different threshold voltages can be achieved by different thicknesses of the channel layers of the semiconductor devices.

[0118] Channel layer 726 is above and on the uppermost transition layer 224. Recesses 712a and 712b are within channel layer 726. Barrier layer 728 conformally extends above and on channel layer 726. Barrier layer 728 conformally extends on the sidewalls and bottom surfaces of channel layer 726, defining the surfaces of respective recesses 712a and 712b. The conformality of barrier layer 728 within recesses 712a and 712b forms gate recesses 722a and 722b, respectively. Channel layer 726 can be the material described above for channel layer 226, and barrier layer 728 can be the material described above for barrier layer 228. Similar to what was previously described, gate layers 432a and 432b are at least partially within gate recesses 722a and 722b, respectively, and may also be partially above and on the upper surface of barrier layer 728.

[0119] The first semiconductor device 702 includes a first source terminal Sa, a first channel region Ca, a first drain terminal Da, and a first gate terminal Ga. The first gate terminal Ga is or includes the gate layer 432a. The first channel region Ca is located in the channel layer 726 below the first gate terminal Ga and below the recess 712a. The first channel region Ca is laterally located between the first drain terminal Da and the first source terminal Sa, which are also located in the channel layer 726. The metal contacts 242a, 244a, and 248a are similar to those described above with respect to Figure 2 In addition, the injection layer 434 is laterally located between the gate layer 432a and the drain metal contact 242a. The injection layer 434 is electrically coupled in a manner similar to that described above with respect to Figure 2 The implantation layer 434 electrically coupled to the drain metal contact 242a forms a hybrid drain.

[0120] The second semiconductor device 704 includes a second source terminal Sb, a second channel region Cb, a second drain terminal Db, and a second gate terminal Gb. The second gate terminal Gb is or includes the gate layer 432b. The second channel region Cb is located in the channel layer 726 below the second gate terminal Gb and below the recess 712b. The second channel region Cb is laterally located between the second drain terminal Db and the second source terminal Sb, also in the channel layer 726. The metal contacts 242b, 244b, and 248b are similar to those described above with respect to Figure 2 Electrical coupling as described.

[0121] The channel layer 726 in the first semiconductor device 702 has a thickness 764a at the recess 712a (e.g., from the bottom surface of the recess 712a to the bottom surface of the channel layer 726). The channel layer 726 in the second semiconductor device 704 has a thickness 764b at the recess 712b. Thickness 764b may be equal to thickness 764a. The channel layer 726 in the third semiconductor device 206 has a thickness 764c. The channel layer 726 in the fourth semiconductor device 208 has a thickness 764d. Thickness 764d may be equal to thickness 764c. Thickness 764a and thickness 764b are each less than thickness 764c and thickness 764d.

[0122] The thickness difference causes the magnitude of the threshold voltage of the first semiconductor device 702 to be greater than each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The thickness difference causes the magnitude of the threshold voltage of the second semiconductor device 704 to be greater than each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The threshold voltages of the first semiconductor device 702 and the second semiconductor device 704 can be equal, and the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208 can be equal. The threshold voltages of the semiconductor devices 202-208 can be positive voltages.

[0123] Figure 8 FIG2 shows a cross-sectional view of an IC 800 according to some examples. In this example, the IC 800 includes a first semiconductor device 402, a second semiconductor device 404, a third semiconductor device 806, a fourth semiconductor device 808, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 402, 404, 210, 212, 214 are as described above with respect to FIG2 . Figure 2 and 4As described. In the illustrated example, the third semiconductor device 806 is an E-mode HEMT. The fourth semiconductor device 808 is a diode-connected E-mode HEMT. More specifically, in some examples, the third semiconductor device 806 may be an E-mode HEMT rated for low-voltage applications and may be an analog HEMT. The fourth semiconductor device 808 may be an E-mode HEMT connected in a diode-connected configuration. Other semiconductor devices may be included in addition to or in place of the illustrated devices. Some examples contemplate that a subset of the illustrated devices may be included in an IC. The illustrated devices are shown for ease of describing various aspects.

[0124] In some examples, the respective magnitudes of the threshold voltages of the first semiconductor device 402 and the second semiconductor device 404 are greater than each of the magnitudes of the respective threshold voltages of the third semiconductor device 806 and the fourth semiconductor device 808. As described later, the different threshold voltages can be achieved by different lengths of the gate layers of the respective semiconductor devices.

[0125] Gate layers 832c, 832d are above and on the upper surface of barrier layer 428. Gate layers 832c, 832d may be the materials described above with respect to gate layers 232a, 232b.

[0126] The third semiconductor device 806 includes a third source terminal Sc, a third channel region Cc, a third drain terminal Dc, and a third gate terminal Gc. The third gate terminal Gc is or includes a gate layer 832c. The third channel region Cc is located in the channel layer 226 and is located laterally between the third drain terminal Dc and the third source terminal Sc, which are also located in the channel layer 226. The metal contacts 242c, 244c, and 248c are similar to those described above with respect to the embodiment of the present invention. Figure 2 Electrical coupling as described.

[0127] The fourth semiconductor device 808 includes a fourth source terminal Sd, a fourth channel region Cd, a fourth drain terminal Dd, and a fourth gate terminal Gd. The fourth gate terminal Gd is or includes a gate layer 832d. The fourth channel region Cd underlies the fourth gate terminal Gd in the channel layer 226. The fourth channel region Cd is laterally located between the fourth drain terminal Dd and the fourth source terminal Sd, also in the channel layer 226. The metal contacts 242d, 244d, and 248d are similar to those described above with respect to Figure 2 The fourth gate terminal Gd is electrically coupled to the fourth source terminal Sd through the gate metal contact 248d, metal vias 2541, 254m, metal line 256k, and source metal contact 244d. Thus, the fourth semiconductor device 808 is electrically connected in a diode-connected configuration.

[0128] The gate layer 432a of the first semiconductor device 402 has a length 866a (e.g., in a direction parallel to the drain (Da) to source (Sa) direction). The gate layer 432b of the second semiconductor device 404 has a length 866b. Length 866b may be equal to length 866a. The gate layer 832c of the third semiconductor device 806 has a length 866c. The gate layer 832d of the fourth semiconductor device 808 has a length 866d. Length 866d may be equal to length 866c. Lengths 866a and 866b are each greater than lengths 866c and 866d. Lengths 866a-866d may correspond to the respective channel lengths of the respective semiconductor devices 402, 404, 806, and 808.

[0129] The length difference causes the magnitude of the threshold voltage of the first semiconductor device 402 to be greater than each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 806 and the fourth semiconductor device 808. The length difference causes the magnitude of the threshold voltage of the second semiconductor device 404 to be greater than each of the corresponding magnitudes of the threshold voltages of the third semiconductor device 806 and the fourth semiconductor device 808. The threshold voltages of the first semiconductor device 402 and the second semiconductor device 404 may be equal, and the threshold voltages of the third semiconductor device 806 and the fourth semiconductor device 808 may be equal. The threshold voltages of the semiconductor devices 402, 404, 806, and 808 may be positive voltages.

[0130] Figure 9 900 according to some examples. In this example, the IC 900 includes a first semiconductor device 902, a second semiconductor device 904, a third semiconductor device 206, a fourth semiconductor device 208, a fifth semiconductor device 210, a sixth semiconductor device 212, and a seventh semiconductor device 214. The semiconductor devices 206, 208, 210, 212, 214 are as described above with respect to FIG. Figure 2 As described. In the illustrated example, the first semiconductor device 902 and the second semiconductor device 904 are each E-mode HEMTs. More specifically, in some examples, the first semiconductor device 902 may be an E-mode HEMT rated for high voltage applications. The second semiconductor device 904 may be an E-mode HEMT rated for low voltage applications. Other semiconductor devices may be included in addition to or in place of the illustrated devices. Some examples contemplate that a subset of the illustrated devices may be included in an IC. The illustrated devices are shown for ease of describing various aspects.

[0131] In some examples, the respective magnitudes of the threshold voltages of the first semiconductor device 902 and the second semiconductor device 904 are greater than each of the magnitudes of the respective threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. As described later, the different threshold voltages can be achieved by different offset lengths of the gate metal contacts relative to the respective gate layers of the semiconductor devices contacted by the gate metal contacts.

[0132] Gate metal contacts 948a, 948b pass through the first dielectric layer 236, the fourth dielectric layer 246, and the third dielectric layer 240. Gate metal contact 948a contacts the gate layer 432a. Gate metal contact 948b contacts the gate layer 432b. Gate metal contacts 948a, 948b may be similar to those described above with respect to Figure 2 Gate metal contacts 248a, 248b are depicted.

[0133] The first semiconductor device 902 includes a first source terminal Sa, a first channel region Ca, a first drain terminal Da, and a first gate terminal Ga. The first gate terminal Ga is or includes a gate layer 432a. The first channel region Ca is located in the channel layer 226 below the first gate terminal Ga and below the gate recess 422a in which the gate layer 432a is at least partially disposed. The first channel region Ca is laterally located between the first drain terminal Da and the first source terminal Sa, also in the channel layer 226. The metal contacts 242a, 244a are similar to those described above with respect to Figure 2 The gate metal contact 948a is electrically coupled to the first gate terminal Ga (e.g., gate layer 432a). In addition, the injection layer 434 is laterally located between the gate layer 432a and the drain metal contact 242a. The injection layer 434 is electrically coupled to the drain metal contact 242a in a manner similar to that described above. Figure 2 The described manner is electrically coupled to the drain metal contact 242a. The implantation layer 434 electrically coupled to the drain metal contact 242a forms a hybrid drain.

[0134] The second semiconductor device 904 includes a second source terminal Sb, a second channel region Cb, a second drain terminal Db, and a second gate terminal Gb. The second gate terminal Gb is or includes a gate layer 432b. The second channel region Cb is located in the channel layer 226 below the second gate terminal Gb and below the gate recess 422b in which the gate layer 432b is at least partially disposed. The second channel region Cb is laterally located between the second drain terminal Db and the second source terminal Sb, also in the channel layer 226. The metal contacts 242b, 244b are formed in a manner similar to that described above with respect to Figure 2 The gate metal contact 948b is electrically coupled to the second gate terminal Gb (eg, gate layer 432b).

[0135] The gate metal contact 948a has a length 968a (eg, parallel to the drain-to-source direction) where the gate metal contact 948a contacts the gate layer 432a of the first semiconductor device 902. The gate layer 432a has a length (in Figure 9 Not specifically identified in and similar to Figure 8 Length 866a in FIG. The length of gate layer 432a and length 968a together create a contact offset length 970a. Contact offset length 970a is the length from the outer sidewall of gate metal contact 948a to the corresponding sidewall of gate layer 432a. In the case where gate layer 432a and gate metal contact 948a are ideally aligned, contact offset length 970a may be half the difference between the length of gate layer 432a and length 968a. Furthermore, gate metal contact 948b has a length 968b where gate metal contact 948b contacts gate layer 432b of second semiconductor device 904, and the length of gate layer 432b and length 968b together create a contact offset length 970b. Length 968b may be equal to length 968a. Contact offset length 970b may be equal to contact offset length 970a.

[0136] Gate metal contact 248c has a length 968c where gate metal contact 248c contacts gate layer 232c of third semiconductor device 206, and the length of gate layer 232c and length 968c together create a contact offset length 970c. Gate metal contact 248d has a length 968d where gate metal contact 248d contacts gate layer 232d of fourth semiconductor device 208, and the length of gate layer 232d and length 968d together create a contact offset length 970d. Length 968d may be equal to length 968c. Contact offset length 970d may be equal to contact offset length 970c.

[0137] Contact offset length 970a and contact offset length 970b are each greater than each of contact offset length 970c and contact offset length 970d. Length 968a and length 968b may each be less than each of length 968c and length 968d (e.g., assuming gate layers 432a, 432b, 232c, 232d are of equal length).

[0138] The difference in contact offset lengths causes the magnitude of the threshold voltage of the first semiconductor device 902 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208, as explained above. The difference in contact offset lengths causes the magnitude of the threshold voltage of the second semiconductor device 904 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208. The threshold voltages of the first semiconductor device 902 and the second semiconductor device 904 can be equal, and the threshold voltages of the third semiconductor device 206 and the fourth semiconductor device 208 can be equal. The threshold voltages of the semiconductor devices 902, 904, 206, and 208 can be positive voltages.

[0139] As about Figure 4 The barrier layer 428 having the gate recesses 422a, 422b is described in Figure 8 and 9 In some examples, the barrier layer 228 (eg, without a gate recess) can be implemented as Figure 8 or a modification of 9. In yet other examples, the barrier layer (with the barrier sublayers 612, 614) with the gate recesses 422a, 422b may be implemented as Figure 8 or a modification of 9. In addition, in some examples, the barrier layer 728 and the channel layer 726 can be implemented as Figure 8 or a modification of 9.

[0140] In some examples, the respective magnitudes of the threshold voltages of the semiconductor devices are greater than the magnitudes of the respective threshold voltages of the other semiconductor devices, at least in part due to different dopant concentrations in the gate layers of the semiconductor devices. The different dopant concentrations can be or include different uniform concentrations in the gate layers or different gradient concentrations in the gate layers. For example, the gate layers 232a, 232b, 432a, 432b can have a first dopant concentration, while the gate layers 232c, 232d, 832c, 832d (and the anode layer 332c) can have a second dopant concentration that is different from the first dopant concentration. For example, the first dopant concentration of the gate layers 232a, 232b, 432a, 432b can be greater than the second dopant concentration of the gate layers 232c, 232d, 832c, 832d.

[0141] The difference in dopant concentration affects how much charge the gate / anode layer can provide to replenish the depleted charge in the channel at a given gate / anode voltage, and causes the magnitude of the threshold voltage of the first semiconductor device 202, 402, 502, 702, 902 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808. The difference in dopant concentration causes the magnitude of the threshold voltage of the second semiconductor device 204, 404, 704, 904 to be greater than the respective magnitudes of the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808. The threshold voltages of the first semiconductor device 202, 402, 502, 702, 902 and the second semiconductor device 204, 404, 704, 904 can be equal, and the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808 can be equal. The threshold voltages of the semiconductor devices can be positive voltages.

[0142] In some examples, the respective magnitudes of the threshold voltages of the semiconductor devices are greater than the magnitudes of the respective threshold voltages of the other semiconductor devices due, at least in part, to different metal-barrier work functions in the semiconductor devices caused by different metals of the gate metal contacts. For example, the gate metal contacts 248a, 248b, 948a, 948b can be or include a metal, and the gate metal contacts 248c, 248d and the anode metal contact 348c can be a different metal than the gate metal contacts 248a, 248b, 948a, 948b.

[0143] The difference in the metals of the gate metal contacts produces different metal-barrier work functions, resulting in the threshold voltage of the first semiconductor device 202, 402, 502, 702, 902 having a different magnitude than the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808. The difference in the metals causes the threshold voltage of the second semiconductor device 204, 404, 704, 904 to have a different magnitude than the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808. The threshold voltages of the first semiconductor device 202, 402, 502, 702, 902 and the second semiconductor device 204, 404, 704, 904 can be equal, and the threshold voltages of the third semiconductor device 206, 306, 806 and the fourth semiconductor device 208, 808 can be equal. The threshold voltages of the semiconductor devices can be positive voltages.

[0144] Figure 10 Based on some examples Figure 2 Flowchart of method 1000 of IC 200 . Figure 10The method 1000 is shown by cross-sectional views of the IC 200 at various stages of fabrication. Figures 11 to 21 shown and described in its context. Figure 10 Method 1000 in Figures 11 to 21 The context of the manufacturing Figure 2 IC 200, but Figure 10 Method 1000 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0145] refer to Figure 10 Box 1002 and Figure 11 One or more transition layers 224 are formed above and on the semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on the transition layer 224. At block 1006, a barrier layer 228 is formed above and on the channel layer 226. In some examples, the transition layer 224, the channel layer 226, and the barrier layer 228 can be formed using any suitable deposition process, which can further be an epitaxial growth process. For example, the transition layer 224, the channel layer 226, and the barrier layer 228 can each be epitaxially grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), or another epitaxial process. The materials of the semiconductor substrate 222, the transition layer 224, the channel layer 226, and the barrier layer 228 can be as previously described.

[0146] At block 1008, a gate layer 232 is formed over and on the barrier layer 228. In some examples, the gate layer 232 can be epitaxially grown, for example, by MOCVD, MBE, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer epitaxy, or another epitaxial process. The gate layer 232 can be doped in situ during deposition (e.g., epitaxial growth) or after deposition by implantation (e.g., ion implantation). After formation, the gate layer 232 has a thickness 1102. The material, any dopants, and any concentrations of the dopants for the gate layer 232 can be as previously described.

[0147] refer to Figure 10 Box 1010 and Figure 12, the gate layer 232 is patterned into the gate layers 232a, 232b, 232c, 232d and the implant layer 234. Once patterned, each of the gate layers 232a-232d and the implant layer 234 has a thickness 1102 that is approximately the same as the gate layer 232 (e.g., with a small amount of loss due to the patterning process). The gate layer 232 can be patterned using appropriate photolithography and etching processes. For example, to pattern the gate layer 232, a photoresist is deposited (e.g., by spin coating) on ​​and / or onto the semiconductor substrate 222 (e.g., on and / or onto the gate layer 232) and patterned using photolithography. The photoresist is patterned to remain in areas corresponding to the areas where the gate layers 232a-232d and the implant layer 234 will be formed. With the patterned photoresist, an etching process, such as anisotropic etching, such as reactive ion etching (RIE), etc., is performed using the patterned photoresist as a mask to pattern the gate layer 232. After the etching process, the photoresist is removed, such as by ashing.

[0148] refer to Figure 10 Box 1012 and Figure 13 A first dielectric layer 236 is conformally formed over and on the barrier layer 228, gate layers 232a-232d, and implant layer 234. The first dielectric layer 236 can be deposited using any suitable deposition process, such as LPCVD, PECVD, and the like. The material of the first dielectric layer 236 can be as described above. At block 1014, a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. The second dielectric layer 238 can be deposited using any suitable deposition process, such as LPCVD, PECVD, and the like. The material of the second dielectric layer 238 can be as described above.

[0149] refer to Figure 10 Box 1016 and Figure 14 , forming an isolation structure 230. The isolation structure 230, which is a trench isolation structure in this example, can be formed by forming a recess through the second dielectric layer 238, the first dielectric layer 236, the barrier layer 228, and the channel layer 226 into the transition layer 224. The recess can be formed using appropriate photolithography and etching processes, similar to those described above. Isolation material can be deposited in the recess, for example, by chemical vapor deposition (CVD), such as high aspect ratio CVD (HAR-CVD), flowable CVD (FCVD), etc. Any excess isolation material above the second dielectric layer 238 can be removed by selective etching of the isolation material, which can be a wet isotropic etch. In other examples, other isolation structures can be formed by other processes.

[0150] refer to Figure 10 Box 1018 and Figure 15, portions of the second dielectric layer 238 are removed from the regions where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. Additionally, corresponding portions of the second dielectric layer 238 can be removed from the regions where the semiconductor devices 202-208 will be formed, as shown. By removing the portion of the second dielectric layer 238 from the region where the sixth semiconductor device 212 will be formed and masking the portion of the second dielectric layer 238 in the region where the fifth semiconductor device 210 will be formed (e.g., such that the portion remains), a thickness 262e of the gate insulator or gate dielectric layer (e.g., the first dielectric layer 236 and the second dielectric layer 238) of the fifth semiconductor device 210 can be achieved, and a thickness 262f of the gate insulator (e.g., the first dielectric layer) of the sixth semiconductor device 212 can be achieved. The portion of the second dielectric layer 238 can be removed using a suitable photolithography process, such as described above, to mask the region where the fifth semiconductor device 210 will be formed and selectively etch the exposed portion of the second dielectric layer 238. The etching process may be a wet isotropic etching.

[0151] refer to Figure 10 Box 1020 and Figure 16 , reducing the respective thicknesses of gate layers 232c, 232d. The thicknesses of gate layers 232c, 232d are reduced from thickness 1102 to thicknesses 260c, 260d. In some examples, the thicknesses of gate layers 232a, 232b are not reduced from thickness 1102; Figure 16 , as shown in FIG. 2 as thicknesses 260 a and 260 b. The thicknesses of gate layers 232 c and 232 d can be reduced using an appropriate photolithography process, such as described above, to expose regions corresponding to gate layers 232 c and 232 d while masking other regions. Using a photoresist as a mask, gate layers 232 c and 232 d and first dielectric layer 236 overlying gate layers 232 c and 232 d are etched, for example, by anisotropic etching. Etching gate layers 232 c and 232 d can reduce the corresponding thicknesses.

[0152] refer to Figure 10 Box 1022 and Figure 17 A third dielectric layer 240 is formed over the semiconductor substrate 222. The third dielectric layer 240 is over and on the first dielectric layer 236 and the second dielectric layer 238. The third dielectric layer 240 is over the gate layers 232a-232d and the implant layer 234. The third dielectric layer 240 can be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, etc. The material of the third dielectric layer 240 can be as described above.

[0153] Reference frame 1024 and Figure 18Drain metal contacts 242a-242g and source metal contacts 244a-244g are formed through the third dielectric layer 240, the first dielectric layer 236, and, if appropriate, through the second dielectric layer 238. Respective source / drain contact openings can be formed through the third dielectric layer 240, the first dielectric layer 236, and, if appropriate, through the second dielectric layer 238 to the barrier layer 228, or through the barrier layer 228 to the channel layer 226. The source / drain contact openings can be formed using appropriate photolithography and etching processes. One or more metals are deposited in the source / drain contact openings and on and above the upper surface of the third dielectric layer 240. The one or more metals deposited in the source / drain contact openings form the drain metal contacts 242a-242g and the source metal contacts 244a-244g. The metal can be deposited using an appropriate deposition process, such as CVD, physical vapor deposition (PVD), or the like. In some examples, the metal can be a corresponding conformal layer in the source / drain contact openings that does not fill the source / drain contact openings, and in some examples, the metal can fill the source / drain contact openings. The metal above the upper surface of the third dielectric layer 240 is patterned into the portions of the drain metal contacts 242a-242g and the source metal contacts 244a-244g on the upper surface of the third dielectric layer 240. The metal can be patterned using appropriate photolithography and etching processes.

[0154] refer to Figure 10 Box 1026 and Figure 19 A fourth dielectric layer 246 is formed over semiconductor substrate 222. Fourth dielectric layer 246 conformally overlies third dielectric layer 240, drain metal contacts 242a-242g, and source metal contacts 244a-244g. Fourth dielectric layer 246 may be deposited using any suitable deposition process, such as CVD, LPCVD, PECVD, or the like. The material of fourth dielectric layer 246 may be as described above.

[0155] Reference box 1028 and Figure 20, gate metal contacts 248a-248g and implant metal contact 250 are formed through fourth dielectric layer 246 and third dielectric layer 240. Relevant gate / injection contact openings can be formed through fourth dielectric layer 246 and third dielectric layer 240, and as appropriate, to gate layers 232a-232d, implant layer 234, second dielectric layer 238, first dielectric layer 236, and barrier layer 228. The gate / injection contact openings can be formed using appropriate photolithography and etching processes. A variety of photolithography and etching processes can be implemented to form the gate / injection contact openings. For example, photolithography and etching processes may be used to form gate / injection contact openings through fourth dielectric layer 246, third dielectric layer 240, and (in some areas) first dielectric layer 236 to form gate / injection contact openings to gate layers 232a-232d and injection layer 234 (for semiconductor devices 202-208) and to form gate / injection contact openings to barrier layer 228 (for seventh semiconductor device 214). Other photolithography and etching processes may be used to form gate / injection contact openings through fourth dielectric layer 246 and third dielectric layer 240 to second dielectric layer 238 and first dielectric layer 236 to form gate / injection contact openings to second dielectric layer 238 (for fifth semiconductor device 210) and to form gate / injection contact openings to first dielectric layer 236 (for sixth semiconductor device 212). In some examples, the gate / implant contact openings for the gate metal contacts 248a-248g can be formed using a photolithography process and an etching process, such as by including one or more etch stop layers so that the etching process stops at an appropriate depth in the structure.

[0156] One or more metals are deposited into the gate / injection contact openings and over and on the upper surface of the fourth dielectric layer 246. The one or more metals deposited into the gate / injection contact openings form gate metal contacts 248a-248g and injection metal contact 250. The metal can be deposited using a suitable deposition process, such as CVD, PVD, or the like. In some examples, the metal can be a corresponding conformal layer in the gate / injection contact openings that does not fill the gate / injection contact openings, and in some examples, the metal can fill the gate / injection contact openings. The metal above the upper surface of the fourth dielectric layer 246 is patterned into portions of the gate metal contacts 248a-248g and injection metal contact 250 on the upper surface of the fourth dielectric layer 246. The metal can be patterned using suitable photolithography and etching processes.

[0157] In some examples, different metals can be implemented for the different gate metal contacts 248a-248g and the implant metal contact 250. Different metals can be implemented for the gate metal contacts 248a-248g to achieve different threshold voltages. For some semiconductor devices, it may be desirable to have a Schottky junction between the gate metal contact and the corresponding gate layer, while for other semiconductor devices, it may be desirable to have an ohmic junction between the gate metal contact and the corresponding gate layer. The junction can be implemented based on the material of the gate layer and the material of the gate metal contact. For example, to implement the semiconductor device 306 as a diode, an ohmic junction may be desirable, while to implement the first semiconductor device 202 as, for example, an Emode HEMT, a Schottky junction may be desirable. Different metals can be implemented as the gate metal contacts 248a-248g by different deposition of the respective different metals and different patterning of those metals.

[0158] Although implanted metal contact 250 is shown as being formed by the process of forming gate metal contacts 248a-248g, implanted metal contact 250 may be formed by the process of forming drain metal contacts 242a-242g and source metal contacts 244a-244g, as described above with respect to FIG. Figure 18 described.

[0159] Reference box 1030 and Figure 21 A fifth dielectric layer 252 is formed over and on the gate electrical contacts 248a-248g, the implanted metal contact 250, and the fourth dielectric layer 246. The fifth dielectric layer 252 may be deposited using any suitable deposition process, such as PECVD or the like. The fifth dielectric layer 252 may be any of the materials described above with respect to the fifth dielectric layer 252. The fifth dielectric layer 252 may be planarized, for example, by chemical mechanical polishing (CMP).

[0160] Reference box 1032 and Figure 2Metal vias 254a-254v are formed through the fifth dielectric layer 252 and, if appropriate, through the fourth dielectric layer 246, and metal lines 256a-256t are formed above and on the fifth dielectric layer 252. Via openings can be formed through the fifth dielectric layer 252 and, if appropriate, through the fourth dielectric layer 246 to the corresponding metal contacts 242a-242g, 244a-244g, 248a-248g, 250 using appropriate photolithography and etching processes. The metal for the metal vias 254a-254v and the metal lines 256a-256t is deposited above the fifth dielectric layer 252 and in the via openings. The metal can be deposited using an appropriate deposition process, such as CVD, PVD, etc. The metal can be patterned into the metal lines 256a-256t using appropriate photolithography and etching processes. Metal vias 254a-254v are formed underlying metal lines 256a-256t and metal in corresponding via openings through fifth dielectric layer 252 and, where appropriate, fourth dielectric layer 246.

[0161] Figure 10 The method 1000 may also be implemented for manufacturing Figure 3 IC 300. To achieve this, source metal contact 244c may be omitted (e.g., source / drain openings corresponding to source metal contact 244c are omitted, and patterning of the metal corresponding to source metal contact 244c is omitted). Furthermore, similarly, metal via 254j and metal line 256i may be omitted. An anode layer 332c may be formed similarly to gate layer 232c; a cathode metal contact 342c may be formed similarly to drain metal contact 242c; and an anode metal contact 348c may be formed similarly to gate metal contact 248c. Such modifications may be made to the IC manufacturing method described later to implement third semiconductor device 306 or similar semiconductor devices.

[0162] Figure 22 Based on some examples Figure 4 Flowchart of method 2200 of IC 400. Figure 22 The method 2200 is shown by a cross-sectional view of the IC 400 at various stages of fabrication. Figures 23 to 26 shown and described in its context. Figure 22 Method 2200 in Figures 23 to 26 The context of the manufacturing Figure 4 IC 400, but Figure 22 Method 2200 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0163] refer to Figure 22 Box 1002 and Figure 23, one or more transition layers 224 are formed above and on semiconductor substrate 222. At block 1004, channel layer 226 is formed above and on transition layer 224. At block 1006, barrier layer 428 is formed above and on channel layer 226. The processing of blocks 1002-1006 can be as previously described. Barrier layer 428 is formed to have a thickness 2302.

[0164] Reference box 2202 and Figure 24 , gate recesses 422a, 422b are formed in barrier layer 428. Gate recesses 422a, 422b can be formed using suitable photolithography and etching processes. After forming gate recesses 422a, 422b, barrier layer 428 has thicknesses 460a, 460b at the respective gate recesses 422a, 422b. Furthermore, after forming gate recesses 422a, 422b, barrier layer 428 has thicknesses 460c, 460d, 462, which are approximately the thickness 2302 (e.g., with a small amount of loss due to processing).

[0165] refer to Figure 22 Box 1008 and Figure 25 , a gate layer 432 is formed above and on the barrier layer 428. The gate layer 432 is formed conformally in the gate recesses 422a, 422b. Figure 22 Box 1010 and Figure 26 , patterning the gate layer 432 into the gate layers 432a, 432b, 232c, 232d and the implantation layer 434. Subsequently, Figure 4 In the IC 400, at block 1012, a first dielectric layer 236 is conformally formed over and on the barrier layer 428, the gate layers 432a, 432b, 232c, 232d, and the implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. At block 1016, an isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1008-1018 can be as previously described.

[0166] exist Figure 22 At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. Figure 22 At block 1026, a fourth dielectric layer 246 is formed. Figure 22 At block 1028, gate metal contacts 248a-248g and implant metal contact 250 are formed. Figure 22At block 1030, a fifth dielectric layer 252 is formed. At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0167] It can also be implemented Figure 22 Method 2200 to manufacture Figure 5 IC 500. To achieve this, implant recess 524 is formed, for example, when gate recesses 422a, 422b are formed. Implant layer 534 can be formed similarly to implant layer 434. Such modifications can be made to the IC fabrication method described later to implement this aspect of IC 500.

[0168] Figure 27 Based on some examples Figure 6 Flowchart of method 2700 of IC 600. Figure 27 The method 2700 is shown by a cross-sectional view of the IC 600 at various stages of manufacture. Figures 28 to 32 shown and described in its context. Figure 27 Method 2700 in Figures 28 to 32 The context of the manufacturing Figure 6 IC 600, but Figure 27 Method 2700 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0169] refer to Figure 27 Box 1002 and Figure 28 , one or more transition layers 224 are formed above and on the semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on the transition layer 224. The processes of blocks 1002 and 1004 may be as previously described. At block 2702, a first blocking sublayer 612 is formed above and on the channel layer 226. The first blocking sublayer 612 may be formed using the process described with respect to forming the blocking layer 228 in block 1006.

[0170] Reference box 2704 and Figure 29 , openings 622a, 622b are formed through the first barrier sublayer 612. The openings 622a, 622b may be formed using appropriate photolithography and etching processes.

[0171] Reference box 2706 and Figure 30A second blocking sublayer 614 is formed above and on the first blocking sublayer 612 and the channel layer 226 exposed by the openings 622a and 622b. The second blocking sublayer 614 is conformally formed on the first blocking sublayer 612 and in the openings 622a and 622b. The second blocking sublayer 614 conforms to the surface of the openings 622a and 622b passing through the first blocking sublayer 612, forming gate recesses 422a and 422b. The first and second blocking sublayers 612 and 614 can together form a blocking layer. The second blocking sublayer 614 can be considered a regrown layer. The blocking layer at the gate recesses 422a and 422b has thicknesses 460a and 460b, which correspond to the thickness of the second blocking sublayer 614. The blocking layer also has thicknesses 460c and 460d corresponding to the combined thickness of the first and second blocking sublayers 612 and 614. The second blocking sublayer 614 may be formed using the process described with respect to forming the blocking layer 228 in block 1006 .

[0172] refer to Figure 27 Box 1008 and Figure 31 , a gate layer 432 is formed on the barrier layer (eg, the second barrier sublayer 614) and the upper portion. Figure 27 Box 1010 and Figure 32 , the gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d and implant layer 434. The processing of blocks 1008, 1010 may be as previously described.

[0173] Then, to form Figure 6 IC 600, in Figure 27 At block 1012, a first dielectric layer 236 is conformally formed over and on the barrier layer 428, the gate layers 432a, 432b, 232c, 232d, and the implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. At block 1016, the isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1012-1018 can be as previously described.

[0174] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. Figure 27 At block 1026, a fourth dielectric layer 246 is formed. Figure 27 At block 1028, gate metal contacts 248a-248g and implant metal contact 250 are formed. Figure 27 At block 1030, a fifth dielectric layer 252 is formed. Figure 27At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0175] Figure 27 Method 2700 can also be implemented to manufacture a device similar to Figure 5 To achieve this, an opening corresponding to the injection layer is formed through the first blocking sublayer 612, such as when the openings 622a, 622b are formed. This can form an injection recess, similar to Figure 5 5. An implantation layer may be formed in the implantation recess, similar to implantation layer 534. Such modifications may be made to the subsequently described IC fabrication methods to implement this aspect of IC 500.

[0176] Figure 33 Based on some examples Figure 7 Flowchart of method 3300 of IC 700. Figure 33 The method 3300 is shown by a cross-sectional view of the IC 700 at various stages of manufacture. Figures 34 to 37 shown and described in its context. Figure 33 Method 3300 in Figures 34 to 37 The context of the manufacturing Figure 7 IC 700, but Figure 33 Method 3300 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0177] refer to Figure 33 Box 1002 and Figure 34 One or more transition layers 224 are formed over and on semiconductor substrate 222. At block 1004, a channel layer 726 is formed over and on transition layer 224. Channel layer 726 is formed with a thickness 3402. The processing of blocks 1002, 1004 may be as previously described.

[0178] refer to Figure 33 Box 3302 and Figure 35 , recesses 712a, 712b are formed in the channel layer 726. Recesses 712a, 712b can be formed using appropriate photolithography and etching processes. After forming recesses 712a, 712b, the channel layer 726 has thicknesses 764a, 764b at the respective recesses 712a, 712b. Furthermore, after forming recesses 712a, 712b, the channel layer 726 has thicknesses 764c, 764d, which are approximately the thickness 3402 (e.g., there may be a small amount of loss due to processing).

[0179] refer to Figure 33 Box 1006 and Figure 36, a barrier layer 728 is formed above and on the channel layer 726. The barrier layer 728 is conformally formed on the channel layer 726 and in the recesses 712a, 712b. The barrier layer 728 conforms to the surface of the recesses 712a, 712b in the channel layer 726, forming gate recesses 722a, 722b. At block 1008, a gate layer 432 is formed above and on the barrier layer 728. The gate layer 432 is formed so as to conformally form the gate recesses 722a, 722b. The processes of blocks 1006 and 1008 can be as previously described.

[0180] refer to Figure 33 Box 1010 and Figure 37 , patterning the gate layer 432 into the gate layers 432a, 432b, 232c, 232d and the implantation layer 434. Subsequently, Figure 7 IC 700, in Figure 33 At block 1012, a first dielectric layer 236 is conformally formed over and on the barrier layer 428, the gate layers 432a, 432b, 232c, 232d, and the implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. At block 1016, the isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1010-1018 may be as previously described.

[0181] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1028, gate metal contacts 248a-248g and an implant metal contact 250 are formed. At block 1030, a fifth dielectric layer 252 is formed. At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0182] Figure 8 IC 800 (or another IC implementing a gate layer of varying lengths) can be manufactured using any of the methods described above and by implementing a photolithographic mask during patterning of the gate layer to achieve lengths 866a, 866b, 866c, 866d. The photolithographic mask can be used, for example, at block 1010 and with reference to FIG. Figure 12 、 26 , 32 or 37 in the photolithography process.

[0183] Figure 9IC 900 (or another IC implementing varying lengths of gate metal contacts) can be manufactured using any of the methods described above by implementing a photolithographic mask during patterning of gate contact openings to lengths 968a, 968b, 968c, 968d. The photolithographic mask can be used, for example, at block 1028 and with reference to FIG. Figure 20 In the photolithography process implemented.

[0184] Figure 38 is a flow chart of a method 3800 of fabricating an IC in which gate layers have different doping concentrations, according to some examples. Figure 38 The method 3800 comprises a cross-sectional view showing an IC at various stages of fabrication. Figures 39 to 42 shown and described in its context. Figure 38 Method 3800 in Figures 39 to 42 is shown in the context of manufacturing the IC shown, but Figure 38 Method 3800 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0185] refer to Figure 38 Box 1002 and Figure 39 , one or more transition layers 224 are formed above and on semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on transition layer 224. At block 1006, a barrier layer 428 is formed above and on channel layer 226. At block 2202, gate recesses 422a, 422b are formed in barrier layer 428. The processing of blocks 1002-1006, 2202 can be as previously described.

[0186] At block 3802, a first gate sublayer 3902 is formed over and on the barrier layer 428. The first gate sublayer 3902 can be formed using the processes described above with respect to forming the gate layer 432 at block 1008. More specifically, the first gate sublayer 3902 can be formed using an epitaxial growth process at a first dopant concentration, such as in-situ doping with a p-type dopant. At block 3804, a mask layer 3904 is formed over the first gate sublayer 3902. The mask layer 3904 can be or include silicon nitride, or the like, and can be deposited by PECVD or another deposition process.

[0187] refer to Figure 38 Box 3806 and Figure 40 , patterning the mask layer 3904 and the first gate sublayer 3902. Patterning can be performed by appropriate photolithography and etching processes.

[0188] refer to Figure 38 Box 3808 and Figure 41, forming a second gate sublayer 4102 above and on the barrier layer 428. The second gate sublayer 4102 is formed at the location where the first gate sublayer 3902 is removed during patterning at block 3806. The second gate sublayer 4102 can be formed using the processing described above with respect to forming the gate layer 432 at block 1008. More specifically, the second gate sublayer 4102 can be formed using a selective epitaxial growth process that in-situ dopes, for example, with a p-type dopant at a second dopant concentration. The second dopant concentration is different from the first dopant concentration (e.g., the difference is a different uniform concentration or a different gradient concentration). After forming the second gate sublayer 4102, the mask layer 3904 can be removed, for example, using an etching process that is selective to the material of the mask layer 3904 (e.g., a wet etch). The first gate sublayer 3902 and the second gate sublayer 4102 together form a gate layer (e.g., gate layer 432).

[0189] refer to Figure 38 Box 1010 and Figure 42 , gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d, and implant layer 434. Gate layers 432a, 432b, and implant layer 434 are patterned from first gate sublayer 3902 and have a first dopant concentration. Gate layers 232c, 232d are patterned from second gate sublayer 4102 and have a second dopant concentration. Subsequently, at block 1012, a first dielectric layer 236 is conformally formed over and on barrier layer 428, gate layers 432a, 432b, 232c, 232d, and implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on first dielectric layer 236. Figure 38 At block 1016, an isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1010-1018 can be as previously described.

[0190] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1028, gate metal contacts 248a-248g and an implant metal contact 250 are formed. At block 1030, a fifth dielectric layer 252 is formed. At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0191] Figure 43 is a flow chart of a method 4300 of fabricating an IC having gate layers with different doping concentrations, according to some examples. Figure 43Method 4300 comprises a cross-sectional view showing an IC at various stages of fabrication. Figure 44 and 45 shown and described in its context. Figure 43 Method 4300 in Figure 44 and 45 is shown in the context of manufacturing the IC shown, but Figure 43 Method 4300 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0192] refer to Figure 43 Box 1002 and Figure 44 , one or more transition layers 224 are formed above and on semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on transition layer 224. At block 1006, a barrier layer 428 is formed above and on channel layer 226. At block 2202, gate recesses 422a, 422b are formed in barrier layer 428. The processing of blocks 1002-1006, 2202 can be as previously described.

[0193] exist Figure 43 At block 1008, a gate layer 432 is formed over and on the barrier layer 428. The gate layer 432 can be formed using the processes described above with respect to block 1008. More specifically, the gate layer 432 can be formed using an epitaxial growth process that is in-situ doped with, for example, a p-type dopant at a first dopant concentration. At block 4302, a dopant is implanted into the gate layer 432. The dopant is implanted into portions of the gate layer 432 where the dopant concentration will be greater than the first dopant concentration. For example, portions of the gate layer 432 can be masked, for example, by Figure 44 4. Photoresist 4402 is shown, and other portions of gate layer 432 are exposed and implanted with dopants via implant 4404. Photoresist 4402 can be deposited and patterned using appropriate photolithography processes. Implant 4404 implants the dopant into the exposed portions of gate layer 432 to a second concentration greater than the first concentration. Thereafter, photoresist 4402 can be removed, for example, by ashing.

[0194] refer to Figure 43 Box 1010 and Figure 45, gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d and implant layer 434. Because the portion of gate layer 432 that forms gate layers 432a, 432b and implant layer 434 is masked by photoresist 4402 during implant 4404, gate layers 432a, 432b and implant layer 434 have a first dopant concentration. Because the portion of gate layer 432 that forms gate layers 232c, 232d is implanted with a dopant by implant 4404, gate layers 232c, 232d have a second dopant concentration. The processing of block 1010 can be as previously described.

[0195] Subsequently, at block 1012, a first dielectric layer 236 is conformally formed over and on barrier layer 428, gate layers 432a, 432b, 232c, 232d, and implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on first dielectric layer 236. At block 1016, isolation structure 230 is formed. At block 1018, portions of second dielectric layer 238 are removed from the areas where sixth semiconductor device 212 and seventh semiconductor device 214 will be formed. The processing of blocks 1012-1018 may be as previously described.

[0196] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1028, gate metal contacts 248a-248g and an implant metal contact 250 are formed. At block 1030, a fifth dielectric layer 252 is formed. At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0197] Figure 46 is a flow chart of a method 4600 for fabricating an IC having gate layers with different doping concentrations, according to some examples. Figure 46 The method 4600 comprises a cross-sectional view showing an IC at various stages of fabrication. Figures 47 to 49 shown and described in its context. Figure 46 Method 4600 in Figures 47 to 49 is shown in the context of manufacturing the IC shown, but Figure 46 Method 4600 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0198] refer to Figure 46 Box 1002 and Figure 47, one or more transition layers 224 are formed above and on semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on transition layer 224. At block 1006, a barrier layer 428 is formed above and on channel layer 226. At block 2202, gate recesses 422a, 422b are formed in barrier layer 428. The processing of blocks 1002-1006, 2202 can be as previously described.

[0199] At block 1008, a gate layer 432 is formed over and on the barrier layer 428. The gate layer 432 may be formed using the processes described above with respect to block 1008. During formation, the gate layer 432 may or may not be doped in situ. At block 4602, a dopant is implanted into the gate layer 432. The dopant is implanted into portions of the gate layer 432 where the dopant concentration is to be a first dopant concentration. For example, portions of the gate layer 432 may be implanted, for example Figure 47 The photoresist 4702 shown is masked, and other portions of the gate layer 432 are exposed and implanted by implant 4704. The photoresist 4702 can be deposited and patterned using a suitable photolithography process. The implant 4704 implants the dopant into the exposed portions of the gate layer 432 to a first concentration. Thereafter, the photoresist 4702 can be removed, for example, by ashing.

[0200] refer to Figure 46 Box 4604 and Figure 48 , dopants are implanted into the gate layer 432. The dopants are implanted into portions of the gate layer 432 where the dopant concentration is the second dopant concentration. For example, some portions of the gate layer 432 may be implanted. Figure 48 Photoresist 4802 is shown masking, and other portions of gate layer 432 are exposed and implanted with dopants via implant 4804. Photoresist 4802 can be deposited and patterned using appropriate photolithography processes. Implant 4804 implants dopants into the exposed portions of gate layer 432 to a second concentration different from the first concentration. Thereafter, photoresist 4802 can be removed, for example, by ashing.

[0201] refer to Figure 46 Box 1010 and Figure 49, gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d and implant layer 434. Because the portion of gate layer 432 that formed gate layers 432a, 432b and implant layer 434 during implant 4704 was implanted by implant 4804 and masked by photoresist 4702, gate layers 432a, 432b and implant layer 434 have the second dopant concentration. Because the portion of gate layer 432 that formed gate layers 232c, 232d during implant 4804 was implanted by implant 4704 and masked by photoresist 4802, gate layers 232c, 232d have the first dopant concentration. The processing of block 1010 can be as previously described.

[0202] Subsequently, at block 1012, a first dielectric layer 236 is conformally formed over and on barrier layer 428, gate layers 432a, 432b, 232c, 232d, and implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on first dielectric layer 236. At block 1016, isolation structure 230 is formed. At block 1018, portions of second dielectric layer 238 are removed from the areas where sixth semiconductor device 212 and seventh semiconductor device 214 will be formed. The processing of blocks 1012-1018 may be as previously described.

[0203] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1028, gate metal contacts 248a-248g and an implant metal contact 250 are formed. At block 1030, a fifth dielectric layer 252 is formed. At block 1032, metal vias 254a-254v and metal lines 256a-256t are formed. The processing of blocks 1022-1032 can be as previously described.

[0204] Various methods have been described in which the gate metal contact is formed "last"—that is, it is the last metal contact formed among the metal contacts. In the above examples, the drain and source metal contacts are formed before the gate metal contact. In other examples, the gate metal contact may be formed before the source and drain metal contacts. In such examples where the gate metal contact is formed before the source and drain metal contacts, the method can be considered a gate-first process.

[0205] Figure 50 is a flow chart of a method 5000 of fabricating an IC using a gate-first process, according to some examples. Figure 50 The method 5000 is also a self-aligned process for aligning, for example, gate metal contacts with corresponding gate layers. Figure 50The method 5000 comprises a cross-sectional view showing an IC at various stages of fabrication. Figures 51 to 55 Shown and described in its context. Figure 55 The IC is similar to Figure 4 IC 400. Although Figure 50 Method 5000 in Figures 51 to 55 to manufacture such ICs, but Figure 50 Method 5000 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0206] refer to Figure 50 Box 1002 and Figure 51 , one or more transition layers 224 are formed above and on the semiconductor substrate 222. At block 1004, a channel layer 226 is formed above and on the transition layer 224. At block 1006, a barrier layer 428 is formed above and on the channel layer 226. At block 2202, gate recesses 422a, 422b are formed in the barrier layer 428. At block 1008, a gate layer 432 is formed above and on the barrier layer 428. The processing of blocks 1002-1006, 2202, 1008 can be as previously described.

[0207] At block 5002, a gate contact layer 5102 is formed over and on the gate layer 432. The gate contact layer 5102 may be the material of the gate metal contacts 248a-248d and the implanted metal contact 250. The gate contact layer 5102 may be deposited by PVD, CVD, or another deposition process.

[0208] refer to Figure 50 Box 5004 and Figure 52 , gate contact layer 5102 and gate layer 432 are patterned. Gate contact layer 5102 is patterned into gate metal contacts 5102a, 5102b, 5102c, 5102d and implant metal contact 5104. Gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d and implant layer 434. Gate contact layer 5102 and gate layer 432 can be patterned using appropriate photolithography and etching processes.

[0209] refer to Figure 50 Box 5006 and Figure 53 , a first dielectric layer 236 is conformally formed over and on barrier layer 428, gate layers 432a, 432b, 232c, 232d, implant layer 434, gate metal contacts 5102a, 5102b, 5102c, 5102d, and implant metal contact 5104. The processing of block 5006 may be similar to the processing of block 1012.

[0210] refer to Figure 50Box 1014 and Figure 54 , a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. At block 1016, an isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1014-1018 can be as previously described.

[0211] At block 1022, a third dielectric layer 240 is formed. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1030, a fifth dielectric layer 252 is formed. The processing of blocks 1022, 1024, 1026, and 1030 can be as previously described.

[0212] refer to Figure 50 Box 1032 and Figure 55 , forming metal vias 254a-254v and metal lines 256a-256t. The process of block 1032 can be as previously described. Through-hole openings of metal vias 254b, 254c, 254f, 254i, and 254l are formed through the fifth dielectric layer 252 and the first dielectric layer 236 to expose the implant metal contact 5104 and the gate metal contacts 5102a, 5102b, 5102c, and 5102d, respectively. Therefore, the metal vias 254b, 254c, 254f, 254i, and 254l are electrically coupled and contact the implant metal contact 5104 and the gate metal contacts 5102a, 5102b, 5102c, and 5102d, respectively. Furthermore, via openings of metal vias 254o, 254r, 254u may respectively expose second dielectric layer 238, first dielectric layer 236, and barrier layer 228. Metal vias 254o, 254r, 254u may form gate terminals of respective semiconductor devices 210, 212, 214.

[0213] Figure 56 is a flow chart of a method 5600 for fabricating an IC using a gate-first process, according to some examples. Figure 56 The method 5600 is also a self-alignment process for aligning, for example, gate metal contacts with corresponding gate layers. Figure 50 Method 5000 as described and Figures 51 to 55 Processing is performed as shown in . Figure 56 After the gate contact layer 5102 and the gate layer 432 are patterned into gate metal contacts 5102a, 5102b, 5102c, 5102d and implant metal contact 5104 at block 5004, the length of the gate metal contact is reduced at block 5602, as shown. Figure 57 As shown in . Figure 57In the embodiment of the present invention, the length of gate metal contacts 5102a, 5102b is reduced to form gate metal contacts 5702a, 5702b. Gate metal contacts 5102c, 5102d and implant metal contact 5104 can be masked, for example, by using a photoresist patterned using photolithography. An isotropic etch, such as a wet etch, selective to the metal of gate metal contacts 5102a, 5102b is performed to reduce the length of gate metal contacts 5102a, 5102b. The isotropic etch can also reduce the thickness of gate metal contacts 5102a, 5102b. The resulting gate metal contacts 5702a, 5702b have reduced lengths 5704a, 5704b, further resulting in contact offset lengths 5706a, 5706b. Thus, in the example shown, gate metal contacts 5102c, 5102d have the same lateral footprint as gate layers 232c, 232d, respectively, and gate metal contacts 5702a, 5702b have a different lateral footprint than gate layers 232a, 232b, respectively. Processing and subsequent processing as described above with respect to block 5006 then proceeds.

[0214] Figure 58 is a flow chart of a method 5800 of manufacturing an IC using a gate-first process, according to some examples. Figure 58 The method 5800 comprises a cross-sectional view showing an IC at various stages of fabrication. Figures 59 to 62 Shown and described in its context. Figure 58 The IC is similar to Figure 4 IC 400. Although Figure 58 Method 5800 in Figures 59 to 62 to manufacture such ICs, but Figure 58 Method 5800 may also be implemented to manufacture examples consistent with aspects of any IC described herein.

[0215] refer to Figure 58 Box 1002 and Figure 59, one or more transition layers 224 are formed over and on semiconductor substrate 222. At block 1004, a channel layer 226 is formed over and on transition layer 224. At block 1006, a barrier layer 428 is formed over and on channel layer 226. At block 2202, gate recesses 422a, 422b are formed in barrier layer 428. At block 1008, a gate layer 432 is formed over and on barrier layer 428. At block 1010, gate layer 432 is patterned into gate layers 432a, 432b, 232c, 232d, and implant layer 434. At block 1012, a first dielectric layer 236 is conformally formed over and on barrier layer 428, gate layers 432a, 432b, 232c, 232d, and implant layer 434. At block 1014, a second dielectric layer 238 is conformally formed over and on the first dielectric layer 236. At block 1016, an isolation structure 230 is formed. At block 1018, portions of the second dielectric layer 238 are removed from the areas where the sixth semiconductor device 212 and the seventh semiconductor device 214 will be formed. The processing of blocks 1002-1006, 2202, 1008-1018 may be as previously described.

[0216] refer to Figure 58 Box 5802 and Figure 60, forming gate metal contacts 6002a, 6002b, 6002c, 6002d, 6002e, 6002f, 6002g and implant metal contact 6004. Gate metal contacts 6002a, 6002b, 6002c, 6002d, 6002g, and implant metal contact 6004 are formed through first dielectric layer 236. Relevant gate / injection contact openings can be formed through first dielectric layer 236, as appropriate, to gate layers 232a-232d, implant layer 234, and barrier layer 228. The gate / injection contact openings can be formed using suitable photolithography and etching processes. One or more metals are deposited into the gate / injection contact openings and onto and above the upper surface of first dielectric layer 236 or second dielectric layer 238. The metals can be deposited using suitable deposition processes, such as CVD, PVD, and the like. In some examples, the metal may be a corresponding conformal layer in the gate / injection contact opening that does not fill the gate / injection contact opening, and in some examples, the metal may fill the gate / injection contact opening. The metal above the upper surface of the respective dielectric layer 236, 238 is patterned into portions of the gate metal contacts 6002a-6002g and the injection metal contact 6004 on the upper surface of the respective dielectric layer 236, 238. The metal may be patterned using appropriate photolithography and etching processes. The patterned metal, some of which may be deposited into the respective gate / injection contact opening, forms the gate metal contacts 6002a-6002g and the injection metal contact 6004. The gate metal contacts 6002e, 6002f, 6002g may form the gate terminals of the respective semiconductor devices 210, 212, 214.

[0217] refer to Figure 58 Box 1022 and Figure 61 , forming a third dielectric layer 240. At block 1024, drain metal contacts 242a-242g and source metal contacts 244a-244g are formed. At block 1026, a fourth dielectric layer 246 is formed. At block 1030, a fifth dielectric layer 252 is formed. The processing of blocks 1022, 1024, 1026, and 1030 can be as previously described.

[0218] refer to Figure 58 Box 1032 and Figure 62, forming metal vias 254a-254v and metal lines 256a-256t. The processing of block 1032 can be as previously described. Through-hole openings of metal vias 254b, 254c, 254f, 254i, 254l, 254o, 254r, 254u are formed through the fifth dielectric layer 252 to expose the implant metal contact 6004 and the gate metal contacts 6002a, 6002b, 6002c, 6002d, 6002e, 6002f, 6002g, respectively. Thus, metal vias 254b, 254c, 254f, 254i, 254l, 254o, 254r, 254u are electrically coupled to and contact implant metal contact 5104 and gate metal contacts 6002a, 6002b, 6002c, 6002d, 6002e, 6002f, 6002g, respectively.

[0219] Figure 63 is a graph illustrating threshold voltage of a semiconductor device (eg, an Emode HEMT) as a function of gate layer thickness, according to some examples. For a given process node of a given semiconductor device, the threshold voltage increases as gate layer thickness increases.

[0220] Figure 64 Graphs illustrating threshold voltage of a semiconductor device (e.g., an Emode HEMT) as a function of gate layer dopant concentration, according to some examples. For a given process node of a given semiconductor device, the threshold voltage increases as the dopant concentration of the gate layer (e.g., at the interface between the gate layer and the barrier layer) increases.

[0221] Figure 65 is a graph illustrating threshold voltage of a semiconductor device (eg, an Emode HEMT) as a function of barrier layer thickness, according to some examples. For a given process node of a given semiconductor device, the threshold voltage decreases as the barrier layer thickness increases.

[0222] Figure 66 66 is a graph showing threshold voltage as a function of gate length for semiconductor devices (e.g., Emode HEMTs of different designs) according to some examples. The graph shows data points (shown as circles) for a first design of the semiconductor device at varying gate lengths. Trend line 6602 shows that for the first design, the threshold voltage initially decreases relatively quickly and then increases as the gate length increases. The graph shows data points (shown as triangles) for a second design of the semiconductor device at varying gate lengths. Trend line 6604 shows that for the second design, the threshold voltage decreases over a range of increasing gate lengths.

[0223] Figure 6767 is a graph showing threshold voltage of semiconductor devices (e.g., Emode HEMTs of different designs) as a function of contact offset length, according to some examples. The graph shows data points (shown as circles) for a first design of the semiconductor device at varying contact offset lengths. Trend line 6702 shows that for the first design, the threshold voltage increases as the contact offset length increases. The graph shows data points (shown as triangles) for a second design of the semiconductor device at varying contact offset lengths. Trend line 6704 shows that for the second design, the threshold voltage increases as the contact offset length increases.

[0224] Figures 68 to 72 are corresponding cross-sectional views of semiconductor devices illustrating different isolation techniques according to some examples. For any of the semiconductor devices described above, any isolation technique may be implemented, such as described in U.S. patent application Ser. No. 18 / 534,056, filed on Dec. 8, 2023, and entitled “Integrated devices with conductive barrier structure,” which is incorporated herein by reference in its entirety. Figures 68 to 72 The semiconductor devices in FIG. 1 are simplified relative to previously shown semiconductor devices in order to avoid obscuring aspects shown in these figures.

[0225] Figures 68 to 72 The semiconductor devices include corresponding first semiconductor devices 6802, 6902, 7002, 7102, 7202 and corresponding second semiconductor devices 6804, 6904, 7004, 7104, 7204. These semiconductor devices may be or include any of the semiconductor devices described previously, which may include Figures 68 to 72 Modification of semiconductor devices in.

[0226] Figures 68 to 72The semiconductor substrate 6812, one or more transition layers 6814, a channel layer 6816, and a barrier layer 6818 are included. The semiconductor substrate 6812, transition layers 6814, channel layers 6816, and barrier layers 6818 may have structures and / or materials similar to the semiconductor substrate 222, transition layers 224, channel layers 226, 726, and barrier layers 228, 428, 528, 728 (or barrier sublayers 612, 614) described and illustrated previously. The first semiconductor devices 6802, 6902, 7002, 7102, 7202 each include a gate layer 6820a and a gate metal contact 6822a, which may have structures and / or materials similar to any gate layer and any gate metal contact described above. In each of the first semiconductor devices 6802, 6902, 7002, 7102, and 7202, a drain metal contact 6824a extends through the barrier layer 6818 to the channel layer 6816. The drain metal contact 6824a electrically couples the drain terminal of the corresponding semiconductor device. In other examples, the drain metal contact 6824a contacts but does not extend through the barrier layer 6818. In each of the first semiconductor devices 6802, 6902, and 7002, a source metal contact 6826a extends through the barrier layer 6818 into the channel layer 6816, and further, in the illustrated example, through the transition layer 6814 to the semiconductor substrate 6812. The source metal contact 6826a electrically couples the source terminal of the corresponding semiconductor device. A source-coupled field plate 6828b is electrically coupled to the source metal contact 6826a and extends laterally therefrom onto the gate layer 6820a.

[0227] Each of the second semiconductor devices 6804, 6904, 7004, 7104, and 7204 includes a gate layer 6820b and a gate metal contact 6822b, which can each have a structure and / or materials similar to any gate layer and any gate metal contact described above. In each of the second semiconductor devices 6804, 6904, 7004, 7104, and 7204, a drain metal contact 6824b extends through the barrier layer 6818 to the channel layer 6816. The drain metal contact 6824b electrically couples the drain terminal of the corresponding semiconductor device. In other examples, the drain metal contact 6824b contacts but does not extend through the barrier layer 6818. In each of the first semiconductor devices 6802, 6902, and 7002, a source metal contact 6826b extends through the barrier layer 6818 to the channel layer 6816 and, in the illustrated example, through the transition layer 6814 to the semiconductor substrate 6812. The source metal contact 6826b is electrically coupled to the source terminal of the corresponding semiconductor device. The source-coupled field plate 6828b is electrically coupled to the source metal contact 6826b and extends laterally therefrom onto the gate layer 6820b.

[0228] refer to Figure 68Trench 6830 is laterally located between semiconductor devices 6902 and 6904 and extends through barrier layer 6818, channel layer 6816, and transition layer 6814 to the upper surface of semiconductor substrate 6812. Trench 6830 can be filled with an isolation material (e.g., silicon oxide). A doped well 6832 extends from the upper surface of semiconductor substrate 6812 to a depth within semiconductor substrate 6812. Doped well 6832 laterally overlaps trench 6830. Doped well 6832 underlies second semiconductor device 6804. Source metal contact 6826b can be electrically coupled to doped well 6832. Doped well 6832 does not extend to underlie first semiconductor device 6802. In some examples, semiconductor substrate 6812 is doped with a p-type dopant, and doped well 6832 is doped with an n-type dopant at a greater concentration than the p-type dopant of semiconductor substrate 6812. The doped well 6832 can be formed by implanting dopants (which can be further subjected to a photolithography process to mask non-implanted areas), for example, before forming the transition layer 6814, the channel layer 6816, and / or the barrier layer 6818. The doped well 6832 can provide lateral junction isolation in the semiconductor substrate 6812.

[0229] refer to Figure 69 A trench 6930 is laterally disposed between the semiconductor devices 6902 and 6904 and extends through the barrier layer 6818, the channel layer 6816, and the transition layer 6814 into the semiconductor substrate 6812. The trench 6930 may be filled with an isolation material (e.g., silicon oxide). Doped wells 6932a and 6932b extend from the upper surface of the semiconductor substrate 6812 to a depth within the semiconductor substrate 6812. The doped well 6932a underlies the first semiconductor device 6902, and the doped well 6932b underlies the second semiconductor device 6904. A source metal contact 6826a may be electrically coupled to the doped well 6932a, and a source metal contact 6826b may be electrically coupled to the doped well 6932b. The trench 6930 extends between the doped wells 6932a and 6932b in the semiconductor substrate 6812, separating the doped wells 6932a and 6932b. In some examples, the semiconductor substrate 6812 is doped with a p-type dopant, and the doped wells 6932a, 6932b are doped with an n-type dopant at a greater concentration than the p-type dopant of the semiconductor substrate 6812. The doped wells 6932a, 6932b can be formed by implanting dopants (which can be further subjected to a photolithography process to mask non-implanted areas), for example, before forming the transition layer 6814, the channel layer 6816, and / or the barrier layer 6818. The doped wells 6932a, 6932b can provide vertical junction isolation in the semiconductor substrate 6812.

[0230] refer to Figure 70Trench 7030 is laterally located between semiconductor devices 7002 and 7004 and extends through barrier layer 6818, channel layer 6816, and transition layer 6814 into semiconductor substrate 6812. Trench 7030 may be filled with an isolation material (e.g., silicon oxide). Semiconductor substrate 6812 includes isolation layer 7032, which may make semiconductor substrate 6812 an SOI substrate. Isolation layer 7032 may be an oxide layer (e.g., a buried oxide (BOX) layer). Trench 7030 further extends into isolation layer 7032.

[0231] refer to Figure 71 A trench 7130 is laterally disposed between the semiconductor devices 7102 and 7104 and extends through the barrier layer 6818, the channel layer 6816, and the transition layer 6814 into the semiconductor substrate 6812. The trench 7130 may be filled with an isolation material (e.g., silicon oxide). The channel layer 6816 of the semiconductor devices 7102 and 7104 contains two-dimensional hole gas (2DHG) 7134a and 7134b. The 2DHGs 7134a and 7134b are located below the 2DEG in the channel layer 6816. The 2DHGs 7134a and 7134b may be formed by band bending in the channel layer 6816, which may be achieved, for example, by selecting the materials of the sublayers of the channel layer 6816. The 2DHGs 7134a and 7134b may provide hole injection isolation. In semiconductor devices 7102 and 7104, respective source metal contacts 7126a and 7126b extend through barrier layer 6818 to channel layer 6816. Source metal contacts 7126a and 7126b electrically couple respective source terminals of respective semiconductor devices. Source coupling field plates 6828a and 6828b are electrically coupled to respective source metal contacts 7126a and 7126b and extend laterally therefrom onto gate layers 6820a and 6820b.

[0232] refer to Figure 72The trench 7230 is laterally located between the semiconductor devices 7202 and 7204 and extends through the barrier layer 6818, the channel layer 6816, and the transition layer 6814 into the semiconductor substrate 6812. The trench 7230 can be filled with an isolation material (e.g., silicon oxide). The channel layer 6816 of the first semiconductor device 7202 includes a doped region 7236a. The channel layer 6816 of the second semiconductor device 7204 includes a doped region 7236b. The doped regions 7236a and 7236b are located in the channel layer 6816 below the respective 2DEGs. The trench 7230 is laterally located between and separates the doped regions 7236a and 7236b. The doped regions 7236a and 7236b can be formed by implanting dopants (which can be further photolithographically masked to mask unimplanted regions), for example, before forming the barrier layer 6818. Doped regions 7236a and 7236b can provide a conductive layer in the channel layer 6816 to trap leakage. In the first semiconductor device 7202, a source metal contact 7226a extends through the barrier layer 6818 into the channel layer 6816 and reaches the doped region 7236a. Source metal contact 7226a electrically couples the source terminal of the semiconductor device. In the second semiconductor device 7204, a source metal contact 7226b extends through the barrier layer 6818 into the channel layer 6816 and reaches the doped region 7236b. Source metal contact 7226b electrically couples the source terminal of the semiconductor device and the doped region 7236b. Source coupling field plates 6828a and 6828b are electrically coupled to the respective source metal contacts 7226a and 7226b and extend laterally therefrom onto the gate layers 6820a and 6820b.

[0233] As used herein, the term "coupled" may encompass any connection, communication, or signal path that supports a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, but the intermediate component C does not alter the functional relationship between devices A and B, such that device B is controlled by device A via the control signal generated by device A.

[0234] Also, in this specification, the recitation “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may vary depending on Y and any number of other factors.

[0235] A device that is "configured" to perform a task or function may be configured (e.g., programmed and / or hardwired) at the time of manufacture by the manufacturer to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be programmable through the device's firmware and / or software, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0236] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless explicitly stated to the contrary, these terms are generally used to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0237] A circuit or device described herein as including specific components may actually be adapted to be coupled to these components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or IC package), and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacture, such as by an end user and / or a third party, to form the described structure.

[0238] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used with minimal or no changes to the remaining circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs), bipolar junction transistors (BJTs, such as NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, extended drain mode devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0239] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0240] When a FET is "on" or "enabled" in this article, it means that the FET's conduction channel is present and drain current can flow through the FET. When a FET is "off" or "disabled" in this article, it means that the conduction channel is not present, so drain current cannot flow through the FET. However, an "off" FET may have current flowing through the transistor's body diode.

[0241] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality that was available before the components were replaced. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component can be a plurality of resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor, respectively.

[0242] Although some elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) integrated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0243] Use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0244] In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means no more than + / - 10% from the parameter, or if the parameter is zero, within a reasonable range of about zero.

[0245] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

[0246] Although various examples have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the scope defined by the appended claims.

Claims

1. An integrated circuit IC, comprising: semiconductor substrates; a channel layer on the semiconductor substrate, wherein the channel layer comprises gallium nitride (GaN) material; a barrier layer on the channel layer; a first semiconductor device on the semiconductor substrate, the first semiconductor device including a first terminal above the barrier layer, and the first semiconductor device having a first threshold voltage; as well as A second semiconductor device on the semiconductor substrate includes a second terminal above the barrier layer and has a second threshold voltage different from the first threshold voltage, wherein the first and second threshold voltages are both positive or negative voltages. 2 . The IC of claim 1 , wherein the first terminal comprises a first semiconductor layer, and the second terminal comprises a second semiconductor layer. 3 . The IC of claim 2 , wherein each of the first and second semiconductor layers comprises a p-type doped GaN layer.

4. The IC of claim 2 , wherein the first semiconductor device is a first enhancement mode high electron mobility transistor (HEMT), the first terminal is a first gate of the first enhancement mode HEMT, and the first enhancement mode HEMT includes a first drain and a first source; and The second semiconductor device is a second enhancement-mode HEMT, the second terminal is a second gate of the second enhancement-mode HEMT, and the second enhancement-mode HEMT includes a second drain and a second source.

5. The IC of claim 4 , wherein the first enhancement-mode HEMT comprises a first metal contact on the first semiconductor layer, the first metal contact forming a junction with the first semiconductor layer, the junction being a Schottky junction or an Ohmic junction; and The first enhancement-mode HEMT includes a first diode terminal electrically coupled to the first source and the first metal contact, and a second diode terminal electrically coupled to the first drain.

6. The IC of claim 2 , wherein the first semiconductor device includes a first metal contact on the first semiconductor layer, the first terminal is configured as a first diode terminal, the first metal contact forms an ohmic junction with the first semiconductor layer, and the first semiconductor device includes a third terminal configured as a second diode terminal.

7. The IC of claim 1 , wherein the first semiconductor device is a first depletion-mode HEMT, the first terminal is a first gate of the first depletion-mode HEMT, the first terminal being on a first dielectric layer; and The second semiconductor device is a second depletion-mode HEMT, the second terminal is a second gate of the second depletion-mode HEMT, and the second gate is on a second dielectric layer.

8. The IC of claim 1 , wherein the first terminal comprises a first semiconductor layer over a surface of the barrier layer, the first semiconductor layer having a first thickness over the surface of the barrier layer; and The second terminal comprises a second semiconductor layer above the surface of the barrier layer, the second semiconductor layer having a second thickness above the surface of the barrier layer, the second thickness being different from the first thickness.

9. The IC of claim 1, wherein the first terminal is on the barrier layer and the second terminal extends into the barrier layer.

10. The IC of claim 1 , wherein: The first semiconductor device is a HEMT, the first terminal is a gate, and the first semiconductor device includes: drain; source; semiconductor layer; as well as A third metal contact is on the semiconductor layer, the third metal contact being electrically coupled to the drain.

11. The IC of claim 1 , wherein: The barrier layer comprises: a first blocking sublayer over the channel layer, the first blocking sublayer having an opening therethrough; as well as a second barrier sublayer overlying the first barrier sublayer and conformally disposed in the opening to form a recess; The first terminal extends into the recess and onto the second blocking sublayer; and The second terminal is on the barrier layer.

12. The IC of claim 1 , wherein: The channel layer has a first recess; The barrier layer is conformally disposed in the first recess, thereby forming a second recess; The first terminal extends into the second recess; and The second terminal is on the barrier layer and laterally outside the second recess.

13. The IC of claim 1, wherein the first terminal is a first gate having a first gate length, and the second terminal is a second gate having a second gate length different from the first gate length.

14. The IC of claim 1 , wherein the first semiconductor device includes a first metal contact on the first terminal, the first metal contact having the same lateral footprint as the first terminal; and The second semiconductor device includes a second metal contact on the second terminal, and the second metal contact has a different lateral footprint than the second terminal.

15. The IC of claim 1, wherein the first and second terminals have different compositions.

16. The IC of claim 15, wherein the first terminal comprises a first semiconductor layer, the second terminal comprises a second semiconductor layer, and the first and second semiconductor layers have different dopant concentrations.

17. The IC of claim 1, wherein the first terminal is on a first dielectric layer, the second terminal is on a second dielectric layer, and the first and second dielectric layers have different dielectric constants.

18. The IC of claim 1, wherein the semiconductor substrate includes an isolation structure between the first and second semiconductor devices.

19. The IC of claim 1, wherein both the first and second semiconductor devices have first and second positive threshold voltages, respectively, and the IC further comprises a third semiconductor device on the semiconductor substrate, the third semiconductor device having a third negative threshold voltage.

20. The IC of claim 1, wherein both the first and second semiconductor devices have first and second negative threshold voltages, respectively, and the IC further comprises a third semiconductor device on the semiconductor substrate, the third semiconductor device having a third positive threshold voltage.

21. The IC of claim 1, wherein the first semiconductor device is a first depletion-mode HEMT and the second semiconductor device is a second depletion-mode HEMT.

22. The IC of claim 21 , wherein the first depletion-mode HEMT has a first gate on a first dielectric layer, the second depletion-mode HEMT has a second gate on a second dielectric layer, and the first and second dielectric layers have at least one of: different thicknesses or different dielectric constants.

23. An IC comprising: semiconductor substrates; a first HEMT on the semiconductor substrate, the first HEMT coupled between a power terminal and a switch terminal; a second HEMT on the semiconductor substrate, the second HEMT coupled between the switch terminal and a ground terminal; as well as A diode is provided on the semiconductor substrate, the diode being coupled between the switch terminal and the ground terminal, the diode having a different threshold voltage than at least one of the first HEMT and the second HEMT.

24. The IC of claim 23, wherein the diode is a diode-connected HEMT.

25. An IC comprising: semiconductor substrates; a first depletion-mode HEMT on the semiconductor substrate, the first depletion-mode HEMT coupled between a power terminal and a clamp terminal, the first depletion-mode HEMT having a first threshold voltage; an enhancement-mode HEMT on the semiconductor substrate, the enhancement-mode HEMT coupled between the clamp terminal and a ground terminal, the enhancement-mode HEMT having a gate terminal; as well as a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being electrically coupled to the clamp terminal, the second comparator input being electrically coupled to a reference terminal, and the comparator output being electrically coupled to the gate terminal, the comparator including a second depletion-mode HEMT on the semiconductor substrate, the second depletion-mode HEMT having a second threshold voltage different from the first threshold voltage.

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