Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof. The preparation method comprises the following steps: providing a silicon substrate, wherein the silicon substrate is provided with a first surface and a second surface which are oppositely arranged; forming a tunneling layer on the first surface and / or the second surface; forming a first dielectric layer on one side, far away from the silicon substrate, of the tunneling layer; forming a first doping layer on one side, far away from the tunneling layer, of the first dielectric layer; and annealing to convert the first dielectric layer and the first doped layer into a passivation contact layer. According to the invention, the first dielectric layer is prepared between the tunneling layer and the doping layer, so that the doping agent can be prevented from diffusing inwards during annealing, and the metal slurry can be effectively prevented from burning through or damaging the passivation contact layer during electrode preparation. On one hand, the passivation effect of the passivation contact layer can be improved, thereby improving the open-circuit voltage; on the other hand, the overall thickness of the passivation contact layer can be reduced, parasitic light absorption of the passivation contact layer is reduced, light absorption is improved, and then short-circuit current is improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaics, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] Currently, the development of solar cell technology aims to improve photoelectric conversion efficiency and reduce production costs. Building on the PERC cell (Passivated Emitter and Rear Cell), TOPCon (Tunnel Oxide Passivated Contact) cells, due to their superior backlight passivation and efficient current transmission capabilities, can improve photoelectric conversion efficiency. Currently, they have reached a high conversion efficiency of 24.8%, making them a key research focus in the photovoltaic industry.

[0003] The tunneling passivation contact structure is usually composed of a tunneling layer and a doped polysilicon layer (poly layer). However, in the poly layer preparation process, there is a risk of the tunneling layer being damaged, which affects the passivation effect and restricts the improvement of battery efficiency.

[0004] In view of this, it is necessary to provide an improved solar cell and a preparation method thereof to solve the above technical problems. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. The present invention provides a solar cell and a method for preparing the same, which optimizes the preparation process, maintains an excellent passivation effect, and further improves the photoelectric conversion efficiency of the solar cell.

[0006] In order to achieve one of the above-mentioned objects, the present invention adopts the following technical solution:

[0007] A method for preparing a solar cell comprises the following steps: providing a silicon substrate having a first surface and a second surface disposed opposite to each other; forming a tunneling layer on the first surface and / or the second surface of the silicon substrate; forming a first dielectric layer on a side of the tunneling layer remote from the silicon substrate; forming a first doped layer on a side of the first dielectric layer remote from the tunneling layer; and annealing to transform the first dielectric layer and the first doped layer into a passivation contact layer.

[0008] In some embodiments, during annealing, the dopant of the first doping layer diffuses into the first dielectric layer; after annealing, the first dielectric layer is transformed into a conductive passivation layer, and the conductive passivation layer and the annealed first doping layer together constitute the passivation contact layer.

[0009] In some embodiments, before annealing, the first dielectric layer and the first doped layer have the same crystal structure; and / or the conductive passivation layer and the first doped layer after annealing have the same crystal structure.

[0010] In some embodiments, an intrinsic amorphous silicon layer is formed on a side of the tunneling layer away from the silicon substrate as the first dielectric layer; or, an intrinsic amorphous silicon layer is deposited as the first dielectric layer using a PECVD process, with a silane flow rate of 2500sccm to 4500sccm; a hydrogen flow rate of 10000sccm to 16000sccm; a deposition temperature of 380°C to 480°C; a chamber pressure of 2000mTorr to 4000mTorr; a deposition power of 9000W to 20000W; a duty cycle range of 1:(5 to 20); and a deposition time of 30s to 100s.

[0011] In some embodiments, the thickness of the first dielectric layer is 1 nm to 15 nm.

[0012] In some embodiments, the thickness of the first doping layer is 20 nm to 60 nm.

[0013] In some embodiments, the first doped layer is a phosphorus-doped amorphous silicon layer; and / or, a doped amorphous silicon layer is deposited using a PECVD process as the first doped layer.

[0014] In some embodiments, the method for preparing the solar cell further includes forming a second doping layer on a side of the first doping layer away from the first dielectric layer, and the doping concentration of the first doping layer is not greater than the doping concentration of the second doping layer; or the method for preparing the solar cell further includes forming a second doping layer between the first doping layer and the first dielectric layer, and the doping concentration of the first doping layer is not less than the doping concentration of the second doping layer.

[0015] In some embodiments, the method for preparing a solar cell further includes forming a second dielectric layer between the first doping layer and the second doping layer; and / or

[0016] The first doping layer and the second doping layer are both phosphorus-doped amorphous silicon layers; or, the first doping layer and the second doping layer are formed by a PECVD process, and the flow rate of phosphine in forming the first doping layer and the second doping layer close to the silicon substrate is not greater than the flow rate of phosphine in forming the first doping layer and the second doping layer far from the silicon substrate; and / or the time for forming the first doping layer and the second doping layer far from the substrate is not greater than the time for forming the first doping layer and the second doping layer far from the silicon substrate; or, The first doped layer or the second doped layer is deposited by the PECVD process, with a silane flow rate of 2500 sccm to 4500 sccm; a hydrogen flow rate of 10000 sccm to 16000 sccm; a phosphine flow rate of 50 sccm to 2000 sccm; a deposition temperature of 380°C to 480°C; a chamber pressure of 2000 mTorr to 4000 mTorr; a deposition power of 9000 W to 20000 W; a duty cycle range of 1:(5 to 20); and a deposition time of 30 s to 600 s.

[0017] In some embodiments, the thickness of the second doping layer accounts for 10% to 90% of the sum of the thicknesses of the first doping layer and the second doping layer; and / or the thickness of the first doping layer is 3nm to 15nm, and the thickness of the second doping layer is 20nm to 40nm; or the thickness of the first doping layer is 20nm to 40nm, and the thickness of the second doping layer is 3nm to 15nm.

[0018] In some embodiments, the method for preparing the solar cell further includes forming a third doping layer between the tunneling layer and the first dielectric layer, wherein the doping concentration of the first doping layer is not less than the doping concentration of the third doping layer.

[0019] In some embodiments, the doping concentration of the first doping layer is 1.2-5 times the doping concentration of the third doping layer.

[0020] In some embodiments, the thickness of the first doping layer is 60 nm to 120 nm; and / or the thickness of the third doping layer is 10 nm to 20 nm.

[0021] In some embodiments, the annealing temperature is 850° C. to 950° C., and the annealing time is 1800s to 2600s or 1800s to 2600s; or, after annealing, the sheet resistance of the passivation contact layer is 50Ω / sq to 65Ω / sq, and / or the doping concentration of the passivation contact layer is 6e+20cm -3 .

[0022] In some embodiments, the silicon substrate is an N-type silicon wafer, the first surface is the light-receiving surface, and the second surface is the backlight surface; a tunneling layer and a passivation contact layer are formed on both the first surface and the second surface of the silicon substrate, the passivation contact layer located on the light-receiving side has an opposite doping type to that of the silicon substrate, and the passivation contact layer located on the backlight side has the same doping type as that of the silicon substrate.

[0023] In some embodiments, the silicon substrate is an N-type silicon wafer, the first surface is the backlight surface, and the second surface is the light-receiving surface; a tunneling layer and a passivation contact layer are formed on the side where the light-receiving surface is located, the second surface has an electrode area and a non-electrode area, and the passivation contact layer of the non-electrode area is removed.

[0024] A solar cell is prepared by any of the above-mentioned methods for preparing a solar cell.

[0025] The present invention has the following beneficial effects: The solar cell fabrication method of the present invention forms a first dielectric layer between the tunneling layer and the first doping layer. This first dielectric layer can reduce ion damage to internal film layers such as the tunneling layer during subsequent fabrication of the doping layer; prevent dopants from diffusing inward during annealing, preventing dopants from passing through the tunneling layer and improving the crystallization rate during the annealing process; and effectively prevent metal slurry from burning through or damaging the passivation contact layer during electrode fabrication. This layer maintains good lateral transmission resistance and enhances back surface field passivation, significantly improving the conversion efficiency of the cell.

[0026] Overall, the introduction of the first dielectric layer can, on the one hand, enhance the passivation effect of the passivation contact layer, thereby increasing the open-circuit voltage. It can also reduce the overall thickness of the passivation contact layer, reducing the parasitic absorption of light by the passivation contact layer, thereby increasing light absorption and, in turn, the short-circuit current. Overall, this can increase the efficiency of existing cells to around 25.5%, or even to 26% or above. It can also reduce special gas consumption and process time, effectively lowering production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of preparing a first tunneling layer and a first passivation contact layer on the first surface (backlight side) of a silicon substrate in one embodiment of the present invention.

[0028] Figure 2 This is a schematic diagram of preparing a first tunneling layer and a first passivation contact layer on the first surface (backlight side) of a silicon substrate in another embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of preparing a first tunneling layer and a first passivation contact layer on the first surface (backlight side) of a silicon substrate in another embodiment of the present invention.

[0030] Figure 4This is a schematic diagram of preparing a first tunneling layer and a first passivation contact layer on the first surface (backlight side) of a silicon substrate in another embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram of preparing a first tunneling layer and a first passivation contact layer on the first surface (backlight side) of a silicon substrate in another embodiment of the present invention.

[0032] Figure 6 Schematic diagram of preparing a second tunneling layer and a second passivation contact layer on the second surface (light-receiving surface) of a silicon substrate in one embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram of preparing a second tunneling layer and a second passivation contact layer on the second surface (light-receiving surface) of a silicon substrate in another embodiment of the present invention.

[0034] Figure 8 Schematic diagram of the structure of a solar cell in one embodiment of the present invention.

[0035] Figure 9 Schematic diagram of the structure of a solar cell in another embodiment of the present invention.

[0036] Figure 10 1 is an ECV curve diagram of the solar cell of Example 1 and Comparative Example 1.

[0037] Among them, 100-solar cell, 1-silicon substrate, 11-first surface, 12-second surface, 13-electrode area, 14-non-electrode area; 2-first passivation contact structure, 21-first tunneling layer, 20-first passivation contact layer; 22-first dielectric layer, 23-first doping layer, 24-second doping layer, 25-second dielectric layer, 26-third doping layer, 3-first anti-reflection layer, 4-first electrode, 5-second passivation contact structure, 51-second tunneling layer, 52-second passivation contact layer, 53-boron diffusion layer, 6-passivation layer, 7-second anti-reflection layer, 8-second electrode. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by those skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0039] In the various drawings of the present invention, for the sake of convenience, some sizes of structures or parts are exaggerated relative to other structures or parts, and thus, are only used to illustrate the basic structure of the subject matter of the present invention.

[0040] Please refer to Figures 1 to 7 1 , which illustrates a method for preparing a solar cell according to a preferred embodiment of the present invention.

[0041] The method for preparing a solar cell includes the following steps: providing a silicon substrate 1 having a first surface 11 and a second surface 12 disposed opposite each other; forming a tunneling layer on the first surface 11 and / or the second surface 12 of the silicon substrate 1; forming a first dielectric layer 22 on a side of the tunneling layer remote from the silicon substrate 1; forming a first doped layer 23 on a side of the first dielectric layer 22 remote from the tunneling layer; and performing annealing to transform the first dielectric layer 22 and the first doped layer 23 into a passivating contact layer.

[0042] By forming a first dielectric layer 22 between the tunneling layer and the first doped layer 23, the present invention prevents dopants from diffusing inward during annealing, enhancing structural stability, effectively reducing degradation of the tunneling layer during high-temperature annealing, and preventing an increase in interface composite density. It also effectively prevents metal slurry from burning through or damaging the passivation contact layer during electrode preparation. This improves the passivation effect of the passivation contact layer, thereby increasing the open-circuit voltage. It also reduces the overall thickness of the passivation contact layer, reducing its parasitic absorption of light, increasing light absorption, and thus increasing short-circuit current. Overall, it can increase existing cell efficiency to 26% or above. It can also reduce special gas consumption and process time, effectively lowering production costs.

[0043] The silicon substrate is an N-type silicon wafer with a resistivity of 0.3Ω·cm to 7Ω·cm, preferably 1Ω·cm to 3.5Ω·cm, so as to take into account both carrier migration efficiency and electrical conductivity.

[0044] Furthermore, the silicon substrate 1 is a single crystal silicon wafer that has been subjected to alkali polishing, and its surface has good flatness and cleanliness, ensuring the deposition uniformity and passivation effect of subsequent film layers.

[0045] One of the first surface 11 and the second surface 12 faces the sun and is called the light-receiving surface (primary light-receiving surface), while the other faces away from the sun and is called the backlight surface (secondary light-receiving surface). The following describes the preparation method of the present invention using the first surface 11 as the backlight surface and the second surface 12 as the light-receiving surface as an example.

[0046] For ease of description, the tunneling layer formed on the side of the first surface 11 is referred to as the first tunneling layer 21, and the tunneling layer formed on the side of the second surface 12 is referred to as the second tunneling layer 51. The passivation contact layer can be formed on the side of the first surface 11 and is referred to as the first passivation contact layer 20. It can also be formed on the side of the second surface 12 and is referred to as the second passivation contact layer 52.

[0047] The dopant in the first doping layer 23 may be a P-type dopant or an N-type dopant. P-type dopants include, but are not limited to, boron, aluminum, etc. N-type doping layers include, but are not limited to, phosphorus, arsenic, etc.

[0048] A P-type dopant is doped into the first doping layer 23 to form a P-type passivation contact layer; and an N-type dopant is doped into the first doping layer 23 to form an N-type passivation contact layer.

[0049] The present invention selects the dopant type based on the cell structure. In one embodiment, the first doped layer 23 on the light-receiving side has a doping type opposite to that of the silicon substrate 1, while the first doped layer 23 on the backlight side has a doping type identical to that of the silicon substrate 1. Alternatively, the first doped layer 23 on the light-receiving side may have a doping type identical to that of the silicon substrate 1, while the first doped layer 23 on the backlight side has a doping type opposite to that of the silicon substrate 1. All doped layers on the first surface 11 side have a consistent doping type, while all doped layers on the second surface 12 side have a consistent doping type.

[0050] In one specific embodiment, the silicon substrate 1 is an N-type single-crystal silicon wafer, with a first surface 11 serving as the backlight side and a second surface 12 serving as the light-receiving side. The first doped layer 23 located on the side of the first surface 11 is a phosphorus-doped layer. The first doped layer 23 located on the side of the second surface 12 is a boron-doped layer. The present invention will be described primarily using this example.

[0051] Please refer to Figures 1 to 5 As shown, the present invention directly forms the first tunneling layer 21 on the first surface 11 (backlight surface), which can form an effective chemical passivation effect on the surface of the silicon substrate 1 and provide an efficient tunneling transmission path for realizing rapid transfer of carriers.

[0052] The first tunneling layer 21 is a silicon oxide layer (Si x O y ), a combination of one or more silicon carbide layers (SiC), which achieves efficient electron transmission through the tunneling effect, while providing chemical passivation function and reducing interface recombination losses.

[0053] The silicon oxide layer is stable in high-temperature environments and has excellent chemical passivation properties. The silicon carbide layer can further enhance electrical properties and reduce interface resistance while maintaining the passivation effect.

[0054] The thickness of the first tunneling layer 21 is controlled within the range of 0.5nm to 3nm, preferably 1nm to 2nm or 1.6nm to 1.8nm. A too thin tunneling layer may lead to insufficient passivation and increased interfacial recombination; while an overly thick tunneling layer may hinder carrier tunneling and reduce battery performance.

[0055] In one embodiment of the present invention, the first tunneling layer 21 may be deposited using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. By precisely controlling the deposition time and gas flow rate, the first tunneling layer 21 with a uniform thickness may be obtained.

[0056] Taking the deposition of a silicon oxide layer as the first tunneling layer 21 as an example, the silicon substrate 1 is placed in a deposition device (such as a tube furnace), and nitrous oxide is introduced as a reaction gas to deposit a first silicon oxide tunneling layer 21 with a thickness of 0.5 nm to 3 nm, thereby reducing interface recombination losses and providing excellent tunneling current transmission capability.

[0057] Specifically, the flow rate of nitrous oxide is controlled to be 8000sccm to 13000sccm, preferably 10000sccm to 12000sccm. The deposition temperature is 380℃ to 480℃, preferably 420℃ to 440℃. The chamber pressure is 1500mTorr to 2300mTorr, preferably 1600mTorr to 2000mTorr. The deposition power is 9000W to 20000W, preferably 10000W to 16000W. The duty cycle range is 1:(50 to 120), preferably 1:(80 to 100), and the deposition time is 60s to 100s, forming a first silicon oxide tunneling layer 21 with a thickness of 0.5nm to 3nm, which is used to improve the interface chemical passivation effect and realize efficient electron transmission through the tunneling effect.

[0058] The duty cycle is the effective time of discharge per unit time, and its value affects the deposition rate of the film layer.

[0059] In a specific embodiment, the deposition temperature is 430° C.; the nitrous oxide flow rate is 11,000 sccm; the chamber pressure is 1,800 mTorr; the deposition power is 13,000 W; the duty cycle range is 1:90; and a silicon oxide layer with a thickness of 1.5 nm is deposited as the first tunneling layer 21 .

[0060] Please refer to Figure 1 As shown, a first dielectric layer 22 and a first doped layer 23 are formed on the side of the first tunneling layer 21 facing away from the silicon substrate 1. During the annealing process, the dopant in the first doped layer 23 diffuses into the first dielectric layer 22. After annealing, the first dielectric layer 22, due to the incorporation of the dopant, is transformed into a conductive passivation layer. The conductive passivation layer and the annealed first doped layer 23 together constitute the first passivation contact layer 20. The first passivation contact layer 20 and the first tunneling layer 21 together passivate the surface of the silicon substrate 1 and achieve selective carrier collection.

[0061] In one embodiment of the present invention, before annealing, the first dielectric layer 22 and the first doping layer 23 have the same crystal structure, which facilitates dopant internal diffusion and doping during annealing. Furthermore, / or, the conductive passivation layer formed after annealing has the same crystal structure as the first doping layer 23 after annealing, thereby improving passivation and carrier collection.

[0062] In one embodiment, before annealing, the first dielectric layer 22 and the first doped layer 23 are each a combination of one or more of an amorphous silicon layer, a microcrystalline layer, and a polycrystalline layer. After annealing, the conductive passivation layer and the first doped layer 23 are both polycrystalline silicon layers, which reduces lattice defects and lowers carrier recombination.

[0063] In some embodiments, the first dielectric layer 22 is an intrinsic amorphous silicon layer. During the annealing process, the dopant can diffuse well and be converted into a doped polysilicon layer. The first dielectric layer 22 can enhance the chemical passivation effect and prevent the dopant (phosphorus) in subsequent steps from diffusing into the silicon substrate 1.

[0064] An intrinsic amorphous silicon layer is formed on a side of the first tunneling layer 21 away from the silicon substrate 1 as the first dielectric layer 22 .

[0065] The present invention uses silane and hydrogen as reaction gases to prepare an intrinsic amorphous silicon layer as the first dielectric layer 22 through a PECVD process. The silane flow rate is 2500 sccm to 4500 sccm, preferably 3000 sccm to 4000 sccm. The hydrogen flow rate is 10000 sccm to 16000 sccm, preferably 11000 sccm to 14000 sccm, and preferably 10000 sccm to 13000 sccm. The deposition temperature is 380°C to 480°C, preferably 420°C to 440°C. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000 W to 20000 W, preferably 10000 W to 16000 W. The duty cycle range is 1:(5 to 20), preferably 1:(5 to 10). The deposition time is 30s to 100s, and the deposition thickness is 1-15nm, preferably 3nm to 10nm, or preferably 1nm to 2nm.

[0066] In one embodiment, the silane flow rate is 3500 sccm; the hydrogen flow rate is 12500 sccm; the deposition temperature is 430° C.; the chamber pressure is 3000 mTorr; the deposition power is 13000 W; the duty cycle range is 1:8; and the deposition thickness is 1.5 nm.

[0067] In some embodiments, the first doped layer 22 formed on the backlight side is a phosphorus-doped amorphous silicon layer. The phosphorus-doped amorphous silicon layer and the intrinsic amorphous silicon layer have substantially the same crystal structure, and the two are highly compatible. During the annealing process, phosphorus diffuses into the intrinsic amorphous silicon layer without encountering any additional obstacles. After annealing, the two layers form a phosphorus-doped polycrystalline silicon layer with a substantially identical crystal structure. There is no distinct interface between the two layers, which facilitates carrier transport and collection, thereby improving battery efficiency.

[0068] The present invention adopts a PECVD process to form the first doped layer 22 on the side where the backlight surface is located. A first doped amorphous silicon layer is deposited on the side where the backlight surface is located as the first doped layer 22 using a PECVD process. The flow rate of silane is 2500sccm to 4500sccm, preferably 3000sccm to 4000sccm. The flow rate of hydrogen is 10000sccm to 16000sccm, preferably 11000sccm to 14000sccm, or preferably 10000sccm to 13000sccm. The flow rate of phosphine is 50sccm-2000sccm, preferably 100sccm-1000sccm, preferably 100sccm-2000sccm, preferably 300sccm to 600sccm, preferably 150sccm to 300sccm. The deposition temperature is 380℃ to 480℃, preferably 420℃ to 440℃. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000 W to 20000 W, preferably 10000 W to 16000 W. The duty cycle ranges from 1:(5 to 20), preferably 1:(5 to 10). The deposition time is 30 s to 600 s. The deposition thickness is 20 nm to 60 nm, preferably 23 nm to 55 nm, or preferably 40 nm to 60 nm.

[0069] In one embodiment, the silane flow rate is 3500 sccm; the hydrogen flow rate is 12500 sccm; the phosphine flow rate is 450 sccm; the deposition temperature is 430°C; the chamber pressure is 3000 mTorr; the deposition power is 13000 W; the duty cycle range is 1:8; the deposition thickness is 55 nm, and the phosphorus doping concentration is 1E21 cm -3 .

[0070] In addition, the thickness of the first dielectric layer 22 and the doping concentration and thickness of the first doping layer 23 are key factors that determine the optical and electrical properties of the first passivation contact layer 20 .

[0071] In one embodiment, the thickness of the first dielectric layer is 1 nm to 15 nm, preferably about 5 nm. If the first dielectric layer is too thin, it cannot block the diffusion of dopants and metal pastes; if it is too thick, it will affect carrier transport after the battery is formed.

[0072] The thickness of the first doping layer 23 is controlled to be between 23 nm and 55 nm, ensuring good contact with the metal electrode and preventing the metal electrode from burning through the first doping layer 23 and damaging the first passivation contact layer 20 .

[0073] In some embodiments, the doping concentration of the first passivation contact layer 20 gradually increases in a direction away from the silicon substrate 1 , which is more conducive to the separation and collection of carriers and improves the battery efficiency.

[0074] Please refer to Figure 2 As shown, in one embodiment, the solar cell manufacturing method further includes forming a second doping layer 24 on a side of the first doping layer 23 away from the first dielectric layer 22. Compared to the above embodiment, layered deposition of doping layers allows for more flexible control of the doping concentration distribution and film quality of the first passivation contact layer 20.

[0075] The doping concentration of the first doping layer 23 is no greater than the doping concentration of the second doping layer 24. The doping concentration of the second doping layer 24 farther from the silicon substrate 1 is higher, while the doping concentration of the first doping layer 23 closer to the silicon substrate 1 is lower. During the annealing process, dopants diffuse inward, facilitating the formation of a first passivation contact layer 20 with a gradient doping concentration, thereby enhancing carrier separation and transport. The thickness distribution of the first doping layer 23 and the second doping layer 24 is designed based on different functional requirements.

[0076] In one embodiment, the thickness of the second doped layer 24 accounts for 10% to 90% of the combined thickness of the first doped layer 23 and the second doped layer 24, preferably 35% to 90%, and more preferably 50% to 70%. This reduces contact resistance while maintaining low optical absorption. By adjusting the doping concentration and thickness distribution, current transmission performance and contact characteristics can be optimized.

[0077] In one embodiment, the thickness of the first doped layer 23 is 3 nm to 15 nm, preferably about 5 nm, to maintain good passivation and provide adequate carrier mobility. The thickness of the second doped layer 24 is 20 nm to 40 nm, preferably about 30 nm, to reduce contact resistance and improve current collection efficiency.

[0078] For the combined design of the first doping layer 23 and the second doping layer 24, the thickness of the first doping layer 23 is controlled to be 3nm to 15nm to enhance the interface passivation effect and reduce the recombination loss. Its doping concentration is 1E18cm-3 ~1E20cm -3 , ensuring proper conductivity and reducing carrier recombination. The thickness of the second doping layer 24 is 20nm to 40nm, and its doping concentration is 1E19cm -3 ~1E21cm -3 , by enhancing conductivity through high-concentration doping, reducing contact resistance and improving current collection efficiency.

[0079] Through the above design, the solar cell 100 of the present invention reasonably distributes the doping concentration and thickness ratio of the first doping layer 23 and the second doping layer 24, so that the passivation contact structure 2 significantly reduces the contact resistance and enhances the carrier transfer efficiency while ensuring an excellent passivation effect, thereby achieving a good balance between electrical performance and contact performance, thereby achieving higher photoelectric conversion efficiency and good production adaptability.

[0080] It should be noted that, referring to Figure 3 By reasonable arrangement, the second doping layer 24 can also be arranged between the first doping layer 23 and the first dielectric layer 22. In this case, the concentration of the first doping layer 23 is not less than the concentration of the second doping layer 24. In this way, the same technical effect as the aforementioned solution (arranging the second doping layer 24 on the side of the first doping layer 23 away from the first dielectric layer 22) can still be obtained.

[0081] In this embodiment, it is equivalent to Figure 2 The positions of the first doping layer 23 and the second doping layer 24 are swapped, and other parameters remain unchanged.

[0082] In summary, the maximum thickness of the passivation contact structure 2 is controlled to be 50nm to 60nm. This thickness range effectively reduces parasitic absorption, improves short-circuit current (Isc), and cell efficiency while maintaining excellent backlight passivation. Furthermore, by controlling the overall thickness range, both the uniformity of the thin film material and the controllability of the preparation process are taken into account, thus ensuring production consistency and reliability.

[0083] In some embodiments, the first doping layer 23 and the second doping layer 24 formed on the side where the backlight surface is located are both phosphorus-doped amorphous silicon layers. The present invention uses a PECVD process to form the first doping layer 23 and the second doping layer 24 on the side where the backlight surface is located. The flow rate of phosphine used to form the doping layer close to the silicon substrate 1 in the first doping layer 23 and the second doping layer 24 is not greater than the flow rate of phosphine used to form the doping layer 24 far from the silicon substrate 1 in the first doping layer 23 and the second doping layer 24; and / or the time for forming the doping layer close to the silicon substrate 1 in the first doping layer 23 and the second doping layer 24 is not greater than the time for forming the doping layer far from the silicon substrate 1 in the first doping layer 23 and the second doping layer 24. By controlling the flow rate and / or deposition time of phosphine, doping layers with different doping concentrations can be obtained.

[0084] In a specific embodiment, a PECVD process is used to deposit the first doping layer 23 and the second doping layer 24, which is closer to the silicon substrate 1, on the side where the backlight is located. The flow rate of silane is 2500 sccm to 4500 sccm, preferably 3000 sccm to 4000 sccm. The flow rate of hydrogen is 10,000 sccm to 16,000 sccm, preferably 11,000 sccm to 14,000 sccm, or preferably 10,000 sccm to 13,000 sccm. The flow rate of phosphine is 50 sccm to 2000 sccm, preferably 100 sccm to 1000 sccm, and preferably 150 sccm to 300 sccm. The deposition temperature is 380°C to 480°C, preferably 420°C to 440°C. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000W to 20000W, preferably 10000W to 16000W. The duty cycle range is 1:(5-20), preferably 1:(5-10). The deposition time is 30s to 600s. The deposition thickness is 3nm to 15nm, preferably 5nm±2nm.

[0085] The first doping layer 23 and the second doping layer 24, which are closer to the silicon substrate 1, are deposited on the backlight side using a PECVD process. The flow rate of silane is 2500 sccm to 4500 sccm, preferably 3000 sccm to 4000 sccm. The flow rate of hydrogen is 10000 sccm to 16000 sccm, preferably 11000 sccm to 14000 sccm, or preferably 10000 sccm to 13000 sccm. The flow rate of phosphine is 200 sccm to 2000 sccm, preferably 300 sccm to 1000 sccm, and preferably 300 sccm to 600 sccm. The deposition temperature is 380°C to 480°C, preferably 420°C to 440°C. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000W to 20000W, preferably 10000W to 16000W. The duty cycle range is 1:(5-20), preferably 1:(5-10). The deposition time is 30s to 600s. The deposition thickness is 20nm to 40nm, preferably 30nm±2nm.

[0086] Please refer to Figure 5 As shown, in some embodiments, the method for preparing the solar cell further includes: forming a second dielectric layer 25 between the second doping layer 24 and the first doping layer 23 .

[0087] The introduction of the second dielectric layer 25 can prevent the high-concentration dopant in the outer layer from diffusing inward, and can reduce the damage to the internal second doping layer 24 and the first tunneling layer 21 caused by ion ionization when forming the first doping layer 23; it can also improve the crystallization rate of the post-annealing process, while retaining good lateral transmission resistance and improving the back surface field passivation effect, greatly improving the conversion efficiency of the battery.

[0088] The thickness of the second dielectric layer 25 is within the same range as the thickness of the first dielectric layer 22. In one embodiment, the thickness of the second dielectric layer 25 is not less than the thickness of the first dielectric layer 22, thereby enhancing the protection of the internal film layers. In another embodiment, the thickness of the second dielectric layer 25 is not less than the thickness of the first dielectric layer 22, thereby facilitating the formation of a high-quality first passivation contact layer 20.

[0089] Please refer to Figure 4 As shown, in some embodiments, the method for preparing the solar cell further includes forming a third doping layer 26 between the tunneling layer 21 and the first dielectric layer 22 .

[0090] The doping concentration of the first doping layer 23 is no less than the doping concentration of the third doping layer 26. The doping concentration of the first doping layer 23 is higher in areas farther from the silicon substrate 1, while the doping concentration of the third doping layer 26 is lower in areas closer to the silicon substrate 1. During the annealing process, dopants diffuse inward, facilitating the formation of a first passivation contact layer 20 with a suitable doping gradient, thereby enhancing carrier separation and transport. The combination of the first doping layer 23 and the third doping layer 26 provides the first passivation contact layer 20 with a suitable doping concentration gradient, enhancing carrier separation and collection.

[0091] The thickness of the first doping layer 23 is not less than the thickness of the third doping layer 26. The first doping layer 23 is thicker away from the silicon substrate 1, and the third doping layer 26 is thinner near the silicon substrate 1. This effectively prevents dopants from passing through the first tunneling layer 21 and diffusing into the silicon substrate 1, thereby ensuring a passivation effect.

[0092] In one embodiment, the thickness of the third doping layer 26 is 10 nm to 20 nm, preferably about 15 nm, to maintain good passivation and provide appropriate carrier mobility. The thickness of the first doping layer 23 is 60 nm to 120 nm, preferably about 80 nm, to reduce contact resistance and improve current collection efficiency.

[0093] For the combination design of the first doping layer 23 and the third doping layer 26, the thickness of the third doping layer 26 is controlled at 15nm±2nm to enhance the interface passivation effect and reduce the recombination loss. Its doping concentration is 1E18cm -3 ~1E20cm -3 , ensuring proper conductivity and reducing carrier recombination. The thickness of the first doping layer 23 is 20nm to 40nm, and its doping concentration is 1E19cm -3 ~1E21cm -3 , by enhancing conductivity through high-concentration doping, reducing contact resistance and improving current collection efficiency.

[0094] Based on these embodiments, the deposition process of the first doping layer 23 is as follows: the flow rate of silane is 2500 sccm to 4500 sccm, preferably 3000 sccm to 4000 sccm. The flow rate of hydrogen is 10000 sccm to 16000 sccm, preferably 11000 sccm to 14000 sccm, or preferably 10000 sccm to 13000 sccm. The flow rate of phosphine is 200 sccm to 2000 sccm, preferably 300 sccm to 1000 sccm, preferably 300 sccm to 600 sccm. The deposition temperature is 380°C to 480°C, preferably 420°C to 440°C. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000 W to 20000 W, preferably 10000 W to 16000 W. The duty ratio range is 1:(5-20), preferably 1:(5-10). The deposition thickness is 60nm-120nm, preferably 80nm±10nm. The deposition time is 30s-600s.

[0095] The deposition process of the third doping layer 23 is as follows: the flow rate of silane is 2500 sccm to 4500 sccm, preferably 3000 sccm to 4000 sccm. The flow rate of hydrogen is 10000 sccm to 16000 sccm, preferably 11000 sccm to 14000 sccm, or preferably 10000 sccm to 13000 sccm. The flow rate of phosphine is 50 sccm to 2000 sccm, preferably 100 sccm to 1000 sccm, and preferably 150 sccm to 300 sccm. The deposition temperature is 380°C to 480°C, preferably 420°C to 440°C. The chamber pressure is 2000 mTorr to 4000 mTorr, preferably 2500 mTorr to 3500 mTorr. The deposition power is 9000 W to 20000 W, preferably 10000 W to 16000 W. The duty ratio range is 1:(5-20), preferably 1:(5-10). The deposition thickness is 10nm-20nm, preferably 15nm±2nm. The deposition time is 30s-600s.

[0096] The annealing step is completed in an annealing furnace at a temperature of 850°C to 950°C, preferably 880°C to 910°C, for 1800s to 2600s, preferably 1800s to 2500s, or preferably 2000s to 2600s. During this process, the amorphous silicon in the doped layer is gradually transformed into polycrystalline silicon, while optimizing the distribution of dopant atoms and the conductive properties of the film, forming the final first passivation contact layer 20. This step significantly improves the carrier migration efficiency and the backlight side current collection capability.

[0097] Specifically, the annealing process can promote the transformation of amorphous silicon materials into more conductive crystalline silicon and optimize the current transmission characteristics of the battery by adjusting the doping concentration and junction depth. In this process, controlling the junction depth is particularly important, because too deep or too shallow a junction depth will affect the contact resistance, thereby affecting the overall performance of the solar cell.

[0098] Through annealing, the first dielectric layer 22, the first doping layer 23 and the third doping layer 24 can all be optimized, which not only improves the contact performance, but also helps to reduce the contact resistance between the second electrode 8 and the first doping layer 23, thereby enhancing the current collection capability and further improving the photoelectric conversion efficiency of the solar cell.

[0099] Through the above steps, a complete passivation contact structure 2 is constructed layer by layer. Finally, an annealing process is performed to optimize crystallization and doping properties, ensuring that the passivation contact structure 2 has excellent passivation and conductivity. This preparation method balances film quality, production efficiency, and cell performance, providing a reliable solution for the large-scale production of high-efficiency solar cells.

[0100] Based on the above preparation method, it is ensured that the solar cell has optimized passivation effect and conductive performance on both the light-receiving side and the backlight side, thereby greatly improving the photoelectric conversion efficiency and being able to adapt to the large-scale production of high-efficiency solar cells.

[0101] like Figure 6 and Figure 7 As shown, the present invention can also employ any of the aforementioned embodiments to form a second tunneling layer 51 and a second passivation contact layer 52 on the light-receiving side. The only difference lies in the dopant in the doped layer, replacing phosphorus with boron, i.e., replacing phosphine with borane, boron trichloride, or boron tribromide. The corresponding annealing temperature is increased to 900°C-1000°C to facilitate the activation of boron and its internal propagation.

[0102] The second surface 12 (light-receiving surface) of the silicon substrate 1 has an electrode region 13 and a non-electrode region 14 . The second passivation contact layer 52 of the non-electrode region 14 is removed to reduce light absorption by the film layer in the non-electrode region 14 .

[0103] Furthermore, a laser process is used to define the specific positions of the electrode region 13 and the non-electrode region 14, and the second passivation contact layer 52 in the non-electrode region 14 is removed to ensure that the second passivation contact layer 52 remains only on the electrode region 13. In the non-electrode region 14, these deposited thin film layers are removed to avoid optical absorption losses caused by the polysilicon layer.

[0104] Specifically, the second passivation contact layer 52 and the second tunneling layer 51 in the non-electrode region 14 can be removed by laser removal technology, and specifically, ultraviolet picosecond laser or green picosecond laser can be used for local treatment.

[0105] The ultraviolet picosecond laser has a power of 3W to 20W, a spot diameter of 100μm to 150μm, and a scanning speed of 40m / s to 80m / s. The green picosecond laser has a power of 5W to 50W, a spot diameter of 100μm to 500μm, a frequency of 500kHz to 600kHz, and a scanning speed of 40m / s to 80m / s. Laser removal of the deposited film layer in the non-electrode region 14 ensures that the second passivation contact structure 5 is located only within the electrode region 13, avoiding optical and current losses.

[0106] By removing the deposited layer from the non-electrode region 14, the solar cell 100 of the present invention can effectively improve the cell's photoelectric conversion efficiency, reduce optical absorption in the non-electrode region of the light-receiving surface, and ensure a rational and efficient surface structure on the cell's light-receiving surface. This process can be precisely controlled using laser or photolithography techniques, further optimizing the solar cell's optical and electrical performance.

[0107] Of course, if Figure 9 As shown, the light-receiving surface of the silicon substrate 1 can also be formed into a boron diffusion layer 53 by boron diffusion, and the boron diffusion layer 53 serves as a P-type emitter, replacing Figure 8 The second passivation contact structure 5 in the P-type emitter 53 is a boron-doped emitter with a doping concentration of 3E18cm -3 ~3E19cm -3 , the square resistance is 40Ω / sq~300Ω / sq, preferably 100Ω / sq~180Ω / sq.

[0108] Finally, an electrode is formed on the side of the passivation contact layer facing away from the silicon substrate. The electrode located on the first surface 11 is called the first electrode 4, and the electrode located on the second surface 12 is called the second electrode 8.

[0109] Exemplarily, the first electrode is an Ag / Al gate line electrode, and the second electrode is an Ag gate line electrode.

[0110] The present invention adopts screen printing and sintering processes to prepare the electrode, forming a low-ohmic contact with the doping layer 23 to achieve efficient current transmission.

[0111] In one embodiment of the present invention, before preparing the electrodes, the method for preparing the solar cell further includes the following steps: preparing a passivation layer 6 on the light-receiving surface. Preferably, an atomic layer deposition (ALD) process is used to deposit an aluminum oxide layer on the light-receiving surface of the silicon substrate 1. The thickness of the aluminum oxide layer is controlled between 2 nm and 7 nm, preferably 5 nm, to provide excellent chemical passivation, reduce interfacial recombination in the first electrode region 13, and increase the open-circuit voltage. The ALD process can precisely control the thickness of the aluminum oxide layer to ensure uniform deposition, and due to the negative fixed charge of the aluminum oxide layer, it can effectively passivate the silicon surface, thereby improving the stability and efficiency of the solar cell.

[0112] In one embodiment of the present invention, before preparing the electrodes, the method for preparing a solar cell further includes the following steps: forming a first anti-reflection layer 3 and a second anti-reflection layer 7 on the side where the first surface 11 is located and the side where the second surface 12 is located, respectively. The main function of the anti-reflection layer is to reduce the reflectivity of light, increase the light absorptivity, and increase the short-circuit current of the solar cell, thereby enhancing the photoelectric conversion efficiency.

[0113] Specifically, the first anti-reflection layer 3 and the second anti-reflection layer 7 are deposited simultaneously on the light-receiving surface and the backlight surface through a PECVD process.

[0114] The anti-reflection layer uses one or more of silicon nitride, silicon oxynitride, and silicon oxide to form a stacked film structure. Depending on the design requirements, these materials can be used alone or in combination to optimize optical performance and increase solar cell efficiency.

[0115] Specifically, silicon nitride is a preferred anti-reflection material, boasting strong optical properties and excellent thermal stability. It can effectively reduce light reflection from both the illuminated and backlit surfaces, thereby increasing the cell's light absorption rate. Furthermore, silicon oxynitride and silicon oxide, as alternative materials, can be used in conjunction with silicon nitride to further improve the anti-reflection effect, particularly in the design of a second anti-reflection layer, which can enhance light absorption efficiency.

[0116] The thickness of the second anti-reflection layer 7 is controlled to be between 60nm and 130nm, preferably 80nm and 100nm. The thickness of the first anti-reflection layer 3 is also controlled to be between 60nm and 130nm, preferably 80nm. Appropriate materials and thicknesses are selected based on the optical properties of different materials to effectively reduce reflection while ensuring film stability and long-term battery performance.

[0117] By precisely controlling the material and thickness of the anti-reflection layer, the solar cell of this invention effectively reduces optical reflection losses on both the illuminated and backlit surfaces, significantly improving the solar cell's short-circuit current and overall photoelectric conversion efficiency. This anti-reflection design also further enhances the cell's light absorption performance, improving its performance under various lighting conditions.

[0118] The solar cell and the preparation method thereof of the present invention will be described in detail below with specific embodiments.

[0119] Example 1 (please refer to Figure 2 )

[0120] Step 1: Texturing the silicon wafer and performing boron diffusion to form a PN junction.

[0121] In this step, conventional process is used to diffuse boron to form a boron diffusion layer. The doping concentration of the boron diffusion layer is 3E18cm -3 ~3E19cm -3 , the square resistance is 40Ω / sq~300Ω / sq.

[0122] The backlight surface is polished with a polishing alkali solution, and then pickled with acid or RCA cleaned (Radio Corporation of America clean). After the backlight surface is flat, the silicon wafer is inserted into a graphite boat and placed in the furnace tube.

[0123] Step 2. Heat the furnace tube to between 420℃ and 450℃ and keep the temperature constant for 180s.

[0124] Step 3. Prepare a tunneling layer on the backlight side. Nitrous oxide is introduced into the furnace tube at a flow rate of 10,000 sccm to 12,000 sccm for 60 to 100 seconds, and the silicon oxide film thickness is controlled to be 1.6 nm to 1.8 nm.

[0125] Step 4: Prepare an intrinsic amorphous silicon layer. Silane at a flow rate of 3000-4000 sccm and hydrogen at a flow rate of 10000-13000 sccm are introduced into the furnace tube for 30-100 seconds, and the film thickness is controlled to be 3nm-15nm.

[0126] Step 5. Prepare a lightly doped amorphous silicon layer. Silane is introduced into the furnace at a flow rate of 3000-4000 sccm, hydrogen at a flow rate of 10000-13000 sccm, and phosphine at a flow rate of 100-1000 sccm. The reaction time is 30-100 seconds, and the film thickness is controlled to be 3nm-15nm.

[0127] Step 6. Prepare a heavily doped amorphous silicon layer. Silane is introduced into the furnace at a flow rate of 3000-4000 sccm, hydrogen at a flow rate of 10000-13000 sccm, and phosphine at a flow rate of 100-2000 sccm. The reaction time is 300-600 seconds, and the film thickness is controlled to be 20nm-40nm.

[0128] Step 7. After the entire process is complete, the overall film thickness on the backside is controlled between 50nm and 60nm. The silicon wafer is removed from the furnace tube and placed in a quartz boat for annealing within the furnace tube. The annealing temperature is between 880°C and 910°C, and the annealing time is between 2000s and 2600s. The measured overall sheet resistance is between 50Ω and 65Ω, the doping concentration is 6e+20, and the junction depth is between 0.15nm and 0.19nm.

[0129] Step 8. After annealing, use acid to remove PSG on the front and edge of the silicon wafer, use alkali to remove the coating on the front and edge, and finally use HF to remove BSG and PSG.

[0130] Step 9. Prepare a 2nm-7nm aluminum oxide layer as a passivation layer and a 60nm-130nm silicon nitride layer as an anti-reflection layer on the front side of the cleaned silicon wafer, and prepare a silicon nitride layer as an anti-reflection layer on the back side. Finally, print and sinter to form electrodes to form a complete battery cell.

[0131] Comparative Example 1

[0132] The only difference between Comparative Example 1 and Experimental Example 1 is that step 4 is omitted.

[0133] Experimental Example 1 and Comparative Example 1 were tested under the same conditions, and the results are as follows: Figure 2 As shown in Table 1, the efficiency of the two groups is as follows: the open circuit voltage of the experimental group is 0.8mv lower than that of the control group, the short circuit current is 34mA higher, the silver filling (FF) is 0.16 lower, and the efficiency is 0.04% higher.

[0134] Table 1 Electrical performance parameters of solar cells

[0135] Grouping Eta (%) Voc(V) Isc(A) FF(%) Rs(mΩ) Rsh(mΩ) Example 1 26.27 0.7377 7.331 84.78 6.40E-01 3.15E+03 Comparative Example 1 26.23 0.7385 7.297 84.94 6.40E-01 3.11E+03

[0136] Example 2 (please refer to Figure 4 )

[0137] The difference between Example 2 and Example 1 is that:

[0138] The order of step 4 and step 5 is replaced, and the first dielectric layer 22 is located between the third doping layer 26 and the first doping layer 23 .

[0139] Comparative Example 2:

[0140] The only difference between Comparative Example 2 and Experimental Example 2 is that step 4 is omitted.

[0141] After testing, the electrical performance parameters of the solar cells in Example 2 of the present invention and Comparative Example 2 are shown in Table 2.

[0142] Table 2: Electrical performance parameters of solar cells

[0143]

[0144]

[0145] Explanation of symbols in Tables 1 and 2: RUN1 and RUN2 represent two production lines, respectively. Quantity represents the number of solar cells produced on each production line. Eta represents the cell efficiency. Isc represents the dark saturation current. Voc represents the open-circuit voltage. FF represents the fill factor. Rs represents the resistance. Rs is the series resistance, and Rsh is essentially RshuntDr, the shunt resistance measured using linear regression of dark-field reverse bias voltage. IRev2 represents the reverse current.

[0146] As can be seen from Table 2, in Example 2, by adding an intrinsic amorphous silicon layer between the lightly doped polysilicon layer and the heavily doped polysilicon layer, the open circuit voltage (Voc) of the solar cell can be increased by 0.001 V, the fill factor (FF) can be increased by 0.15%, and the conversion efficiency (Eta) can be increased by 0.05% to 0.06%.

[0147] It can be seen from Examples 1 and 2 that the first dielectric layer 22 is disposed on the surface of the first tunneling layer 21 away from the silicon substrate 1, and the doped layers are all located on the side of the first dielectric layer 22 away from the tunneling layer 21, which can better ensure the passivation effect and obtain a higher Voc gain.

[0148] Please refer to Figure 8 and Figure 9 As shown, the present invention further provides a solar cell 100, which can be prepared using the above preparation method.

[0149] The solar cell 100 includes a silicon substrate 1, a first passivation contact structure 2 located on a first surface 11 of the silicon substrate 1, a first electrode 4 in contact with the first passivation contact structure 2; a second passivation contact structure 5 located on a second surface 12 of the silicon substrate 1, and a second electrode 8 in contact with the second passivation contact structure 5.

[0150] The silicon substrate is configured as described above and will not be described in detail herein. The solar cell of the present invention will be described in detail below with the first surface 11 being the backlight surface and the second surface 12 being the light-receiving surface.

[0151] The first passivation contact structure 2 is prepared by the above-mentioned preparation method. The first passivation contact structure 2 includes a first tunneling layer 21 disposed on the first surface 11 and a first passivation contact layer 20 located on a side of the first tunneling layer 21 away from the silicon substrate 1 .

[0152] The material and thickness of the first tunneling layer 21 are as described above. It is directly formed on the surface of the silicon substrate 1 and can provide an efficient tunneling transmission path for realizing rapid transfer of carriers and forming an effective chemical passivation effect at the interface.

[0153] The first passivation contact layer 20 is an N-type doped polysilicon layer, which is prepared by any of the above methods. Preferably, the doping concentration of the first passivation contact layer 20 gradually increases in a direction away from the silicon substrate 1 .

[0154] The overall thickness of the passivation contact structure 2 is controlled between 50nm and 60nm. This means the combined thickness of the first tunneling layer 21 and the first passivation contact layer 20 is between 50nm and 60nm. This thickness range effectively reduces parasitic absorption, improves short-circuit current (Isc), and increases battery efficiency while maintaining excellent backlight passivation. Furthermore, by controlling the overall thickness range, both the uniformity of the thin film material and the controllability of the fabrication process are maintained, ensuring consistent and reliable production.

[0155] Through the above design, the solar cell 100 of the present invention reasonably distributes the doping concentration of the first passivation contact layer 20, so that the passivation contact structure 2 significantly reduces the contact resistance and enhances the carrier transfer efficiency while ensuring an excellent passivation effect, thereby achieving a good balance between electrical performance and contact performance, thereby achieving higher photoelectric conversion efficiency and good production adaptability.

[0156] In one embodiment of the present invention, the solar cell 100 further includes a first anti-reflection layer 3 located on a side of the first passivation contact layer 20 away from the first tunneling layer 21 , the main function of which is to increase the short-circuit current of the solar cell 100 by reducing the optical reflection of the backlight surface and improving the light absorption efficiency.

[0157] The first anti-reflection layer 3 is a laminated film formed by one or more selected from silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiO2). The thickness of the first anti-reflection layer 3 is 60nm to 130nm.

[0158] The second electrode 8 is formed by screen printing technology and forms an ohmic contact with the second N-type doped polysilicon layer 232 ′ to efficiently extract current.

[0159] Through the above structural design, the solar cell 100 of the present invention can effectively reduce the parasitic absorption of the backlight surface, improve the open circuit voltage and short circuit current, and at the same time ensure good contact performance, thereby improving the overall photoelectric conversion efficiency and being suitable for the mass production of high-efficiency solar cells.

[0160] The inventors have found that the back surface of the traditional TOPCon cell is passivated by SiO2 and Poly layers, while the front surface is only passivated by an aluminum oxide layer. When using a burn-through slurry, there is still direct contact between the metal and the silicon substrate. Therefore, the composite loss on the light-exposed side has the greatest impact on the efficiency of the TOPCon cell. Based on this, Figure 8 As shown, the present invention adopts a passivation contact structure to replace the traditional boron diffusion layer, thereby improving the passivation effect of the light-receiving surface.

[0161] In one embodiment of the present invention, the solar cell 100 further includes a second passivation contact structure 5 located on the light-receiving surface of the silicon substrate 1 and a second electrode 8 in contact with the second passivation contact structure 5 .

[0162] The second passivation contact structure 5 is prepared by any of the above-mentioned preparation methods.

[0163] In one embodiment, the structure of the second surface side is the same as that of the first surface side, except that the N-type doped polysilicon layer is replaced by a P-type doped polysilicon layer, and the P-type doped polysilicon layer is only located in the electrode region 13 .

[0164] In one embodiment, the second passivation contact structure 5 includes a second tunneling layer 51 disposed on the second surface 12 and a second passivation contact layer 52 (P-type doped polysilicon layer) located on a side of the second tunneling layer 51 away from the silicon substrate 1 .

[0165] The second tunneling layer 51 is selected from a silicon oxide layer or a silicon carbide layer, and has a thickness of 0.5 nm to 3 nm, which can effectively passivate the surface of the silicon substrate 1 and reduce interface recombination loss.

[0166] The doping concentration of the P-type doped polysilicon layer is 1E20 cm^-3 to 8E20 cm^-3, and the thickness is 60 nm to 90 nm, so as to provide good contact performance with the second electrode 8 while maintaining the passivation effect.

[0167] The inventors further discovered that the P-type passivation contact structure has weaker passivation capability than the N-type passivation contact structure, and that the polysilicon on the light-receiving surface causes strong optical absorption. Based on this, the present invention sets the P-type passivation contact structure as a discontinuous structure.

[0168] The light-receiving surface of the silicon substrate 1 comprises an electrode region 13 and a non-electrode region 14. The second passivation contact structure 5 is located only in the electrode region 13, and the second electrode 8 does not contact the silicon substrate 1, significantly reducing contact resistance. The non-electrode region 14 is not affected by the P-type doped polysilicon layer, thus avoiding additional optical absorption losses caused by the polysilicon layer in this area, further improving short-circuit current and battery efficiency. Furthermore, the scope of the electrode region 13 is precisely defined through techniques such as laser etching, ensuring that the second passivation contact structure 5 only covers the electrode region 13.

[0169] The second electrode 8 forms a low-resistance contact with the P-type doped polysilicon layer in the second passivation contact structure 5 through a screen printing or evaporation process, thereby further improving the current transmission efficiency.

[0170] Through the above design, the solar cell 100 of the present invention avoids the optical absorption loss of the non-electrode area 14 by setting a second passivation contact structure 5 that only covers the electrode area 13 on the light-receiving surface, while ensuring the excellent contact performance of the second electrode 8, thereby significantly improving the photoelectric conversion efficiency and optimizing the overall battery performance.

[0171] The solar cell 100 further includes a passivation layer 6 on the light-receiving surface, through which the second electrode 8 contacts the P-type doped polysilicon layer. The passivation layer 6 contacts the P-type doped polysilicon layer in the electrode region 13 and contacts the silicon substrate 1 in the non-electrode region 14.

[0172] The passivation layer 6 is an aluminum oxide layer with a thickness of 2 nm to 7 nm. The aluminum oxide layer provides excellent field passivation effect. Through its negative charge, it effectively reduces the interface recombination loss of the first electrode region 13 and improves the open circuit voltage of the solar cell 100.

[0173] Furthermore, the solar cell 100 further includes a second anti-reflection layer 7 located on a side of the passivation layer 6 away from the silicon substrate 1 , and the second electrode 8 passes through the second anti-reflection layer 7 and contacts the passivation layer 6 with the P-type doped polysilicon layer.

[0174] The second anti-reflection layer 7 is a laminated film formed by one or more of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the second anti-reflection layer 7 is 60 nm to 130 nm.

[0175] Through the above structural design, the passivation layer 6 and the second anti-reflection layer 7 work together to significantly reduce the optical and interface composite losses of the light-receiving surface, thereby improving the short-circuit current and overall photoelectric conversion efficiency of the solar cell 100, and at the same time improving the stability of the cell under complex lighting conditions.

[0176] The second electrode 8 forms a low-resistance contact with the P-type doped polysilicon layer in the second passivation contact structure 5 through screen printing, thereby further improving the current transmission efficiency.

[0177] In summary, the solar cell of the present invention has more excellent interface passivation, optical absorption performance and electrical transmission performance, and improves the efficiency and stability of the cell.

[0178] In addition, the thickness of each film layer in the present invention is in the thickness direction of the silicon substrate 1 ( Figure 1 Dimensions in the up and down directions.

[0179] It should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0180] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Providing a silicon substrate, wherein the silicon substrate has a first surface and a second surface disposed opposite to each other; forming a tunneling layer on the first surface and / or the second surface of the silicon substrate; forming a first dielectric layer on a side of the tunneling layer away from the silicon substrate; forming a first doping layer on a side of the first dielectric layer away from the tunneling layer; Annealing is performed to transform the first dielectric layer and the first doped layer into a passivation contact layer.

2. The method for preparing a solar cell according to claim 1, wherein: During the annealing process, the dopant of the first doping layer diffuses into the first dielectric layer; after annealing, the first dielectric layer is transformed into a conductive passivation layer, and the conductive passivation layer and the annealed first doping layer together constitute the passivation contact layer.

3. The method for preparing a solar cell according to claim 2, wherein: Before annealing, the first dielectric layer and the first doped layer have the same crystal structure; and / or the conductive passivation layer and the first doped layer after annealing have the same crystal structure.

4. The method for preparing a solar cell according to claim 1, wherein: forming an intrinsic amorphous silicon layer as the first dielectric layer on a side of the tunneling layer away from the silicon substrate; Alternatively, an intrinsic amorphous silicon layer is deposited as the first dielectric layer using a PECVD process, with a silane flow rate of 2500sccm to 4500sccm; a hydrogen flow rate of 10000sccm to 16000sccm; a deposition temperature of 380°C to 480°C; a chamber pressure of 2000mTorr to 4000mTorr; a deposition power of 9000W to 20000W; a duty cycle range of 1:(5 to 20); and a deposition time of 30s to 100s.

5. The method for preparing a solar cell according to claim 1, wherein: The thickness of the first dielectric layer is 1 nm to 15 nm.

6. The method for preparing a solar cell according to claim 1, wherein: The thickness of the first doping layer is 20 nm to 60 nm.

7. The method for preparing a solar cell according to claim 1, wherein: The first doped layer is a phosphorus-doped amorphous silicon layer; And / or, a doped amorphous silicon layer is deposited as the first doped layer using a PECVD process.

8. The method for preparing a solar cell according to claim 1, wherein: The method for preparing the solar cell further includes forming a second doping layer on a side of the first doping layer away from the first dielectric layer, wherein the doping concentration of the first doping layer is not greater than the doping concentration of the second doping layer; or The method for preparing the solar cell further includes forming a second doping layer between the first doping layer and the first dielectric layer, wherein the doping concentration of the first doping layer is not less than the doping concentration of the second doping layer.

9. The method for preparing a solar cell according to claim 8, wherein: The method for preparing a solar cell further includes forming a second dielectric layer between the first doping layer and the second doping layer; and / or The first doped layer and the second doped layer are both phosphorus-doped amorphous silicon layers; Alternatively, the first doping layer and the second doping layer are formed by a PECVD process, and the flow rate of phosphine used to form the doping layer close to the silicon substrate of the first doping layer and the second doping layer is not greater than the flow rate of phosphine used to form the doping layer far from the silicon substrate of the first doping layer and the second doping layer; and / or the time for forming the first doping layer and the second doping layer close to the silicon substrate is not longer than the time for forming the first doping layer and the second doping layer far from the silicon substrate; Alternatively, the first doping layer or the second doping layer is deposited by a PECVD process, with a silane flow rate of 2500 sccm to 4500 sccm; a hydrogen flow rate of 10000 sccm to 16000 sccm; a phosphine flow rate of 50 sccm to 2000 sccm; a deposition temperature of 380°C to 480°C; a chamber pressure of 2000 mTorr to 4000 mTorr; a deposition power of 9000 W to 20000 W; a duty cycle range of 1:(5 to 20); and a deposition time of 30 s to 600 s.

10. The method for preparing a solar cell according to claim 8, wherein: The thickness of the second doping layer accounts for 10% to 90% of the sum of the thicknesses of the first doping layer and the second doping layer; And / or, the thickness of the first doping layer is 3nm~15nm, and the thickness of the second doping layer is 20nm~40nm; or, the thickness of the first doping layer is 20nm~40nm, and the thickness of the second doping layer is 3nm~15nm.

11. The method for preparing a solar cell according to claim 1, wherein: The method for preparing the solar cell further includes forming a third doping layer between the tunneling layer and the first dielectric layer, wherein the doping concentration of the first doping layer is not less than the doping concentration of the third doping layer.

12. The method for preparing a solar cell according to claim 11, wherein: The doping concentration of the first doping layer is 1.2-5 times the doping concentration of the third doping layer.

13. The method for preparing a solar cell according to claim 11, wherein: The thickness of the first doping layer is 60nm to 120nm; And / or, the thickness of the third doping layer is 10 nm to 20 nm.

14. The method for preparing a solar cell according to any one of claims 1 to 13, characterized in that: The annealing temperature is 850° C. to 950° C., and the annealing time is 1800s to 2600s or 1800s to 2600s; Alternatively, after annealing, the sheet resistance of the passivation contact layer is 50Ω / sq to 65Ω / sq, and / or the doping concentration of the passivation contact layer is 6e+20cm -3 .

15. The method for preparing a solar cell according to any one of claims 1 to 13, characterized in that: The silicon substrate is an N-type silicon wafer, the first surface is a light-receiving surface, and the second surface is a backlight surface; A tunneling layer and a passivation contact layer are formed on both the first and second surfaces of the silicon substrate. The passivation contact layer on the light-receiving side has a doping type opposite to that of the silicon substrate, while the passivation contact layer on the backlight side has the same doping type as that of the silicon substrate.

16. The method for preparing a solar cell according to any one of claims 1 to 13, characterized in that: The silicon substrate is an N-type silicon wafer, the first surface is the backlight surface, and the second surface is the light-receiving surface; a tunneling layer and a passivation contact layer are formed on the side where the light-receiving surface is located, and the second surface has an electrode area and a non-electrode area, and the passivation contact layer of the non-electrode area is removed.

17. A solar cell, characterized in that: The solar cell is manufactured according to the method for manufacturing a solar cell according to any one of claims 1 to 13.

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