TOPCon battery structure and preparation method thereof

Abstract

The TOPCon battery structure comprises a silicon wafer, a tunneling oxide layer, a polycrystalline silicon layer, an ATO layer and a silicon nitride layer which are sequentially arranged from the side close to the silicon wafer to the side away from the silicon wafer are arranged on the back face of the silicon wafer, a back face metal electrode is further arranged on the back face of the silicon wafer, and the silicon nitride layer is arranged on the back face of the silicon wafer. The back metal electrode and the ATO layer form ohmic contact; the ATO layer is made of aluminum-doped titanium oxide, and the polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon layer; the thickness of the polycrystalline silicon layer is 30 to 40 nm; the thickness of the ATO layer ranges from 5 nm to 10 nm. The method has the effects of improving the efficiency of the TOPCon battery, reducing parasitic absorption and improving the passivation capability.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a TOPCon cell structure and a preparation method thereof. Background Art

[0002] Crystalline silicon (c-Si) solar cells currently dominate the global photovoltaic market, primarily due to their continued cost reduction and gradual improvement in power conversion efficiency (PCE). Polysilicon passivation contacts are a key technology for improving the efficiency of silicon solar cells, particularly as they approach the theoretical efficiency limit of 29.4%. However, during the metallization process, the silicon surface passivation layer degrades, requiring a thicker polysilicon layer to prevent degradation. However, such a thick silicon layer reduces light transmittance and increases deposition time. Furthermore, the low-bandgap doped silicon layer exhibits significant light absorption losses, compromising solar cell performance.

[0003] Currently, the back of traditional TOPCon cells uses an "n-type silicon substrate / silicon dioxide / polysilicon / silicon nitride" structure. The Poly-Si layer usually needs to be thicker (>100nm) to ensure the passivation effect, but thick Poly-Si will cause parasitic absorption of light (especially in the near-infrared band), thereby reducing the short-circuit current (Jsc) of the cell. In addition, the contact resistance between Poly-Si and the electrode in the subsequent metallization process is high, and usually needs to be optimized through high-temperature annealing, but this can easily cause interface defects and limit efficiency improvement. Existing passivation materials (such as aluminum oxide or silicon nitride) have insufficient electron-selective passivation ability for polysilicon, making it difficult to balance carrier transport and surface recombination. Therefore, it is necessary to develop a structure that has high passivation ability, low parasitic absorption and compatibility with thin-layer Poly-Si to break through the efficiency bottleneck of existing TOPCon cells. Summary of the Invention

[0004] In order to improve the efficiency of TOPCon cells, reduce parasitic absorption and improve passivation capability, the present application provides a TOPCon cell back structure and a preparation method thereof.

[0005] In the first aspect, the present application provides a TOPCon battery back structure, which adopts the following technical solutions:

[0006] A TOPCon cell back structure includes a silicon wafer, wherein the back of the silicon wafer is provided with a tunneling oxide layer, a polysilicon layer, an ATO layer, and a silicon nitride layer arranged in sequence from the side close to the silicon wafer to the side away from the silicon wafer. The back of the silicon wafer is also provided with a back metal electrode, and the back metal electrode forms an ohmic contact with the ATO layer; the ATO layer is aluminum-doped titanium oxide, and the polysilicon layer is phosphorus-doped polysilicon layer;

[0007] The thickness of the polysilicon layer is 30-40 nm;

[0008] The thickness of the ATO layer is 5-10 nm.

[0009] Optionally, the thickness of the polysilicon layer can be 30 nm, 31 nm, 32 nm, 33 nm, 34 nm, 35 nm, 36 nm, 37 nm, 38 nm, 39 nm, 40 nm, etc., and the thickness of the ATO layer can be 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, etc.

[0010] By employing the aforementioned technical solution, aluminum-doped titanium oxide (ATO) is used to passivate and modify the phosphorus-doped polysilicon layer, reducing the thickness of the polysilicon layer and minimizing parasitic optical absorption. The ATO layer also provides additional protection between the polysilicon layer and the metal electrode, minimizing damage to the polysilicon layer during the metallization process. This improves the passivation contact, lowers the contact resistivity (ρc) of the metal electrode, and enhances the ohmic contact with the electrode during subsequent metallization. Compared to traditional tunnel oxide / polysilicon layer (>100nm) passivation structures, this tunnel oxide / polysilicon / ATO stacked structure not only provides better passivation but also reduces parasitic optical absorption.

[0011] Optionally, in the ATO layer, the doping ratio of aluminum in titanium oxide is 4-6%, and the preparation method of the ATO layer includes: using atomic layer deposition, trimethylaluminum as the aluminum source, and tetraisopropyltitanium as the titanium source.

[0012] Optionally, the method for preparing the ATO layer comprises the following steps:

[0013] (1) Place the substrate silicon wafer into the ALD chamber, set the substrate temperature at 200-250°C (taking into account the reactivity of trimethylaluminum and tetraisopropyltitanium), and evacuate the chamber;

[0014] (2) Open the quick valve of the trimethylaluminum source bottle and introduce high-purity nitrogen as a carrier gas. The flow rate of high-purity nitrogen is 200 sccm. Introduce trimethylaluminum (flow rate of 200 sccm, pulse time of 0.5 s) into the ALD chamber. Nitrogen (flow rate of 200 sccm) is purged for 15 s to remove residual trimethylaluminum. Then, open the quick valve of the H2O source bottle and introduce high-purity nitrogen (flow rate of 200 sccm) as a carrier gas. Introduce water source (flow rate of 50 sccm, pulse time of 0.5 s) into the ALD chamber. Nitrogen (200 sccm) is purged for 15 s to remove residual water source. This step is repeated once.

[0015] (3) Open the quick valve of the tetraisopropyl titanium source bottle and introduce high-purity nitrogen (flow rate of 200 sccm) as a carrier gas. Introduce tetraisopropyl titanium (flow rate of 200 sccm, pulse time of 1 s) into the ALD chamber. Purge nitrogen (flow rate of 200 sccm) for 15 s to remove residual tetraisopropyl titanium. Then open the quick valve of the H2O source bottle and introduce water (flow rate of 50 sccm, pulse time of 0.5 s). Also introduce high-purity nitrogen as a carrier gas. Purge nitrogen (200 sccm) for 15 s to remove residual water. This step is repeated 19 times to obtain an aluminum-doped titanium oxide (ATO) film with an aluminum doping ratio of 4-6%.

[0016] By adopting the above technical solution, excessive or insufficient aluminum doping will directly affect the conductivity, band gap, carrier concentration, optical properties, and stability of the ATO layer. During the preparation process, the flow rate and purge time of the aluminum and titanium sources are controlled to achieve an aluminum doping ratio of 4-6% in titanium oxide, resulting in an ATO layer with better conductivity, band gap, carrier concentration, optical properties, and stability.

[0017] Optionally, the silicon nitride layer on the back of the silicon wafer has a thickness of 67-91 nm, and the silicon nitride layer is a stacked layer structure of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the silicon nitride layer on the back of the silicon wafer can be 67 nm, 70 nm, 73 nm, 76 nm, 80 nm, 85 nm, 88 nm, 90 nm, etc.

[0018] Optionally, the silicon wafer is an N-type silicon wafer, the thickness of the silicon wafer is 125 μm, and the sheet resistance of the silicon wafer is 0.4-1.6 Ω·cm.

[0019] Optionally, the thickness of the tunnel oxide layer is 1.2-2.0 nm. The thickness of the tunnel oxide layer can be 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc.

[0020] Optionally, the front side of the silicon wafer is provided with a P+ doped layer, an aluminum oxide layer and a silicon nitride layer arranged in sequence from the side close to the silicon wafer to the side away from the silicon wafer. The front side of the silicon wafer is also provided with a front metal electrode, and the front metal electrode forms an ohmic contact with the P+ doped layer.

[0021] Optionally, the thickness of the P+ doped layer is 110-160 nm, the thickness of the aluminum oxide layer is 3-4 nm, and the thickness of the silicon nitride layer on the front side of the silicon wafer is 66-86 nm. The thickness of the aluminum oxide layer can be 3.2 nm, 3.4 nm, 3.6 nm, 3.8 nm, 4 nm, etc., and the thickness of the silicon nitride layer on the front side of the silicon wafer can be 66 nm, 70 nm, 72 nm, 74 nm, 76 nm, 78 nm, 80 nm, 84 nm, 86 nm, etc.

[0022] In a second aspect, the present application provides a method for preparing a TOPCon battery back structure, using the following technical solution:

[0023] A method for preparing a TOPCon battery back structure comprises the following steps:

[0024] S1, cleaning and texturing the N-type silicon wafer;

[0025] S2. Boron is diffused on the front side of the N-type single crystal silicon wafer to form a P+ doped layer, which forms a PN junction with the N-type substrate single crystal silicon. The diffusion temperature is 800-1000°C and the diffusion time is 10-50 minutes. After diffusion, the square resistance of the P+ doped layer is 120Ω / □, the junction depth is 0.2-0.4μm, and the thickness of the borosilicate glass layer is 110-160nm.

[0026] S3, laser SE is applied to the front of the silicon wafer by laser, and the boron source is selectively pushed into the SE region, so that the metal electrode and the silicon wafer contact part and the vicinity are highly doped to reduce the ohmic contact; wherein, the doping concentration of the SE region is 10 20 ~10 21 cm -3 , the doping concentration of the non-SE region is 10 18 ~10 19 cm -3 ;

[0027] S4: Heat and oxidize the silicon wafer after laser SE, further push the boron source deeper, deepen the junction depth, and generate more BSG to protect the PN junction on the front side. After boron doping, the sheet resistance of the SE area is 80Ω, the sheet resistance of other parts is 220-230Ω, and the junction depth is 1.4-1.5μm.

[0028] S5, removing the back and side BSG layers using HF; polishing the back side using a mixed solution of NaOH, additives, and deionized water;

[0029] S6, depositing a tunnel oxide layer and a polysilicon layer in sequence on the back side of the silicon wafer;

[0030] S7, doping the back side of the silicon wafer with phosphorus to form a phosphosilicate glass layer; the phosphorus-doped layer has a sheet resistance of 40-50Ω and a thickness of 25-75 nm;

[0031] S8, using HF to completely remove the phosphosilicate glass layer on the front and side surfaces;

[0032] S9, coating aluminum oxide on the front side of the silicon wafer;

[0033] S10, plating silicon nitride on the front side of the silicon wafer;

[0034] S11, coating an ATO layer, i.e., an aluminum-doped titanium oxide layer, on the back of the silicon wafer by atomic layer deposition;

[0035] S12, plating silicon nitride on the back side of the silicon wafer;

[0036] S13. Screen printing and sintering are performed on the front and back sides of the silicon wafer, and annealing is performed using a one-step annealing method at an annealing temperature of 800-900°C.

[0037] By adopting the above technical solution, the battery performance is improved by optimizing the thickness of the ATO layer to 5-10nm, the doping ratio of aluminum in titanium oxide to 4-6%, and controlling the annealing temperature to 800-900℃.

[0038] In summary, this application has the following beneficial effects:

[0039] 1. Use wide-bandgap metal oxides (i.e., aluminum-doped titanium oxide) to passivate and modify the phosphorus-doped Poly-Si layer, thereby reducing the thickness of the Poly-Si layer and reducing parasitic optical absorption. At the same time, the ATO layer provides additional protection between the Poly-Si layer and the metal electrode, reducing damage to the Poly-Si layer during the metallization process, thereby improving the passivation contact, reducing the contact resistivity (ρc) of the metal electrode, and improving the ohmic contact with the electrode during the subsequent metallization process.

[0040] 2. Develop a new passivation contact by designing a SiO2 / Poly-Si (≤40nm) / ATO (5-10nm) stacked structure. This structure provides excellent surface passivation while exhibiting high electron selectivity. Compared with traditional SiO2 / Poly-Si (>100nm) layers, this SiO2 / Poly-Si / ATO stacked structure not only provides better passivation but also reduces parasitic light absorption. Specifically, the ATO layer was deposited using thermally grown SiO2 and atomic layer deposition. By optimizing the thickness of the ATO layer, the aluminum doping ratio in aluminum titanium oxide, and the annealing temperature, the battery performance was improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1Schematic diagram of the battery structure of Example 1.

[0042] Figure 2 Schematic diagram of the battery structure of Comparative Example 1.

[0043] Figure 3 This is a diagram representing the battery structure and performance.

[0044] Explanation of the accompanying symbols: 1. Silicon wafer; 2. Tunneling oxide layer; 3. Polysilicon layer; 4. ATO layer; 5. Silicon nitride layer; 6. Back metal electrode; 7. P+ doped layer; 8. Aluminum oxide layer; 9. Front metal electrode. DETAILED DESCRIPTION

[0045] Example 1

[0046] Reference Figure 1 A TOPCon cell structure includes a silicon wafer 1. The back side of the silicon wafer 1 is provided with a tunneling oxide layer 2, a polysilicon layer 3, an ATO layer 4, and a silicon nitride layer 5, which are arranged in sequence from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. The back side of the silicon wafer 1 is also provided with a back metal electrode 6, and the back metal electrode 6 forms an ohmic contact with the ATO layer 4.

[0047] The silicon wafer 1 is an N-type silicon wafer 1, the thickness of the silicon wafer 1 is 125 μm, and the sheet resistance of the silicon wafer 1 is 0.4 Ω·cm;

[0048] The thickness of the tunnel oxide layer 2 is 1.2 nm;

[0049] The ATO layer 4 is aluminum-doped titanium oxide, and the polysilicon layer 3 is phosphorus-doped polysilicon layer 3; the thickness of the polysilicon layer 3 is 30nm; the thickness of the ATO layer is 5nm; the thickness of the silicon nitride layer 5 on the back of the silicon wafer is 67nm, and the silicon nitride layer 5 is a stacked layer structure of silicon nitride, silicon oxynitride and silicon oxide.

[0050] The front of the silicon wafer 1 is provided with a P+ doped layer 7, an aluminum oxide layer 8 and a silicon nitride layer 5, which are arranged in sequence from the side close to the silicon wafer 1 to the side away from the silicon wafer 1. The front of the silicon wafer is also provided with a front metal electrode 9, which forms an ohmic contact with the P+ doped layer 7. The thickness of the P+ doped layer is 110nm, the thickness of the aluminum oxide layer 8 is 3nm, and the thickness of the silicon nitride layer 5 is 66nm.

[0051] A method for preparing a TOPCon battery structure comprises the following steps:

[0052] S1. Select an N-type single-crystalline silicon wafer as the substrate and pre-clean and texturize the wafer on both sides using a mixed solution of NaOH, additives, and deionized water. The N-type single-crystalline silicon wafer has a thickness of 125 µm, an area of ​​182 mm × 183 mm, and a sheet resistance of 0.4 Ω.cm.

[0053] S2. Select BCl3 as the boron source and use a low-pressure, high-temperature diffusion furnace to diffuse boron on the front side of the N-type single-crystalline silicon wafer to form a P+ doped layer, thereby forming a PN junction with the N-type substrate single-crystalline silicon. The diffusion temperature is 800°C and the diffusion time is 10 minutes. After diffusion, the square resistance of the P+ doped layer is 120Ω / □, the junction depth is 0.2μm, and the thickness of the borosilicate glass (BSG) layer is 110nm.

[0054] S3. Use a laser to perform laser SE on the front side of the silicon wafer, selectively advance the boron source, and make the contact part between the metal gate line and the silicon wafer and the vicinity thereof be doped with high concentration to reduce the ohmic contact;

[0055] S4: Use a low-pressure, high-temperature diffusion furnace to heat and oxidize the silicon wafer after laser SE, further pushing the boron source deeper, making the junction deeper and generating more BSG to protect the PN junction on the front side. After boron doping, the square resistance of the SE area is 80Ω, the square resistance of other parts is 220Ω, and the junction depth is 1.4μm.

[0056] S5. Using a BSG removal chain machine, HF is used to remove the BSG layer on the back and side surfaces; the back surface is polished by using a mixed solution of NaOH, additives and deionized water;

[0057] S6. Using LPCVD equipment, sequentially deposit a tunnel oxide layer and a polysilicon layer on the back side of the silicon wafer. The thickness of the tunnel oxide layer is 1.2 nm, and the thickness of the polysilicon layer is 30 nm.

[0058] S7, doping the back side of the silicon wafer with phosphorus to form a phospho-silicate glass (PSG) layer; wherein the square resistance of the phosphorus-doped layer is 40-50Ω, and the thickness of the phospho-silicate glass layer is 25 nm;

[0059] S8. Use a PSG removal chain machine to completely remove PSG on the front and side surfaces with HF. At this time, some BPSG corrosion remains. Use NaOH or KOH to remove the front Poly winding. At the same time, use the adsorption group of the additive to protect the PSG and BPSG on the back surface, and the accelerating group of the additive to accelerate the removal of Poly. Use HF or HF / HCl to remove the remaining BSG and BPSG.

[0060] S9, using an ALD device to deposit aluminum oxide on the front side of the silicon wafer; wherein the thickness of the aluminum oxide layer is 3 nm;

[0061] S10, using a PECVD device to deposit silicon nitride on the front side of the silicon wafer; wherein the thickness of the silicon nitride layer is 66 nm, and the silicon nitride layer is a stacked layer of silicon nitride, silicon oxynitride, and silicon oxide;

[0062] S11. ATO layer (aluminum-doped titanium oxide layer) is deposited on the back of the silicon wafer by atomic layer deposition (ALD). The thickness of the ATO layer is 5 nm.

[0063] S12, using a PECVD device to deposit a silicon nitride layer on the back of the silicon wafer, wherein the thickness of the silicon nitride layer is 67 nm, and the silicon nitride layer is a stacked layer of silicon nitride, silicon oxynitride, and silicon oxide;

[0064] S13. Screen printing is performed on the front and back sides of the silicon wafer, and the wafer is sintered. The wafer is annealed in a one-step annealing process at a temperature of 800°C.

[0065] Among them, the specific steps of S11, using atomic layer deposition (ALD) to plate an ATO layer on the back of the silicon wafer are as follows:

[0066] (1) Place the substrate silicon wafer into the ALD chamber, set the substrate temperature at 230°C (taking into account the reactivity of trimethylaluminum and tetraisopropyltitanium), and evacuate the chamber;

[0067] (2) Open the quick valve of the trimethylaluminum source bottle and introduce high-purity nitrogen as a carrier gas. The flow rate of high-purity nitrogen is 200 sccm. Introduce trimethylaluminum (flow rate of 200 sccm, pulse time of 0.5 s) into the ALD chamber. Nitrogen (flow rate of 200 sccm) is purged for 15 s to remove residual trimethylaluminum. Then, open the quick valve of the H2O source bottle and introduce high-purity nitrogen (flow rate of 200 sccm) as a carrier gas. Introduce water source (flow rate of 50 sccm, pulse time of 0.5 s) into the ALD chamber. Nitrogen (200 sccm) is purged for 15 s to remove residual water source. This step is repeated once.

[0068] (3) Open the quick valve of the tetraisopropyl titanium source bottle, introduce high-purity nitrogen (flow rate of 200 sccm) as a carrier gas, introduce tetraisopropyl titanium (flow rate of 200 sccm, pulse time of 1 s) into the ALD chamber, and purge the nitrogen (flow rate of 200 sccm) for 15 s to remove the residual tetraisopropyl titanium. Then, open the quick valve of the H2O source bottle and introduce water (flow rate of 50 sccm, pulse time of 0.5 s). Also introduce high-purity nitrogen as a carrier gas, and purge the nitrogen (flow rate of 200 sccm) for 15 s to remove the residual water. This step is repeated 19 times to obtain an aluminum-doped titanium oxide (ATO) film with an aluminum doping ratio of 5%.

[0069] Example 2-3

[0070] A method for preparing a TOPCon battery structure is based on Example 1, except that the preparation condition parameters of each step are different.

[0071] The preparation conditions and parameters of Examples 1 to 3 are shown in the following table.

[0072] Table 1 Preparation Conditions Parameters of Example 1-Example 3

[0073]

[0074] Example 4

[0075] A TOPCon battery structure is different from Example 2 in that the doping ratio of aluminum-doped titanium oxide in S11 is 4%, and the remaining steps are the same.

[0076] Example 5

[0077] A TOPCon battery structure is different from Example 2 in that the doping ratio of aluminum-doped titanium oxide in S11 is 6%, and the remaining steps are the same.

[0078] Example 6

[0079] A TOPCon battery structure is different from Example 2 in that the doping ratio of aluminum-doped titanium oxide in S11 is 10%, and the remaining steps are the same.

[0080] Example 7

[0081] A TOPCon battery structure is different from Example 2 in that the doping ratio of aluminum-doped titanium oxide in S11 is 2%, and the remaining steps are the same.

[0082] Comparative Example 1

[0083] A TOPCon battery structure, which is different from Example 1 in that Figure 2 As shown, the thickness of the ATO layer is 0 nm, and the thickness of the polysilicon layer deposited on the back is 100 nm, and the back metal electrode forms an ohmic contact with the polysilicon layer.

[0084] The method for preparing the TOPCon cell structure is different from that of Example 1 in that the thickness of the polysilicon layer deposited in S6 is 100 nm, and step S11 is not performed, that is, the ATO layer is not prepared.

[0085] Comparative Example 2

[0086] A TOPCon cell structure differs from Example 2 in that the film layer deposited on the outside of the polysilicon layer is aluminum-doped zirconium oxide with a thickness of 5 nm and an aluminum doping ratio of 4%.

[0087] Comparative Example 3

[0088] A TOPCon cell structure differs from Example 2 in that the film layer deposited on the outside of the polysilicon layer is aluminum-doped hafnium oxide with a thickness of 5 nm and an aluminum doping ratio of 4%.

[0089] The battery structures of Examples 1 to 3 were tested. There was no significant substantial difference in the test results of Examples 1 to 3, so Example 2 was selected as the preferred example.

[0090] Performance testing

[0091] The tests include:

[0092] 1. Minority Carrier Lifetime (MCL)

[0093] The minority carrier lifetime is a key parameter that measures the average survival time of minority carriers (electrons or holes) in semiconductor materials before recombination, and directly affects the open circuit voltage (Voc) and fill factor (FF) of TOPCon batteries.

[0094] 1. Test equipment and software

[0095] Microwave photoconductivity decay (μ-PCD): Sinton Instruments WCT-100 (USA);

[0096] Supporting software: The equipment usually comes with dedicated analysis software (such as Sinton's WCT software and Newport's SolarWorks) to process signal attenuation data and calculate lifespan.

[0097] 2. Test conditions

[0098] Sample requirements: It must be a complete cell (or uniformly doped silicon wafer) without electrode obstruction, avoid the introduction of additional recombination centers by metal electrodes, and the surface must be clean.

[0099] Temperature control: usually at room temperature (25±5℃).

[0100] Light intensity and wavelength: The test light is simulated sunlight (AM1.5G, 100 mW / cm²).

[0101] 2. SunsVoc (Sunlight-Induced Open Circuit Voltage)

[0102] SunsVoc is used to evaluate the characteristics of the open circuit voltage (Voc) of TOPCon cells under illumination as the light intensity changes, reflecting the recombination mechanism of the cell (such as radiative recombination, Auger recombination, and defect recombination).

[0103] 1. Test equipment and software

[0104] Mainstream devices:

[0105] Dedicated SunsVoc tester: PV Testing Systems SUNS-VOC 2000 (USA);

[0106] Supporting software:

[0107] The equipment comes with software (such as PV Testing's SunsVoc Controller) for controlling the light source, sweeping the voltage, and recording the data.

[0108] 2. Test conditions

[0109] Light intensity adjustment:

[0110] A wide range of light intensities needs to be covered (e.g. 0.1-100 times AM1.5G, i.e. 10-10000 mW / cm²).

[0111] Temperature control: usually at room temperature (25±5℃).

[0112] Sample status: It must be a complete cell (with electrodes), the electrodes must completely cover the main grid (to avoid edge leakage current), and the cell surface must be free of damage (such as scratches).

[0113] 3. Efficiency IV Characteristics (Current-Voltage, IV)

[0114] The efficiency IV test is the core method for evaluating the photoelectric conversion efficiency (η) of TOPCon cells. By measuring the IV curve, the short-circuit current (Isc), open-circuit voltage (Voc), fill factor (FF) and conversion efficiency (η=Voc·Isc·FF / Pin, where Pin is the incident light power) are obtained.

[0115] 1. Test equipment and software

[0116] Mainstream Equipment: Solar Simulators: Newport Sol3A (AAA Grade, 1000 W / m²), AMETEK LS100 (xenon lamp), Sciencetech 94023 (LED). Electronic Load / Source Meter: Keithley 2600 Series (high precision), Keysight E5270B (high current). Integrating Sphere: Used to measure the active area of ​​the cell (to avoid edge light leakage errors).

[0117] Supporting software:

[0118] The device comes with software (Keithley's LabTracer) for automatically scanning the IV curve and calculating parameters.

[0119] 2. Test conditions (standard test conditions, STC)

[0120] Spectrum: AM1.5G (solar constant 1000 W / m², wavelength distribution in accordance with IEC 60904-3).

[0121] Temperature: 25±1°C (use a thermostat or Peltier cooling system to control the battery temperature).

[0122] Irradiance: 1000 W / m² (the solar simulator output must be calibrated with a power meter, with an error of <1%).

[0123] Efficiency calculation:

[0124] Isc: The current at the intersection of the IV curve and V=0 (A).

[0125] Voc: The voltage at the intersection of the IV curve and I=0 (V).

[0126] FF: (Vmp·Imp) / (Voc·Isc)×100% (Vmp and Imp are the maximum power point voltage and current).

[0127] η: (Vmp·Imp) / (A·Pin)×100% (Pin is the incident light power, A is the effective area).

[0128] The test results are shown in Tables 2 to 4.

[0129] Table 2: Minority carrier lifetime test results

[0130]

[0131] Table 3: SunsVoc test results

[0132]

[0133] Table 4: Electrical performance test results

[0134]

[0135] Combine Figure 3As can be seen from the electrical performance test data in Tables 2 to 4, the Lifetime and SunsVoc test results of Example 2 are improved compared to Comparative Example 1, mainly reflected in the improvement of I-Voc, I-FF, Voc, and pFF, and the decrease in Jo. In addition, the efficiency of Example 2 is improved by 0.18% compared to Comparative Example 1, mainly due to the improvement of Voc and FF, especially the improvement of Isc. Compared with Comparative Example 1, the Voc and FF of Example 2 are improved by 1.104V and 0.09%, respectively. This is mainly due to the good passivation effect provided by the SiO2 / Poly-Si / ATO structure, which effectively reduces the contact resistivity between the metal electrode and the battery, thereby improving the Voc and FF. In addition, the Isc of Example 2 is improved by 61mA compared to Comparative Example 1. This is mainly due to the thinning of the Poly-Si layer in the SiO2 / Poly-Si / ATO structure, which reduces the parasitic absorption of Poly-Si. At the same time, ATO exhibits a higher QE in the long wavelength range (>800nm), indicating lower back-side carrier recombination.

[0136] Combining the test results of Examples 2, 4-5, and 6-7 with those of Tables 2 to 4, we can see that the test results of Examples 2 and 4-5 are superior to those of Examples 6-7. This is because if the aluminum doping ratio is too low (as in Example 7), it may lead to insufficient passivation capability, increased surface recombination, and decreased Voc and FF. If the aluminum doping ratio is too high (as in Example 6), it may cause a surge in defect states, increased leakage current, and phase separation that disrupts uniformity, potentially degrading Voc, FF, and Isc.

[0137] Combining Example 2 with Comparative Example 2 and the test results in Tables 2 to 4 shows that Example 2 outperforms Comparative Example 2. This is due to the following: Although zirconium dioxide (bandgap: 5.0-5.8 eV) and hafnium oxide (bandgap: 5.6-6.0 eV) are both wide-gap metal oxides, the conduction band bottom of zirconium dioxide (approximately -3.0 to -2.5 eV vs. vacuum level) is significantly higher than that of silicon. The carrier injection barrier is approximately 1.5 to 1.0 eV, which, while lower than that of aluminum oxide, still results in significant carrier transport losses. During high-temperature processes (such as annealing), zirconium dioxide readily reacts with silicon to form silicon dioxide and zirconium silicate. Silicon dioxide is a highly resistive insulating phase, significantly increasing the density of recombination centers at the silicon-oxide interface and degrading contact performance. Furthermore, undoped zirconium dioxide is inherently an insulator (resistivity >10¹² Ω·cm), making it difficult to achieve sufficiently low resistivity even with doping (e.g., Si or Al).

[0138] Combining Example 2 with Comparative Example 3 and the test results in Tables 2 to 4, it can be seen that Example 2 outperforms Comparative Example 3. This is due to the significant difference between the conduction band bottom of hafnium dioxide (approximately -2.8 to -2.5 eV vs. the vacuum level) and the energy level of silicon, resulting in a carrier injection barrier of approximately 1.2 to 1.5 eV, which limits electron transport efficiency. At high temperatures, hafnium dioxide reacts more vigorously with silicon, easily forming a mixed layer of hafnium silicate and silicon dioxide. The high resistivity of silicon dioxide can disrupt ohmic contact. Furthermore, the n-type doping of hafnium dioxide (e.g., Si or Al) is limited by lattice matching, resulting in low doping efficiency and difficulty achieving effective conductivity.

[0139] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.

Claims

1. A TOPCon cell structure, comprising a silicon wafer (1), characterized in that: The back side of the silicon wafer (1) is provided with a tunneling oxide layer (2), a polysilicon layer (3), an ATO layer (4), and a silicon nitride layer (5) which are sequentially arranged from the side close to the silicon wafer (1) to the side away from the silicon wafer (1); the back side of the silicon wafer is also provided with a back metal electrode (6), and the back metal electrode (6) forms an ohmic contact with the ATO layer (4); the ATO layer (4) is aluminum-doped titanium oxide, and the polysilicon layer (3) is a phosphorus-doped polysilicon layer; The thickness of the polysilicon layer (3) is 30-40 nm; The thickness of the ATO layer (4) is 5-10 nm.

2. A TOPCon battery structure according to claim 1, characterized in that: In the ATO layer (4), the doping ratio of aluminum in titanium oxide is 4-6%. The preparation method of the ATO layer (4) comprises: using atomic layer deposition, trimethylaluminum as an aluminum source, and tetraisopropyltitanium as a titanium source.

3. A TOPCon battery structure according to claim 1, characterized in that: The silicon nitride layer (5) on the back side of the silicon wafer (1) has a thickness of 67-91 nm, and the silicon nitride layer (5) is a stacked layer structure of silicon nitride, silicon oxynitride, and silicon oxide.

4. A TOPCon battery structure according to claim 1, characterized in that: The silicon wafer (1) is an N-type silicon wafer, and the sheet resistance of the silicon wafer (1) is 0.4-1.6 Ω·cm.

5. A TOPCon battery structure according to claim 1, characterized in that: The thickness of the tunnel oxide layer (2) is 1.2-2.0 nm.

6. A TOPCon battery structure according to claim 5, characterized in that: The front surface of the silicon wafer (1) is provided with a P+ doped layer (7), an aluminum oxide layer (8), and a silicon nitride layer (5) which are arranged in sequence from a side close to the silicon wafer (1) to a side away from the silicon wafer (1). The front surface of the silicon wafer (1) is also provided with a front metal electrode (9), and the front metal electrode (9) forms an ohmic contact with the P+ doped layer (7).

7. A TOPCon battery structure according to claim 6, characterized in that: The thickness of the P+ doped layer (7) is 110-160 nm, the thickness of the aluminum oxide layer (8) is 3-4 nm, and the thickness of the silicon nitride layer (5) on the front side of the silicon wafer (1) is 66-86 nm.

8. A method for preparing a TOPCon battery structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1, cleaning and texturing the N-type silicon wafer; S2. Boron is diffused on the front side of the N-type single crystal silicon wafer to form a P+ doped layer, which forms a PN junction with the N-type substrate single crystal silicon. The diffusion temperature is 800-1000°C and the diffusion time is 10-50 minutes. After diffusion, the square resistance of the P+ doped layer is 120Ω / □, the junction depth is 0.2-0.4μm, and the thickness of the borosilicate glass layer is 110-160nm. S3, laser SE is performed on the front side of the silicon wafer through a laser, selectively advancing the boron source in the SE area, so that the contact part between the metal electrode and the silicon wafer and the vicinity are highly doped, reducing the ohmic contact; S4: Heat and oxidize the silicon wafer after laser SE, further push the boron source deeper, deepen the junction depth, and generate more BSG to protect the PN junction on the front side. After boron doping, the sheet resistance of the SE area is 80Ω, and the sheet resistance of other parts is 220-230Ω, with a junction depth of 1.4-1.5μm. S5, removing the back and side BSG layers using HF; polishing the back side using a mixed solution of NaOH, additives, and deionized water; S6, depositing a tunnel oxide layer and a polysilicon layer in sequence on the back side of the silicon wafer; S7, doping the back side of the silicon wafer with phosphorus to form a phosphosilicate glass layer; the phosphorus-doped layer has a sheet resistance of 40-50Ω and a thickness of 25-75 nm; S8, using HF to completely remove the phosphosilicate glass layer on the front and side surfaces; S9, plating an aluminum oxide layer on the front side of the silicon wafer; S10, plating a silicon nitride layer on the front side of the silicon wafer; S11, coating an ATO layer, i.e., an aluminum-doped titanium oxide layer, on the back of the silicon wafer by atomic layer deposition; S12, plating a silicon nitride layer on the back side of the silicon wafer; S13. Screen printing and sintering are performed on the front and back sides of the silicon wafer, and annealing is performed using a one-step annealing method at an annealing temperature of 800-900°C.

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