Display panel, display panel assembly, and electronic device including the same

Abstract

A display panel, a display panel assembly, and an electronic device including the display panel are disclosed. A display panel in which a display area and a non-display area are defined includes a lower substrate, an upper substrate, and a filler disposed between the lower substrate and the upper substrate. The non-display area includes: a first edge area extending in a first direction; a second edge region spaced apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; the third edge region is connected with the first edge region and the second edge region; and a fourth edge region spaced apart from the third edge region in the first direction. The sealing member is disposed between the upper substrate and the lower substrate in at least one of the first to fourth edge regions, and at least a portion of the filler extends from the display region to be disposed in at least one of the first to fourth edge regions where the sealing member is not disposed.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2024-0037020, filed on March 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display panel and a display panel assembly for forming a plurality of unit display panels. Background Art

[0003] Electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and gaming devices include a display panel that displays images. The display panel includes a lower substrate and an upper substrate, and the lower substrate includes a light-emitting element.

[0004] A display panel assembly for forming a plurality of unit display panels includes a lower mother substrate, an upper mother substrate, and a sealing member and a filler for combining the lower mother substrate with the upper mother substrate. Summary of the Invention

[0005] The present disclosure provides a display panel with improved reliability.

[0006] The present disclosure provides a display panel assembly with improved process efficiency.

[0007] An embodiment of the present disclosure provides a display panel, wherein a display area and a non-display area surrounding the display area are defined. The display panel includes: a lower substrate including a light-emitting element layer; an upper substrate disposed on the lower substrate; and a filler disposed between the lower substrate and the upper substrate to overlap with the display area. The non-display area includes: a first edge area extending in a first direction; a second edge area spaced apart from the first edge area in a second direction perpendicular to the first direction and extending in the first direction; a third edge area extending in the second direction and connecting one end of the first edge area and one end of the second edge area; and a fourth edge area spaced apart from the third edge area in the first direction and extending in the second direction. A seal is disposed between the upper substrate and the lower substrate in at least one edge area from the first edge area to the fourth edge area, and at least a portion of the filler extends from the display area to be disposed in at least one edge area from the first edge area to the fourth edge area where the seal is not disposed.

[0008] In one embodiment, the sealing member may be directly disposed between the upper substrate and the lower substrate to combine the upper substrate and the lower substrate.

[0009] In one embodiment, the seal may be provided in one edge region from the first to the fourth edge regions, and the filler may be extended to be provided in the remaining three edge regions from the first to the fourth edge regions where the seal is not provided.

[0010] In one embodiment, the seal may be provided in two edge regions from the first to the fourth edge regions, and the filler may be extended to be provided in the remaining two edge regions from the first to the fourth edge regions where the seal is not provided.

[0011] In one embodiment, the seal may be provided in three edge regions from the first to the fourth edge regions, and the filler may be extended to be provided in the remaining one edge region from the first to the fourth edge regions where the seal is not provided.

[0012] In one embodiment, the non-display area may further include a pad area spaced apart from the display area and close to the first edge area.

[0013] In one embodiment, the lower substrate may further include an encapsulation layer arranged on the light-emitting element layer, and the encapsulation layer may include: a first inorganic encapsulation layer, arranged on the light-emitting element layer; an organic encapsulation layer, arranged on the first inorganic encapsulation layer; and a second inorganic encapsulation layer, arranged on the organic encapsulation layer, and the sealant may overlap with the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may not overlap with the organic encapsulation layer.

[0014] One embodiment of the present inventive concept provides a display panel assembly comprising a plurality of unit display panels, each of the plurality of unit display panels defining a display area and a non-display area surrounding the display area. The display panel assembly includes: a lower mother substrate including a light-emitting element layer; an upper mother substrate disposed on the lower mother substrate; and a filler disposed between the lower mother substrate and the upper mother substrate to overlap the display area. The non-display area includes: a first edge area extending in a first direction; a second edge area spaced apart from the first edge area in a second direction perpendicular to the first direction and extending in the first direction; a third edge area extending in the second direction and connecting one end of the first edge area and one end of the second edge area; and a fourth edge area spaced apart from the third edge area in the first direction and extending in the second direction. A sealant is disposed between the upper mother substrate and the lower mother substrate in at least one edge area among the first to fourth edge areas, and at least a portion of the filler extends from the display area to be disposed in at least one edge area among the first to fourth edge areas where the sealant is not disposed.

[0015] In one embodiment, a cutting area surrounding each of the plurality of unit display panels may be defined in the display panel assembly.

[0016] In one embodiment, the sealing member may be directly disposed between the upper mother substrate and the lower mother substrate to combine the upper mother substrate and the lower mother substrate.

[0017] In one embodiment, the non-display area may further include a pad area spaced apart from the display area and close to the first edge area.

[0018] In one embodiment, the plurality of unit display panels may include a plurality of first unit display panels and a plurality of second unit display panels, the plurality of second unit display panels being spaced apart from the plurality of first unit display panels in the first direction and arranged alternately with the plurality of first unit display panels, the seal may be arranged in two edge regions from the first edge region to the fourth edge region defined in each of the plurality of first unit display panels, and the filler may extend to be arranged in the remaining two edge regions from the first edge region to the fourth edge region defined in each of the plurality of first unit display panels where the seal is not arranged.

[0019] In one embodiment, the seal may be disposed in one edge region from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and the filler may extend to be disposed in the remaining three edge regions from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels in which the seal is not disposed.

[0020] In one embodiment, the seal may be disposed in the second edge region and the third edge region of each of the plurality of first unit display panels, the filler may be extended to be disposed in the first edge region and the fourth edge region of each of the plurality of first unit display panels, the seal may be disposed in the second edge region of each of the plurality of second unit display panels, and the filler may be extended to be disposed in the first edge region, the third edge region, and the fourth edge region of each of the plurality of second unit display panels.

[0021] In one embodiment, the seal may be disposed in the first edge region and the third edge region of each of the plurality of first unit display panels, the filler may be extended to be disposed in the second edge region and the fourth edge region of each of the plurality of first unit display panels, the seal may be disposed in the first edge region of each of the plurality of second unit display panels, and the filler may be extended to be disposed in the second edge region, the third edge region, and the fourth edge region of each of the plurality of second unit display panels.

[0022] In one embodiment, the seal may be arranged in two edge regions from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and the filler may be extended to be arranged in the remaining two edge regions from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels where the seal is not arranged.

[0023] In one embodiment, the seal may be disposed in the first edge region and the second edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels, and the filler may extend to be disposed in the third edge region and the fourth edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels.

[0024] In one embodiment, the seal may be disposed in the first edge region and the third edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels, and the filler may extend to be disposed in the second edge region and the fourth edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels.

[0025] In one embodiment, the seal may be arranged in three edge regions from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and the filler may be extended to be arranged in the remaining one edge region from the first edge region to the fourth edge region defined in each of the plurality of second unit display panels in which the seal is not arranged.

[0026] In one embodiment, the seal may be disposed in the first edge region and the second edge region defined in each of the plurality of first unit display panels, the filler may be extended to be disposed in the third edge region and the fourth edge region defined in each of the plurality of first unit display panels, the seal may be disposed in the first edge region, the second edge region, and the fourth edge region defined in each of the plurality of second unit display panels, and the filler may be extended to be disposed in the third edge region defined in each of the plurality of second unit display panels.

[0027] One embodiment of the present inventive concept provides an electronic device comprising: a display panel; an input sensor disposed on the display panel; a window disposed on the input sensor; and a housing disposed below the display panel. The display panel defines a display area and a non-display area, the non-display area comprising: a first edge area extending in a first direction; a second edge area spaced apart from the first edge area in a second direction perpendicular to the first direction and extending in the first direction; a third edge area extending in the second direction and connecting one end of the first edge area and one end of the second edge area; and a fourth edge area spaced apart from the third edge area in the first direction and extending in the second direction. The display panel comprises: a lower substrate comprising a light-emitting element layer; an upper substrate disposed on the lower substrate; a filler disposed between the lower substrate and the upper substrate and overlapping the display area; and a sealant disposed between the upper substrate and the lower substrate in at least one of the first to fourth edge areas. The filler extends from the display area to be disposed in at least one of the first to fourth edge areas.

[0028] According to the above, the sealing member is used to combine the upper substrate and the lower substrate of the display panel, and the underfilling, overfilling and / or cracking defects of the sealing member are reduced. Therefore, the reliability of the display panel is improved.

[0029] According to the above, the use of a sealing member for bonding an upper mother substrate to a lower mother substrate in a display panel assembly is reduced, thereby reducing defects caused by unevenness and overlap of the sealing member. Accordingly, the process efficiency of the display panel assembly is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other advantages of the present disclosure will become apparent by referring to the following detailed description considered in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is an assembled perspective view of an embodiment of an electronic device according to the present disclosure;

[0032] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure;

[0033] Figure 3A and Figure 3B For the Figure 2 A cross-sectional view of the electronic device taken along line II';

[0034] Figure 4 is a plan view of an embodiment of a display panel according to the present disclosure;

[0035] Figure 5 is a cross-sectional view of an embodiment of a portion of a display area according to the present disclosure;

[0036] Figures 6 and 7 is a cross-sectional view of an embodiment of a portion of a display panel in an embodiment of the present disclosure; and

[0037] Figures 8A to 8E is a plan view of an embodiment of a display panel assembly according to the present disclosure. DETAILED DESCRIPTION

[0038] The present disclosure can be modified in various ways and implemented in many different forms, and thus will be illustrated in the accompanying drawings and illustrative embodiments will be described in detail below. However, the present disclosure should not be limited to the specific disclosed form, and should be construed to include all modifications, equivalents or alternatives included in the spirit and scope of the present disclosure.

[0039] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0040] It will be further understood that the terms “include” and / or “comprises” when used in this specification specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0041] In this disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present.

[0042] For ease of description, spatially relative terms such as “below,” “lower,” “above,” “upper,” etc. may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the drawings.

[0043] In the present disclosure, the term “on” may mean that a portion of one element is disposed at a lower portion as well as an upper portion of another element.

[0044] In this disclosure, when an element is referred to as being "directly connected" to another element, there are no intervening elements between one layer, film, region, or substrate and the other layer, film, region, or substrate. For example, the term "directly connected" may mean that two layers or two components are disposed without using an additional adhesive between them.

[0045] As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0046] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element, and vice versa, without departing from the teachings of the present disclosure.

[0047] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0048] In the accompanying drawings, the proportions and sizes (eg, thickness) of components are exaggerated for efficient description of technical contents.

[0049] Hereinafter, a display panel and a display panel assembly of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 FIG. 1 is an assembled perspective view of an electronic device (ELD) according to an embodiment of the present disclosure. Figure 2 FIG. 1 is an exploded perspective view of an electronic device (ELD) according to an embodiment of the present disclosure.

[0051] refer to Figure 1 The electronic device ELD can be activated in response to an electrical signal and can display an image. In one embodiment, the electronic device ELD can be applied to large display devices such as televisions and outdoor billboards, as well as small and medium-sized display devices such as monitors, mobile phones, tablet computers, navigation units, and gaming units. However, these are merely exemplary embodiments, and the electronic device ELD can be applied to other display devices as long as they do not deviate from the concept of the present disclosure.

[0052] The electronic device ELD can be rigid or flexible. As used herein, the term "flexible" refers to a property of being bendable. In one embodiment, the flexible electronic device ELD can be, for example, a bendable device, a rollable device, or a foldable device.

[0053] In the illustrated embodiment, the third direction DR3 may be substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2. The front (or top) and rear (or bottom) surfaces of each component of the electronic device ELD may be opposite to each other in the third direction DR3, and the normal direction of each of the front and rear surfaces may be substantially parallel to the third direction DR3. The separation distance between the front and rear surfaces in the third direction DR3 may correspond to the thickness of each component in the third direction DR3.

[0054] In this disclosure, the expression "in a plan view" may refer to a state viewed in the third direction DR3. In this disclosure, the expression "in a cross-section" may refer to a state viewed in the first direction DR1 or the second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative to each other, and therefore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to other directions.

[0055] The electronic device ELD can display an image IM toward a third direction DR3 via a display surface IS that is substantially parallel to a plane defined by the first direction DR1 and the second direction DR2. However, the shape of the display surface IS should not be limited thereto or thereby, and the display surface IS may further include a curved surface that bends from at least one side of the plane. The display surface IS displaying the image IM may correspond to the front surface of the electronic device ELD. The image IM may include video as well as still images. Figure 1A clock widget and application icons are shown as representative embodiments of the image IM.

[0056] The electronic device ELD may have a quadrilateral shape in a plan view, for example, a rectangular shape having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 intersecting (e.g., perpendicular) to the first direction DR1. However, the shape of the electronic device ELD should not be limited to a quadrilateral shape (e.g., a rectangular shape), and the electronic device ELD may have various shapes in a plan view, such as a circular shape, other polygonal shapes, etc.

[0057] The electronic device ELD can sense an external input TC applied thereto from the outside. The external input TC may include various forms of input, such as force (e.g., pressure), temperature, light, and the like. In the illustrated embodiment, a touch input generated by the hand of the user US and applied to the front surface of the electronic device ELD will be described as an exemplary embodiment of the external input TC. However, this is only one of the embodiments, and the external input TC may include all types of inputs that cause a change in capacitance. The area of ​​the electronic device ELD that senses the external input TC should not be limited to the front surface of the electronic device ELD, and the electronic device ELD may sense the external input TC applied by the user US to the side surface or rear surface of the electronic device ELD according to the structure of the electronic device ELD.

[0058] The display surface IS of the electronic device ELD may include an image area IA and a frame area BZA. An image IM may be displayed via the image area IA. A user may view the image IM via the image area IA. In the illustrated embodiment, the image area IA may have a quadrilateral shape with curved vertices. However, this is only one embodiment, and the image area IA may have various shapes.

[0059] The bezel area BZA may have a predetermined color and may block light. The bezel area BZA may be defined as being adjacent to (or proximate to) the image area IA. In one embodiment, the bezel area BZA may be disposed outside the image area IA and may surround the image area IA. Accordingly, the shape of the image area IA may be substantially defined by the bezel area BZA, however, this is only one embodiment. That is, the bezel area BZA may be disposed only on one side of (or proximate to) the image area IA, may be disposed on a side surface of the electronic device ELD, or may be omitted.

[0060] refer to Figure 1 and Figure 2 , the electronic device ELD may include a window WM, a display device DD, an optical member AF, an electronic module EM, a power module PSM and a housing EDC.

[0061] The window WM may be provided on the display device DD and the optical member AF. The window WM may protect the display device DD from external impact and scratches applied to the display device DD. The front surface of the window WM may correspond to the display surface IS of the electronic device ELD.

[0062] The optical member AF may be provided on the display device DD. The optical member AF may reduce the reflectivity of the display device DD with respect to external light. In one embodiment, the optical member AF may include a polarizing film including a retarder and / or a polarizer, a plurality of reflective layers that destructively interfere with reflected light, or a plurality of color filters provided to correspond to the arrangement of pixels and the color of emitted light. Figure 2 Unlike the structure of the electronic device ELD shown in , the electronic device ELD may not include the optical member AF.

[0063] The display device DD may generate an image IM output to the outside of the electronic device ELD and may sense an external input TC. The display device DD may include a display panel DP and an input sensor ISP.

[0064] The display panel DP can display an image IM in response to an electrical signal. In one embodiment, the display panel DP can be a light-emitting display panel, however, this is not particularly limited. In one embodiment, the display panel DP can be, for example, an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. Hereinafter, an organic light-emitting display panel will be described as an exemplary embodiment of the display panel DP.

[0065] The input sensor ISP may be provided on the display panel DP. The input sensor ISP may sense the external input TC and may provide an input signal including information about the external input TC to allow the display panel DP to display an image IM corresponding to the external input TC. The input sensor ISP may be driven by various methods such as a capacitance method, a resistance film method, an infrared method, an acoustic wave method, or a pressure method, however, it should not be particularly limited. Figure 2 The structure of the electronic device ELD shown in FIG is different from that of FIG. , and the electronic device ELD may not include the input sensor ISP.

[0066] The display device DD may include an active area AA and a peripheral area NAA defined as being adjacent to (or adjacent to) the active area AA. The light-emitting elements of the display panel DP or the sensing electrodes of the input sensor ISP may be disposed in the active area AA. The display device DD may be activated in response to an electrical signal to display an image IM in the active area AA, or may sense an external input TC in the active area AA. Driving circuits, signal lines, and pads may be disposed in the peripheral area NAA to drive the elements in the active area AA.

[0067] The active area AA may overlap with the image area IA of the electronic device ELD, and the peripheral area NAA may overlap with the bezel area BZA of the electronic device ELD. Components disposed in the peripheral area NAA may be prevented from being seen from the outside by the bezel area BZA.

[0068] The electronic device ELD may further include a main circuit board MCB, a flexible circuit film FCB, a data driver DIC, a sensor control circuit T-IC, and a main controller 100 .

[0069] The main circuit board MCB may include a plurality of driving elements. The main circuit board MCB may be electrically connected to the display panel DP and the input sensor ISP via a flexible circuit film FCB. The main circuit board MCB may be electrically connected to the electronic module EM via a connector.

[0070] The flexible circuit film FCB may be connected to the display panel DP to electrically connect the display panel DP to the main circuit board MCB. The input sensor ISP may be electrically connected to the display panel DP and may be electrically connected to the main circuit board MCB via the flexible circuit film FCB, however, the present disclosure should not be limited thereto or thereby. In one embodiment, the input sensor ISP may be electrically connected to the main circuit board MCB via an additional flexible circuit film, or the flexible circuit film FCB may be omitted and the main circuit board MCB may be directly connected to the display panel DP.

[0071] Each of the data driver DIC, the sensor control circuit T-IC, and the main controller 100 may be provided in an integrated chip. The data driver DIC may be provided (e.g., mounted) on the display panel DP, and the sensor control circuit T-IC and the main controller 100 may be provided (e.g., mounted) on the main circuit board MCB. However, the present disclosure should not be limited thereto or thereby. In one embodiment, the data driver DIC may be provided (e.g., mounted) on a flexible circuit film FCB.

[0072] The main controller 100 may control the overall operation of the electronic device (ELD). In one embodiment, the main controller 100 may control the operation of the display panel DP and the input sensor ISP. Additionally, the main controller 100 may control the operation of, for example, the electronic module EM. The main controller 100 may include at least one microprocessor.

[0073] The data driver DIC may include a driving circuit for driving pixels of the display panel DP. The data driver DIC may receive image data and control signals from the main controller 100. In one embodiment, the control signals may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal.

[0074] The sensor control circuit T-IC may provide an electrical signal to the input sensor ISP to drive the input sensor ISP. The sensor control circuit T-IC may receive a control signal such as a clock signal from the main controller 100.

[0075] The electronic module EM may include various functional modules to drive the display device DD. In one embodiment, the electronic module EM may include a wireless communication module, an image input module, an audio input module, an audio output module, a memory, an external interface module, etc. The modules of the electronic module EM may be disposed (e.g., mounted) on the main circuit board MCB, or may be electrically connected to the main circuit board MCB via a separate flexible circuit board.

[0076] The power supply module PSM may be electrically connected to the electronic module EM. The power supply module PSM may supply power required for the overall operation of the electronic device ELD. In one embodiment, the power supply module PSM may include a conventional battery.

[0077] The housing EDC can be coupled to the window WM to define the exterior of the electronic device ELD. The window WM can be coupled to the housing EDC to form an interior space for accommodating components of the electronic device ELD. The display device DD, the flexible circuit film FCB, the main circuit board MCB, the electronic module EM, and the power supply module PSM can be accommodated in the interior space. The display panel DP can be bent to allow the flexible circuit film FCB and the main circuit board MCB to face the rear surface of the display device DD, and can then be accommodated in the housing EDC. The housing EDC can be disposed below the display panel DP.

[0078] The housing EDC may be made of a relatively rigid material. In one embodiment, the housing EDC may include a frame and / or plate made of glass, plastic, metal, or a combination thereof. The housing EDC can absorb external impact and prevent foreign matter or moisture from entering, thereby protecting the display device DD.

[0079] Figure 3A and Figure 3B For the Figure 2 A cross-sectional view of the electronic device ELD taken along line II'.

[0080] Figure 3A and Figure 3B Various embodiments of stacking structures of components included in an electronic device ELD are shown, and reference is made to Figure 1 and Figure 2 The details of the described window WM, display panel DP and input sensor ISP can be applied to Figure 3A and Figure 3B The window WM, display panel DP and input sensor ISP in it.

[0081] refer to Figure 3A and Figure 3B The window WM may include a base film WBB and a frame pattern WBM. The base film WBB may include an optically transparent insulating material. The base film WBB may include at least one of a glass film and a synthetic resin film. The base film WBB may have a single-layer structure or a multi-layer structure of two or more films attached to each other. The window WM may further include a functional layer disposed on the base film WBB, such as an anti-fingerprint layer, a phase control layer, a hard coating layer, and the like.

[0082] The frame pattern WBM may be a colored layer formed on the surface of the base film WBB. The frame pattern WBM may include a material having a predetermined color. In one embodiment, the frame pattern WBM may include a colored organic layer. The frame pattern WBM may have a single-layer or multi-layer structure. The frame pattern WBM having a multi-layer structure may include a colored layer and a light-blocking layer having a non-color (e.g., black). The frame pattern WBM may be formed by a deposition, printing, or coating process.

[0083] The frame pattern WBM may be provided to coincide with the frame area BZA of the electronic device ELD (refer to Figure 1 The area of ​​the window WM where the frame pattern WBM is provided may have a lower light transmittance than the area where the frame pattern WBM is not provided.

[0084] The first adhesive layer AL1 may be provided between the window WM and the optical member AF. The window WM may be coupled to the optical member AF via the first adhesive layer AL1, however, the present disclosure should not be limited thereto or thereby. In one embodiment, the first adhesive layer AL1 may be omitted, and the window WM may be provided directly on the optical member AF.

[0085] refer to Figure 3A The input sensor ISP can be directly disposed on the display panel DP. The input sensor ISP can be formed on the substrate surface provided by the display panel DP through a continuous process during the manufacturing process of the display device DD. The input sensor ISP can be integrally coupled to the display panel DP without the need for a separate adhesive.

[0086] refer to Figure 3A The optical member AF may be directly disposed on the display device DD. In one embodiment, the optical member AF may be formed on the upper surface of the input sensor ISP through a continuous process. The optical member AF may include a color filter and may be formed by coating, patterning, or printing a composition for a color filter on the surface of a substrate provided by the input sensor ISP.

[0087] However, the present disclosure should not be limited thereto or thereby, and reference is made to Figure 3BThe optical member AF may be coupled to the display device DD via the second adhesive layer AL2. In one embodiment, the optical member AF may be provided in the form of a film such as a polarizing film and may be coupled to the display device DD via the second adhesive layer AL2 provided on the upper surface of the input sensor ISP.

[0088] refer to Figure 3B The display device DD may further include a third adhesive layer AL3 disposed between the input sensor ISP and the display panel DP. The input sensor ISP may be coupled to the display panel DP via the third adhesive layer AL3. In one embodiment, the input sensor ISP may be provided as a touch panel manufactured using a separate process from that of the display panel DP, and the input sensor ISP may be coupled to the display panel DP via the third adhesive layer AL3 disposed on the upper surface of the display panel DP.

[0089] Each of the first adhesive layer AL1, the second adhesive layer AL2 and the third adhesive layer AL3 may include a transparent adhesive, such as an optically clear adhesive ("OCA") film, an optically clear resin ("OCR") or a pressure-sensitive adhesive ("PSA") film, however, the adhesive included in the first adhesive layer AL1, the second adhesive layer AL2 and the third adhesive layer AL3 should not be limited thereto or thereby.

[0090] Figure 3A and Figure 3B The stacking structure and stacking order of the components included in the electronic device ELD shown in FIG. 1 are merely exemplary embodiments, and the present disclosure should not be limited thereto or thereby. In one embodiment, the electronic device ELD may further include a protective layer disposed below the display panel DP, or the optical member AF may be omitted. Furthermore, the stacking order of the optical member AF and the input sensor ISP may be changed, and the optical member AF may be disposed between the display panel DP and the input sensor ISP.

[0091] Figure 4 FIG. 4 is a plan view of an embodiment of a display panel DP according to the present disclosure.

[0092] refer to Figure 4 The display panel DP may include a base layer BL, a plurality of pixels PX, a plurality of signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2 and PL electrically connected to the pixels PX, a scan driver SDV, an emission driver EDV and a plurality of pads PD1.

[0093] The base layer BL may provide a base surface on which the elements and lines of the display panel DP are arranged. The base layer BL may include a display area DA and a non-display area NDA. The display area DA may be an area where pixels PX are arranged to display an image, and the non-display area NDA may be an area where elements and lines are arranged to drive the pixels PX and do not display an image, and may be arranged close to (or adjacent to) the display area DA. The display area DA may be aligned with the active area AA (refer to FIG. 1 ) of the display device DD. Figure 2 ), and the non-display area NDA may correspond to the peripheral area NAA of the display device DD (reference Figure 2 )correspond.

[0094] The display panel DP may include a display area DA and a non-display area NDA defined therein. The non-display area NDA may be defined to surround the display area DA.

[0095] The non-display area NDA may include an edge area NDA1. Specifically, the edge area NDA1 may include a first edge area NDA1-1 extending in a first direction DR1, a second edge area NDA1-2 spaced apart from the first edge area NDA1-1 in a second direction DR2 and extending in the first direction DR1, a third edge area NDA1-3 extending in the second direction DR2 and connecting one end of the first edge area NDA1-1 and one end of the second edge area NDA1-2, and a fourth edge area NDA1-4 spaced apart from the third edge area NDA1-3 in the first direction DR1 and extending in the second direction DR2. The fourth edge area NDA1-4 may connect opposite ends of the first edge area NDA1-1 and opposite ends of the second edge area NDA1-2.

[0096] The non-display area NDA may further include a pad area NDA2 spaced apart from the display area DA and close to (or adjacent to) the edge area NDA1. Specifically, the pad area NDA2 may be disposed close to (or adjacent to) the first edge area NDA1-1. The pad PD1 may be disposed in the pad area NDA2.

[0097] Each of the pixels PX may include a pixel driving circuit including a plurality of transistors (e.g., a switching transistor, a driving transistor, etc.) and a light-emitting element electrically connected to the pixel driving circuit. Each of the pixels PX may emit light in response to an electrical signal applied thereto.

[0098] Each of the scan driver SDV, the data driver DIC, and the emission driver EDV may be disposed in the non-display area NDA, however, the present disclosure should not be limited thereto or thereby. In one embodiment, at least one of the scan driver SDV, the data driver DIC, and the emission driver EDV may be disposed in the display area DA, thereby reducing the size of the non-display area NDA.

[0099] The signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL may include a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, a first control line CSL1, a second control line CSL2, and a power line PL. Each of m and n is a natural number greater than 1. Each pixel PX may be electrically connected to a corresponding scan line among the scan lines SL1 to SLm, a corresponding data line among the data lines DL1 to DLn, and a corresponding emission line among the emission lines EL1 to ELm. Depending on the configuration of the pixel driving circuit of the pixel PX, more types of signal lines may be provided in the display panel DP.

[0100] The scan lines SL1 to SLm may extend in a direction opposite to the first direction DR1 and may be electrically connected to the scan driver SDV. The data lines DL1 to DLn may extend in a direction opposite to the second direction DR2 and may be electrically connected to the data driver DIC. The emission lines EL1 to ELm may extend in the first direction DR1 and may be electrically connected to the emission driver EDV.

[0101] The power line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion of the power line PL extending in the first direction DR1 and the portion of the power line PL extending in the second direction DR2 may be provided in different layers and may be connected to each other via contact holes, however, they should not be limited thereto or thereby. In one embodiment, the portion of the power line PL extending in the first direction DR1 and the portion of the power line PL extending in the second direction DR2 may be provided in the same layer and may be integrally provided with each other.

[0102] A portion of the power line PL extending in the first direction DR1 may extend to the display area DA and may be electrically connected to the pixel PX, and a portion of the power line PL extending in the second direction DR2 may be disposed in the non-display area NDA and may extend to the pad PD1. The power line PL may receive a power voltage and may provide the power voltage to the pixel PX.

[0103] The first control line CSL1 may be electrically connected to the scan driver SDV, and the second control line CSL2 may be electrically connected to the emission driver EDV.

[0104] The pads PD1 may be positioned near (or adjacent to) the lower end of the non-display area NDA. The pads PD1 may be positioned closer to the lower end of the display panel DP than the lower end of the data driver DIC to the display panel DP. The pads PD1 may be arranged to be spaced apart from each other in the first direction DR1. The pads PD1 may be electrically connected to a circuit board that provides signals for controlling the operation of the scan driver SDV, the data driver DIC, and the emission driver EDV.

[0105] Each of the pads PD1 can be connected to a corresponding signal line among the signal lines SL1 to SLm, DL1 to DLn, EL1 to ELm, CSL1, CSL2, and PL. In one embodiment, the power line PL, the first and second control lines CSL1 and CSL2, and the data lines DL1 to DLn can be connected to the corresponding pads PD1. The data lines DL1 to DLn can be connected to the corresponding pads PD1 via the data driver DIC.

[0106] The scan driver SDV generates a plurality of scan signals in response to a scan control signal. The scan signals are applied to pixels PX via scan lines SL1 to SLm. The data driver DIC generates a plurality of data voltages corresponding to image signals in response to the data control signal. The data voltages are applied to pixels PX via data lines DL1 to DLn. The emission driver EDV generates a plurality of emission signals in response to an emission control signal. The emission signals are applied to pixels PX via emission lines EL1 to ELm.

[0107] The pixels PX may receive a data voltage in response to a scan signal. The pixels PX may emit light having a brightness corresponding to the data voltage in response to an emission signal, thereby displaying an image. The emission timing of the pixels PX may be controlled by the emission signal. Accordingly, the display panel DP may display an image through the display area DA using the pixels PX.

[0108] Figure 5 FIG. 4 is a cross-sectional view of a portion of a display area DA according to an embodiment of the present disclosure.

[0109] Figure 5 The lower substrate LSB of the display panel DP (refer to Figure 6 and Figure 7 ) layers. In detail, Figure 5 Pixels PX included in the display area DA of the display panel DP (refer to Figure 4 ) is taken as an exemplary embodiment.

[0110] The display panel DP may include a base layer BL, a circuit layer DP-CL, a light emitting element layer DP-OLED, and an upper insulating layer TFL. The circuit layer DP-CL, the light emitting element layer DP-OLED, and the upper insulating layer TFL may be disposed on the base layer BL.

[0111] The base layer BL provides a base surface upon which the circuit layer DP-CL, the light-emitting element layer DP-OLED, and the upper insulating layer TFL are stacked. The base layer BL can be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable. The base layer BL can be a glass substrate, a metal substrate, or a polymer substrate, but is not limited thereto or thereby. In one embodiment, the base layer BL can include an inorganic layer, an organic layer, or a composite material layer.

[0112] The base layer BL may have a multi-layer structure. In one embodiment, the base layer BL may include, for example, a first synthetic resin layer, an inorganic layer having a single-layer or multi-layer structure, and a second synthetic resin layer disposed on the inorganic layer having a single-layer or multi-layer structure. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide resin, however, this should not be particularly limited.

[0113] The circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The conductive layer of the circuit layer DP-CL may form a signal line or a control circuit of a pixel.

[0114] The light-emitting element layer DP-OLED may be disposed on the circuit layer DP-CL. The light-emitting element layer DP-OLED may include light-emitting elements. In one embodiment, the light-emitting element layer DP-OLED may include, for example, organic light-emitting elements, inorganic light-emitting elements, organic-inorganic light-emitting elements, micro light-emitting diodes ("micro-LEDs"), nano-LEDs, quantum light-emitting elements, electrophoretic light-emitting elements, electrowetting light-emitting elements, and the like.

[0115] The upper insulating layer TFL may include a capping layer CPL and an encapsulation layer (eg, a thin film encapsulation layer) TFE.

[0116] The upper insulating layer TFL may be disposed on the light-emitting element layer DP-OLED and may protect the light-emitting element layer DP-OLED from moisture, oxygen, and foreign substances such as dust particles. The upper insulating layer TFL may encapsulate the light-emitting element layer DP-OLED to prevent moisture and oxygen from entering the light-emitting element layer DP-OLED.

[0117] The circuit layer DP-CL may include at least one insulating layer and circuit elements. The circuit elements may include signal lines and pixel driving circuits. The circuit layer DP-CL may be formed by a coating or deposition process for forming insulating layers, semiconductor layers, and conductive layers, and a photoetching process for patterning the insulating layers, semiconductor layers, and conductive layers.

[0118] The buffer layer BFL may include at least one inorganic layer. The semiconductor pattern may be disposed on the buffer layer BFL. The buffer layer BFL may increase the coupling force between the base layer BL and the semiconductor pattern.

[0119] The semiconductor pattern may include polysilicon, however, it should not be limited thereto or thereby.The semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 A portion of the semiconductor pattern is shown, and the semiconductor pattern may be further provided in other regions of the pixel in a plan view. The semiconductor pattern may be arranged in a predetermined regular pattern throughout the pixel PX.

[0120] A semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region A1 having a relatively low doping concentration and relatively low conductivity, and second regions S1 and D1 having a relatively high doping concentration and relatively high conductivity. One second region S1 may be disposed on one side of the first region A1, and another second region D1 may be disposed on the opposite side of the first region A1. The second regions S1 and D1 may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant. The first region A1 may be an undoped region, or may be doped at a lower concentration than that of the second regions S1 and D1.

[0121] The second regions S1 and D1 may substantially function as electrodes or signal lines. One second region S1 may correspond to a source portion of the transistor TR, and the other second region D1 may correspond to a drain portion of the transistor TR. Figure 5 A portion of the connection signal line SCL including or consisting of a semiconductor pattern is shown. Figure 5 Although not shown in the figure, in a plan view, the connection signal line SCL may be connected to the drain portion of the transistor TR.

[0122] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may overlap with the pixels arranged in the display area DA and may cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. Not only the first insulating layer 10, but also other insulating layers of the circuit layer DP-CL described later may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure.

[0123] The gate portion G1 may be disposed on the first insulating layer 10. The gate portion G1 may be a portion of a metal pattern. The gate portion G1 may overlap the first region A1. The gate portion G1 may be used as a mask in a process of doping the semiconductor pattern.

[0124] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate portion G1. The second insulating layer 20 may overlap with the pixel. The upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the gate portion G1. The upper electrode UE may include multiple metal layers. In one embodiment, the upper electrode UE may be omitted.

[0125] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the upper electrode UE. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL via a contact hole CNT-1 defined through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0126] The fourth insulating layer 40 may be disposed on the third insulating layer 30, and the fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fourth insulating layer 40 may be an organic layer. The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined through the fourth insulating layer 40.

[0127] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0128] The light-emitting element OLED may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined through the fifth insulating layer 50. The pixel defining layer PDL may be provided with a pixel opening OP defined therethrough. At least a portion of the first electrode AE ​​may be exposed through the pixel opening OP of the pixel defining layer PDL. The pixel defining layer PDL may be an organic layer.

[0129] The display area DA may include a pixel area PXA and a non-pixel area NPXA adjacent to (or adjacent to) the pixel area PXA. The non-pixel area NPXA may surround the pixel area PXA. In the illustrated embodiment, the pixel area PXA may be defined to correspond to a portion of the first electrode AE ​​exposed through the pixel opening OP.

[0130] The light-emitting element OLED may include a first electrode AE, a hole transport region HTR, an emission layer EML, an electron transport region ETR, and a second electrode CE. The hole transport region HTR may be disposed on the first electrode AE. The emission layer EML may be disposed on the hole transport region HTR. The electron transport region ETR may be disposed on the emission layer EML. The second electrode CE may be disposed on the electron transport region ETR. The second electrode CE may have a single overall shape.

[0131] The hole transport region HTR, the light emitting layer EML, and the electron transport region ETR may be formed together throughout the pixel using an open mask, however, the present disclosure should not be limited thereto or thereby. In one embodiment, at least one of the hole transport region HTR, the light emitting layer EML, and the electron transport region ETR may be formed using a mask through a patterning process.

[0132] The upper insulating layer TFL may be disposed on the light-emitting element layer DP-OLED and may include multiple thin layers. In one embodiment, the upper insulating layer TFL may include a capping layer CPL and an encapsulation layer TFE disposed on the capping layer CPL. The capping layer CPL may be disposed on the second electrode CE and may contact the second electrode CE. The capping layer CPL may include an organic material.

[0133] The encapsulation layer TFE may include a first inorganic encapsulation layer TIOL1, an organic encapsulation layer TOL disposed on the first inorganic encapsulation layer TIOL1, and a second inorganic encapsulation layer TIOL2 disposed on the organic encapsulation layer TOL. The first and second inorganic encapsulation layers TIOL1 and TIOL2 may protect the light-emitting element layer DP-OLED from moisture and oxygen, and the organic encapsulation layer TOL may protect the light-emitting element layer DP-OLED from foreign substances such as dust particles.

[0134] Figures 6 and 7 is a cross-sectional view of a portion of the display panel DP according to the present disclosure.

[0135] Figure 6 and Figure 7 The above-mentioned edge area NDA1 and a portion of the display area DA close to (or adjacent to) the edge area NDA1 are shown as an exemplary embodiment. Figure 6 and Figure 7 The edge area NDA1 shown in FIG can be connected with the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3 and the fourth edge area NDA1-4 (refer to FIG Figure 4 ) corresponds to at least one of .

[0136] refer to Figure 6 and Figure 7 , the display panel DP may include a lower substrate LSB, an upper substrate USB disposed on the lower substrate LSB, and a filler FLL disposed between the lower substrate LSB and the upper substrate USB.

[0137] The lower substrate LSB may include a circuit layer DP-CL, a light emitting element layer DP-OLED, and an encapsulation layer TFE. In addition, the lower substrate LSB may further include a color filter layer CF disposed on the upper insulating layer TFL. Figure 6 and Figure 7Although not shown, the lower substrate LSB may further include a functional layer disposed over the upper insulating layer TFL to improve light emitting quality, in addition to the color filter layer CF.

[0138] The upper substrate USB may also be referred to as a packaging substrate. The upper substrate USB may include a plastic substrate, a glass substrate, a metal substrate, or an organic and / or inorganic composite material substrate. The upper substrate USB may be separated from the lower substrate LSB by a predetermined gap.

[0139] The filler FLL may be disposed to overlap at least the display area DA. The filler FLL may be disposed between the upper substrate USB and the lower substrate LSB and may be filled between the upper substrate USB and the lower substrate LSB. The filler FLL may include a desiccant or a resin material.

[0140] The sealant SSL may be disposed (eg, directly disposed) between the upper substrate USB and the lower substrate LSB and may couple the upper substrate USB with the lower substrate LSB. The sealant SSL may include an organic adhesive or a frit.

[0141] The dam DAM may be provided in the edge area NDA1. The dam DAM may include an insulating material. In a plan view, the dam DAM may be provided to surround the display area DA.

[0142] refer to Figure 6 , the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3 and the fourth edge area NDA1-4 (reference Figure 4 ) may include a sealant SSL disposed between the upper substrate USB and the lower substrate LSB. The sealant SSL may be disposed between the upper substrate USB and the lower substrate LSB and may couple the upper substrate USB with the lower substrate LSB. In a plan view, the sealant SSL may be disposed to overlap the first inorganic encapsulation layer TIOL1 and the second inorganic encapsulation layer TIOL2, and may be disposed to not overlap the organic encapsulation layer TOL.

[0143] The filler FLL may extend from the display area DA and may be disposed to overlap a portion of the area in which the sealant SSL is disposed. Figure 6 As shown in FIG, the filler FLL extending from the display area DA may be spaced apart from the sealant SSL in a plan view, or may be disposed in contact with the sealant SSL in a plan view.

[0144] refer to Figure 7 , the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3 and the fourth edge area NDA1-4 (reference Figure 4 ) may include a filler FLL between the upper substrate USB and the lower substrate LSB, but does not include a seal SSL (reference Figure 6 In this case, the filler FLL may extend from the display area DA and may be disposed in at least one of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4. Figure 7 As shown in FIG, the filler FLL extending from the display area DA may be completely provided over at least one edge area of ​​the first, second, third, and fourth edge areas NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where the sealant SSL is not provided.

[0145] In one embodiment, the sealant SSL may be provided in one edge area of ​​the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the display panel may have the following features: Figure 6 In this case, the sealant SSL may not be provided in the other three edge areas (i.e., the remaining three edge areas) of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the filler FLL may extend from the display area DA and may be provided in the other three edge areas (i.e., the remaining three edge areas). The display panel may have Figure 7 The cross section shown in .

[0146] In one embodiment, the sealant SSL may be provided in two edge areas among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the display panel may have the following features: Figure 6 In this case, the sealant SSL may not be provided in the other two edge areas (i.e., the remaining two edge areas) of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the filler FLL may extend from the display area DA and may be provided in the other two edge areas (i.e., the remaining two edge areas). The display panel may have Figure 7 The cross section shown in .

[0147] In one embodiment, the sealant SSL may be provided in three edge areas of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the display panel may have the following features: Figure 6In this case, the sealant SSL may not be provided in the other edge area (i.e., the remaining edge area) of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the filler FLL may extend from the display area DA and may be provided in the other edge area (i.e., the remaining edge area). The display panel may have Figure 7 The cross section shown in .

[0148] Figures 8A to 8E is a plan view of an embodiment of a display panel assembly ASS according to the present disclosure.

[0149] The seal member SSL is disposed between the upper mother substrate UMB and the lower mother substrate LMB. Figures 8A to 8E , the sealant SSL is illustrated to show an arrangement relationship of the sealant SSL between the upper mother substrate UMB and the lower mother substrate LMB in a plan view.

[0150] The display panel assembly ASS is used to form a plurality of unit display panels DPU. Figures 8A to 8E A structure in which four unit display panels DPU are arranged in the display panel assembly ASS is shown, however, the present disclosure should not be limited thereto or thereby. By way of example, two, three, five or more unit display panels DPU may be arranged in the display panel assembly ASS.

[0151] refer to Figures 8A to 8E , the display panel assembly ASS may include a unit display panel DPU, and a cutting area CA surrounding the unit display panel DPU in a plan view may be defined in the display panel assembly ASS. The cutting area CA may be removed after cutting.

[0152] The display panel assembly ASS may include an upper mother substrate UMB, a lower mother substrate LMB, and a filler FLL (refer to FIG. Figure 6 and Figure 7 ). In a plan view, the upper mother substrate UMB may overlap with the lower mother substrate LMB.

[0153] refer to Figure 6 and Figure 7 The description of the upper substrate USB is also applicable to the unit display panel DPU of the upper mother substrate UMB. Figure 6 and Figure 7 The description of the lower substrate LSB may be equally applicable to the unit display panel DPU of the lower mother substrate LMB.

[0154] At least one of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 may include a sealant SSL disposed between the upper mother substrate UMB and the lower mother substrate LMB. The sealant SSL may be directly disposed between the upper mother substrate UMB and the lower mother substrate LMB and may couple the upper mother substrate UMB with the lower mother substrate LMB.

[0155] The filler FLL may extend from the display area DA of the unit display panel DPU and may be disposed to overlap a portion of the area in which the sealant SSL is disposed. Figure 6 As shown in FIG, the filler FLL extending from the display area DA may be spaced apart from the sealant SSL in a plan view, or may be disposed in contact with the sealant SSL in a plan view.

[0156] At least one edge area among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 may include a filler FLL between the upper substrate USB and the lower substrate LSB without including the sealant SSL. In this case, the filler FLL may extend from the display area DA and may be provided in at least one of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4. Figure 7 As shown in FIG, the filler FLL extending from the display area DA may be completely provided over at least one edge area of ​​the first, second, third, and fourth edge areas NDA1-1, NDA1-2, NDA1-3, and NDA1-4 where the sealant SSL is not provided.

[0157] The unit display panel DPU may include a plurality of first unit display panels DPU1 and a plurality of second unit display panels DPU2 spaced apart from the first unit display panels DPU1 in the first direction DR1 and arranged alternately with the first unit display panels DPU1 .

[0158] In one embodiment, the seal SSL may be provided in two edge areas of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the first unit display panel DPU1, and the display panel may have the following configuration: Figure 6In this case, the filler FLL extending from the display area DA may be provided in the other two edge areas (i.e., the remaining two edge areas) where the sealant SSL is not provided among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the first unit display panel DPU1, and the display panel may have the following structure: Figure 7 The cross section shown in .

[0159] In one embodiment, the seal SSL may be provided in one of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following configuration: Figure 6 In this case, the filler FLL extending from the display area DA may be provided in the other three edge areas (i.e., the remaining three edge areas) where the sealant SSL is not provided among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following structure: Figure 7 The cross section shown in .

[0160] In detail, such as Figure 8B As shown in , the sealant SSL may be provided in the second edge area NDA1-2 and the third edge area NDA1-3 of the first unit display panel DPU1. In the first unit display panel DPU1, the sealant SSL may not be provided in the first edge area NDA1-1 and the fourth edge area NDA1-4, and the filler FLL may be extended to be provided in the first edge area NDA1-1 and the fourth edge area NDA1-4. In the second unit display panel DPU2, the sealant SSL may be provided in the second edge area NDA1-2. In the second unit display panel DPU2, the sealant SSL may not be provided in the first edge area NDA1-1, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the filler FLL may be extended to be provided in the first edge area NDA1-1, the third edge area NDA1-3, and the fourth edge area NDA1-4.

[0161] In one embodiment, if Figure 8CAs shown in , in the first unit display panel DPU1, the sealant SSL may be provided in the first edge area NDA1-1 and the third edge area NDA1-3. In the first unit display panel DPU1, the sealant SSL may not be provided in the second edge area NDA1-2 and the fourth edge area NDA1-4, and the filler FLL may be extended to be provided in the second edge area NDA1-2 and the fourth edge area NDA1-4. In the second unit display panel DPU2, the sealant SSL may be provided in the first edge area NDA1-1. In the second unit display panel DPU2, the sealant may not be provided in the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4, and the filler FLL may be extended to be provided in the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4.

[0162] In one embodiment, the seal SSL may be provided in two edge areas of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following configuration: Figure 6 In this case, the filler FLL extending from the display area DA may be provided in the other two edge areas (i.e., the remaining two edge areas) where the sealant SSL is not provided among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following structure: Figure 7 The cross section shown in .

[0163] In detail, such as Figure 8A As shown in FIG, in both the first unit display panel DPU1 and the second unit display panel DPU2, the sealant SSL may be provided in the first edge area NDA1-1 and the second edge area NDA1-2. In both the first unit display panel DPU1 and the second unit display panel DPU2, the sealant SSL may not be provided in the third edge area NDA1-3 and the fourth edge area NDA1-4, and the filler FLL may be provided in the third edge area NDA1-3 and the fourth edge area NDA1-4.

[0164] In one embodiment, if Figure 8EAs shown in FIG, in both the first unit display panel DPU1 and the second unit display panel DPU2, the sealant SSL may be provided in the first edge area NDA1-1 and the third edge area NDA1-3. In both the first unit display panel DPU1 and the second unit display panel DPU2, the sealant SSL may not be provided in the second edge area NDA1-2 and the fourth edge area NDA1-4, and the filler FLL may be provided in the second edge area NDA1-2 and the fourth edge area NDA1-4.

[0165] In one embodiment, the seal SSL may be provided in three edge areas of the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following configuration: Figure 6 In this case, the filler FLL extending from the display area DA may be provided in the other edge area (i.e., the remaining edge area) where the sealant SSL is not provided among the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 defined in the second unit display panel DPU2, and the display panel may have the following structure: Figure 7 The cross section shown in .

[0166] In detail, such as Figure 8D As shown in , in the first unit display panel DPU1, the sealant SSL may be provided in the first edge area NDA1-1 and the second edge area NDA1-2. In the first unit display panel DPU1, the sealant SSL may not be provided in the third edge area NDA1-3 and the fourth edge area NDA1-4, and the filler FLL may be extended to be provided in the third edge area NDA1-3 and the fourth edge area NDA1-4. In the second unit display panel DPU2, the sealant SSL may be provided in the first edge area NDA1-1, the second edge area NDA1-2, and the fourth edge area NDA1-4. In the second unit display panel DPU2, the sealant SSL may not be provided in the third edge area NDA1-3, and the filler FLL may be extended to be provided in the third edge area NDA1-3.

[0167] like Figures 8A to 8EAs shown in , in the edge area NDA1 included in the unit display panel DPU, the seal SSL may be provided in at least one edge area, and may not be provided in at least one edge area. According to the display panel assembly ASS having the above structure, the process for forming the seal SSL can be simplified compared to a display panel assembly having a structure in which the seal is formed in all of the first edge area NDA1-1 to the fourth edge area NDA1-4. In addition, in the area where the first edge area NDA1-1, the second edge area NDA1-2, the third edge area NDA1-3, and the fourth edge area NDA1-4 contact each other, unevenness or overlap of the seal SSL can be reduced. Accordingly, it is possible to prevent the seal SSL from being partially underfilled or overfilled, and to prevent the seal SSL from being broken.

[0168] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but rather that those skilled in the art may make various changes and modifications within the spirit and scope of the present disclosure as claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined according to the appended claims.

Claims

1. A display panel, wherein a display area and a non-display area are defined, wherein the non-display area comprises: a first edge region extending in a first direction; a second edge region spaced apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one end of the first edge region and one end of the second edge region; and a fourth edge region, spaced apart from the third edge region in the first direction and extending in the second direction; The display panel comprises: a lower substrate including a light-emitting element layer; an upper substrate, disposed on the lower substrate; a filler disposed between the lower substrate and the upper substrate and overlapping the display area; and a sealing member disposed between the upper substrate and the lower substrate in at least one edge region among the first edge region to the fourth edge region, At least a portion of the filler extends from the display region to be disposed in at least one edge region from the first edge region to the fourth edge region where the sealing member is not disposed. 2 . The display panel according to claim 1 , wherein the sealing member is directly disposed between the upper substrate and the lower substrate and combines the upper substrate with the lower substrate.

3. The display panel according to claim 1 , wherein the seal is provided in one edge region among the first to fourth edge regions, and the filler extends to be provided in the remaining three edge regions among the first to fourth edge regions where the seal is not provided.

4. The display panel according to claim 1, wherein the seal is provided in two edge regions from the first edge region to the fourth edge region, and the filler extends to be provided in the remaining two edge regions from the first edge region to the fourth edge region where the seal is not provided.

5. The display panel according to claim 1, wherein the seal is provided in three edge regions from the first edge region to the fourth edge region, and the filler is extended to be provided in the remaining one edge region from the first edge region to the fourth edge region where the seal is not provided. 6 . The display panel of claim 1 , wherein the non-display area further comprises a pad area spaced apart from the display area and close to the first edge area.

7. The display panel according to claim 1 , wherein the lower substrate further comprises an encapsulation layer disposed on the light emitting element layer. The encapsulation layer comprises: a first inorganic encapsulation layer, disposed on the light-emitting element layer; an organic encapsulation layer, disposed on the first inorganic encapsulation layer; as well as a second inorganic encapsulation layer disposed on the organic encapsulation layer, and The sealing member overlaps with the first inorganic encapsulating layer and the second inorganic encapsulating layer, and does not overlap with the organic encapsulating layer.

8. A display panel assembly, comprising a plurality of unit display panels, each of the plurality of unit display panels defining a display area and a non-display area, the non-display area comprising: a first edge region extending in a first direction; a second edge region spaced apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one end of the first edge region and one end of the second edge region; and a fourth edge region, spaced apart from the third edge region in the first direction and extending in the second direction; The display panel assembly comprises: a lower mother substrate, comprising a light-emitting element layer; an upper mother substrate, disposed on the lower mother substrate; a filler disposed between the lower mother substrate and the upper mother substrate and overlapping the display area; and a sealing member disposed between the upper mother substrate and the lower mother substrate in at least one edge region among the first edge region to the fourth edge region, At least a portion of the filler extends from the display region to be disposed in at least one edge region from the first edge region to the fourth edge region where the sealing member is not disposed. 9 . The display panel assembly of claim 8 , wherein a cutting area surrounding each of the plurality of unit display panels is defined in the display panel assembly. 10 . The display panel assembly of claim 8 , wherein the sealing member is directly disposed between the upper mother substrate and the lower mother substrate and combines the upper mother substrate with the lower mother substrate. 11 . The display panel assembly of claim 8 , wherein the non-display area further comprises a pad area spaced apart from the display area and adjacent to the first edge area.

12. The display panel assembly according to claim 8, wherein the plurality of unit display panels include a plurality of first unit display panels and a plurality of second unit display panels, the plurality of second unit display panels being spaced apart from the plurality of first unit display panels in the first direction and being alternately arranged with the plurality of first unit display panels, wherein the sealing member is provided in two edge regions among the first edge region to the fourth edge region defined in each of the plurality of first unit display panels, and The filler extends to be disposed in the remaining two edge regions where the sealant is not disposed, from the first edge region to the fourth edge region defined in each of the plurality of first unit display panels.

13. The display panel assembly according to claim 12, wherein the sealant is provided in one edge region among the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and The filler extends to be disposed in the remaining three edge regions, where the sealant is not disposed, from the first to fourth edge regions defined in each of the plurality of second unit display panels.

14. The display panel assembly according to claim 13 , wherein the sealant is disposed in the second edge region and the third edge region of each of the plurality of first unit display panels, and the filler extends to be disposed in the first edge region and the fourth edge region of each of the plurality of first unit display panels. The sealant is disposed in the second edge region of each of the plurality of second unit display panels, and the filler extends to be disposed in the first edge region, the third edge region, and the fourth edge region of each of the plurality of second unit display panels.

15. The display panel assembly according to claim 13 , wherein the sealant is disposed in the first edge region and the third edge region of each of the plurality of first unit display panels, and the filler extends to be disposed in the second edge region and the fourth edge region of each of the plurality of first unit display panels. The sealant is disposed in the first edge region of each of the plurality of second unit display panels, and the filler extends to be disposed in the second edge region, the third edge region, and the fourth edge region of each of the plurality of second unit display panels.

16. The display panel assembly according to claim 12, wherein the sealant is provided in two edge regions among the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and The filler extends to be disposed in the remaining two edge regions, where the sealant is not disposed, among the first to fourth edge regions defined in each of the plurality of second unit display panels.

17. The display panel assembly according to claim 16, wherein the sealant is provided in both the first edge region and the second edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels, and The filler extends to be disposed in the third edge region and the fourth edge region of both each of the plurality of first unit display panels and each of the plurality of second unit display panels.

18. The display panel assembly according to claim 16, wherein the sealant is provided in the first edge region and the third edge region of both each of the plurality of first unit display panels and each of the plurality of second unit display panels, and The filler extends to be disposed in both the second edge region and the fourth edge region of each of the plurality of first unit display panels and each of the plurality of second unit display panels.

19. The display panel assembly according to claim 12, wherein the sealant is provided in three edge regions among the first edge region to the fourth edge region defined in each of the plurality of second unit display panels, and The filler extends to be disposed in a remaining one edge region, in which the sealant is not disposed, among the first to fourth edge regions defined in each of the plurality of second unit display panels.

20. The display panel assembly according to claim 19, wherein the sealant is provided in the first edge region and the second edge region defined in each of the plurality of first unit display panels, and the filler extends to be provided in the third edge region and the fourth edge region defined in each of the plurality of first unit display panels. The sealant is disposed in the first, second, and fourth edge regions defined in each of the plurality of second unit display panels, and the filler extends to be disposed in the third edge region defined in each of the plurality of second unit display panels.

21. An electronic device comprising: Display panel; an input sensor, disposed on the display panel; a window disposed on the input sensor; as well as a housing, disposed below the display panel; The display panel is defined as a display area and a non-display area, and the non-display area includes: a first edge region extending in a first direction; a second edge region spaced apart from the first edge region in a second direction perpendicular to the first direction and extending in the first direction; a third edge region extending in the second direction and connecting one end of the first edge region and one end of the second edge region; and a fourth edge region, spaced apart from the third edge region in the first direction and extending in the second direction; The display panel comprises: a lower substrate including a light-emitting element layer; an upper substrate, disposed on the lower substrate; a filler disposed between the lower substrate and the upper substrate and overlapping the display area; and a sealing member disposed between the upper substrate and the lower substrate in at least one edge region among the first edge region to the fourth edge region, At least a portion of the filler extends from the display region to be disposed in at least one edge region from the first edge region to the fourth edge region where the sealing member is not disposed.

22. The electronic device of claim 21, wherein the electronic device comprises at least one selected from a television, an outdoor billboard, a monitor, a mobile phone, a tablet computer, a navigation unit, and a gaming unit.

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