Reticle front-side potential control with clamping stub connection

Abstract

An electrostatic reticle jig includes a dielectric body, an electrode configured to apply an electrical charge to a first side of the dielectric body to electrostatically clamp a reticle on a second side of the dielectric body, a plurality of tabs located on the second side of the dielectric body and configured to contact the reticle, an electrically conductive coating, a power source, and a controller, the conductive coating is disposed on a surface of the subset of the burns, and the controller is configured to provide a voltage of the power source to the conductive coating.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. application 63 / 445,262, filed February 13, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to systems and methods for reducing particle formation on reticles. Background Art

[0004] In various types of lithography processes, particle formation can create significant defects, leading to yield loss. Defectivity is typically measured as particles per reticle pass (PRP), which is typically measured as particles per 10,000 wafers per reticle.

[0005] For example, in EUV lithography, during an EUV pulse, the EUV beam exposes the reticle. Electrons released into the reticle microenvironment (RME) actually originate from two sources: 1) from the photoelectric effect (expulsion from the reticle), and 2) from electrons generated by photoionization within the volume. As electrons are released from the reticle, the reticle front side acquires a positive charge (not all electrons return to the reticle). The cumulative effect of all these electrons, along with the EUV plasma, creates negatively charged particles in the RME. These particles are then attracted to the positively charged reticle front side, resulting in an increase in PRP.

[0006] There is a continuing need to reduce PRP to increase yield. Summary of the Invention

[0007] The present invention provides the ability to control the potential on the back side of the mask, and therefore the potential on the mask front side of the clamped mask, using an electrostatic mask clamp.By controlling the potential on the mask front side, PRP can be reduced.

[0008] In an embodiment, an electrostatic reticle clamp includes a dielectric, an electrode configured to apply a charge to a first side of the dielectric to electrostatically clamp a reticle on a second side of the dielectric, a plurality of burls located on the second side of the dielectric and configured to contact the reticle, a conductive coating disposed on a surface of a subset of the burls, and a power supply and a controller configured to apply a voltage from the power supply to the conductive coating.

[0009] In an embodiment, the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to a backside of a reticle mounted on the burl, thereby reducing an amount of electrons released into the reticle microenvironment during an EUV pulse.

[0010] In an embodiment, the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to the front side of the reticle. In an embodiment, the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the back side of a reticle mounted on the burl, thereby causing the front side of the reticle to repel particles between EUV pulses.

[0011] In an embodiment, the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the front side of the reticle. In an embodiment, the conductive coating comprises a chromium (Cr) coating or a titanium nitride (TiN) coating.

[0012] In one embodiment, the electrostatic mask plate clamp further comprises a plurality of high voltage and ground connections on the clamp ears, wherein the ears are coated with a conductive clamp ear coating, and wherein the conductive clamp ear coating is connected to a ground pin on at least one clamp ear. In one embodiment, the electrostatic mask plate clamp further comprises one or more covers disposed over the ears, wherein the one or more covers are electrically connected to the conductive clamp ear coating.

[0013] In an embodiment, the conductive coating spans a raised structure that separates the clamp ears from the burls, wherein the raised structure includes a leaky seal for connecting the burls. In an embodiment, a ground connection on one of the ears is modified to provide a voltage to the conductive coating, and wherein a ground pin on the other ear remains grounded. In an embodiment, at least one electrode is grounded. In an embodiment, the conductive coating provides a conductive path from the power source to a surface on a subset of the burls.

[0014] In an embodiment, a method of forming an electrostatic mask fixture includes providing a dielectric having a plurality of burls on a first side thereof; applying a conductive coating to the first side of the dielectric; and patterning the conductive coating on the first side of the dielectric by retaining the coating on a subset of the burls and conductive paths to enable application of a potential to the subset of the burls through the conductive paths.

[0015] In an embodiment, the patterning comprises a photolithographic patterning process to provide a conductive path from at least one clamp ear to a subset of the burls at a peripheral portion of the clamp. In an embodiment, the method further comprises disposing at least one glass body on a second side of the dielectric body and disposing two electrodes between the dielectric body and the at least one glass body. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A lithographic apparatus according to an embodiment is schematically depicted.

[0017] Figure 2 Embodiments of a lithocell or litho cluster according to embodiments are schematically depicted.

[0018] Figure 3 According to the embodiment Figure 1 Schematic diagram of a similar lithographic projection apparatus.

[0019] Figure 4 A more detailed view of a lithographic projection apparatus is schematically depicted.

[0020] Figure 5 A reticle holder is schematically depicted.

[0021] Figure 6 A cross-sectional view of an exploded reticle holder is schematically depicted.

[0022] Figure 7 The clamping function of the reticle clamp is schematically depicted.

[0023] Figure 8 Schematic depiction of the charged particle effect and the reticle bias when the exposure beam is turned on.

[0024] Figure 9 Schematic depiction of the charged particle effect and the reticle bias when the exposure beam is turned on.

[0025] Figure 10 Schematic depiction of the charged particle effect and the reticle bias when the exposure beam is turned off.

[0026] Figure 11 An embodiment of an electrostatic mask clamp is schematically depicted.

[0027] Figure 12 An embodiment of implementing reticle front side potentials is schematically depicted.

[0028] Figures 13A-13B An embodiment enabling burl potential control is schematically depicted.

[0029] Figures 14A-14B An embodiment that enables burl potential control and true grounding is schematically depicted.

[0030] Figure 15 An embodiment of a burl configuration is schematically depicted. DETAILED DESCRIPTION

[0031] Typically, a mask or reticle is a transparent block of material covered with a pattern defined by a different, opaque material. Various masks are fed into a lithography apparatus and used to form the various layers of a semiconductor device. The pattern defined on a given mask or reticle corresponds to the features to be produced in one or more layers of the semiconductor device. Typically, during the manufacturing process, multiple masks or reticles are automatically fed into the lithography apparatus to be used to form the corresponding layers of the semiconductor device. A fixture in the lithography apparatus (e.g., an electrostatic reticle fixture) is used to secure the mask or reticle during processing. Over time, this fixture may become contaminated by particles of material transferred from the reticle, resulting in performance degradation and requiring periodic cleaning to restore performance.

[0032] Cleaning these fixtures can require stopping the lithography equipment and the manufacturing process. This cleaning can take hours to complete, exposing the environment inside the lithography equipment to the surrounding environment, which may introduce other contaminants into the system and / or have other adverse effects. In addition, there is a rinse process in which extremely clean dry air (XCDA) is circulated through the chamber to remove particles, but this method also takes hours and is not completely effective in cleaning these particles, as the particles will eventually adhere to the front side of the reticle, thereby affecting the PRP performance.

[0033] Compared to previous approaches, the present system and method provide a system in which particles are repelled from the front side of the reticle, preventing them from attaching to it. In this system and method, a ground pin in an electrostatic reticle fixture is repurposed to serve as a potential connection for the front side of the reticle. A strip of conductive coating (e.g., Cr, TiN) can extend from the fixture's ear to a small portion of the fixture's burl. This connection can drive a weak positive voltage, such as 5-10V. The reticle can include a conductive coating that electrically connects the fixture's back side to the front side. When the reticle's back side contacts the electrically connected fixture burl, voltage can be supplied from the ground pin through the fixture's conductive coating to the conductive coating on the reticle. This creates a positive charge on the front side of the reticle, repelling particles.

[0034] Although specific reference may be made herein to the fabrication of integrated circuits (ICs), it should be understood that the description herein may have other possible applications. For example, it may be used to fabricate integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin-film magnetic heads, and the like. Those skilled in the art will understand that, in the context of such alternative applications, any use of the terms "reticle," "wafer," or "die" herein may be considered synonymous with the more general terms "mask," "substrate," and "target portion," respectively. Furthermore, any use of the terms "reticle" or "mask" herein may be considered synonymous with the more general term "patterning device."

[0035] To introduce, before the pattern from a reticle (such as a mask) is transferred to the substrate, the substrate may undergo various procedures such as resist coating, resist application, and soft baking. After exposure, the substrate may undergo additional procedures ("post-exposure procedures") such as post-exposure baking (PEB), development, hard baking, and measurement and / or other inspection of the transferred pattern. This series of procedures forms the basis for fabricating the individual layers of a device (such as an IC). The substrate may then undergo various processes such as etching, ion implantation (doping), metallization, oxidation, and chemical mechanical polishing, all to complete the individual device layers. If the device requires multiple layers, the entire procedure, or a variation thereof, is repeated for each layer. Ultimately, a device is formed for each target portion on the substrate. These devices are then separated from each other by techniques such as dicing or sawing, allowing the individual devices to be mounted on a carrier, connected to pins, and so on.

[0036] The manufacture of devices (such as semiconductor devices) typically involves processing a substrate (such as a semiconductor wafer) using a variety of manufacturing processes to form the various features and multilayer structures of the device. These layers and features are typically manufactured and processed using processes such as deposition, photolithography, etching, chemical mechanical polishing, ion implantation, and / or other processes. Multiple devices can be manufactured on multiple dies on a substrate and then separated into individual devices. This device manufacturing process can be considered a patterning process. The patterning process includes a patterning step, such as optical and / or nanoimprint lithography using a mask in a photolithography apparatus to transfer the pattern on the mask to the substrate, and typically (but optionally) also includes one or more related pattern processing steps, such as developing the resist using a developer, baking the substrate using a bake tool, and etching according to the pattern using an etching apparatus. The patterning process typically involves one or more metrology processes.

[0037] Photolithography is a step in the manufacture of devices, such as integrated circuits, in which patterns formed on a substrate define the functional components of the device, such as a microprocessor or memory chip. Similar photolithography techniques are also used in the manufacture of flat-panel displays, microelectromechanical systems (MEMS), and other devices.

[0038] As semiconductor manufacturing processes continue to advance, the number of functional elements (such as transistors) per device has steadily increased over the past few decades, while the size of these elements has continued to decrease. This trend is often referred to as "Moore's Law." Under current technology, the various layers of a device are manufactured using photolithography projection equipment that projects the design layout onto a substrate using deep ultraviolet radiation, resulting in individual functional elements with dimensions significantly smaller than 100 nm, or less than half the wavelength of the radiation from the source (e.g., a 193 nm source).

[0039] This process of printing features smaller than the classical resolution limit of a lithographic projection system is often referred to as low-k1 lithography, derived from the resolution equation CD = k1 × λ / NA, where λ is the wavelength of the radiation used (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics in the lithographic projection system, CD is the "critical dimension" (typically the minimum feature size that can be printed), and k1 is the empirical resolution factor. Generally, the smaller k1, the more difficult it is to reproduce a pattern on the substrate with a shape and size similar to the designer's intended, in order to achieve specific electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the lithographic projection system, design layout, or reticle. Examples of these complex fine-tuning steps include, but are not limited to, optimizing NA and optical coherence settings, customizing illumination schemes, using phase-shifting reticles, performing optical proximity correction (OPC, sometimes also called "optical and process correction") in the design layout, overlay measurement, or other methods often referred to as "resolution enhancement techniques" (RET).

[0040] The term "projection optics" as used herein should be broadly understood to encompass various types of optical systems, including, for example, refractive optics, reflective optics, apertures, and catadioptric optics. The term "projection optics" may also include components that operate according to any of these design types for guiding, shaping, or controlling a projection radiation beam, either collectively or individually. The term "projection optics" may include any optical component in a lithographic projection apparatus, regardless of where the optical component is located in the optical path of the lithographic projection apparatus. Projection optics may include optical components for shaping, conditioning, and / or projecting radiation from a source before it passes through a reticle, and / or optical components for shaping, conditioning, and / or projecting radiation from a source after it passes through a reticle. Projection optics typically do not include a source and a reticle.

[0041] Figure 1An embodiment of a lithographic apparatus LA is schematically depicted, which may be included in or associated with the present system and / or method. The apparatus comprises an illumination system (illuminator) IL configured to condition a radiation beam B (e.g., UV radiation, DUV radiation, or EUV radiation); a support structure (e.g., a mask table) MT constructed to support a reticle (e.g., mask) MA and coupled to a first positioner PM configured to accurately position the reticle according to specific parameters; a substrate table (e.g., a wafer stage) WT (e.g., WTa, WTb, or both) configured to hold a substrate (e.g., a resist-coated wafer) W and coupled to a second positioner PW configured to accurately position the substrate according to specific parameters; and a projection system (e.g., a refractive projection lens system) PS configured to project a pattern imparted by the reticle MA to the radiation beam B onto a target portion C (e.g., comprising one or more dies, often referred to as a field) of the substrate W. The projection system is supported on a reference frame (RF). As shown, the device is of the transmissive type (eg, using a transmissive mask). Alternatively, the device may be of the reflective type (eg, using a programmable mirror array of the type described above, or using a reflective mask).

[0042] The illuminator IL receives a radiation beam from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example, when the radiation source is an excimer laser. In this case, the source is not considered to form part of the lithographic apparatus, and the radiation beam is transferred from the radiation source SO to the illuminator IL with the aid of a beam delivery system BD (e.g., including suitable directing mirrors and / or a beam expander). In other cases, the source may be an integral part of the apparatus, for example, when the source is a mercury lamp. The source SO and illuminator IL, and beam delivery system BD (if necessary), may be collectively referred to as a radiation system.

[0043] The illuminator IL can vary the intensity distribution of the beam. The illuminator can be arranged to limit the radial extent of the radiation beam so that the intensity distribution is non-zero within an annular region in a pupil plane of the illuminator IL. Additionally or alternatively, the illuminator IL can be operated to limit the beam distribution in the pupil plane so that the intensity distribution is non-zero within a plurality of equally spaced sectors in the pupil plane. The intensity distribution of the radiation beam in the pupil plane of the illuminator IL can be referred to as an illumination pattern.

[0044] The illuminator IL may include an adjuster AD configured to adjust the (angular / spatial) intensity distribution of the beam. Typically, at least the outer and / or inner extent of the intensity distribution in the pupil plane of the illuminator (commonly referred to as σ-outer and σ-inner, respectively) can be adjusted. The illuminator IL may be operable to vary the angular distribution of the beam. For example, the illuminator may be operable to vary the number and angular extent of sectors in the pupil plane where the intensity distribution is non-zero. By adjusting the beam intensity distribution in the pupil plane of the illuminator, different illumination patterns can be achieved. For example, by limiting the radial and angular extent of the intensity distribution in the pupil plane of the illuminator IL, the intensity distribution can have a multipolar distribution, such as a dipole, quadrupole, or sextupole distribution. This illumination pattern can be achieved, for example, by inserting optics into the illuminator IL that provide the desired illumination pattern or by using a spatial light modulator.

[0045] The illuminator IL may be operable to change the polarization of the beam and may be operable to adjust the polarization using an adjuster AD. The polarization state of the radiation beam passing through the pupil plane of the illuminator IL may be referred to as a polarization mode. Using different polarization modes can result in an image formed on the substrate W having higher contrast. The radiation beam may be unpolarized. Alternatively, the illuminator may be arranged to linearly polarize the radiation beam. The polarization direction of the radiation beam may vary across the pupil plane of the illuminator IL. The polarization direction of the radiation may be different in different regions within the pupil plane of the illuminator IL. The polarization state of the radiation may be selected according to the illumination mode. For a multipolar illumination mode, the polarization of each pole of the radiation beam may be generally perpendicular to the position vector of that pole within the pupil plane of the illuminator IL. For example, for a dipole illumination mode, the radiation may be linearly polarized in a direction substantially perpendicular to a line bisecting two opposing sectors of the dipole. The radiation beam may be polarized in one of two different orthogonal directions, which may be referred to as an X polarization state and a Y polarization state. For a quadrupole illumination mode, the radiation within each sector of the pole may be linearly polarized in a direction substantially perpendicular to a line bisecting the sector. This polarization mode may be referred to as XY polarization. Similarly, for a hexapole illumination mode, the radiation within the sector of each pole may be linearly polarized in a direction substantially perpendicular to the line bisecting the sector. This polarization mode may be referred to as TE polarization.

[0046] In addition, the illuminator IL typically includes various other components, such as an integrator IN and a condenser CO. The illumination system may include various types of optical components for directing, shaping, or controlling the radiation, such as refractive, reflective, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof. Thus, the illuminator provides a conditioned radiation beam B having a desired uniformity and intensity distribution in its cross-section.

[0047] The support structure MT supports the reticle in a manner that depends on the orientation of the reticle, the design of the lithographic apparatus, and other conditions (e.g., whether the reticle is held in a vacuum environment). The support structure can use mechanical, vacuum, electrostatic, or other clamping techniques to hold the reticle. The support structure can be a frame or a stage, for example, which can be fixed or movable as needed. The support structure can ensure that the reticle is in a desired position, such as relative to the projection system.

[0048] The term "reticle," as used herein, should be broadly interpreted as referring to any device that can be used to impart a pattern in a target portion of a substrate. In embodiments, a reticle is any device that can be used to impart a radiation beam with a pattern in its cross-section so as to form a pattern in the target portion of the substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate, for example if the pattern includes phase-shifting features or so-called assist features. Generally, the pattern imparted to the radiation beam will correspond to a particular functional layer in a device (such as an integrated circuit) to be formed in the target portion of the device.

[0049] The patterning device may be transmissive or reflective. Examples of patterning devices include reticles or masks, programmable mirror arrays, and programmable LCD panels. Reticles or masks are well known in photolithography and include mask types such as binary, alternating phase shift, and attenuated phase shift, as well as various hybrid mask types. An example of a programmable mirror array uses a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incident radiation beam in different directions. The tilted mirrors impart a pattern in the radiation beam that is reflected by the mirror matrix.

[0050] The term "projection system" as used herein should be broadly interpreted to encompass any type of projection system appropriate to the exposure radiation used or to other factors such as the use of an immersion liquid or the use of a vacuum, including refractive, reflective, catadioptric, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof. Any use of the term "projection lens" herein should be considered synonymous with the more general term "projection system."

[0051] The projection system PS has a potentially non-uniform optical transfer function, which affects the pattern imaged onto the substrate W. For unpolarized radiation, this effect can be well described by two scalar diagrams: the transmission (vignetting) and relative phase (aberrations) of the radiation emerging from the projection system PS as a function of its position within the pupil plane. These scalar diagrams (which may be referred to as the transmission diagram and the relative phase diagram) can be expressed as linear combinations of a complete set of basis functions. A useful set is the Zernike polynomials, which form a set of orthogonal polynomials defined on the unit circle. Determining each scalar diagram may involve determining the coefficients in such an expansion. Since the Zernike polynomials are orthogonal on the unit circle, the Zernike coefficients can be determined by sequentially computing the inner product of the measured scalar diagram with each Zernike polynomial and dividing the inner product by the square of the norm of the Zernike polynomial.

[0052] Transmission and relative phase maps are field- and system-dependent. That is, each projection system PS typically has a different Zernike expansion for each field point (i.e., for each spatial position in the image plane of the projection system). The relative phase of a projection system PS in its pupil plane can be determined by projecting radiation (e.g., from a point source in the object plane of the projection system PS (i.e., the plane of the reticle MA)) through the projection system PS and measuring the wavefront (i.e., the locus of points with the same phase) using a shearing interferometer. A shearing interferometer is a common-path interferometer and, therefore, advantageously, does not require a secondary reference beam to measure the wavefront. The shearing interferometer can include a diffraction grating (e.g., a two-dimensional grating) located in the image plane of the projection system (i.e., substrate table WTa or WTb) and a detector arranged to detect an interference pattern in a plane conjugate to the pupil plane of the projection system PS. The interference pattern is related to the derivative of the radiation's phase with respect to its coordinate in the pupil plane, in the shear direction. The detector can include an array of sensing elements, such as a charge-coupled device (CCD).

[0053] The projection system PS of a lithographic apparatus may not produce visible fringes. Therefore, phase stepping techniques (e.g., by moving a diffraction grating) can be used to improve the accuracy of wavefront determination. Stepping can be performed in the plane of the diffraction grating, perpendicular to the scanning direction of the measurement. The stepping range can be one grating period, and at least three (evenly spaced) phase steps can be used. Thus, for example, three scanning measurements can be performed in the y-direction, each for a different position in the x-direction. This stepping of the diffraction grating effectively converts phase changes into intensity changes, allowing phase information to be determined. The grating can also be stepped in a direction perpendicular to the diffraction grating (z-direction) to calibrate the detector.

[0054] The diffraction grating can be scanned sequentially in two perpendicular directions, which can coincide with the axes (x and y) of the coordinate system of the projection system PS, or can be angled relative to these axes (such as 45 degrees). The scan can be performed over an integer number of grating periods, such as one grating period. The scan averages the phase variation in one direction, allowing reconstruction of the phase variation in the other direction. This allows the wavefront to be determined as a function of both directions.

[0055] The transmission (apodization or vignetting) of the projection system PS in its pupil plane can be determined by projecting radiation through the projection system PS (e.g., from a point source in the object plane of the projection system PS (i.e., the plane of the reticle MA)) and measuring the intensity of the radiation in a plane conjugate to the pupil plane of the projection system PS using a detector. The same detectors as those used to measure the wavefront to determine aberrations can be used.

[0056] The projection system PS may include multiple optical (e.g., lens) elements and may also include an adjustment mechanism configured to adjust one or more optical elements to correct for aberrations (phase variations across the pupil plane across the field). To achieve this, the adjustment mechanism may be operable to manipulate one or more optical (e.g., lens) elements within the projection system PS in one or more different ways. The projection system may have a coordinate system with its optical axis extending along the z-direction. The adjustment mechanism may be operable to perform any combination of the following operations: displacing one or more optical elements; tilting one or more optical elements; and / or deforming one or more optical elements. Displacing the optical elements may be performed in any direction (x, y, z, or a combination thereof). Tilting of the optical elements is typically achieved out of a plane perpendicular to the optical axis by rotating about axes along the x- and / or y-directions, although rotation about the z-axis may also be used for non-rotationally symmetric aspheric optical elements. Deformations of the optical elements may include low-frequency shaping (e.g., astigmatism) and / or high-frequency shaping (e.g., free-form aspheric surfaces). Deforming the optical element can be performed, for example, by applying a force on one or more sides of the optical element using one or more actuators, and / or heating one or more selected regions of the optical element using one or more heating elements. Typically, the projection system PS may not be adjusted to correct for vignetting (variations in transmittance across the pupil plane). A transmission map of the projection system PS can be used when designing a reticle (e.g., mask) MA for the lithographic apparatus LA. Using computational lithography techniques, the reticle MA can be designed to at least partially correct for vignetting.

[0057] The lithographic apparatus may be a dual-stage machine having two or more tables (e.g., two or more substrate tables WTa, WTb, two or more reticle tables, substrate table WTa and a dedicated table WTb located below the projection system and free of substrates, for example, to facilitate measurement and / or cleaning). In such a "multi-stage" machine, the additional tables may be used in parallel, or preparatory steps may be performed on one or more tables while one or more other tables are being used for exposure. For example, alignment measurements may be performed using an alignment sensor AS, and / or level (height, tilt, etc.) measurements may be performed using a level sensor LS.

[0058] The lithographic apparatus may also be of a type in which at least a portion of the substrate may be covered by a liquid having a relatively high refractive index (e.g., water) so as to fill the space between the projection system and the substrate. Immersion liquid may also be applied to other spaces in the lithographic apparatus, such as the space between the reticle and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems. The term "immersion" as used herein does not imply that a structure, such as a substrate, is necessarily immersed in the liquid, but only that the liquid is located between the projection system and the substrate during exposure.

[0059] In operation of the lithographic apparatus, a radiation beam is conditioned and provided by an illumination system IL. The radiation beam B is incident on a reticle (e.g., mask) MA, which is held on a support structure (e.g., mask table) MT. After passing through the reticle MA, the radiation beam B passes through a projection system PS, which focuses the beam onto a target portion C of a substrate W. With the aid of a second positioner PW and a position sensor IF (e.g., an interferometer arrangement, a linear encoder, a 2-D encoder, or a capacitive sensor), the substrate table WT can be accurately moved, for example, in order to position a different target portion C in the path of the radiation beam B. Similarly, the substrate table WT can be accurately moved using a first positioner PM and a further position sensor (e.g., an interferometer arrangement, a linear encoder, a 2-D encoder, or a capacitive sensor), for example after mechanical retrieval from a mask library, or during scanning. Figure 1The support structure MT is provided with a plurality of actuators (not explicitly depicted in the figure) for accurately positioning the mask MA relative to the path of the radiation beam B. In general, movement of the support structure MT may be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning) which form part of the first positioner PM. Similarly, movement of the substrate table WT may be realized using a long-stroke module and a short-stroke module which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the support structure MT may be connected to the short-stroke actuator only, or may be fixed. Reticle alignment marks M1, M2 and substrate alignment marks P1, P2 may be used to align the patterning device MA with the substrate W. Although the substrate alignment marks shown occupy dedicated target portions, the marks may be located in the spaces between target portions (these marks are called scribe line alignment marks). Similarly, where more than one die is provided on the mask MA, the reticle alignment marks may be located between the dies.

[0060] The described apparatus can be used in at least one of the following modes: 1. In step mode, a pattern imparted to the radiation beam is projected once onto a target portion C while the support structure MT and substrate table WT are held essentially stationary (i.e., a single static exposure). The substrate table WT is then shifted in the X and / or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure. 2. In scan mode, a pattern imparted to the radiation beam is projected onto a target portion C while the support structure MT and substrate table WT are scanned synchronously (i.e., a single dynamic exposure). The speed and direction of the substrate table WT relative to the support structure MT can be determined by the (de-)magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width of the target portion in a single dynamic exposure (in the non-scanning direction), while the length of the scanning motion determines the height of the target portion (in the scanning direction). 3. In another mode, the support structure MT holding the programmable reticle is maintained substantially stationary, and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam is projected onto a target portion C. In this mode, a pulsed radiation source is typically employed, and the programmable reticle is updated as required after each movement of the substrate table WT, or between successive radiation pulses during a scan. This mode of operation may be readily applicable to maskless lithography using a programmable reticle (e.g., a programmable mirror array of the type described above). Combinations and / or variations of the above-described modes of use, or entirely different modes of use, may also be employed.

[0061] The substrate can be processed before or after exposure, for example, in a track unit (a tool that typically applies a resist layer to a substrate and develops the exposed resist), a metrology tool, or an inspection tool. Where applicable, the disclosure herein can be applied to these and other substrate processing tools. Furthermore, a substrate can be processed more than once, for example, to form a multi-layer IC, so that the term substrate as used herein may also refer to a substrate that already includes multiple processed layers.

[0062] As used herein, the terms "radiation" and "beam" are intended to encompass all types of electromagnetic radiation, including ultraviolet (UV) or deep ultraviolet (DUV) radiation (e.g., having a wavelength of 365, 248, 193, 157, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 5-20 nm), as well as particle beams (such as ion beams or electron beams).

[0063] Various patterns on or provided by a reticle can have different process windows, which is the space of process variables that produce patterns that are within specifications. Examples of pattern specifications related to potential systematic defects include necking detection, line shrinkage, line thinning, critical dimension (CD), edge placement, overlap, resist top loss, resist undercut, and / or bridging. The process window of a pattern on a reticle or a region thereof can be obtained by combining (such as overlapping) the process windows of each individual pattern. The process window boundaries of a group of patterns include the boundaries of the process windows of some of the individual patterns. In other words, these individual patterns limit the process window of the group of patterns. These patterns can be referred to as "hot spots" or "process window limiting patterns (PWLPs)", which are used interchangeably herein. When controlling a portion of the patterning process, focusing on hot spots is practical and economical. When a hot spot is defect-free, the other patterns are likely to be defect-free as well.

[0064] like Figure 2 As shown, the lithography apparatus LA can form part of a lithocell LC (sometimes also referred to as a litho cell or cluster), which also includes equipment for performing pre-exposure and post-exposure processes on substrates. Typically, this equipment includes one or more spin coaters SC for depositing one or more resist layers, one or more developers for developing the exposed resist, one or more chill plates CH, and / or one or more bake plates BK. A substrate transport device or robot RO picks up one or more substrates from input / output ports I / O1 and I / O2, moves the substrates between the various process equipment, and delivers them to a loading station LB of the lithography apparatus. These devices, often collectively referred to as a track, are under the control of a track control unit TCU, which is itself controlled by a supervisory control system SCS, which in turn controls the lithography apparatus via the lithography control unit LACU. Thus, the various devices can be operated to maximize throughput and processing efficiency.

[0065] In order to correctly and consistently expose a substrate exposed by a lithographic apparatus, and / or to monitor a portion of a patterning process (e.g., a device manufacturing process) that includes at least one pattern transfer step (e.g., an optical lithography step), it is desirable to inspect the substrate or other object to measure or determine one or more properties, such as alignment, overlay (which may be, for example, between structures in superimposed layers, or between structures in the same layer that have been separately provided to said layers by, for example, a double patterning process), line thickness, critical dimension (CD), focus offset, or material properties. For example, contaminants on a reticle holding membrane (e.g., as described herein) may adversely affect overlay because clamping the reticle on such contaminants may cause deformation of the reticle. Therefore, a manufacturing facility in which a lithography cell LC is located also typically includes a metrology system that measures the properties of substrates W ( Figure 1 ) or other objects in the lithocell. The metrology system may be part of the lithocell LC, for example, it may be part of the lithographic apparatus LA (such as an alignment sensor AS ( Figure 1 )).

[0066] For example, one or more measurement parameters may include alignment, overlay between successive layers formed in or on a patterned substrate, critical dimensions (CD) of features formed in or on the patterned substrate (e.g., critical line width), focus or focus error of an optical lithography step, dose or dose error of an optical lithography step, optical aberrations of an optical lithography step, and the like. Such measurements may be performed on a target on the product substrate itself and / or on a dedicated metrology target disposed on the substrate. The measurements may be performed after resist development but before etching, after etching, after deposition, and / or at other times.

[0067] There are various techniques for measuring the structures formed during the patterning process, including the use of scanning electron microscopes, image-based measurement tools, and / or various specialized tools. As mentioned above, one fast and non-invasive specialized measurement tool is one that directs a radiation beam onto a target on the substrate surface and measures the properties of the scattered (diffracted / reflected) beam. By evaluating one or more properties of the radiation scattered by the substrate, one or more properties of the substrate can be determined. This can be referred to as diffraction-based metrology. One application of diffraction-based metrology is measuring the asymmetry of features within a target. For example, this can be used as an overlay measurement, but other methods are also known. For example, asymmetry can be measured by comparing opposite portions of the diffraction spectrum (e.g., comparing the -1st and +1st orders in the diffraction spectrum of a periodic grating). This can be performed as described above, and as described, for example, in U.S. Patent Application Publication US 2006 / 0066855, which is incorporated herein by reference in its entirety. Another application of diffraction-based metrology is measuring the width (CD) of features within a target.

[0068] Therefore, during a device manufacturing process (e.g., a patterning process, a lithography process, etc.), a substrate or other object may be subjected to various types of measurements during or after the process. These measurements can determine whether a particular substrate has defects, establish adjustments to the process and equipment used in the process (e.g., aligning two layers on a substrate or aligning a mask to a substrate), measure the performance of the process and equipment, or be used for other purposes. Examples of measurements include optical imaging (e.g., optical microscopy), non-imaging optical measurements (e.g., diffraction-based measurements, such as ASML YieldStar metrology tools, ASML SMASH metrology systems), mechanical measurements (e.g., profilometry using a stylus, atomic force microscopy (AFM)), and / or non-optical imaging (e.g., scanning electron microscopy (SEM)). The SMASH (Smart Alignment Sensor Hybrid) system, as described in U.S. Patent No. 6,961,116 (which is incorporated herein by reference in its entirety), employs a self-referencing interferometer that produces two overlapping and relatively rotated images of an alignment mark, detects the intensity in the pupil plane that causes interference in the Fourier transforms of the images, and extracts position information from the phase difference between the diffraction orders of the two images, which manifests as intensity variations in the interference orders.

[0069] The metrology results can be provided directly or indirectly to the supervisory control system (SCS). If an error is detected, adjustments can be made to the exposure of subsequent substrates (especially if the inspection can be completed quickly enough so that one or more other substrates in the batch are still exposed) and / or to the subsequent exposure of already exposed substrates. Furthermore, already exposed substrates can be stripped and reworked to improve yield, or discarded to avoid further processing of known defective substrates. In the event that only some target portions of a substrate are defective, further exposures can be performed only on those target portions that meet specifications.

[0070] In a metrology system, metrology equipment is used to determine one or more properties of a substrate, particularly how one or more properties vary between different substrates, or how different layers of the same substrate vary from layer to layer. As described above, the metrology equipment can be integrated into the lithographic apparatus LA or lithocell LC, or it can be a standalone device.

[0071] To enable metrology, one or more targets may be placed on a substrate. In one embodiment, the targets are specially designed and may include periodic structures. In one embodiment, the targets are part of a device pattern, such as a periodic structure of the device pattern. In one embodiment, the device pattern is a periodic structure of a memory device (e.g., a bipolar transistor (BPT) or a bitline contact (BLC)).

[0072] In an embodiment, the target on the substrate may include one or more 1-D periodic structures (e.g., gratings) printed such that, after development, the periodic structural features consist of solid resist lines. In an embodiment, the target may include one or more 2-D periodic structures (e.g., gratings) printed such that, after development, the periodic structural features consist of solid resist posts or vias in the resist. The posts, posts, or vias may alternatively be etched into the substrate (e.g., into one or more layers on the substrate).

[0073] In an embodiment, one of the parameters of interest in the patterning process is overlay. Overlay can be measured using dark-field scatterometry, where the zeroth order of refraction (corresponding to specular reflection) is blocked and only higher orders are processed. Examples of dark-field metrology can be found in PCT Patent Application Publication Nos. WO 2009 / 078708 and WO 2009 / 106279, which are incorporated herein by reference in their entireties. Further developments of this technology are described in U.S. Patent Application Publications Nos. US2011 / 0027704, US2011 / 0043791, and US2012 / 0242970, which are incorporated herein by reference in their entireties. Refraction-based overlay using dark-field detection of refractive orders enables overlay measurement of smaller targets. These targets can be smaller than the illumination spot and can be surrounded by device product structures on the substrate. In an embodiment, multiple targets can be measured in a single radiation capture.

[0074] As lithography nodes continue to shrink, increasingly complex wafer designs are becoming feasible. Designers can use a variety of tools and / or techniques to ensure that complex designs are accurately transferred to the physical wafer. These tools and techniques may include mask optimization, source mask optimization (SMO), OPC, control design, and / or other tools and / or techniques. For example, a source mask optimization process is described in U.S. Patent No. 9,588,438, entitled "Optimization Flows of Source, Mask and Projection Optics," which is incorporated herein by reference in its entirety.

[0075] The present systems and / or methods may be used as stand-alone tools and / or techniques, and / or may be used in conjunction with semiconductor manufacturing processes to enhance the accurate transfer of complex designs to physical wafers.

[0076] Figure 3 Schematically depicts the Figure 1An exemplary lithographic projection apparatus LA, similar or identical to the apparatus shown, can be used in conjunction with the techniques described herein. The apparatus includes an illumination system IL configured to condition a radiation beam B. In this example, the illumination system also includes a radiation source SO. The apparatus includes a first object stage (e.g., reticle stage) MT, which is provided with a reticle holder for holding a reticle MA (e.g., a patterning device). The first object stage is coupled to a first positioner for accurately positioning the reticle relative to an object PS. The apparatus includes a second object stage (substrate stage) WT, which is provided with a substrate holder for holding a substrate W (e.g., a silicon wafer coated with resist). The second object stage is coupled to a second positioner for accurately positioning the substrate relative to the object PS. The apparatus includes a projection system ("lens") PS (e.g., a refractive, reflective, or catadioptric optical system) for imaging an illuminated portion of the reticle MA onto a target portion C (e.g., comprising one or more dies) of the substrate W.

[0077] As described, the device LA is transmissive (e.g., having a transmissive reticle). However, in general, the device LA can also be reflective (e.g., having a reflective reticle). The device can use reticles other than classical masks; examples include programmable mirror arrays or LCD matrices.

[0078] A source SO (e.g., a mercury lamp or excimer laser, LPP (laser produced plasma), or EUV source) generates a radiation beam. This beam is fed into an illumination system (illuminator) IL, for example, directly or after passing through a conditioning device (such as a beam expander). The illuminator IL may include conditioning devices for setting the outer radial extent and / or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the radiation beam. Additionally, the illuminator typically includes various other components, such as an integrator and a condenser. In this manner, the beam B incident on the reticle MA has a desired uniformity and intensity distribution in its cross-section.

[0079] about Figure 3 It should be noted that the source SO may be located within the housing of the lithographic projection apparatus (as is typically the case, for example, when the source SO is a mercury lamp), but may also be remote from the lithographic projection apparatus so that the radiation beam it generates is introduced into the apparatus (for example, with the aid of suitable directing mirrors); the latter case is more common when the source SO is an excimer laser (for example, based on KrF, ArF or F2 lasers).

[0080] The beam B then encounters the reticle MA, which is held on the reticle table MT. After passing through the reticle MA, the beam B passes through a lens PL, which focuses the beam B onto a target portion C of the substrate W. With the help of the second positioning device (and the interferometry device), the substrate table WT can be accurately moved, for example, to position a different target portion C in the beam path. Similarly, the first positioning device can be used to accurately position the reticle MA relative to the path of the beam B, for example after mechanical retrieval of the reticle MA from a reticle library or during a scan. Typically, movement of the object table MT, WT is realized with the help of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which are not explicitly depicted. However, in the case of a stepper (in contrast to a step-and-scan tool), the reticle table MT may be connected only to the short-stroke actuator or may be fixed.

[0081] As described above, the LA can be used in two modes. In step mode, the reticle table MT remains essentially stationary, and the entire reticle image is projected onto a target portion C in a single operation (i.e., a single "flash"). The substrate table WT is then moved in the x- and / or y-direction so that the beam can irradiate different target portions C. In scan mode, essentially the same scenario applies, except that a given target portion C is not exposed in a single "flash." Instead, the reticle table MT is moved in a given direction (the so-called "scanning direction," e.g., the y-direction) at a velocity v, thereby scanning the projection beam B across the reticle image. Simultaneously, the substrate table WT is moved in the same or opposite direction at a velocity V=Mv, where M is the magnification of the lens PL (typically, M=1 / 4 or 1 / 5). In this way, relatively large target portions C can be exposed without sacrificing resolution.

[0082] Figure 4 A lithographic apparatus LA is shown in greater detail and includes a source collector module SO, an illumination system IL, and a projection system PS. An EUV radiation-emitting plasma 210 can be formed by a plasma source. The EUV radiation can be generated by a gas or vapor, such as Xe gas, Li vapor, or Sn vapor, wherein the radiation-emitting plasma 210 is generated to emit radiation in the EUV range of the electromagnetic spectrum. In one embodiment, an excited tin (Sn) plasma is provided to generate EUV radiation.

[0083] Radiation emitted by the radiation emitting plasma 210 passes from the source chamber 211 into the collector chamber 212. The collector chamber 212 may include a radiation collector CO. Radiation passing through the radiation collector CO may be focused into a virtual source point IF. The virtual source point IF is often referred to as an intermediate focus, and the source collector module SO is arranged such that the virtual source point IF is located at or near an opening 221 in the enclosure 220. The virtual source point IF is an image of the radiation emitting plasma 210.

[0084] The radiation then passes through an illumination system IL, which may include a faceted field mirror arrangement 22 and a faceted pupil mirror arrangement 24 arranged to provide a desired angular distribution of the unpatterned beam 21 at the patterning device MA, and a desired uniformity of radiation intensity at the patterning device MA. Upon reflection of the unpatterned beam 21 at the patterning device MA held by the support structure MT, a patterned beam 26 is formed, and the patterned beam 26 is imaged by the projection system PS via reflective elements 28, 30 onto a substrate W held by the substrate table WT.

[0085] Typically, there may be more elements in the illumination system IL and the projection system PS than shown. Furthermore, there may be more mirrors than shown in the figures, e.g. Figure 4 As shown in , there may be 1 to 6 additional reflective elements in the projection system PS. Alternatively, the source collector module SO may be part of an LPP radiation system.

[0086] like Figure 3 As shown, in an embodiment, a lithographic apparatus LA comprises an illumination system IL and a projection system PS. The illumination system IL is configured to emit a radiation beam B. The projection system PS is separated from a substrate table WT by an intervening space. The projection system PS is configured to project a pattern imparted to the radiation beam B onto a substrate W. The pattern is EUV radiation from the radiation beam B.

[0087] The space between the projection system PS and the substrate table WT may be at least partially evacuated.The intervening space may be defined at the location of the projection system PS by a solid surface through which the employed radiation is directed towards the substrate table WT.

[0088] Figure 5A reticle clamp is schematically depicted. The clamp is an electrostatic clamp. The reticle clamp CL has four high-voltage electrodes HVE positioned vertically relative to each other, and each electrode extends horizontally across the length of the clamp CL. The interior of the clamp CL includes a plurality of burls BU protruding from the surface of the clamp CL. The burls BU are arranged on a grid spanning the entire surface of the clamp CL. The burls BU are used to hold the reticle MA on the clamp CL. The burls BU use electrostatic charges to clamp the reticle MA. Thereafter, the reticle MA can be released from the burls BU by removing the charge. The use of the burls BU allows the reticle MA to contact only a small surface area of ​​the clamp CL. This prevents the reticle MA from being contaminated. In addition, each side of the clamp CL has a first ear EAR1 and a second ear EAR2. The first ear EAR1 includes a first connection CON1, which can be used to drive a subset of the burls BU to a specific voltage. The second ear EAR2 includes a second connection CON2, which is used to drive another subset of the burls BU to a specific voltage. The reasons for using only a subset of the burls BU will be described in detail below.

[0089] As an example, in one embodiment, there may be about 2000 burls BU on the surface of the clamp CL. However, in other embodiments, there may be 500 to 5000 burls. Figure 5 However, the burls BU may also be square, triangular, oval, or any shape that provides a solid contact with the mask MA.

[0090] Figure 6 A schematic cross-sectional view of an exploded reticle holder CL is depicted. The holder CL comprises a thin glass sheet GBU, which is a dielectric body and has burls BU. Below the thin glass sheet GBU are multiple thin high-voltage electrodes HVE (four such electrodes are shown in the illustrated embodiment). Below that is a glass plate GLA. The final layer is a glass plate GCC with grooves. When the glass plate GCC is tightly fitted to the glass plate GLA, these grooves form closed cooling channels CC, which cool the holder CL. A cooling fluid is pumped through the cooling channels CC to cool the reticle MA. All glass and electrode layers are bonded or fused together to form the holder CL.

[0091] Figure 7 The clamping function of the reticle clamp is schematically depicted. The controller CONT controls the clamping function of the reticle clamp. The controller CONT may include a CPU, a microprocessor, a control unit, hardware, software, or any other control device for controlling the clamping function. The clamp CL is connected to a power supply PS. The power supply PS may include a wall outlet, a battery, a fuel cell, or any other power source suitable for use with the clamp CL. Figure 7As shown, when the switch is closed, current flows through the circuit. The fixture CL has a high-voltage electrode HVE that is charged by the current. Consequently, the left high-voltage electrode HVE develops a positive charge, while the right high-voltage electrode HVE becomes negatively charged. The mask MA includes an imaging pattern PATT on its front side (to be exposed on the substrate W), a mask substrate SUB, and a conductive backside coating COAT. When the switch is closed, the mask MA becomes charged via the coating COAT and is attracted to the charged fixture CL. The left half of the coating COAT becomes negatively charged and is attracted to the positively charged left high-voltage electrode HVE. The right half of the coating COAT becomes positively charged and is attracted to the negatively charged right high-voltage electrode HVE. This attraction holds the mask MA on the fixture CL at the burl BU. Therefore, the charge of the high-voltage electrode HVE holds the mask MA on the fixture CL.

[0092] On the other hand, when the switch is open, the clamp CL does not include an electric charge and the mask MA is not attracted to the clamp CL. In one embodiment, the conductive backside coating COAT is made of chromium nitride (CrN) or tantalum boride (TaB). However, any conductive material that can be attracted or repelled by the high-voltage electrode HVE can be used. Additionally, the high-voltage electrode HVE applies a voltage of 3000 V to attract or otherwise clamp the mask MA. However, the present invention is not limited to this, and in other non-limiting examples, the high-voltage electrode HVE can apply a voltage in the range of 1000 V to 5000 V. Furthermore, although two high-voltage electrodes HVE are shown, the present invention is not limited to this. For example, Figure 5 、 Figure 6 13 and 14 each have four high voltage electrodes HVE. In various non-limiting examples, there may be two to eight high voltage electrodes HVE.

[0093] Figure 8-10 Schematic depiction of the charged particle effect and the bias voltage of the mask. Figure 8 As shown in the figure, when beam B (e.g., an EUV lithography beam) exposes reticle MA, secondary electrons (denoted by the symbol "e-") are emitted from the surface of reticle MA into the space below. This is due to the photoelectric effect on plasma beam B. During exposure, plasma beam B emits many electrons. However, by biasing the front side of reticle MA with a positive charge, fewer electrons are emitted into the reticle microenvironment (RME). Maintaining a net positive potential on the front side of the reticle reduces the number of electrons released during the pulse. A positively charged reticle MA reduces the number of electrons released into space.

[0094] Figure 9The effect of beam exposure is shown. The particles P in the space below the mask MA (where the secondary electrons reside) may be primarily negatively charged. Therefore, the particles P are attracted to the front side of the positively charged mask MA. Due to the opposite charges, the electrostatic attraction F el The particles P act on the particles P and push them toward the mask MA. Therefore, during beam exposure, the particles P may adhere to the front side of the mask MA. If this happens, when the mask MA is exposed, the areas with the particles P will transfer an inaccurate pattern to the substrate W, resulting in a higher defect rate.

[0095] Figure 10 The mask biasing method is shown. Between the beam exposure pulses, the front surface of the mask MA is biased with a negative charge. Therefore, the negatively charged particles P will be repelled away from the negatively charged surface of the mask MA. The electrostatic attraction F el Particles P are pushed toward the reticle masking (REMA) plate BL. The plate BL is used to block portions of the reticle MA that should not be exposed during the current pass. However, in this case, the plate also acts as a particle collector. By biasing the front side of the reticle MA between beam pulses, particles P are repelled away from the reticle MA, thereby reducing the defect rate.

[0096] When the plasma beam is on, the front side of the reticle MA can be biased with a positive charge to reduce the number of electrons released from the plasma beam and repel contaminant particles. When the plasma beam is off, the front side of the reticle MA is biased with a negative charge to cause the reticle MA to repel electrons. Because the plasma beam pulses frequently switch from on to off and back on, the bias voltage on the front side of the reticle also changes accordingly, from positive to negative and then back to positive.

[0097] Figure 11 An electrostatic mask holder 11 is depicted. The electrostatic mask holder 11 comprises a support structure MT having elements of a holder CL (see for more details Figure 6 ). A plurality of burls 70 (e.g., conical protrusions) on the support surface 42 of the support structure MT face the non-patterned backside surface 41 of the reticle MA. When the reticle MA is clamped onto the support structure MT, the non-patterned surface 41 contacts the distal ends of the plurality of burls 70. Not every one of the plurality of burls necessarily contacts the non-patterned surface 41. Typically, the distal ends of one or more of the plurality of burls 70 may contact the non-patterned surface 41 of the reticle MA. On the other hand, the patterned frontside surface 40 is located on the other side of the reticle MA, and the exposure beam is incident on the patterned surface 40.

[0098] Non-patterned surface 41 is electrically connected to voltage source 61 via a plurality of burls 70. The electrical connection between voltage source 61 and burls 70 may include electrically connecting support surface 42 of support structure MT to voltage source 61, electrically connecting burls 70 to support surface 42 of support structure MT, and electrically connecting burls 70 to non-patterned surface 41 of reticle MA. Not every burl is necessarily electrically connected to non-patterned surface 41. Typically, one or more burls 70 may be electrically connected to non-patterned surface 41.

[0099] Furthermore, the patterned surface 40 and the non-patterned surface 41 are electrically connected. The electrical connection between the patterned surface 40 and the non-patterned surface 41 can be achieved by a path that is an integral part of the mask MA itself. Alternatively, the electrical connection between the patterned surface 40 and the non-patterned surface 41 can be achieved by an external path (such as wiring), such as Figure 11 shown.

[0100] Between the voltage source 61 and the plurality of protrusions 70, there may be at least one of a resistor 62, a diode, and a switch. The voltage source 61 and the resistor 62 are part of the voltage system 60 of the electrostatic mask holder 11. Additionally or alternatively, between the non-patterned surface and the patterned surface, there may be at least one of a resistor 63, a diode, and a switch. Further details of these components will be provided below.

[0101] During each EUV radiation pulse, voltage source 61 may output a very large current. This current can be large enough to damage components such as voltage source 61. Furthermore, when very large currents are supplied to reticle MA, reticle MA may heat up. This can cause deformation of reticle MA, which may result in errors in the pattern projected from reticle MA onto substrate W. To alleviate this problem, patterning surface 40 may be connected to voltage source 61 via at least one of resistors 62 and 63, a diode, or a switch.

[0102] When resistors 62 and 63 are placed in the path between voltage source 61 and patterned surface 40, the current output from voltage source 61 during an EUV radiation pulse is limited by the additional resistance in the circuit. The resistance of resistors 62 and 63 (or the effective resistance of the resistor combination) can be greater than 1 kΩ, preferably greater than 10 kΩ. Desirably, this resistance is less than 100 kΩ. In this manner, an RC characteristic of the circuit can be achieved of approximately 1 µs. Desirably, the RC characteristic is less than approximately 10 µs.

[0103] Alternatively, a switch may be provided between the voltage source 61 and the patterned surface 40. The electrostatic mask clamp 11 may be configured such that the switch is open when an EUV radiation pulse is being generated and closed when an EUV radiation pulse is not being generated. In other words, a bias voltage may be provided to the patterned surface 40 when the EUV pulse is off, but no bias voltage is provided to the patterned surface 40 when the EUV pulse is on. In this manner, the mask MA may not draw current when an EUV radiation pulse is being generated, which prevents a surge in current from the voltage source 61 to the patterned surface 40 when an EUV pulse is being generated.

[0104] To achieve this functionality, the switch can be capable of operating at the same frequency as the EUV pulse frequency. For example, the switch can be capable of operating at a frequency greater than 49 kHz, preferably greater than 59 kHz, and more preferably greater than 99 kHz. For example, the switch can be capable of operating at 100 kHz. The switch can be configured to be controlled by a signal from another component within the lithographic apparatus LA that corresponds to the on and off switching of the EUV pulses. In other words, the control of the switch on and off can be synchronized with the on and off switching of the EUV radiation pulses.

[0105] Here, a scenario is described in which the bias voltage is cycled between negative and positive voltages. If a positive bias voltage is applied to the patterned surface 40 when the EUV radiation pulse is on, the number of photoelectrons released from the patterned surface 40 is reduced. Immediately after the EUV radiation pulse is turned off, the bias voltage on the patterned surface 40 is switched to a negative voltage. Therefore, a voltage bias system that applies a positive bias voltage to the patterned surface 40 when the EUV radiation pulse is on still has the effect of reducing the total number of photoelectrons released for a given EUV pulse.

[0106] The above embodiment involves applying a negative bias voltage to the patterned surface 40, causing the patterned surface 40 to repel negatively charged contaminant particles. However, there may be situations where contaminant particles in the reticle environment become positively charged. In such cases, a positive bias voltage can be applied to the patterned surface 40, causing the positively charged patterned surface 40 to repel positively charged contaminant particles.

[0107] To further reduce the number of contaminant particles attracted to patterned surface 40 during EUV lithography, the pressure within the reticle environment can be increased. When the pressure is increased, contaminant particles P generated within the reticle environment are more likely to be extracted. Consequently, the number of negatively charged contaminant particles decreases, mitigating the problem of negatively charged particles being attracted to patterned surface 40 when it becomes positively charged during an EUV radiation pulse.

[0108] Figure 12An embodiment for implementing the potential of the front side of the mask is schematically depicted. The clamp CL comprises a first ear EAR1 and a second ear EAR2, which have a first connection CON1 and a second connection CON2, respectively, for controlling the potential of the mask. In the previous text, both connections CON1 and CON2 were grounded. However, in this case, one of the ground pins can be used instead for the potential of the front side of the mask. Thus, the first connection CON1 is used to drive the potential of the front side of the mask (positive or negative, depending on the exposure sequence), while the second connection CON2 is used as a ground connection. The first connection CON1 is connected to a burl potential coating BPC or a conductive coating, which can extend to a subset of the burls (see Figure 15 ). When a subset of burls is covered by the burl potential coating BPC, each burl in the subset of burls no longer provides a clamping function. The coating BPC covering the burls eliminates the clamping effect of these burls. On the other hand, the subset of burls is now driven to a small potential by the burl potential coating BPC to provide a mask bias, such as Figure 8-10 shown.

[0109] For example, as a non-limiting example, a subset of approximately 20 burls can be provided with a burl potential coating (BPC). Thus, out of approximately 2,000 burls (as an example), only 20 burls (as an example) can be used for reticle front side potential control. Therefore, these burls can be driven to a slightly negative voltage. These burls are connected together via the conductive reticle backside coating. By driving the burls to a negative voltage, the front side 40 of the reticle MA can have a negative potential. Thus, the front side 40 of the reticle MA can function as a particle repellent mechanism and reduce the defect rate of the reticle front side 40. Furthermore, the burls can also be driven to a positive potential.

[0110] In the above example, since only 20 of the 2000 burls are connected to the burl potential coating BPC, it should be apparent that only a relatively small number of burls (or a subset) are required to transmit the reticle front-side potential. The majority of burls (1980 in this example) are still used to clamp the reticle MA. The burls with the conductive coating are no longer used for clamping; instead, they are used only for reticle biasing. Although 20 burls no longer provide clamping, this does not affect clamping of the reticle MA. The remaining 1980 burls still have sufficient clamping capacity to hold the reticle MA without any performance impact. By using a subset of 20 burls for reticle front-side potential control and the remaining 1980 burls for clamping, the clamp CL can simultaneously perform both voltage biasing and clamping. In other words, the clamp CL can hold the reticle MA while reducing the number of particles adhering to it.

[0111] In the example above, using only 20 burls as a subset of burls is sufficient to provide sufficient reticle bias to reduce the number of particles adhering to reticle MA. Using significantly more burls may allow for greater reticle bias, but this will negatively impact the clamping capability of fixture CL. If all burls were used for reticle bias, reticle MA would not be able to attach to fixture CL. Thus, there is a trade-off between providing clamping and providing reticle bias. It has been found that for a fixture CL with 2000 burls, repurposing 20 burls for reticle bias is optimal. In other embodiments, as few as 6 and as many as 100 burls may be used for reticle bias.

[0112] The burl potential coating (BPC) is electrically conductive and transfers the potential at the connection to the connected burl. If a slightly positive voltage is applied to the connection, the connected burl will also be set to that slightly positive voltage due to the BPC's connection. The BPC can be made of chromium (Cr) or titanium nitride (TiN).

[0113] Furthermore, the slight negative voltage can be between 5-10V, but is not limited to this range. The slight positive voltage can range from 20V to any voltage greater than 0V. Furthermore, there is no interference between the clamping voltage of the high-voltage electrode HVE (3000V) and the slight voltage of the burl potential coating (BPC) (5-10V). The slight voltage is so small that it does not affect the clamping of the mask MA.

[0114] Furthermore, the connection of the back side 41 of the reticle to the front side 40 must be achieved by modifying the reticle design itself, such as by connecting a conductive coating from the reticle back side 41 to the front side 40. With this modification, the front side 40 of the reticle can be controlled to a calibrated potential (positive or negative, depending on the exposure sequence), thereby serving as a way to prevent particles from depositing on the reticle FS, thereby reducing the defect rate of the reticle front side 40.

[0115] Figures 13A-13B An embodiment enabling burl potential control is schematically depicted. Figure 13A A fixture CL having a plurality of electrodes HVE and ELE is shown. Figure 7 Similar to that described in , the high voltage electrodes HVE are placed vertically to each other, and each electrode extends in the horizontal direction. Each of the four high voltage electrodes HVE is used to clamp the mask MA to a corresponding portion of the jig CL using a burl BU.

[0116] Furthermore, electrodes ELE are located around the high voltage electrode HVE inside the fixture. The top electrode ELE is located above the top high voltage electrode HVE, and the bottom electrode ELE is located below the bottom high voltage electrode HVE. The ear portion of the fixture has a UNICAP surface UNI.

[0117] Figure 13B yes Figure 13A Detailed view of the ear located below the UNICAP surface UNI in FIG. The ear is coated with a fixture ear coating CEC. The connection CON is shown in the middle of the ear. The connection CON is connected to the burl potential coating BPC to transfer the potential. The burl potential coating BPC is also shown in FIG. Figure 13A The burl potential coating BPC1 connecting the connection portion CON to the burl potential coating BPC spans over a clamp dam separating the ear portion from the burl. The clamp dam is a leak-proof seal.

[0118] In this embodiment, the connection CON is driven to the burl potential, which can be a slightly positive voltage, a slightly negative voltage, or even ground. When this happens, the electrode ELE, the clamp ear coating CEC, and the UNICAP surface UNI are also set to the burl potential. Several burls connected to the burl potential coating BPC are also set to the burl potential.

[0119] Figures 14A-14B An embodiment that enables burl potential control and true grounding is schematically depicted. Figure 14A and Figure 13A The difference is that ear EAR1 is connected to the true ground. On the other hand, ear EAR2 is still connected to the burl potential. Figure 14B The ear EAR2 below the UNICAP surface UNI is shown in more detail. In this embodiment, the burl with the burl potential coating BPC will be set to the burl potential. However, the electrode ELE, the clamp ear coating CEC and the UNICAP surface are all grounded.

[0120] By achieving both burl potential control and true grounding, multiple benefits can be achieved. This embodiment provides greater flexibility and controllability of the pins. Furthermore, the burl potential can be decoupled from ground. Thus, the burl and lug can be controlled independently.

[0121] Figure 15 An embodiment of a burl configuration is schematically depicted. Figure 15A cross-section of a burl used for reticle front-side bias is shown. The burl BU is supported on a top plate TP. The burl BU is coated with a burl potential coating (BPC). The BPC may be a titanium nitride (TiN) coating covering both the top and side surfaces of the burl BU. The BPC biases selected burls BU to provide reticle front-side bias. When the plasma beam is on, a positive charge is applied, and when the plasma beam is off, a negative charge is applied. This reduces defectivity.

[0122] This application document describes an electrostatic mask clamp CL, such as Figure 6 As shown, the electrostatic mask clamp includes a dielectric body GBU, an electrode HVE, and the electrode is configured to apply a charge to a first side of the dielectric body GBU facing the electrode HVE to electrostatically clamp the mask MA on a second side of the dielectric body GBU (a plurality of burls BU protruding from the second side) (see FIG. Figure 7 ), a plurality of burls BU, the plurality of burls being located on the second side of the dielectric body GBU and being configured to contact the mask MA, such as Figure 15 The conductive coating BPC shown is provided on the surface of a subset of the burls BU, as shown in FIG. Figure 7 The power supply PS and the controller CONT are configured to provide voltage from the power supply PS to the conductive coating BPC.

[0123] The controller CONT and the power supply PS of the electrostatic mask holder CL are configured to supply power to the conductive coating BPC (see Figure 12-15 ). Therefore, the positive voltage will be applied to the conductive backside coating COAT (such as Figure 7 The back side 41 of the mask MA mounted on the burl BU is positively charged to reduce the electrons released into the mask microenvironment during the EUV pulse B (in Figure 8-9 A positive voltage is applied when the EUV beam B is turned on to minimize the number of electrons released into the RME. Figure 8-9 The EUV beam B is shown in the ON state. When the back side 41 of the mask MA receives positive charge, the charge reaches the front side 40 of the mask MA. Therefore, the controller CONT and the power supply PS of the electrostatic mask clamp CL are configured to supply the conductive coating BPC (see Figure 12-15 ) applies a positive voltage to apply positive charges to the front side 40 of the mask MA having the imaging pattern PATT.

[0124] Controller CONT and power supply PS ( Figure 7 ) is configured to provide a conductive coating to the BPC ( Figure 12-15 ) to apply a negative voltage to the conductive backside coating COAT (such as Figure 7A negative charge is applied to the back side 41 of the mask MA (shown in FIG. 1 ) mounted on the burl BU, so that the front side 40 of the mask MA repels particles P between EUV pulses. A negative voltage is applied when the EUV beam B is turned off so that the negatively charged particles P repel the front side 40 of the mask MA, which is also negatively charged. This embodiment is as follows Figure 10 As shown. When the back side 41 of the mask MA receives negative charge, the charge will reach the front side 40 of the mask MA. Therefore, the controller CONT and the power supply PS of the electrostatic mask holder CL are configured to supply a negative charge to the conductive coating BPC (see Figure 12-15 ) applies a negative voltage, thereby applying a negative charge to the front side 40 of the mask MA having the imaging pattern PATT.

[0125] like Figure 12-15 As shown, the conductive coating BPC (also called the burl potential coating) includes a coating made of chromium (Cr). Alternatively, the conductive coating BPC may be made of a titanium nitride (TiN) material. In addition, the mask holder CL includes a plurality of high voltage and ground connections CON1 and CON2 on the ears EAR1 and EAR2 of the holder CL, as shown in FIG. Figure 12 As shown, the ear is coated with a conductive fixture ear coating CEC (see Figure 13B and Figure 14B ), and wherein the conductive coating CEC is connected to a ground pin on at least one of the fixture ears EAR1 and EAR2. One or more cover parts UNI (see Figure 13A and 14A ) are located in the ears EAR1 and EAR2 (see Figure 12-1 4) Above, one or more cover portions are electrically connected to the conductive fixture ear coating CEC.

[0126] Conductive coating BPC1 (such as Figure 13B As shown in FIG, the protruding structure that separates the clamp ear EAR from the burl BU includes a leak-proof sealing portion for connecting the burl. The protruding structure partially isolates the clamp ear EAR from the burl BU. Figure 12 As shown, the ground connection CON1 on one ear EAR1 is changed to provide voltage to the conductive coating BPC. The conductive coating BPC is connected to the connection CON1. ​​Therefore, any voltage provided to the connection CON1 will reach the conductive coating BPC. In addition, the ground pin CON2 on the other ear EAR2 remains grounded. This setting also applies to Figures 14A-14B .like Figure 8 A. Figure 13A and Figure 14A As shown, at least one electrode HVE is grounded. The conductive coating BPC provides a power supply PS ( Figure 7 ) to the surface of a subset of burls BU. The conductive paths of the conductive coating BPC can be Figure 12-1 Seen in 4.

[0127] A method for forming the electrostatic chuck CL ( Figure 6 ) method. First, a dielectric body GBU is provided, wherein the dielectric body has a plurality of burls BU on a first side. Second, a conductive coating BPC ( Figure 15 ) is applied to the first side of the dielectric GBU. Third, a conductive coating BPC is patterned on the first side of the dielectric GBU by leaving the coating BPC on a subset of the burls BU, and the conductive path formed by the conductive coating BPC enables the conductive path to be formed (see Figure 12-1 4) Applying an electrical potential to a subset of the BUs.

[0128] The patterning includes a photolithographic patterning process to provide a conductive path formed by the conductive coating BPC from at least one clamp ear EAR to a subset of the burls BU at the peripheral portion of the clamp, such as Figure 12-1 4. There is at least one glass body GLA on the second side of the dielectric body GBU, and there are two electrodes HVE between the dielectric body GBU and the at least one glass body GLA, as shown in FIG. Figure 6 shown.

[0129] As disclosed in EP 22195470.4 (incorporated herein by reference), the potential of the front side of the reticle can be adjusted / controlled by using connections to the back side of the reticle.

[0130] Various embodiments of the present systems and methods are disclosed in the following numbered list of clauses:

[0131] 1. An electrostatic mask fixture, comprising:

[0132] dielectrics;

[0133] an electrode configured to apply a charge to the first side of the dielectric body to electrostatically clamp the reticle to the second side of the dielectric body;

[0134] a plurality of burls located on the second side of the dielectric body and configured to contact the reticle;

[0135] a conductive coating disposed on a surface of a subset of the burls;

[0136] Power supply; and

[0137] A controller is configured to provide the voltage of the power supply to the conductive coating.

[0138] 2. An electrostatic reticle clamp according to clause 1, wherein the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to the back side of the reticle mounted on the burl to reduce the amount of electrons released into the reticle microenvironment during the EUV pulse.

[0139] 3. The electrostatic reticle fixture of clause 2, wherein the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to the front side of the reticle.

[0140] 4. An electrostatic reticle clamp according to any of the preceding clauses, wherein the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the back side of the reticle mounted on the burl, thereby causing the front side of the reticle to repel particles between EUV pulses.

[0141] 5. The electrostatic reticle clamp of any preceding clause, wherein the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the front side of the reticle.

[0142] 6. The electrostatic reticle holder of any preceding clause, wherein the conductive coating comprises a chromium (Cr) coating or a titanium nitride (TiN) coating.

[0143] 7. The electrostatic reticle fixture of clause 1 further comprising a plurality of high voltage and ground connections on the ears of the fixture, wherein the ears are coated with a conductive fixture ear coating, and wherein the conductive fixture ear coating is connected to a ground pin on at least one fixture ear.

[0144] 8. The electrostatic reticle clamp of clause 7, further comprising one or more cover portions disposed over the ears, wherein the one or more cover portions are electrically connected to the conductive clamp ear coating.

[0145] 9. An electrostatic reticle clamp according to any preceding clause, wherein the conductive coating spans a raised structure separating the clamp ears from the burls, wherein the raised structure includes a leaky seal for connecting the burls.

[0146] 10. The electrostatic reticle fixture of clause 7, wherein the ground connection on one of the ears is modified to provide a voltage to the conductive coating, and wherein the ground pin on the other ear remains at ground.

[0147] 11. An electrostatic reticle holder according to any of clause 10, wherein at least one electrode is grounded.

[0148] 12. The electrostatic reticle fixture of any preceding clause, wherein the conductive coating provides a conductive path from the power source to a surface on a subset of the burls.

[0149] 13. A method of forming an electrostatic mask fixture, comprising:

[0150] providing a dielectric body having a plurality of burls on a first side thereof;

[0151] applying a conductive coating to the first side of the dielectric body; and

[0152] The conductive coating is patterned on the first side of the dielectric body by retaining the coating on a subset of the burls and the conductive paths to enable application of an electrical potential to the subset of the burls through the conductive paths.

[0153] 14. The method of clause 13, wherein the patterning comprises a photolithographic patterning process to provide a conductive path from at least one clamp ear to a subset of burls at a peripheral portion of the clamp.

[0154] 15. The method according to clause 13, further comprising at least one glass body being arranged on the second side of the dielectric body, and two electrodes being arranged between the dielectric body and the at least one glass body.

[0155] The concepts disclosed herein can be associated with any general imaging system for imaging subwavelength features and are particularly applicable to emerging imaging technologies capable of producing shorter and shorter wavelengths. Emerging technologies already in use include EUV (extreme ultraviolet) lithography, which can produce wavelengths of 193 nm using ArF lasers, and even 157 nm using fluorine lasers. Furthermore, EUV lithography can produce wavelengths in the 20-5 nm range by using synchrotrons or bombarding materials (solid or plasma) with high-energy electrons to generate photons in this range.

[0156] While the concepts disclosed herein may be used for wafer fabrication on substrates such as silicon wafers, it should be understood that the disclosed concepts may also be used in any type of manufacturing system, such as systems for fabrication on substrates other than silicon wafers. Furthermore, combinations and subcombinations of the disclosed elements may comprise separate embodiments. For example, a cleaning system and associated lithographic apparatus may comprise separate embodiments, and / or these features may be used together in the same embodiment.

[0157] The above description is intended to be illustrative only, and not restrictive. Therefore, those skilled in the art will appreciate that modifications can be made in the manner described without departing from the scope of the claims set forth below.

Claims

1. An electrostatic mask clamp, comprising: dielectrics; an electrode configured to apply a charge to the first side of the dielectric body to electrostatically clamp the reticle to the second side of the dielectric body; a plurality of burls located on the second side of the dielectric body and configured to contact the reticle; a conductive coating disposed on a surface of a subset of the burls; power supply; and A controller is configured to provide the voltage of the power supply to the conductive coating.

2. The electrostatic reticle clamp of claim 1 , wherein the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to a back side of a reticle mounted on the burl, thereby reducing an amount of electrons released into the reticle microenvironment during an EUV pulse. 3 . The electrostatic reticle clamp of claim 2 , wherein the controller and the power supply are configured to apply a positive voltage to the conductive coating to apply a positive charge to the front side of the reticle.

4. An electrostatic reticle clamp according to any of the preceding claims, wherein the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the back side of the reticle mounted on the burl, thereby repelling particles from the front side of the reticle between EUV pulses.

5. The electrostatic reticle clamp of any one of the preceding claims, wherein the controller and the power supply are configured to apply a negative voltage to the conductive coating to apply a negative charge to the front side of the reticle. 6 . The electrostatic reticle holder according to claim 1 , wherein the conductive coating comprises a chromium (Cr) coating or a titanium nitride (TiN) coating.

7. The electrostatic mask clamp of claim 1 , further comprising a plurality of high voltage and ground connections on the ears of the clamp, wherein the ears are coated with a conductive clamp ear coating, and wherein the conductive clamp ear coating is connected to a ground pin on at least one clamp ear.

8. The electrostatic reticle clamp of claim 7, further comprising one or more cover portions disposed over the ear portions, wherein the one or more cover portions are electrically connected to the conductive clamp ear coating.

9. An electrostatic reticle clamp according to any one of the preceding claims, wherein the conductive coating spans a raised structure separating the clamp ears from the burls, wherein the raised structure includes a leaky seal for connecting the burls.

10. The electrostatic reticle fixture of claim 7, wherein the ground connection on one of the ears is modified to provide a voltage to the conductive coating, and wherein the ground pin on the other ear remains at ground.

11. The electrostatic reticle holder of any one of claims 10, wherein at least one electrode is grounded.

12. An electrostatic reticle fixture according to any one of the preceding claims, wherein the conductive coating provides a conductive path from the power supply to a surface on a subset of the burls.

13. A method for forming an electrostatic mask fixture, comprising: providing a dielectric body having a plurality of burls on a first side thereof; applying a conductive coating to the first side of the dielectric body; as well as The conductive coating is patterned on the first side of the dielectric body by retaining the coating on a subset of the burls and the conductive paths to enable application of an electrical potential to the subset of the burls through the conductive paths.

14. The method of claim 13, wherein the patterning comprises a photolithographic patterning process to provide a conductive path from at least one clamp ear to a subset of the burls at a peripheral portion of the clamp.

15. The method according to claim 13, further comprising disposing at least one glass body on the second side of the dielectric body, and disposing two electrodes between the dielectric body and the at least one glass body.

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