Memory device, memory system and operating method thereof

Abstract

A peripheral circuit of a memory device is configured to perform program verification on a program corresponding to a second (N-M) memory state during the process of programming a first physical page; when the program verification of the second (N-M) memory state is passed, making identifiers corresponding to the first memory state to the second (N-M) memory state stored in the main latch different from identifiers corresponding to the second (N-M) + 1 memory state to the 2Nth memory state; releasing at least one of the N page latches to cache programming data of at least one of the N logical pages of a second physical page; and storing the programming data of one of the N logical pages of the second physical page in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese application No. 202210028189.X filed on January 11, 2022, and the entire contents of the above application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a storage device, a memory system, and an operating method thereof. Background Art

[0004] In non-volatile memory devices, written data is first quickly stored in cache latches and then moved to data latches. During a single programming process to write data to the physical memory cell array of the memory device, only one page of data can be transferred from the cache latches to the data latches. Therefore, when the number of pages of data to be written to the physical memory cell array via programming exceeds one page, it is necessary to wait for programming to complete before individually transferring each page of data from the cache latches to the data latches. Consequently, the process of writing data to the memory cell array is inefficient and does not provide continuous programming. Summary of the Invention

[0005] In one aspect, a memory device includes a memory cell array. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to correspond to a piece of N-bit data. N levels, where N is an integer greater than 1. The memory device also includes a peripheral circuit coupled to the memory cell array and configured to: perform first programming and second programming on the memory cell array in the first physical page and the second physical page in sequence and respectively in a cache programming manner, and during the first programming and the second programming, program at least the selected row of the memory cells based on the N logical pages of the first physical page and the second physical page. The peripheral circuit includes page buffers coupled to the bit lines, respectively. Each page buffer includes a master latch, (N-1) data latches, and a cache latch coupled to the data path. The master latch is configured to store first non-physical page information, and the (N-1) data latches and cache latches are configured to: serve as N page latches during the process of programming the N logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the N logical pages. The peripheral circuit is also configured to: during the process of programming the first physical page, program the data latches corresponding to the second physical page. (N-M) The program corresponding to the memory state performs program verification; when the second (N-M)When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N The method comprises the steps of: releasing at least one of the N page latches to cache programming data of at least one of the N logical pages of the second physical page; and storing the programming data of one logical page of the N logical pages of the second physical page in the released page latch during programming of the first physical page, wherein M is an integer greater than or equal to 1 and less than or equal to (N-2).

[0006] In some embodiments, the peripheral circuit is further configured to: during programming of the first physical page and the second physical page, program the memory from the first memory state to the second memory state using an incremental step pulse programming (ISPP) method; (N -M) Program each memory state.

[0007] In some embodiments, the first non-physical page information includes verification information and program information.

[0008] In some embodiments, the peripheral circuit is further configured to: N The second of the memory states N-1 After performing the program verification on the first memory state, the first memory state stored in the master latch is changed to the second memory state. (N -1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N -1)+1 memory state to the 2nd N an identifier corresponding to a memory state; or in the case of the 2 N After the program verification is performed on the third to last memory state in the memory state, the first memory state to the second memory state stored in the master latch is changed. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the second N -1 memory state to 2nd N The identifier corresponding to each memory state.

[0009] In some embodiments, the peripheral circuit is further configured to: change the first memory state stored in the master latch to the second memory state stored in the master latch; (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd NAfter receiving an identifier corresponding to a memory state, the bit line is floated during the programming process to dump the first non-physical page information in the master latch.

[0010] In some embodiments, the peripheral circuit is further configured to: N The second of the memory states N-1 Before performing program verification on the first memory state, storing program data of a corresponding one of the N logical pages of the first physical page in at least one page latch of the N page latches; and N The second of the memory states N-1 After performing program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

[0011] In some embodiments, the peripheral circuit is further configured to: N After program-verifying a penultimate memory state among the N memory states, the N page latches are released so that the N page latches cache program data of each of the N logical pages of the second physical page.

[0012] In some embodiments, each memory cell is configured to store three bits of data. The peripheral circuit is further configured to program a selected row of memory cells based on three logical pages of the first physical page and the second physical page; and the two data latches and the cache latch are configured to function as three page latches during a programming process for the three logical pages of the first physical page and the second physical page to temporarily store program data to be written into the three logical pages.

[0013] In some embodiments, each memory cell is configured to store four bits of data. The peripheral circuit is further configured to program a selected row of memory cells based on four logical pages of the first physical page and the second physical page; and the three data latches and the cache latch are configured to function as four page latches to temporarily store program data to be written to the four logical pages during a programming process performed on the four logical pages of the first physical page and the second physical page.

[0014] In some embodiments, each page buffer further includes a bias latch configured to store voltage bias information of a corresponding bit line.

[0015] In some implementations, each page buffer further includes a bias latch coupled to the data path, wherein the bias latch is configured to store the second non-physical page information.

[0016] In some embodiments, the storage device further comprises a three-dimensional NAND flash memory device.

[0017] In another aspect, a storage device includes a storage cell array. The storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to correspond to a piece of N-bit data. N levels, where N is an integer greater than 1. The memory device also includes a peripheral circuit, which is coupled to the memory cell array and is configured to: perform first programming and second programming on the memory cell array in the first physical page and the second physical page in sequence and respectively in a cache programming manner, and during the first programming and the second programming, program at least the selected row of the memory cells based on the N logical pages of the first physical page and the second physical page. The peripheral circuit includes page buffers coupled to the bit lines respectively. Each page buffer includes a main latch, a bias latch, (N-1) data latches and a cache latch coupled to the data path. The (N-1) data latches and cache latches are configured to: serve as N page latches in the process of programming the N logical pages of the first physical page and the second physical page to temporarily store the programming data to be written into the N logical pages. The peripheral circuit is also configured to: in the process of programming the first physical page, the bias latch, the (N-1) data latches and the cache latch coupled to the data path. (N-M) +1 memory state corresponding to the programming to perform program verification; when the second (N-M) +1 memory state passes programming verification, releasing at least one page latch of the N page latches to cache programming data of at least one logical page of the N logical pages of the second physical page; and in the process of programming the first physical page, storing the programming data of one logical page of the N logical pages of the second physical page in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

[0018] In some embodiments, the peripheral circuit is further configured to: N After program verification of the third to last memory state of the first memory state, the bit line is floated during the programming process to dump the first non-physical page information in the master latch and to change the first memory state stored in the master latch to the second memory state. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the secondN -1 memory state to 2nd N The identifier corresponding to each memory state.

[0019] In some embodiments, the peripheral circuit is further configured to: N After performing the program verification on the second to last memory state in the memory states, the first memory state stored in the master latch is changed to the second memory state. N - an identifier corresponding to a memory state that is different from the identifier corresponding to the second N The identifier corresponding to each memory state.

[0020] In another aspect, a method for programming a memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to an N-bit data. N One of levels, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers respectively coupled to the bit lines. The method includes: storing N logical pages of a first physical page corresponding to a current first programming in the N page latches, wherein the N page latches include (N-1) data latches in the page buffer and a cache latch coupled to a data path; storing first non-physical page information in a master latch in the page buffer; in a first programming process of the first physical page, performing a first programming process on the first non-physical page corresponding to the second non-physical page; (N-M) The programming process corresponding to each memory state performs programming verification; when the second (N-M) When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N the memory state; releasing at least one page latch of the N page latches to cache programming data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2); and before performing second programming on the second physical page in a cache programming manner, the second programming being performed after the first programming is performed on the second physical page and during the first programming on the first physical page, storing the programming data of one logical page of the N logical pages of the second physical page in the released page latch.

[0021] In some embodiments, performing the first programming and the second programming on the first physical page and the second physical page includes programming the first memory state to the second memory state by using an incremental step pulse programming (ISPP) programming method. (N-M) Program each memory state.

[0022] In some embodiments, the first non-physical page information includes verification information and program information.

[0023] In some embodiments, when the second (N-M) When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N The method further comprises: in the case of the two N The second of the memory states N-1 After performing the program verification on the first memory state, the first memory state stored in the master latch is changed to the second memory state. (N-1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N -1) +1 memory state to 2nd N an identifier corresponding to a memory state; or in the case of the 2 N After performing program verification on the third to last memory state among the memory states, the first memory state stored in the master latch is changed to the second memory state. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the second N -1 memory state to 2nd N The identifier corresponding to each memory state.

[0024] In some embodiments, before changing the first memory state stored in the master latch to the second memory state (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N After receiving an identifier corresponding to a memory state, the method further includes floating the bit line during the programming process to dump the first non-physical page information in the master latch.

[0025] In some embodiments, the method further comprises: N The second of the memory states N-1Before performing the program verification on the first memory state, storing the program data of one logical page of the N logical pages of the first physical page in at least one page latch of the N page latches; and N The second of the memory states N-1 After performing the program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

[0026] In some embodiments, the method further comprises: N After performing program verification on a third-to-last memory state in the N memory states, the N page latches are released so that the N page latches cache program data of each of the N logical pages of the second physical page. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate several aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0028] Figure 1 is a schematic diagram of writing data in a non-volatile memory device according to some embodiments of the present disclosure;

[0029] Figure 2 is a block diagram of a system having a non-volatile storage device according to some embodiments of the present disclosure;

[0030] Figure 3A is a schematic diagram of a memory card according to some embodiments of the present disclosure;

[0031] Figure 3B is a schematic diagram of a solid state drive (SSD) according to some embodiments of the present disclosure;

[0032] Figure 4 is a block diagram of a nonvolatile memory device including a memory cell array and a peripheral circuit according to some embodiments of the present disclosure;

[0033] Figure 5 is a block diagram of a page buffer in a program operation according to some embodiments of the present disclosure;

[0034] Figure 6 is a state encoding table in which user data is not encoded and converted in the page latch according to some embodiments of the present disclosure;

[0035] Figure 7is an encoding status table after encoding and converting program data of a temporarily stored logical page according to some embodiments of the present disclosure.

[0036] Figure 8 is an encoding state table when LV3 programming verification passes and the function of the master latch DS changes according to some embodiments of the present disclosure;

[0037] Figure 9 is a coding status table after LV5 programming verification passes according to some embodiments of the present disclosure;

[0038] Figure 10 is a coding status table after LV6 programming verification passes according to some embodiments of the present disclosure;

[0039] Figure 11 is a schematic flowchart of a programming method of a non-volatile memory device according to some embodiments of the present disclosure;

[0040] Figure 12 is an encoding status table after encoding and converting program data of a temporarily stored logical page according to some embodiments of the present disclosure.

[0041] Figure 13 is a coding status table after LV4 programming verification passes according to some embodiments of the present disclosure;

[0042] Figure 14 is an encoding state table when LV5 programming verification passes and the function of the master latch DS changes according to some embodiments of the present disclosure;

[0043] Figure 15 is a coding status table after LV6 programming verification passes according to some embodiments of the present disclosure;

[0044] Figure 16 is an encoding status table after encoding and converting program data of a temporarily stored logical page according to some embodiments of the present disclosure.

[0045] Figure 17 is an encoding state table when LV7 programming verification passes and the function of the master latch DS changes according to some embodiments of the present disclosure;

[0046] Figure 18 is a coding status table after LV11 programming verification passes according to some embodiments of the present disclosure;

[0047] Figure 19 is an encoding state table when LV13 programming verification passes and the function of the master latch DS changes according to some embodiments of the present disclosure;

[0048] Figure 20 is a coding status table after LV14 programming verification passes according to some embodiments of the present disclosure;

[0049] Figure 21 is an encoding status table after encoding and converting program data of a temporarily stored logical page according to some embodiments of the present disclosure.

[0050] Figure 22 is a coding status table after LV8 programming verification passes according to some embodiments of the present disclosure;

[0051] Figure 23 is a coding status table after LV12 programming verification passes according to some embodiments of the present disclosure;

[0052] Figure 24 is an encoding state table when LV13 programming verification passes and the function of the master latch DS changes according to some embodiments of the present disclosure;

[0053] Figure 25 is a coding status table after LV14 programming verification passes according to some embodiments of the present disclosure;

[0054] Figure 26 This is the coding status table when LV5 programming verification passes and the bit line bias function is disabled;

[0055] Figure 27 is a coding status table after LV6 programming verification passes according to some embodiments of the present disclosure;

[0056] Figure 28 is a schematic flowchart of a programming method of a non-volatile memory device according to some embodiments of the present disclosure;

[0057] Figure 29 is an encoding state table when LV13 program verification passes and the bit line bias function is disabled according to some embodiments of the present disclosure; and

[0058] Figure 30 is a coding status table after LV14 programming verification passes according to some embodiments of the present disclosure;

[0059] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0060] Generally, terms can be understood, at least in part, from their use in context. For example, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey the singular or to convey the plural, depending at least in part on the context. Furthermore, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but can, depending at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0061] In a non-volatile memory device, the written data is first quickly stored in the cache latch and then moved to the data latch. Figure 1 As shown. The period during which the programming data of one logical page (page 3) of the second physical page is moved to the data latch is hidden during the first programming process. That is, during the first programming process of writing data to the physical array of the flash memory, only the movement of the programming data of one of the three logical pages of the second physical page from the cache latch to the data latch can be achieved. In this way, when the number of physical pages programmed into the physical array is greater than one physical page, it is necessary to wait for the end of programming, and the programming data of the other two logical pages in the second physical page are moved from the cache latch to the data latch separately, which makes the writing of data to the memory cell array inefficient and the programming discontinuous. The solution provided by the present disclosure enables the programming data of various logical pages required for the second programming to be temporarily stored in the page latch during the first programming, and therefore there is no need to wait or the waiting time is reduced when the second programming starts, thereby improving the continuity between programming processes.

[0062] Figure 2 FIG2 shows a block diagram of an exemplary system 200 having a non-volatile storage device according to some embodiments of the present disclosure. The system 200 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 2As shown, system 200 may include a host 208 and a memory system 202 having one or more non-volatile memory devices 204 and a controller 206. Non-volatile memory device 204 includes a memory cell array and a multi-page buffer. Host 208 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 208 may be configured to send data to or receive data from non-volatile memory device 204.

[0063] Non-volatile storage device 204 can be any non-volatile storage device disclosed herein. According to some embodiments, controller 206 is coupled to non-volatile storage device 204 and host 208 and is configured to control the non-volatile storage device. Controller 206 can manage data stored in the non-volatile storage device and communicate with host 208. In some embodiments, controller 206 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or for electronic devices such as personal computers, digital cameras, and mobile phones.

[0064] In some embodiments, the controller 206 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) for use as data storage and enterprise storage for mobile devices such as smartphones, tablets, and laptops. The controller 206 can be configured to control operations of the non-volatile storage device 204, such as read, erase, and program operations. The controller 206 can also be configured to manage various functions regarding data stored or to be stored in the non-volatile storage device 204, including but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 206 is also configured to process error correction codes (ECC) for data read from or written to the non-volatile storage device 204. The controller 206 can also perform any other suitable functions, such as formatting the non-volatile storage device 204. For example, the controller 206 can communicate with an external device (e.g., the host 208) according to a specific communication protocol. For example, the controller 206 can communicate with the external device through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc. The controller 206 can be specifically composed of the following: a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic unit, a discrete hardware circuit, or a combination thereof, as well as other suitable hardware, firmware and / or software.

[0065] The controller 206 and the one or more non-volatile storage devices 204 can be integrated into various types of storage devices, for example, included in the same package (such as a universal flash memory (UFS) package or an eMMC package). In other words, the memory system 202 can be implemented and packaged into different types of electronic terminal products. Figure 3AIn one example shown, the controller 206 and the non-volatile storage device 204 may be integrated into a memory card 302. The memory card 302 may include a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 302 may also include a computer program that connects the memory card 302 to a host (e.g., Figure 2 The host computer 208 is coupled to the memory card connector 304. Figure 3B In another example shown, the controller 206 and the plurality of non-volatile storage devices 204 may be integrated into an SSD 306. The SSD 306 may also include a processor that interfaces the SSD 306 with a host (e.g., Figure 2 In some embodiments, the storage capacity and / or operating speed of the SSD 306 is greater than the storage capacity and / or operating speed of the memory card 302.

[0066] Figure 4 A block diagram of a nonvolatile memory device (e.g., nonvolatile memory device 204) according to some embodiments of the present disclosure is shown, including a memory cell array 401 and peripheral circuitry 400. Peripheral circuitry 400 includes a page buffer / amplifier sensor 404, a column decoder / bit line (BL) driver 406, a row decoder / word line (WL) driver 408, a voltage generator 410, control logic 412, registers 414, an interface 416, and a data bus 418. It should be understood that in some examples, according to some embodiments of the present disclosure, additional peripheral circuitry (not shown) may also be included.

[0067] The page buffer / sense amplifier 404 can be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to a control signal from the control logic 412. In one example, the page buffer / sense amplifier 404 can store programming data (write data, also referred to herein as a "data page") to be programmed into one logical page of one physical page of the memory cell array 401. As described in detail below and consistent with the scope of the present disclosure, in a programming operation, the page buffer / sense amplifier 404 may include a plurality of page buffers respectively coupled to the bit lines. Each page buffer includes N-1 data latches and a cache latch coupled to the data path for temporarily storing N-bit data segments received from the data bus 418, and for caching the N-bit data segments into the corresponding selected storage device through the corresponding bit line by a cache programming method.

[0068] The column decoder / bit line (BL) driver 406 may be configured to be controlled by the control logic 412 and to select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 410. The row decoder / word line (WL) driver 408 may also be configured to drive a word line using a word line voltage generated from the voltage generator 410. The voltage generator 410 may be configured to be controlled by the control logic 412 and to generate word line voltages (e.g., a read voltage, a program voltage, a channel pass voltage, a local voltage, a verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 401.

[0069] See also Figure 4 , the peripheral circuit 400 is configured to: perform a first programming process and a second programming process on the memory cell array 401 in sequence through the first physical page and the second physical page in a cache programming manner. And in the first programming / second programming process, the row of the selected memory cell is programmed based on the N logical pages of the first physical page / the second physical page. In some embodiments, the user data is transmitted to the page buffer / sense amplifier 404 via the data bus 418. The page buffer / sense amplifier 404 is configured to convert the user data into programming data based on preset rules to be programmed into each logical page in the selected row of memory cells. During the ongoing first programming operation, the programming data in the N logical pages of the first physical page can be temporarily stored in the page buffer / sense amplifier 404.

[0070] Figure 5 Detailed block diagram of the page buffer / sense amplifier 404 in a programming operation according to some embodiments of the present disclosure is shown. In some embodiments, the page buffer / sense amplifier 404 includes a plurality of page buffer circuits 502. Each page buffer circuit 502 is coupled to a corresponding one of the bit lines BL. In other words, each page buffer circuit 502 can be coupled to a corresponding column of memory cells (e.g., a string of memory cells) through a corresponding bit line BL and is configured to temporarily store data of a selected memory cell during a programming operation. The programming data in the N logical pages of the first physical page / second physical page of the row of memory cells will be programmed. In some embodiments, the page buffer circuit 502 is further configured to: Figure 4 ) pre-processes the received user data and converts it into selected programming data of N logical pages of the first physical page / second physical page in the memory cell row.

[0071] like Figure 5As shown, each page buffer circuit 502 may include (N-1) data latches (D1 to Dn-1) 508 and a cache latch (DC) 506 coupled to the data path. The (N-1) data latches 508 and the cache latch 506 serve as N-page latches to temporarily store program data to be written into the N logical pages during a programming process performed on the N logical pages of the first physical page / the second physical page.

[0072] Each page buffer circuit 502 may further include a plurality of storage units for storing non-physical page information, which refers to information in a physical page other than the programming data of a logical page and is different from the programming data of, for example, N logical pages. The non-physical page information can be used to assist in implementing the data programming process of the physical page during the programming process, and is generally not temporarily stored in the data latch. Figure 5 As shown, in some embodiments, the page buffer circuit 502 includes a master latch (DS) 512 configured to store verification information and programming information, and a bias latch (DL) 510 configured to store bias voltage information of the corresponding bit line BL. Each page buffer circuit 502 may further include a bias circuit 504. The bias circuit 504 is coupled to each bit line BL and is configured to apply a bit line voltage to each selected row of memory cells coupled to the respective bit line BL during a programming operation.

[0073] In some embodiments of the present disclosure, a nonvolatile memory device includes a memory cell array having memory cells arranged in rows and columns. Each memory cell is configured to correspond to a piece of N-bit data (e.g., 3-bit data). N The peripheral circuit is coupled to the memory cell array and configured to: perform a first programming process and a second programming process on the memory cell arrays on the first physical page and the second physical page in a cache programming manner, respectively, and during the first programming process / the second programming process, program the rows of the selected memory cells based on the three logical pages of the first physical page / the second physical page, wherein the three logical pages are a lower page (LP), a middle page (MP), and an upper page (UP).

[0074] The peripheral circuitry includes multiple page buffers, each coupled to a bit line. Each page buffer includes a master latch DS, two data latches D1 and D2, and a cache latch DC coupled to the data path. The master latch DS is configured to store the first non-physical page information; the two data latches D1 and D2 and the cache latch DC are used to serve as three page latches during the programming process for the three logical pages of the first physical page / second physical page, temporarily storing the program data to be written to the three logical pages.

[0075] The peripheral circuit is further configured to: during programming of the first physical page, when the first to second (N-M) When the programming operation of a memory state is completed, the programming operation is performed on the corresponding second (N-M) Program verification is performed on each memory state. (N-M) When the programming verification of the memory state passes, the master latch is subjected to non-target verification, so that the first to second memory states stored in the master latch are (N-M) The identifier corresponding to the memory state is the same as the second (N-M) +1 to 2nd N The nonvolatile memory device includes a first memory state and a second memory state, wherein the identifiers corresponding to the first and second memory states are different, and at least one of the N page latches is released to cache programming data of at least one of the N logical pages of the second physical page. Furthermore, during programming of the first physical page, programming data of one of the N logical pages of the second physical page is stored in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2) (e.g., for TLC, N=3 and M=1). In some embodiments, the nonvolatile memory device includes a three-dimensional NAND flash memory device.

[0076] In some embodiments of the present application, the peripheral circuit is further configured to: when programming the first physical page / the second physical page, use an incremental step pulse programming (ISPP) programming method to program the first to second physical pages. (N-M) In some embodiments, for example, for TLC, N=3, M=1, the peripheral circuit is further configured to: during programming of the first physical page / the second physical page, use an incremental step pulse programming (ISPP) programming method to program the first to second physical pages. 2 Programming operations are performed on each memory state.

[0077] In some embodiments, each memory cell has eight memory states (levels) and can therefore be set to two corresponding to three bits of data. 3 Each memory state may correspond to one of a range of threshold voltages (Vth) of a memory cell. Alternatively, each memory state may correspond to two levels to be stored in a selected row of memory cells. 3 One of three bits of data.

[0078] In some embodiments, see Figure 6 , Figure 6 FIG1 is a state encoding table for temporarily storing user data in page latches according to some embodiments of the present application, showing an example of binary encoding of a one-to-one mapping between 8 memory states (LV0 to LV7) and 8 segments.

[0079] Each segment of three-bit data may be composed of a three-bit binary code, and the three-bit binary code is derived from three logical pages, respectively, and the three logical pages are a low page LP, a middle page MP, and an upper page UP.

[0080] It can be seen that the three page latches store the programming data of the low, middle and high logical pages in sequence. The page latch D1 stores the low page LP, the page latch D2 stores the middle page MP, and the page latch DC stores the high page UP.

[0081] In some embodiments, memory state LV1 may correspond to a segment coded as 011. In some embodiments, memory state LV7 may correspond to another segment coded as 101. Figure 7 According to some embodiments of the present disclosure, the encoding state table is obtained after the programming data of the logical page stored in the page latch is encoded and converted according to a preset rule. Figure 7 As shown, LV1 is encoded from 011 to 001, where code 011 represents LP / MP / UP in sequence. The encoding order of other memory states is also LP / MP / UP. LV2 is encoded from 001 to 101, LV3 is encoded from 000 to 011, LV4 is encoded from 010 to 000, LV5 is encoded from 110 to 010, LV6 is encoded from 100 to 100, and LV7 is encoded from 101 to 110.

[0082] In some embodiments, the peripheral circuit is further configured to: N The second of the memory states N-1 Before performing program verification for each memory state, program data corresponding to one of the N logical pages of the first physical page is stored in at least one page latch of the N page latches.

[0083] And in pair 2 N The second of the memory states N-1 After performing program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

[0084] In some embodiments, before performing program verification on the fourth memory state LV3 among the eight memory states, DC may store programming data of one logical page (current UP) of the three logical pages of the first physical page. D1 may store programming data of the corresponding logical page (current LP) of the first physical page. D2 may store programming data of the corresponding logical page (current MP) of the first physical page. After performing program verification on the fourth memory state LV3 among the eight memory states, programming data of one logical page of the three logical pages of the second physical page is stored in three page latches. Figure 8 for more details.

[0085] In some embodiments, the peripheral circuit is further configured to: N The second of the memory states N-1 After the program verification is performed on each memory state, the non-target verification is performed on the master latch. That is, the 1st to 2nd memory states stored in the master latch DS are (N-1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-1) +1 to 2nd N In some embodiments, reference Figure 8 , after the programming verification of the 4th memory state among the 8 memory states is completed (that is, the 4th memory state LV3 has been verified), the master latch DS stores identifiers corresponding to the 1st to 4th memory states, which are different from the identifiers corresponding to the 5th to 8th memory states. That is, the identifiers of the memory states that have been programmed and verified in the master latch are different from the identifiers of the memory states that have not been programmed and verified. When DS is 1, it means that the memory state has passed the programming verification, and when DS is 0, it means that the memory state has not passed the programming verification. LV3 programming verification passed (LV3 passed) means that the fragments corresponding to the memory states LV0~LV3 are written in the three page latches. Among them, all binary codes in LV0~LV3 can be updated to 1. The encoding state table is as follows Figure 8 As shown. At this time, there are still four memory states LV4, LV5, LV6, and LV7 that have not been programmed and verified. Since one bit of each logical page has two possible states, 0 and 1, the physical unit composed of two page latches has four possible states (2 2=4). Since the identifier of the memory state that has not passed the programming verification in the master latch DS for non-target verification is 0, the combination of the two page latches and the master latch DS for non-target verification can have code 000, code 001, code 010 and code 011, representing LV4, LV5, LV6 and LV7 respectively. In other words, after the LV3 programming verification is passed, only two page latches and the master latch DS for non-target verification are needed to distinguish the four memory states of LV4, LV5, LV6 and LV7. Therefore, after the LV3 programming verification is passed, the page latch DC can be released so that the released page latch caches the programming data of the low page LP of the second physical page. The encoding state table is as follows Figure 8 shown.

[0086] In some embodiments, each page buffer further includes a bias latch configured to store voltage bias information of a corresponding bit line.

[0087] In some embodiments, the peripheral circuit is further configured to: (N-M) The identifier corresponding to the memory state is the same as the second (N-M) +1 to 2nd N After the identifiers corresponding to the memory states are different, the bit line is floated during programming to dump the first non-physical page information in the master latch. In some embodiments, the first non-physical page information includes verification information and programming information. After LV3 programming verification passes, the master latch DS is used to identify memory states that have passed programming verification and memory states that have not passed programming verification. Therefore, the first non-physical page information in the original master latch DS can no longer be stored. Floating the bit line during programming can release the bias latch to dump the first non-physical page information in the master latch.

[0088] In some embodiments, after the LV5 programming verification is passed, it means that the fragments corresponding to the memory states LV0 to LV5 in the three page latches have been written, and there are two memory states LV6 and LV7 that have not passed the verification. Since a bit of each logical page has two possible states of 0 and 1, the main latch DS and the page latch D2 can form code 00 and code 01, respectively representing the memory states LV6 and LV7 that have not passed the programming verification. Therefore, after the LV5 programming verification is passed, the page latch D1 can be released so that the released page latch buffers the middle page MP of the next physical page. The encoding state table is as follows: Figure 9 shown.

[0089] In some embodiments, the peripheral circuit is further configured to: NAfter program verification is performed on the second-to-last (second from the back) memory state of the 8th memory state, the N page latches are released so that the N page latches cache the program data of each of the N logical pages of the second physical page. In some embodiments, after program verification of the second-to-last memory state of the 8th memory state (i.e., the 7th memory state (LV6) has been verified), the three page latches are released so that the three page latches cache the program data of each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 10 As shown, when the programming verification of LV6 passes, that is, DS is 1, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, the page latch DC is further released to cache the programming data of the upper page UP of the second physical page. At this time, the three page latches are released so that all the programming data of each page are stored in the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page MP of the second physical page. And then, whether DS is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it means that the LV7 programming verification has passed, and the data of LV0 to LV7 has been written to the selected memory cell, and the first programming is completed. At this time, the programming data of the three logical pages to be written in the second programming has been cached in the three page latches. Thus, the second programming process can be directly entered. If DS is 0, the program verification fails. Since the three page latches can cache the program data of each of the three logical pages (next LP, next MP, and next UP) of the second physical page after the program verification of LV6, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without the need for a data loading window.

[0090] Based on the non-volatile memory device provided in the above embodiment of the present application, a programming method for the non-volatile memory device is also provided in the embodiment of the present application. The non-volatile memory device includes a memory cell array and a peripheral circuit; the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to an N-bit data. NOne of the levels, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers coupled to the bit lines respectively. The method includes: storing N logical pages of the first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path. During the first programming of the first physical page, when the 1st to 2nd (N-M) When the programming operation of the first memory state is completed, the second (N-M) The program operation corresponding to each memory state performs a program verification operation. (N-M) The programming verification of the memory state passes, so that the master latch stores the first to second (N-M) The identifier corresponding to the memory state is different from the second (N-M) +1 to 2nd N The method includes: providing an identifier corresponding to a memory state of the second physical page, releasing at least one page latch of the N page latches to cache program data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2). The method further includes storing program data of one logical page of the N logical pages of the second physical page in the released page latch during the first programming of the first physical page before performing a second programming of the second physical page in the cache programming mode after the first programming.

[0091] Figure 11 1 is a schematic flow chart of an embodiment of a programming method for a non-volatile memory device provided in some embodiments of the present application. Figure 11 As shown, the programming method includes the following steps:

[0092] Step S101: Store N logical pages of a first physical page corresponding to a current first programming in N page latches, wherein the N page latches include (N-1) data latches in a page buffer and one cache latch coupled to a data path.

[0093] After the programming data of the three logical pages LP, MP, and UP are stored in the page latches, the programming data stored in the page latches are converted into binary codes corresponding to different memory states according to preset rules. Figure 7 .

[0094] Step S102: storing first non-physical page information in a master latch in a page buffer. Here, the first non-physical page information includes verification information and program information.

[0095] In step S101, each memory cell is set to 2 corresponding to a piece of three-bit data in one of the eight memory states.3 one of the levels. After performing program verification on the 4th memory state among the 8 memory states, the programming data of the corresponding one of the three logical pages of the first physical page is stored in at least one page latch of the three page latches. In some embodiments, before performing program verification on the fourth memory state LV3 among the 8 memory states, DC may store the programming data of one logical page (current UP) of the three logical pages of the first physical page corresponding to the current first programming. And D1 may store the programming data of the corresponding logical page (current LP) of the first physical page. And D2 may store the programming data of the corresponding logical page (current MP) of the first physical page. And after program verification on the 4th memory state among the 8 memory states, the programming data of one logical page of the three logical pages of the second physical page is stored in at least one page latch of the three page latches. In some embodiments, reference Figure 8 After program verification of the fourth memory state LV3 among the eight memory states, program data of one logical page among the three logical pages of the second physical page is stored in at least one page latch of the three page latches.

[0096] Step S103: During the first programming of the first physical page, when the first to second (N-M) When the programming operation of the first memory state is completed, execute the same (N-M) A program verification operation corresponding to each memory state is performed.

[0097] In the second (N-M) If the programming verification of the memory state passes, the first to second memory states stored in the master latch are switched. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 to 2nd N The method comprises: providing an identifier corresponding to a memory state and releasing at least one page latch of N page latches to cache programming data of at least one logical page of N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

[0098] And before and during the first programming of the first physical page, the first programming of the first physical page is before the second programming of the second physical page, and the second programming of the second physical page is after the first programming in the cache programming mode, the program data of one logical page of the N logical pages of the second physical page is stored in a released page latch.

[0099] In the above step S103, taking TLC as an example, N=3, M=1, the first programming / second programming is performed on the first physical page / the second physical page, including performing programming operations on the 1st to 4th memory states using the incremental step pulse programming (ISPP) method.

[0100] In some embodiments of the present application, N The second of the memory states N-1 Before performing program verification on the memory states, program data of a corresponding one of the N logical pages of the first physical page is stored in at least one page latch of the N page latches. N The second of the memory states N-1 After performing programming verification on the fourth memory state LV3 among the eight memory states, the programming data of one logical page of the N logical pages of the second physical page is stored in at least one page latch among the N page latches. In some embodiments, before performing programming verification on the fourth memory state LV3 among the eight memory states, DC can store programming data of one logical page (current UP) of the three logical pages of the first physical page. And D1 can store programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store programming data of the corresponding logical page (current MP) of the first physical page. After programming verification on the fourth memory state LV3 among the eight memory states, the programming data of one logical page of the three logical pages of the second physical page is stored in the three page latches. You can refer to Figure 8 to get the details.

[0101] In some embodiments of the present application, N The second of the memory states N-1 After the program verification is performed on each memory state, the master latch DS is made to perform non-target verification. (N -1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-1) +1 to 2nd N The identifier corresponding to each memory state. Specifically, Figure 8As shown, after the programming verification of the 4th memory state among the 8 memory states (that is, the 4th memory state LV3 has been verified), the identifiers corresponding to the 1st to 4th memory states stored in the master latch DS are different from the identifiers corresponding to the 5th to 8th memory states. That is, the identifier of the memory state that has been programmed and verified in the master latch is different from the identifier of the memory state that has not passed the programming verification. When DS is 1, it indicates that the programming verification of the memory state has passed, and when DS is 0, it indicates that the programming verification of the memory state has failed. LV3 programming verification passed (LV3 passed) means that the fragments corresponding to the memory states LV0~LV3 are written in the three page latches. That is, all binary codes in LV0~LV3 can be updated to 1. The encoding state table is as follows Figure 8 As shown. At this time, there are still four memory states LV4, LV5, LV6, and LV7 that have not been programmed and verified. Since one bit of each logical page has two possible states, 0 and 1, the physical unit composed of two page latches has four possible states (2 2 =4). Since the identifier of the memory state that has not passed the programming verification in the master latch DS for non-target verification is 0, the combination of the two page latches and the master latch DS for non-target verification can have code 000, code 001, code 010 and code 011, representing LV4, LV5, LV6 and LV7 respectively. In other words, after the LV3 programming verification is passed, only two page latches and the master latch DS for non-target verification are needed to distinguish the four memory states of LV4, LV5, LV6 and LV7. Therefore, after the LV3 programming verification is passed, the page latch DC can be released so that the released page latch caches the programming data of the low page LP of the second physical page. The encoding state table is as follows Figure 8 shown.

[0102] In some embodiments of the present application, in the second (N-M) If the programming verification of the memory state passes, the first to second memory states stored in the master latch are switched. (N-M) The identifier corresponding to the memory state is the same as the second (N-M) +1 to 2nd N The identifiers corresponding to the memory states are different, including: N The second of the memory states N-1 After the program verification is performed on each memory state, the master latch is caused to perform non-target verification. Non-target verification causes the master latch to store the first to second memory states. N-1 The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-1) +1 to 2nd N The identifier corresponding to each memory state. Figure 8After program verification of the fourth memory state among the eight memory states (i.e., the fourth memory state LV3 has been verified), the master latch DS is caused to perform non-target verification. Non-target verification causes the identifiers corresponding to the first to fourth memory states stored in the master latch to be different from the identifiers corresponding to the fifth to eighth memory states. When DS is 1, it indicates that the memory state has passed program verification, and when DS is 0, it indicates that the memory state has failed program verification.

[0103] In some embodiments of the present application, after the master latch performs non-target verification, the bit line is floated during programming to dump the first non-physical page information in the master latch. Since the non-target verification after LV3 programming verification passes, the master latch is used to identify memory states that have been programmed and verified and memory states that have not yet been programmed and verified. Therefore, it cannot continue to store the first non-physical page information in the original master latch DS. After the non-target verification of the master latch, floating the bit line during programming can release the bias latch to dump the first non-physical page information in the master latch.

[0104] In some embodiments of the present application, N After program-verifying the second-to-last memory state of the eight memory states, the N page latches are released so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In some embodiments, after program-verifying the second-to-last memory state of the eight memory states (i.e., the seventh memory state (LV6) has been verified), three of the page latches are released so that the three page latches cache the programming data of each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 10As shown in , when the programming verification of LV6 passes, that is, DS is 1, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, thereby further releasing the page latch DC to cache the programming data of the upper page UP of the second physical page. At this time, the three page latches are released so that all the programming data of each page are stored in the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page MP of the second physical page. And after this, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it means that the LV7 programming verification has passed and the data of LV0 to LV7 has been written to the selected memory cell. Programming is completed. At this time, the programming data of the three logical pages to be written in the second programming is already in the page latch, so the second programming process can be directly entered. If DS is 0, the program verify determination cannot proceed.

[0105] In some embodiments of the present application, after the peripheral circuit included in the nonvolatile memory device stores the program data of three logical pages in three page latches, the program data of the logical pages stored in the page latches are converted into codes according to a preset rule. Figure 12 As shown, the obtained Figure 6 The encoding state table is converted by the encoding, and each memory state before the encoding conversion includes a three-bit binary code, which comes from LP / MP / UP respectively. After the encoding conversion, LV1 is encoded from 011 to 001, where 011 comes from LP / MP / UP in sequence. Similarly, the encoding order of other memory states is LP / MP / UP, LV2 is encoded from 001 to 101, LV3 is encoded from 000 to 011, LV4 is encoded from 010 to 000, LV5 is encoded from 110 to 010, LV6 is encoded from 100 to 100, and LV7 is encoded from 101 to 110. In some embodiments, DC can store programming data of one logical page (current UP) of the three logical pages of the first physical page, D1 can store programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store programming data of the corresponding logical page (current MP) of the first physical page. LV4 programming verification pass (LV4 pass) means that the segments corresponding to the memory states LV0 to LV4 in the three page latches are all written. That is, all binary codes in LV0 to LV4 can be updated to 1 because they are no longer needed in the first programming operation. The coding state table is as follows Figure 13As shown. At this point, there are still three memory states LV5, LV6, and LV7 that remain unprogrammed but verified. Since one bit of each logical page has two possible states, 0 and 1, the physical unit includes two page latches and has four possible states (2 2 =4). Excluding code 11, which is the same as the memory state that has been programmed and verified, the remaining codes 00, 10, and 01 can represent LV5, LV6, and LV7, respectively.

[0106] In other words, after LV4 programming verification passes, only two page latches are needed to distinguish between the three memory states of LV5, LV6, and LV7. Therefore, after LV4 programming verification passes, page latch DC can be released. The currently programmed data of the upper page UP is replaced by the programmed data of the lower page LP of the second physical page.

[0107] In some embodiments of the present application, the peripheral circuit is further configured to: N After performing program verification on the third to last memory state in the first memory state, non-target verification is performed on the master latch, so that the non-target verification makes the first to second memory states stored in the master latch N -2 memory states correspond to identifiers different from the second N -1 to 2 N In some embodiments, after the programming verification of the third to last (third from the back) memory state among the 8 memory states (i.e., the 6th memory state (LV5) has been verified), the master latch DS performs the following non-target verification: the identifiers corresponding to the 1st to 6th memory states stored in the master latch are different from the identifiers corresponding to the 7th to 8th memory states. When DS is 1, it indicates that the programming verification of the memory state has passed; when DS is 0, it indicates that the programming verification of the memory state has failed. Figure 14 As shown, you can update Figure 13 That is, all data bits in LV5 can be updated to 1 because they are no longer needed in the current first programming operation. Figure 14As shown, DS is 1 at this time, indicating that the LV5 programming verification has passed. At this time, the master latch DS and the page latch D2 can form code 00 and code 01, indicating LV6 and LV7 respectively. In other words, after the LV5 programming verification is passed, only one page latch and the master latch DS for non-target verification are needed to distinguish between the two memory states LV6 and LV7. Therefore, after the LV5 programming verification is passed, the page latch D1 can be released to cache the programming data of the lower page LP of the second physical page, thereby further releasing the page latch DC to cache the programming data of the middle page MP of the second physical page. That is, the next LP can be passed from DC to D1, and the programming data of the next MP can be cached in DC. It should be noted that when the master latch DS is performing target verification, the state bit being subjected to programming verification is 1, and the other state bits are 0.

[0108] Since the non-target verification performed after the LV5 verification passes, the identifiers corresponding to the 1st to 6th memory states stored in the master latch are different from the identifiers corresponding to the 7th to 8th memory states. Therefore, the first non-physical page information in the original master latch DS can no longer be stored. After the non-target verification of the master latch DS, the bit line is floated during programming to release the bias latch DL to dump the first non-physical page information in the master latch DS.

[0109] In some embodiments of the present application, the peripheral circuit is further configured to: N After performing program verification on the second-to-last memory state in the 8th memory state, the N page latches are released so that the N page latches cache the program data of each of the N logical pages of the second physical page. In some embodiments, after program verification on the second-to-last memory state in the 8th memory state (i.e., the 7th memory state (LV6) has been verified), three of the page latches are released so that the three page latches cache the program data of each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 15As shown, when the programming verification of LV6 passes and DS is 1, page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the programming data of the upper page UP of the second physical page. At this time, the three page latches are released so that all the programming data of each page is stored in the three logical pages of the second physical page. At this time, page latch D1 caches the programming data of the lower page LP of the second physical page, page latch D2 caches the programming data of the middle page MP of the second physical page, and page latch DC caches the programming data of the upper page MP of the second physical page. After this, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it means that the LV7 programming verification has passed, and the data of LV0 to LV7 has been written to the selected memory cell, and the first programming is completed. At this point, the programming data of the three logical pages to be written in the second programming has been cached in the three page latches, so that the second programming process can be directly entered. If DS is 0, the program verification cannot proceed. Since the three page latches can cache the program data of each of the three logical pages (next LP, next MP, and next UP) of the second physical page after the program verification of LV6, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without the need for a data loading window.

[0110] Based on the non-volatile memory device according to some embodiments of the present application, a programming method for the non-volatile memory device is provided. The programming method includes the following steps.

[0111] Step S201: Store N logical pages of a first physical page corresponding to a current first programming in N page latches. The N page latches include (N-1) data latches in a page buffer and one cache latch coupled to a data path.

[0112] After the programming data of the three logical pages LP, MP, and UP are stored in the page latches, the programming data stored in the page latches are encoded and converted according to preset rules to obtain binary data corresponding to different memory states. More details are as follows Figure 12 shown.

[0113] Step S202: storing first non-physical page information in an offset latch in a page buffer, wherein the first non-physical page information includes verification information and program information.

[0114] Step S203: During the first programming of the first physical page, when the first to second (N-M)When the programming operation of the first memory state is completed, execute the same (N-M) If the second memory state is programmed and verified (N-M) If the programming verification of the memory state passes, the first to second memory states stored in the master latch are (N-M) The identifier corresponding to the memory state is different from the second (N-M) +1 to 2nd N an identifier corresponding to a memory state, thereby releasing at least one page latch of the N page latches to cache programming data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2); and before and during the first programming of the first physical page in the cache programming of the second physical page after the second programming of the first programming, storing the programming data of one logical page of the N logical pages of the second physical page in the released one page latch.

[0115] In the above step S203, taking TLC as an example, N=3, M=1, the first programming / second programming is performed on the first physical page / the second physical page, including using the incremental step pulse programming ISPP programming method to program the first to second physical pages. 2 Program each memory state.

[0116] In some embodiments, in the second (N-M) If the programming verification of the memory state passes, the first to second memory states stored in the master latch are switched. (N-M) The identifier corresponding to the memory state is the same as the second (N-M) +1 to 2nd N The identifiers corresponding to each memory state are different, including:

[0117] In pair 2 N After the program verification of the third to last memory state in the memory state, the master latch performs non-target verification. The non-target verification makes the first to second memory states stored in the master latch N - The identifiers corresponding to the two memory states are different from the second N -1 to 2 N The identifier corresponding to each memory state. Specifically, refer to Figure 14 After program verification of the third-to-last memory state among the eight memory states (i.e., the third-to-last memory state LV5 has been verified), the master latch DS performs non-target verification, and this non-target verification makes the identifiers corresponding to the first to sixth memory states stored in the master latch different from the identifiers corresponding to the seventh to eighth memory states. When DS is 1, it indicates that the program verification of the memory state has passed, and when DS is 0, it indicates that the program verification of the memory state has failed.

[0118] In some embodiments, after the master latch performs non-target verification, the bit line is floated during programming to dump the first non-physical page information in the master latch. Because the non-target verification performed after LV3 program verification passes, the master latch is used to distinguish between memory states that have passed program verification and memory states that have failed program verification. Therefore, the first non-physical page information originally in the master latch DS cannot be stored. After non-target verification of the master latch DS, the bit line is floated during programming to release the bias latch DL to dump the first non-physical page information in the master latch DS.

[0119] In some embodiments of the present application, N After performing program verification on a penultimate memory state in the plurality of memory states, the N page latches are released so that the N page latches cache program data for each of the N logical pages of the second physical page.

[0120] In some embodiments, after the penultimate memory state of the eighth memory state is program-verified (i.e., the seventh memory state (LV6) has been verified), three of the page latches are released so that the three page latches cache program data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. Figure 15 As shown, when the programming verification of LV6 passes, that is, DS is 1, and the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, the page latch DC is further released to cache the programming data of the upper page UP of the second physical page. At this time, the three page latches are released so that all the programming data of each page are stored in the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page MP of the second physical page. And after this, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DS is 1, it means that the LV7 programming verification has passed, and the data of LV0 to LV7 has been written into the selected storage cell, and the first programming is completed. At this time, the program data of the three logical pages to be written in the second programming has been cached in the three page latches, so that the second programming process can be directly entered. If DS is 0, the program verification determination cannot be continued.

[0121] In some embodiments, a nonvolatile memory device is also provided, the nonvolatile memory device including a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns. Each memory cell is configured to correspond to a piece of N-bit data (e.g., four-bit data). N One of the levels. The peripheral circuit is coupled to the memory cell array. The peripheral circuit is configured to: sequentially and separately perform first programming and second programming on the memory cell array on the first physical page and the second physical page in a cache programming manner; and during the first programming / second programming period, program a selected row of memory cells based on four logical pages of the first physical page / the second physical page. The four logical pages are a lower page (LP), a middle page (MP), an upper page (UP), and an extra page (XP).

[0122] The peripheral circuit includes a plurality of page buffers coupled to the bit lines respectively. Each page buffer includes a master latch DS, three data latches D1, D2, D3, and a buffer coupled to the data path latch DC. The master latch DS is configured to be able to store the first non-physical page information; the three data latches D1, D2, D3 and a cache latch DC are used for the four logical pages of the first physical page / the second physical page as four page latches, which are used to temporarily store the programming data to be written into the four logical pages during the execution of a programming. The peripheral circuit is also configured to: in the process of programming the first physical page, when the first to second (N-M) When the programming operation of the first memory state is completed, (N-M) Perform a program verification operation on the program operation corresponding to the memory state. (N-M) If the programming verification of the memory state passes, the master latch stores the first to second (N-M) The identifier corresponding to the memory state is different from the second (N-M) +1 to 2nd N An identifier corresponding to a memory state is provided, and at least one of four page latches for caching program data of at least one of four logical pages of the second physical page is released. Furthermore, during programming of the first physical page, program data of one of the four logical pages of the second physical page is stored in the released page latch.

[0123] In some embodiments, each memory cell has 16 memory states (levels) and is therefore set to 2 corresponding to a four-bit piece of data. 4 Each memory state can correspond to one of the two levels of the memory cell. 4 On the other hand, each memory state may correspond to 2 of the selected rows of memory cells to be stored.4 In some embodiments, the programming data of the logical page stored in the page latch is subjected to encoding conversion according to a preset rule to obtain codes corresponding to different memory states. Specifically, see Figure 16 , shows an example of binary encoding of a one-to-one mapping between 16 memory states (LV0 to LV15) and 16 segments after code conversion. Each segment of four-bit data can include a four-bit binary code. The four-bit binary code is derived from four logical pages respectively. The four logical pages are low page LP, middle page MP, high page UP, and extra page XP. It can be seen that the four page latches store the programming data of the four logical pages in sequence, page latch D1 stores the low page LP, page latch D2 stores the middle page MP, page latch D3 stores the high page UP, and page latch DC stores the extra page XP. After code conversion, as shown Figure 16 As shown, LV1 is encoded as 0001, where 0001 comes from LP / MP / UP / XP in sequence. Similarly, the encoding order of other memory status bits is LP / MP / UP / XP, LV2 is encoded as 1001, and so on, LV7 is encoded as 1011, LV8 is encoded as 0000, and LV15 is encoded as 1110.

[0124] In some embodiments of the present application, the peripheral circuit is configured to: N The second of the memory states N-1 Before performing program verification on the memory states, storing program data of a corresponding one of the N logical pages of the first physical page in at least one page latch of the N page latches; and N The second of the memory states N-1 After performing program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

[0125] In some embodiments, before performing programming verification on the 8th memory state LV7 among the 16 memory states, DC may store programming data of one logical page (current XP) of the four logical pages of the first physical page. D1 may store programming data of the corresponding logical page (current LP) of the first physical page, D2 may store programming data of the corresponding logical page (current MP) of the first physical page, and D3 may store programming data of the corresponding logical page (current UP) of the first physical page. And after programming verification on the 8th memory state LV7 among the 16 memory states, programming data of one logical page of the four logical pages of the second physical page is stored in four page latches. You can refer to Figure 17 to get the details.

[0126] In some embodiments of the present application, the peripheral circuit is further configured to: N The second of the memory states N-1 After the program verification of the memory state, the master latch performs non-target verification. That is, the first to second memory states stored in the master latch DS are (N-1) The identifier corresponding to the memory state is different from the second (N-1) +1 to 2nd N The identifier corresponding to each memory state. Specifically, refer to Figure 17 After program verification of the 8th memory state among the 16 memory states (i.e., the 8th memory state LV7 has been verified), the identifiers corresponding to the 1st to 8th memory states stored in the master latch DS are different from the identifiers corresponding to the 9th to 16th memory states. In other words, the identifiers of the memory states that have passed program verification in the master latch are different from the identifiers of the memory states that have not passed program verification. When DS is 1, it indicates that program verification of the memory state has passed, and when DS is 0, it indicates that program verification of the memory state has failed.

[0127] At this time, the master latch DS and page latches D1, D2, and D3 can form code 0000, code 0001, code 0010, code 0011, code 0100, code 0101, code 0110, and code 0111, which represent LV8 to LV15 respectively. In other words, after the LV3 programming verification is passed, only three page latches and the master latch DS for non-target verification are needed to distinguish the eight memory states from LV8 to LV15. Therefore, after the LV7 programming verification is passed, the page latch DC can be released to cache the programming data of the low page LP of the second physical page. The encoding state table is as follows: Figure 17 At this time, when DS is 1, it indicates that the LV7 program verification is passed, and the page latch DC can be released to cache the program data of the lower page LP of the second physical page.

[0128] Since the non-target verification after LV7 program verification passes, the master latch is used to distinguish between memory states that have passed program verification and memory states that have not passed program verification. Therefore, the first non-physical page information originally in the master latch DS cannot be stored. After the non-target verification of the master latch DS, the bit line is floated during programming to idle the bias latch, thereby dumping the first non-physical page information in the master latch DS.

[0129] In some embodiments of the present application, passing LV11 program verification means that the segments corresponding to the memory states LV0 to LV11 in the four page latches are all written. At this point, there are four memory states LV12, LV13, LV14, and LV15 that remain unprogrammed and unverified.

[0130] Since each bit of each logical page has two possible states, 0 and 1, the two page latches have four possible states (2 2 =4). In non-target verification, the unprogrammed and unverified status bits of DS are all 0, and the status bits of DS are 1 only after the program verification of the status bits passes.

[0131] At this time, the master latch DS and the page latches D2 and D3 can form code 000, code 001, code 010, and code 011, which represent LV12 to LV15 respectively. In other words, after the LV11 programming verification is passed, only two page latches and the master latch DS for non-target verification are needed to distinguish the four memory states from LV12 to LV15. Therefore, after the LV11 programming verification is passed, the page latch D1 can be released to cache the programming data of the low page LP of the second physical page. Therefore, the page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoding state table is as follows: Figure 18 shown.

[0132] Similarly, after the LV13 programming verification passes, there are still two memory states, LV14 and LV15, that have not passed the programming verification. During the non-target verification process, the unprogrammed and unverified state bits of DS are all 0, and when the programming verification passes, the state bit of DS is 1. At this time, the master latch DS and the page latch D3 can form code 00 and code 01, representing LV14 and LV15, respectively. In other words, after the LV13 programming verification passes, only one page latch D3 and the master latch DS for non-target verification are needed to distinguish between the two memory states LV14 and LV15. Therefore, after the LV13 programming verification passes, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, the page latch DC is further released to cache the programming data of the high page UP of the second physical page, and the encoding state table is as follows. Figure 19 shown.

[0133] In some embodiments of the present application, the peripheral circuit is further configured to: N After program verification of a penultimate memory state in the N memory states, the N page latches are released so that the N page latches cache program data for each of the N logical pages of the second physical page.

[0134] In some embodiments, after the second-to-last memory state of the 16 memory states is program-verified (i.e., the 15th memory state (LV14) has been verified), 4 page latches of the 10 page latches are released so that the 4 page latches cache programming data for each of the four logical pages (next LP, next MP, next UP, next XP) of the second physical page.

[0135] like Figure 20 As shown, when the program verification of LV14 passes, that is, DS is 1, the page latch D3 can be released to cache the program data of the upper page UP of the second physical page. Thus, the page latch DC is further released to cache the program data of the upper page XP of the second physical page. At this time, the four page latches are released so that all the program data of each page are stored in the four logical pages of the second physical page. At this time, the page latch D1 caches the program data of the lower page LP of the second physical page, the page latch D2 caches the program data of the middle page MP of the second physical page, the page latch D3 caches the program data of the upper page UP of the second physical page, and the page latch DC caches the program data of the extra page XP of the second physical page.

[0136] After this, whether DS is 1 can be used to determine whether LV15 has passed program verification. If DS is 1, it means that LV15 program verification has passed, and the data of LV0 to LV15 has been written to the memory cell array, and the first programming is complete. At this point, the program data of the four logical pages to be written in the second programming has been cached in the four page latches, so the second programming process can be directly entered. If DS is 0, the program verification determination cannot be continued.

[0137] In some embodiments of the present application, after the peripheral circuit included in the non-volatile memory device stores the programming data of the four logical pages in the four page latches, the programming data of the logical pages in the code are converted according to a preset rule, and the following is obtained: Figure 21 The code status table after code conversion is shown in FIG. Figure 21 As shown, the data encoding of LV1 is 0001, where 0001 comes from LP / MP / UP / XP in sequence. Similarly, the encoding order of other memory states is LP / MP / UP / XP, LV2 is encoded as 1001, and so on, LV8 is encoded as 1110, and LV15 is encoded as 1100.

[0138] In some embodiments, before performing programming verification on LV8 among the 16 memory states, DC may store programming data of one logical page (current XP) of the four logical pages of the first physical page, D1 may store programming data of the corresponding logical page (current LP) of the first physical page, D2 may store programming data of the corresponding logical page (current MP) of the first physical page, and D3 may store programming data of the corresponding logical page (current UP) of the first physical page. LV8 programming verification passed (LV8 passed) means that all the fragments corresponding to the memory states LV0 to LV8 in the four page latches are written. At this time, there are still 7 memory states LV9, LV10, LV11 to LV15, which have not been programmed and verified. Since one bit of each logical page has two possible states, 0 and 1, the three page latches have 8 possible states (2 3 =8). Excluding the code 111 that is the same as the memory state that has been programmed and verified, there are 7 codes that can represent LV9, LV10, LV11 to LV15 respectively. In other words, after LV8 programming verification is passed, only three page latches are needed to distinguish the 7 memory states of LV9, LV10, LV11 to LV15. Therefore, after LV8 programming verification is passed, the page latch DC can be released to store the programming data of the lower page LP of the second physical page in the released page latch. The encoding state table is as follows: Figure 22 shown.

[0139] Similarly, after LV12 programming verification is passed, there are still three memory states LV13, LV14, and LV15 that have not been programmed and verified. Since each bit of each logical page has two possible states, 0 and 1. The page latch can have four possible states (2 2 =4). Excluding code 11, which is the same as the memory state that has been programmed and verified, the remaining three codes 00, 01, and 10 can represent LV13, LV14, and LV15, respectively.

[0140] In other words, after LV12 programming verification is passed, only two page latches are needed to distinguish the three memory states of LV13, LV14, and LV15. Therefore, after LV12 programming verification is passed, the page latch D1 can be released, so that the released page latch D1 caches the programming data of the low page LP of the second physical page. Therefore, the page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoding state table is as follows: Figure 23 shown.

[0141] In some embodiments of the present application, the peripheral circuit is further configured to: after performing program verification on the third to last memory state in the 16 memory states, the master latch performs non-target verification. The non-target verification causes the first to second memory states stored in the master latch to be N - The identifiers corresponding to the two memory states are different from the second N -1 to 2 N The master latch DS stores identifiers corresponding to the first to fourth memory states. In some embodiments, after program verification of the third-to-last memory state among the 16 memory states (i.e., the 14th memory state (LV3) has been verified), the master latch DS performs non-target verification. The non-target verification causes the identifiers corresponding to the first to fourteenth memory states stored in the master latch to be different from the identifiers corresponding to the fifteenth to sixteenth memory states. When DS is 1, it indicates that program verification of the memory state has passed, and when DS is 0, it indicates that program verification of the memory state has failed. Figure 23 The binary encoding shown can be Figure 24 As shown in FIG5 , all data bits in LV13 can be updated to 1 because they are no longer needed in the current first programming operation. Figure 24 As shown, at this time, the master latch DS and the page latch D3 can form code 01 and code 00, indicating LV14 and LV15 respectively. In other words, only one page latch D3 and one master latch DS for performing non-target verification can distinguish between the two memory states LV14 and LV15. Therefore, after the LV13 programming verification is passed, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page. Therefore, the page latch DC caches the programming data of the upper page UP of the second physical page. That is, the next MP can be passed from DC to D2, and the programming data of the next UP can be cached in DC.

[0142] Because the non-target verification performed after LV13 verification passes, the identifiers corresponding to the 1st to 14th memory states stored in the master latch are different from the identifiers corresponding to the 15th and 16th memory states. Therefore, the first non-physical page information originally stored in the master latch DS can no longer be stored. After the master latch DS performs non-target verification, the bit line is floated during programming to release the bias latch DL and dump the first non-physical page information in the master latch DS.

[0143] In some embodiments of the present application, the peripheral circuit is further configured to: N After program verification of a penultimate memory state in the N memory states, the N page latches are released so that the N page latches cache program data for each of the N logical pages of the second physical page.

[0144] In some embodiments, after programming verification of the second-to-last memory state of the 16 memory states (i.e., the 15th memory state (LV14) has been verified), the four page latches are released so that the four page latches cache programming data for each of the four logical pages (next LP, next MP, next UP, next XP) of the second physical page.

[0145] like Figure 25 As shown in , when the program verification of LV14 passes and DS is 1, page latch D3 can be released to cache the program data of the upper page UP of the second physical page, thereby further releasing page latch DC to cache the program data of the extra page XP of the second physical page. At this time, the four page latches are released to store all the program data of the four logical pages of the second physical page. At this time, page latch D1 caches the program data of the lower page LP of the second physical page, page latch D2 caches the program data of the middle page MP of the second physical page, page latch D3 caches the program data of the upper page UP of the second physical page, and page latch DC caches the program data of the extra page XP of the second physical page.

[0146] After this, whether DS is 1 can be used to determine whether LV15 has passed program verification. If DS is 1, it indicates that LV15 program verification has passed, and the data from LV0 to LV15 has been written to the selected memory cell, and the first programming is complete. At this point, the program data for the four logical pages to be written in the second programming has been cached in the four page latches, allowing the second programming process to proceed directly. If DS is 0, the program verification determination cannot be continued.

[0147] The present disclosure also provides a nonvolatile memory device. The nonvolatile memory device includes a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to a three-bit data. 3 The peripheral circuit is configured to sequentially and separately perform first programming and second programming on the memory cell arrays of the first physical page and the second physical page in a cache programming manner, and to program a selected row of memory cells based on three logical pages of the first physical page and the second physical page during the first programming / second programming period. The three logical pages are a lower page LP, a middle page UP, and an upper page UP.

[0148] The peripheral circuit includes a plurality of page buffers, each coupled to a bit line. Each page buffer includes a main latch, a bias latch DL, (N-1) data latches, and a cache latch coupled to the data path. The bias latch is configured to store second non-physical page information. The (N-1) data latches and one cache latch are used to perform one-time programming on N logical pages of the first physical page / second physical page and temporarily store program data in the N logical pages to be written to the N page latches of the N logical pages (e.g., N=3 for TLC).

[0149] The peripheral circuitry is configured to: disable a bit line bias function to release a bias latch to replace one of the N page latches during programming of a first physical page for program verification of a memory state; and release one of the N page latches to cache program data for one of the N logical pages of a second physical page. Furthermore, during programming of the first physical page, program data for one of the N logical pages of the second physical page is stored in the released page latch. In some embodiments, the non-volatile memory device comprises a three-dimensional NAND flash memory device.

[0150] In some embodiments of the present application, the peripheral circuit is further configured to: during the process of programming the first physical page / the second physical page, use the ISPP programming method to program the first to second physical pages. (N-M) Program each memory state.

[0151] In some embodiments of the present application, the second non-physical page information includes voltage bias information of a corresponding bit line.

[0152] In some embodiments of the present application, the peripheral circuit is further configured to: N The second of the memory states N-1 Before performing program verification on the Nth memory state LV4 among the eight memory states, program data corresponding to one of the N logical pages of the first physical page is stored in at least one of the page latches. In some embodiments, before performing program verification on the fifth memory state LV4 among the eight memory states, DC may store program data of one logical page (current UP) of the three logical pages of the first physical page, D1 may store program data of the corresponding logical page (current LP) of the first physical page, and D2 may store program data of the corresponding logical page (current MP) of the second physical page.

[0153] Performs the same operation on the program data of different logical pages stored in the page latches. Figure 12 After the same encoding conversion as shown in N The second of the memory states N-1After the program verification of the +1 memory state, one of the N logical pages of the second physical page is stored in the N pages of at least one of the latches. That is, after the LV4 program verification passes, the page latch DC is released so that the released page latch caches the program data of the lower page LP of the second physical page. The encoding state table is as follows: Figure 13 shown.

[0154] In some embodiments of the present application, the peripheral circuit is further configured to: N The bit line bias function is disabled after program verification of the third to last memory state among the eight memory states. In some embodiments, the bit line bias function is disabled after program verification of the third to last memory state LV5 among the eight memory states. Figure 26 This is a coding state table after the bit line bias function is disabled, as provided in some embodiments of the present application. It can be seen that the bias latch DL is in an idle state after the bit line bias function is disabled and can be used to replace the page latch to perform program verification of the memory state. The page latch D1 can then be released to cache the program data of the lower page LP of the second physical page, thereby further releasing the page latch DC to cache the program data of the middle page MP of the second physical page.

[0155] In some embodiments of the present application, the peripheral circuitry is further configured to reduce the programming voltage step increment after disabling the bit line bias function. Since the bit line bias function itself is used to reduce the distribution width of the threshold voltage of the memory cells, after disabling the bit line bias function, the reduction in the programming voltage step increment can be used to compensate. In this way, the page latch can be replaced by a bias latch without affecting the functionality of the non-volatile memory device.

[0156] In some embodiments of the present application, the master latch DS is configured to store verification information and program information.

[0157] In some embodiments of the present application, the peripheral circuit is further configured to: N After program verification in the penultimate of the N memory states, the N page latches are released, allowing the data latches to cache each of the N logical pages of the next physical page.

[0158] In some embodiments, after the second to last memory state of the eight memory states is verified (i.e., the seventh memory state (LV6) has been verified), three of the page latches are released so that the three page latches cache the program data of each of the three logical pages (next LP, next MP, next UP) of the second physical page. The encoding state table is as follows: Figure 27As shown in the figure. After the programming verification of LV6 is passed, there is still a memory state LV7 that has not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, the latch has two possible states (2 1 =2). In other words, after LV6 program verification passes, only one bias latch DL is needed to determine whether LV7 program verification passes. Therefore, after LV6 program verification passes, page latch D2 can be released to cache the program data of the middle page MP of the second physical page, thereby further releasing page latch DC to cache the program data of the upper page UP of the second physical page.

[0159] At this time, the three page latches are released so that all the program data of each page are stored in the three logical pages of the second physical page. At this time, page latch D1 caches the program data of the lower page LP of the second physical page, page latch D2 caches the program data of the middle page MP of the second physical page, and page latch DC caches the program data of the upper page MP of the second physical page.

[0160] After this, whether DL is 1 can be used to determine whether LV7 has passed program verification. If DL is 1, it means that LV7 program verification has passed, which means that the data of LV0 to LV7 has been written to the selected memory cell and the first programming is completed. At this point, the program data of the three logical pages to be written in the second programming has been cached in the page latch, so the second programming process can be directly entered. If DL is 0, program verification has failed.

[0161] Based on the non-volatile memory device provided in the above embodiment of the present application, a programming method for the non-volatile memory device is also provided. The non-volatile memory device includes a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to an N-bit data. NOne of levels, and N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers coupled to the bit lines, respectively. The method includes: storing N logical pages of a first physical page corresponding to a current first programming in N page latches. The N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path. The second non-physical page information is stored in a bias latch in the page buffer. During the programming process of the first physical page, the bit line bias function is disabled to release the bias latch to replace one of the N page latches for memory state programming verification, and release one of the N page latches. Before the second programming of the second physical page after the first programming in the cache programming and during the first programming of the first physical page, the programming data of one logical page among the N logical pages in the page is stored in the released page latch.

[0162] Figure 28 1 is a schematic flow chart of some embodiments of a method for programming a non-volatile memory device. Figure 28 As shown, the programming method includes the following steps:

[0163] Step S301: Store N logical pages of the first physical page corresponding to the current first programming in N page latches. The N page latches include (N-1) data latches in the page buffer and a cache latch coupled to the data path. After storing the programming data of the three logical pages LP, MP, and UP in the page latches, perform encoding conversion on the page data stored in the data latches according to a preset rule to obtain binary codes corresponding to different memory states, such as Figure 12 As shown in more detail in .

[0164] In the above step S301, each memory cell is set to 2 corresponding to a three-bit data in one of the eight memory states. 3 DC can store the programming data of one of the three logical pages (current UP) of the first physical page before program verification of the fifth memory state LV4 among the eight memory states, D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. Subsequently, the program data of different logical pages temporarily stored in the page latch are compared with each other. Figure 12 And after LV4 programming verification is passed, the page latch DC is released so that the released page latch caches the programming data of the lower page LP of the second physical page. The encoding status table can be found in Figure 13 .

[0165] Step S302: storing the second non-physical page information in the bias latch in the page buffer. The second non-physical page information includes voltage bias information of the corresponding bit line.

[0166] Step S303: During programming of the first physical page, disabling a bit line bias function to release a bias latch to replace one of the N page latches to perform program verification of the memory state, and releasing one of the N page latches. Before a second physical page is programmed in a second programming of the second physical page after the first programming in the cache programming and during the first programming of the first physical page, program data of one of the N logical pages is stored in the released page latch.

[0167] In the above step S303, the first programming / second programming is performed on the first physical page / the second physical page, including using the incremental step pulse programming ISPP programming method to program the first to second physical pages. (N-M) Each memory state is programmed to perform a programming operation.

[0168] In the above step S303, disabling the bit line bias function includes: N After program verification in the third to last memory state in the memory states, the bit line bias function is disabled. Figure 26 , after program verification of the third-to-last memory state LV5 among the 8 memory states, the bit line bias function is disabled. Figure 26 This table shows the encoding state after disabling the bit line bias function, as provided in some embodiments of the present application. It can be seen that the bias latch DL is in an idle state after the bit line bias function is disabled and can be used to replace the page latch for memory state identification. Page latch D1 can then be released to cache the program data of the lower page LP of the second physical page, thereby further releasing page latch DC to cache the program data of the middle page MP of the second physical page.

[0169] In some embodiments of the present disclosure, after the bit line bias function is disabled, the programming voltage step increment is reduced. Since the bit line bias function itself is intended to reduce the distribution width of the threshold voltage of the memory cells, after the bit line bias function is disabled, the programming voltage step increment can be reduced to compensate. In this way, the page latch can be replaced by a bias latch without affecting the functionality of the non-volatile memory device.

[0170] In some embodiments of the present application, N After performing program verification on a penultimate memory state in the plurality of memory states, the N page latches are released so that the N page latches cache program data for each of the N logical pages of the second physical page.

[0171] In some embodiments, after the penultimate memory state of the eighth memory state is program-verified (i.e., the seventh memory state (LV6) has been verified), three of the page latches are released so that the three page latches cache program data for each of the three logical pages (next LP, next MP, next UP) of the second physical page. The encoding state table is as follows: Figure 27 As shown in the figure. After the programming verification of LV6 is passed, there is still a memory state LV7 that has not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, a latch has two possible states (2 1 =2).

[0172] In other words, after LV6 program verification passes, only one bias latch DL is needed to determine whether LV7 program verification passes. Therefore, after LV6 program verification passes, page latch D2 can be released to cache the program data of the middle page MP of the second physical page. Therefore, page latch DC is further released to cache the program data of the upper page UP of the second physical page.

[0173] At this time, the three page latches are released so that all the program data of each page are stored in the three logical pages of the second physical page. At this time, page latch D1 caches the program data of the lower page LP of the second physical page, page latch D2 caches the program data of the middle page MP of the second physical page, and page latch DC caches the program data of the upper page MP of the second physical page.

[0174] And then, whether DL is 1 can be used to determine whether LV7 has passed the programming verification. If DL is 1, it means that the LV7 programming verification has passed, which means that the corresponding segments of LV0 to LV7 have been written to the selected storage cells, and the first programming is completed. At this time, the programming data of the three logical pages to be written in the second programming have been cached in the page latch, so that the second programming process can be entered directly. If DL is 0, the programming verification fails. Since the three page latches can cache the programming data of each logical page of the three logical pages (next LP, next MP and next UP) of the second physical page after the programming verification of LV6. Therefore, during the first programming operation, the second physical page can be ready. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without the need for a data loading window.

[0175] In some embodiments of the present application, another non-volatile memory device is provided. After the peripheral circuit included in the non-volatile memory device stores the programming data of four logical pages in four page latches, the programming data of the logical pages stored in the page latches is encoded and converted according to a preset, thereby obtaining the following: Figure 21 The encoding status table shown.

[0176] In some embodiments of the present application, before performing programming verification on LV8 in the 16 memory states, DC can store programming data of one logical page (current XP) of the four logical pages of the first physical page, D1 can store programming data of the corresponding logical page (current LP) of the first physical page, D2 can store programming data of the corresponding logical page (current MP) of the first physical page, and D3 can store programming data of the corresponding logical page (current UP) of the first physical page. After the LV8 programming verification passes, the page latch DC is released so that the released page latch caches the programming data of the low page LP of the second physical page. The encoding state table is as follows: Figure 22 As shown. Therefore, after LV12 program verification passes, the page latch D1 is released to cache the program data of the lower page LP of the second physical page. Therefore, the page latch DC is further released to cache the program data of the middle page MP of the second physical page, and the encoding state table is as follows: Figure 23 shown.

[0177] In some embodiments of the present application, the peripheral circuit is further configured to: N The bit line bias function is disabled after program verification in the third to last memory state of the first memory state.

[0178] In some embodiments, after program verification of the third-to-last memory state LV13 among the 16 memory states, the bit line bias function is disabled to release the bias latch DL to replace one of the four page data latches in the memory for program verification of the memory state, and to release one of the four page latches to cache program data of one of the four logical pages of the second physical page. Furthermore, during programming of the first physical page, program data of one of the four logical pages of the second physical page is stored in the released page latch.

[0179] Figure 29This table shows the encoding state after disabling the bit line bias function for some embodiments of the present application. It can be seen that the bias latch DL is in an idle state after the bit line bias function is disabled and can therefore be used to replace one of the four page latches to perform program verification of the memory state. Therefore, the page latch D2 can be further released to cache the program data of the middle page MP of the second physical page. Therefore, the page latch DC is further released to cache the program data of the upper page UP of the second physical page.

[0180] In some embodiments of the present application, the peripheral circuitry is further configured to reduce the programming voltage step increment after disabling the bit line bias function. Since the bit line bias function itself is intended to reduce the distribution width of the threshold voltage of the memory cells, after disabling the bit line bias function, the programming voltage step increment can be reduced to compensate. In this way, one page latch of the data latch can be replaced by a bias latch without affecting the functionality of the non-volatile memory device.

[0181] In some embodiments of the present application, N After performing program verification on a penultimate memory state in the plurality of memory states, the N page latches are released so that the N page latches cache program data for each of the N logical pages of the second physical page.

[0182] In some embodiments, after the second-to-last memory state of the 16 memory states is program-verified (i.e., the 15th memory state (LV14) has been verified), four of the page latches are released so that the four page latches cache programming data for each of the four logical pages (next LP, next MP, next UP, next XP) of the second physical page.

[0183] The encoding status table is as follows Figure 30 As shown. After the programming verification of LV14 is passed, there is still a memory state LV15 that has not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, a latch has two possible states (2 1 =2). In other words, after LV6 program verification passes, only one bias latch DL is needed to determine whether LV7 program verification passes. Therefore, after LV14 program verification passes, page latch D3 can be released to cache the program data of the upper page UP of the second physical page. Therefore, page latch DC is further released to cache the program data of the additional page XP of the second physical page.

[0184] At this time, the four page latches are released so that all the programming data of each page can be stored in the four logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, the page latch D3 caches the programming data of the upper page UP of the second physical page, and the page latch DC caches the programming data of the extra page XP of the second physical page. And then, whether DL is 1 can be used to determine whether LV15 has passed the programming verification. If DL is 1, it means that the LV15 programming verification has passed, which means that the fragment corresponding to LV0~LV15 has been written to the selected storage cell and the first programming is completed. At this time, the programming data of the four logical pages to be written in the second programming have been cached in the four page latches, so that the second programming process can be directly entered.

[0185] If DL is 0, program verification fails, and the program verification determination continues.

[0186] Some embodiments of the present application provide a solution that can temporarily store the programming data of various logical pages required for the second programming in the page latches during the first programming operation. That is, the second physical page can be ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without the need for a data loading window.

[0187] The foregoing descriptions of specific embodiments can be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0188] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0189] Although specific configurations and arrangements are discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the present disclosure may be used in a variety of other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with each other in ways not specifically described in the accompanying drawings, so that such combinations, adjustments, and modifications are within the scope of this disclosure.

Claims

1. A storage device comprising: A memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to a piece of N-bit data N One level among N levels, where N is an integer greater than 1; and a peripheral circuit coupled to the memory cell array and configured to: performing first programming and second programming on the memory cell arrays in the first physical page and the second physical page in sequence and respectively in a cache programming manner, and During the first programming and the second programming, programming at least the selected row of the memory cells based on N logical pages of the first physical page and the second physical page, The peripheral circuit includes page buffers respectively coupled to the bit lines, each page buffer including: a master latch, (N-1) data latches, and a cache latch coupled to the data path, wherein the master latch is configured to store first non-physical page information, and the (N-1) data latches and the cache latch are configured to serve as N page latches to temporarily store programming data to be written into the N logical pages during programming of the N logical pages of the first physical page and the second physical page, Wherein, the peripheral circuit is further configured as follows: During programming of the first physical page, (N-M) performing program verification on the programming corresponding to each memory state; When the second (N-M) When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N An identifier corresponding to a memory state; releasing at least one of the N page latches to cache program data of at least one of the N logical pages of the second physical page; and In the process of programming the first physical page, the program data of one logical page of the N logical pages of the second physical page is stored in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2).

2. The storage device according to claim 1, wherein The peripheral circuit is further configured to: During programming of the first physical page and the second physical page, the memory state from the first to the second memory state is programmed using an incremental step pulse programming (ISPP) method. (N-M) Program each memory state.

3. The storage device according to claim 1, wherein The first non-physical page information includes verification information and program information. The storage device according to claim 1 , wherein: The peripheral circuit is further configured to: In the 2 N The second of the memory states N-1 After performing the program verification on the first memory state, the first memory state stored in the master latch is changed to the second memory state. (N-1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-1) +1 memory state to the 2nd N An identifier corresponding to a memory state; or In the 2 N After performing the program verification on the third to last memory state among the memory states, the first memory state stored in the master latch is changed to the second memory state. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the second N -1 memory state to the 2nd N The identifier corresponding to each memory state.

5. The storage device according to claim 4, wherein: The peripheral circuit is further configured to: In making the first memory state stored in the master latch to the second (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to the 2nd N After receiving an identifier corresponding to a memory state, the bit line is floated during the programming process to dump the first non-physical page information in the master latch. The storage device according to claim 4 , wherein: The peripheral circuit is further configured to: In the 2 N The second of the memory states N-1 Before performing program verification on a memory state, storing program data of a corresponding one of the N logical pages of the first physical page in at least one page latch of the N page latches; as well as In the 2 N The second of the memory states N-1 After performing program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

7. The storage device according to claim 6, wherein: The peripheral circuit is further configured to: In the 2 N After program-verifying a penultimate memory state among the N memory states, the N page latches are released so that the N page latches cache program data of each of the N logical pages of the second physical page. The storage device according to claim 1 , wherein Each memory cell is configured to store three bits of data; The peripheral circuit is further configured to: program the selected row of memory cells based on three logical pages of the first physical page and the second physical page; and The two data latches and the cache latch are configured to function as three page latches to temporarily store program data to be written into the three logical pages during a programming process performed on the three logical pages of the first physical page and the second physical page.

9. The storage device according to claim 1, wherein Each memory cell is configured to store four bits of data; The peripheral circuit is further configured to: program the selected row of memory cells based on four logical pages of the first physical page and the second physical page; and The three data latches and the cache latch are configured to function as four page latches to temporarily store program data to be written into the four logical pages during a programming process performed on the four logical pages of the first physical page and the second physical page.

10. The storage device according to claim 1, wherein Each page buffer further includes a bias latch configured to store voltage bias information of a corresponding bit line. The storage device according to claim 1 , wherein: Each page buffer also includes: A biased latch is coupled to the data path, wherein the biased latch is configured to store second non-physical page information.

12. The memory device of claim 1, further comprising a three-dimensional NAND flash memory device.

13. A storage device comprising: A memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to correspond to a piece of N-bit data. N One level among N levels, where N is an integer greater than 1; and a peripheral circuit coupled to the memory cell array and configured to: performing first programming and second programming on the memory cell arrays in the first physical page and the second physical page in sequence and respectively in a cache programming manner, and During the first programming and the second programming, programming at least the selected row of the memory cells based on N logical pages of the first physical page and the second physical page, The peripheral circuit includes page buffers respectively coupled to the bit lines, each page buffer including: (N-1) data latches, and a cache latch coupled to the data path, Wherein, the (N-1) data latches and the cache latch are configured as follows: In the process of programming the N logical pages of the first physical page and the second physical page, serving as N page latches to temporarily store programming data to be written into the N logical pages, Wherein, the peripheral circuit is further configured as follows: During programming of the first physical page, (N-M) +1 memory state corresponding to the program execution program verification; When the second (N-M) +1 memory state programming verification passes, releasing at least one of the N page latches to cache program data of at least one of the N logical pages of the second physical page; and In the process of programming the first physical page, the program data of one logical page of the N logical pages of the second physical page is stored in the released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N-2). The storage device according to claim 13 , wherein: Each of the page buffers further includes a master latch configured to store first non-physical page information, wherein the peripheral circuit is further configured to: In the 2 N After program verification of the third to last memory state of the first memory state, the bit line is floated during the programming process to dump the first non-physical page information in the master latch and to change the first memory state stored in the master latch to the second memory state. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the second N -1 memory state to 2nd N The identifier corresponding to each memory state.

15. The storage device according to claim 14, wherein: The peripheral circuit is further configured to: In the 2 N After performing the program verification on the second to last memory state in the memory states, the first memory state stored in the master latch is changed to the second memory state. N - an identifier corresponding to a memory state that is different from the identifier corresponding to the second N The identifier corresponding to each memory state.

16. A method for programming a memory device, wherein: The memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to 2 corresponding to a piece of N-bit data. N wherein N is an integer greater than 1; wherein the peripheral circuit includes a plurality of page buffers respectively coupled to the bit lines; and wherein the method includes: storing N logical pages of a first physical page corresponding to a current first programming in the N page latches, wherein the N page latches include (N-1) data latches in the page buffer and a cache latch coupled to a data path; storing first non-physical page information in a master latch in the page buffer; In the first programming of the first physical page, (N-M) Performing program verification during the programming process corresponding to each memory state; When the second (N-M) When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to the 2nd N An identifier corresponding to a memory state; releasing at least one of the N page latches to cache program data of at least one of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N-2); and Before performing a second programming on the second physical page in a cache programming manner, the second programming is performed after performing the first programming on the second physical page and during the first programming on the first physical page, storing the programming data of one logical page of the N logical pages of the second physical page in a released page latch.

17. The method according to claim 16, wherein Performing the first programming and the second programming on the first physical page and the second physical page includes: The first memory state is programmed to the second memory state by using an incremental step pulse programming (ISPP) method. (N-M) Program each memory state.

18. The method according to claim 16, wherein The first non-physical page information includes verification information and program information.

19. The method according to claim 16, wherein When the second (N-M) When the program verification of the first memory state passes, the first memory state stored in the master latch is changed to the second memory state. (N-M) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-M) +1 memory state to 2nd N The identifier corresponding to each memory state also includes: In the 2 N The second of the memory states N-1 After performing the program verification on the first memory state, the first memory state stored in the master latch is changed to the second memory state. (N-1) The identifier corresponding to the memory state is different from the identifier corresponding to the second (N-1) +1 memory state to 2nd N an identifier corresponding to a memory state; or In the 2 N After performing program verification on the third to last memory state among the memory states, the first memory state stored in the master latch is changed to the second memory state. N - The identifier corresponding to the two memory states is different from the identifier corresponding to the second N -1 memory state to 2nd N The identifier corresponding to each memory state.

20. The method according to claim 19, wherein In making the first memory state stored in the master latch to the second (N-M) The identifier corresponding to the first memory state is different from the identifier corresponding to the second memory state (N-M) +1 memory state to 2nd N After the identifier corresponding to the memory state, the method further includes: The bit line is floated during the programming process to dump the first non-physical page information in the master latch.

21. The method according to claim 20, further comprising: In pair 2 N The second of the memory states N-1 Before performing the program verification for each memory state, storing program data of one logical page of the N logical pages of the first physical page in at least one page latch of the N page latches; as well as In pair 2 N The second of the memory states N-1 After performing the program verification for each memory state, program data of one logical page of the N logical pages of the second physical page is stored in at least one page latch of the N page latches.

22. The method according to claim 21, further comprising: In the 2 N After performing program verification on a third-to-last memory state in the N memory states, the N page latches are released so that the N page latches cache program data of each of the N logical pages of the second physical page.

Images