Erase operations in memory devices

Abstract

Example memory devices, systems, and methods for reducing erase interference in memory devices are disclosed. An exemplary method includes, during an erase operation of a block in a memory cell array, erasing one or more memory cells in the block. During an erase operation of the block, it is verified whether the one or more memory cells are erased. During an erase operation of the block, each of the one or more blocks in the memory cell array is respectively read, where the respective reading of each of the one or more blocks includes: applying a first voltage to a first select gate line coupled to a first select gate transistor in the block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, where the first voltage is lower than the second voltage.

Description

Technical Field

[0001] The present disclosure relates to a memory device, a system, and a method for erase operations in a memory device. Background Art

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as programming (writing) and erasing operations, to change the threshold voltage of each memory cell to a corresponding level. For NAND flash memory, the erase operation can be performed at the block level. Summary of the Invention

[0003] The present disclosure relates to a memory device, a system, and a method for erase operations in a memory device.

[0004] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: during an erase operation on a target block in a memory cell array, erasing one or more memory cells in a target block. During the erase operation on the target block, verifying whether the one or more memory cells are erased. During the erase operation on the target block, separately reading each of the one or more blocks in the memory cell array, wherein separately reading each of the one or more blocks includes: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

[0005] The method may include one or more of the following features.

[0006] In some embodiments, the one or more blocks include a first block adjacent to the target block and a second block adjacent to the target block, wherein the first block and the second block are located on two opposite sides of the target block.

[0007] In some embodiments, the one or more blocks include a third block adjacent to the first block and a fourth block adjacent to the second block.

[0008] In some embodiments, separately reading each of the one or more blocks includes: reading a first block and a second block, including: applying a second voltage to a select gate line coupled to a select gate transistor in the first block during a period in which a first voltage is applied to a first select gate line coupled to a first select gate transistor in a target block; and applying a second voltage to a select gate line coupled to a select gate transistor in the second block.

[0009] In some embodiments, separately reading each of the one or more blocks in the memory cell array includes: reading a first block, including: applying a third voltage to a word line coupled to at least one memory cell in the first block, wherein the third voltage is higher than a voltage of a word line coupled to at least one memory cell in the second block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the second block; and applying a second voltage to a select gate line coupled to at least one select gate transistor in the first block, wherein the second voltage is higher than the fourth voltage.

[0010] In some embodiments, separately reading each of the one or more blocks in the memory cell array further includes: after reading the first block, reading the second block, including: applying a third voltage to a word line coupled to at least one memory cell in the second block, wherein the third voltage is higher than a voltage of the word line coupled to at least one memory cell in the first block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the first block; and applying the second voltage to a select gate line coupled to at least one select gate transistor in the second block.

[0011] In some embodiments, reading the first block further includes applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the target block, wherein the fourth voltage is lower than the third voltage.

[0012] In some embodiments, the third voltage ranges from 1.8V to 3.8V, and the second voltage ranges from 2.2V to 3.5V.

[0013] In some embodiments, after erasing one or more memory cells in a target block and before respectively reading each of the one or more blocks, a fifth voltage is applied to a select gate line coupled to at least one select gate transistor in a memory cell array, and a sixth voltage is applied to a word line coupled to at least one memory cell in the memory cell array, wherein the fifth voltage is lower than the sixth voltage.

[0014] In some embodiments, separately reading each of the one or more blocks includes separately reading each of the one or more blocks after erasing one or more memory cells in the target block and during the erase operation on the target block.

[0015] Certain aspects of the subject matter described herein can be implemented as a memory device. The memory device includes: a memory cell array; and peripheral circuitry coupled to the memory cell array and configured to perform an operation, the operation comprising: erasing one or more memory cells in a target block during an erase operation on the target block. During the erase operation on the target block, verifying whether the one or more memory cells are erased. During the erase operation on the target block, separately reading each of the one or more blocks in the memory cell array, wherein separately reading each of the one or more blocks includes: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

[0016] The memory device may include one or more of the following features.

[0017] In some embodiments, the one or more blocks include a first block adjacent to the target block and a second block adjacent to the target block, wherein the first block and the second block are located on two opposite sides of the target block.

[0018] In some embodiments, the one or more blocks include a third block adjacent to the first block and a fourth block adjacent to the second block.

[0019] In some embodiments, separately reading each of the one or more blocks includes: reading a first block and a second block, including: applying a second voltage to a select gate line coupled to a select gate transistor in the first block during a period in which a first voltage is applied to a first select gate line coupled to a first select gate transistor in a target block; and applying a second voltage to a select gate line coupled to a select gate transistor in the second block.

[0020] In some embodiments, separately reading each of the one or more blocks in the memory cell array includes: reading a first block, including: applying a third voltage to a word line coupled to at least one memory cell in the first block, wherein the third voltage is higher than a voltage of a word line coupled to at least one memory cell in the second block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the second block; and applying a second voltage to a select gate line coupled to at least one select gate transistor in the first block, wherein the second voltage is higher than the fourth voltage.

[0021] In some embodiments, separately reading each of the one or more blocks in the memory cell array further includes: after reading the first block, reading the second block, including: applying a third voltage to a word line coupled to at least one memory cell in the second block, wherein the third voltage is higher than a voltage of the word line coupled to at least one memory cell in the first block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the first block; and applying the second voltage to a select gate line coupled to at least one select gate transistor in the second block.

[0022] In some embodiments, reading the first block further includes applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the target block, wherein the fourth voltage is lower than the third voltage.

[0023] In some embodiments, the third voltage ranges from 1.8V to 3.8V, and the second voltage ranges from 2.2V to 3.5V.

[0024] In some embodiments, after erasing one or more memory cells in a target block and before respectively reading each of the one or more blocks, a fifth voltage is applied to a select gate line coupled to at least one select gate transistor in a memory cell array, and a sixth voltage is applied to a word line coupled to at least one memory cell in the memory cell array, wherein the fifth voltage is lower than the sixth voltage.

[0025] In some embodiments, separately reading each of the one or more blocks includes separately reading each of the one or more blocks after erasing one or more memory cells in the target block and during the erase operation on the target block.

[0026] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system includes: a memory device; and a controller coupled to the memory device and configured to initiate an operation. The memory device includes: a memory cell array; and peripheral circuitry coupled to the memory cell array and configured to perform an operation, the operation including: during an erase operation on a target block in the memory cell array, erasing one or more memory cells in a target block. During the erase operation on the target block, verifying whether the one or more memory cells are erased. During the erase operation on the target block, reading each of the one or more blocks in the memory cell array separately, wherein reading each of the one or more blocks separately includes: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

[0027] The memory system may include one or more of the following features.

[0028] In some embodiments, the one or more blocks include a first block adjacent to the target block and a second block adjacent to the target block, wherein the first block and the second block are located on two opposite sides of the target block.

[0029] In some embodiments, the one or more blocks include a third block adjacent to the first block and a fourth block adjacent to the second block.

[0030] In some embodiments, separately reading each of the one or more blocks includes: reading a first block and a second block, including: applying a second voltage to a select gate line coupled to a select gate transistor in the first block during a period in which a first voltage is applied to a first select gate line coupled to a first select gate transistor in a target block; and applying a second voltage to a select gate line coupled to a select gate transistor in the second block.

[0031] In some embodiments, separately reading each of the one or more blocks in the memory cell array includes: reading a first block, including: applying a third voltage to a word line coupled to at least one memory cell in the first block, wherein the third voltage is higher than a voltage of a word line coupled to at least one memory cell in the second block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the second block; and applying a second voltage to a select gate line coupled to at least one select gate transistor in the first block, wherein the second voltage is higher than the fourth voltage.

[0032] In some embodiments, separately reading each of the one or more blocks in the memory cell array further includes: after reading the first block, reading the second block, including: applying a third voltage to a word line coupled to at least one memory cell in the second block, wherein the third voltage is higher than a voltage of the word line coupled to at least one memory cell in the first block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the first block; and applying the second voltage to a select gate line coupled to at least one select gate transistor in the second block.

[0033] In some embodiments, reading the first block further includes applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the target block, wherein the fourth voltage is lower than the third voltage.

[0034] In some embodiments, the third voltage ranges from 1.8V to 3.8V, and the second voltage ranges from 2.2V to 3.5V.

[0035] In some embodiments, after erasing one or more memory cells in a target block and before respectively reading each of the one or more blocks, a fifth voltage is applied to a select gate line coupled to at least one select gate transistor in a memory cell array, and a sixth voltage is applied to a word line coupled to at least one memory cell in the memory cell array, wherein the fifth voltage is lower than the sixth voltage.

[0036] In some embodiments, separately reading each of the one or more blocks includes separately reading each of the one or more blocks after erasing one or more memory cells in the target block and during the erase operation on the target block.

[0037] These and other aspects of the disclosure and details of implementations are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 An example of a schematic circuit diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0039] Figure 2 An example of a side view of a cross-section of a memory cell array including NAND memory strings is shown, according to some aspects of the present disclosure.

[0040] Figure 3 An example of interaction between a host and a device according to some aspects of the present disclosure is shown.

[0041] Figure 4A and Figure 4B Exemplary voltages of components in a memory cell array during an erase operation of a block of memory cells in the memory cell array according to some aspects of the present disclosure are shown.

[0042] Figure 5 Another example of voltages of components in a memory cell array during an erase operation of a block of memory cells in the memory cell array is shown in accordance with aspects of the present disclosure.

[0043] Figure 6 An example of a flowchart of a method for reducing erase disturb in a memory device according to some aspects of the present disclosure is shown.

[0044] Figure 7 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0045] Figure 8AA diagram of a memory card having a memory device according to some aspects of the present disclosure is shown.

[0046] Figure 8B A diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0047] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0048] This specification relates to memory devices, systems, and methods for reducing erase disturbance in memory devices. In some cases, when erasing a memory cell block in a memory cell array, the channel hole potential of the memory cell block cannot be fully discharged. Then, during subsequent erase cycles of the memory cell block, the channel hole potential of the memory cell block will continue to accumulate. Due to the coupling effect between adjacent memory cell blocks, the adjacent blocks in the erased memory cell block will have increased channel hole potential, which may cause an increased voltage difference between the channel and the word line in the adjacent block. These increased voltage differences may cause soft erasure of the adjacent blocks. In order to reduce the above-mentioned erase disturbance, after erasing the memory cell block and verifying the erase, additional read operations can be performed on the adjacent blocks in the memory cell block. These additional read operations can turn on the select gate line of the adjacent block and thereby discharge the channel hole potential in the adjacent block and reduce the erase disturbance in the adjacent block.

[0049] Embodiments of the present disclosure can provide one or more of the following technical effects. For example, the channel hole potential in adjacent blocks of an erased block can be reduced. Consequently, erase interference in adjacent blocks due to block-to-block coupling effects can be reduced, and soft erase in adjacent blocks can be mitigated. Furthermore, the time required to perform additional read operations on adjacent blocks can have a low impact on the performance of the memory device, while the reliability of the memory device can be significantly improved.

[0050] Figure 1An example of a schematic circuit diagram of a memory device 100 including peripheral circuitry according to some aspects of the present disclosure is shown. The memory device 100 may include a memory cell array 101 and peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array in which the memory cells 106 are provided in the form of an array of NAND memory strings 108, each NAND memory string extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be a floating gate type memory cell including a floating gate transistor or a charge trapping type memory cell including a charge trapping transistor.

[0051] In some embodiments, each memory cell 106 is a single-level cell (SLC) having two possible storage states and therefore capable of storing one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 106 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to achieve a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to achieve one of three possible programming levels from an erased state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0052] like Figure 1As shown, each NAND memory string 108 can include a source select gate (SSG) 110 located at its source terminal and a drain select gate (DSG) 112 located at its drain terminal. The SSG 110 and DSG 112 can be configured to activate a selected NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 108 located in the same block 104 are coupled via the same source line (SL) 114 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 108 located in the same block 104 have an array common source (ACS). According to some embodiments, the DSG 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 108 is configured to be selected or deselected by applying a select voltage or a deselect voltage (e.g., 0V) to a corresponding DSG 112 through one or more DSG lines 113 and / or by applying a select voltage or a deselect voltage (e.g., 0V) to a corresponding SSG 110 through one or more SSG lines 115.

[0053] like Figure 1 As shown, a NAND memory string 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114 (e.g., coupled to an ACS). In some embodiments, each block 104 is a basic data unit for erase operations, i.e., all memory cells 106 located on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and unselected blocks 104 in the same plane as the selected block 104 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). In some examples, erase operations can be performed at the half-block level, the quarter-block level, or any suitable number of blocks or any suitable fraction of a block. Memory cells 106 of adjacent NAND memory strings can be coupled by word lines 118, which select which row of memory cells 106 is affected by read and program operations. Each word line 118 may include a plurality of control gates (gate electrodes) at each memory cell 106 and a gate line coupling the control gates. Figure 1 The exemplary word lines (WL) shown in illustrative figures include dummy WLs, WL1 , WL2 , WL3 , WL4 , and WL5 , located between one or more DSG lines 113 and one or more SSG lines 115 .

[0054] Figure 21 shows an example of a side view of a cross section of a memory cell array 101 including NAND memory strings 108 according to some aspects of the present disclosure. Figure 2 As shown, the NAND memory strings 108 can extend vertically through a memory stack 204 above a substrate 202. The substrate 202 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0055] The memory stack 204 may include interleaved gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of gate conductive layer 206 and gate-to-gate dielectric layer 208 pairs in the memory stack 204 may determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate, DSG 112, or SSG 110 surrounding the memory cell 106 and may extend laterally as a DSG line 113 at the top of the memory stack 204, extend laterally as an SSG line 115 at the bottom of the memory stack 204, or extend laterally between the DSG line 113 and the SSG line 115 as a word line 118.

[0056] The peripheral circuit 102 is coupled to the memory cell array 101 via the bit lines 116, the word lines 118, the source lines 114, the SSG lines 115, and the DSG lines 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed signal circuitry for facilitating the operation of the memory cell array 101 by applying a voltage signal and / or a current signal to and sensing a voltage signal and / or a current signal from each target memory cell in the memory cells 106 via the bit lines 116, the word lines 118, the source lines 114, the SSG lines 115, and the DSG lines 113. The peripheral circuit 102 may include various types of peripheral circuitry formed using metal oxide semiconductor (MOS) technology. For example, Figure 3Some exemplary peripheral circuits according to some aspects of the present disclosure are shown. The exemplary peripheral circuits include page buffers / sense amplifiers 304, column decoders / bit line drivers 306, row decoders / word line drivers 308, voltage generators 310, control logic units 312, registers 314, interfaces 316, and data buses. In some examples, the peripheral circuits may also include Figure 3 No additional peripheral circuits are shown.

[0057] The page buffer / sense amplifier 304 can be configured to read data from the memory cell array 101 and program (write) data to the memory cell array 101 according to control signals from the control logic unit 312. In one example, the page buffer / sense amplifier 304 can store a page of program data (write data) to be programmed into one page of the memory cell array 101. In another example, the page buffer / sense amplifier 304 can perform a program verification operation to ensure that the data has been properly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 can also sense a low-power signal from the bit line 116 representing the data bit stored in the memory cell 106 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 306 can be configured to be controlled by the control logic unit 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from the voltage generator 310.

[0058] The row decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and to select / deselect the block 104 of the memory cell array 101 and to select / deselect the word line 118 of the block 104. The row decoder / word line driver 308 can also be configured to drive the word line 118 using the word line voltage generated from the voltage generator 310. In some embodiments, the row decoder / word line driver 308 can also select / deselect and drive the SSG line 115 and the DSG line 113. The row decoder / word line driver 308 can be configured to apply a read voltage to the selected word line 118 in a read operation of the memory cell 106 coupled to the selected word line 118.

[0059] The voltage generator 310 may be configured to be controlled by the control logic unit 312 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to supply to the memory cell array 101 .

[0060] The control logic unit 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The register 314 may be coupled to the control logic unit 312 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The status register of the register 314 may include one or more registers configured to store open block information indicating open blocks in all blocks 104 in the memory cell array 101 (e.g., having an automatic dynamic start voltage (ADSV) list). In some embodiments, the open block information also indicates the last programmed page of each open block.

[0061] The interface 316 can be coupled to the control logic unit 312 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 312, as well as buffer status information received from the control logic unit 312 and relay it to the host. The interface 316 can also be coupled to the column decoder / bit line driver 306 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data from and to the memory cell array 101.

[0062] Figure 4A and Figure 4B 4 shows exemplary voltages of components in a memory cell array during an erase operation 400 of a block of memory cells in the memory cell array according to some aspects of the present disclosure. Figure 4A and Figure 4B As shown, an erase operation 400 is performed on a memory cell block BLKn (e.g., a target block). Memory cell blocks BLKn-1 (e.g., a first block) and BLKn+1 (e.g., a second block) are two blocks adjacent to BLKn and located on opposite sides of BLKn. Memory block BLKn-2 (e.g., a third block) is adjacent to BLKn-1, and memory block BLKn+2 (e.g., a fourth block) is adjacent to BLKn+1. Each of BLKn-2, BLKn-1, BLKn, BLKn+1, and BLKn+2 may be Figure 1 An example of block 104 in FIG.

[0063] like Figure 4A and Figure 4BAs shown, the erase operation 400 of BLKn can include two phases, namely, a BLKn erase and verify phase 402, followed by a dummy read phase 424. In some embodiments, the BLKn erase and verify phase 402 can be performed to erase BLKn. The dummy read phase 424 can then be performed to discharge the channel hole potential accumulated during the BLKn erase and verify phase 402 in blocks proximate to BLKn and thereby mitigate the issue of soft erase of blocks proximate to BLKn (e.g., BLKn-2, BLKn-1, BLKn+1, and / or BLKn+2).

[0064] like Figure 4B As shown, the virtual read phase 424 may include read operations 426, 428, 430, and 432, which are sequentially performed on BLKn-2, BLKn-1, BLKn+1, and BLKn+2, respectively. In some embodiments, the order of the four read operations 426, 428, 430, and 432 in the virtual read phase 424 may be rearranged. In some embodiments, the read operations within the virtual read phase 424 may be performed on more than four memory cell blocks proximate to BLKn. In some embodiments, the read operations within the virtual read phase 424 may be performed on a subset of the four memory cell blocks BLKn-1, BLKn+1, BLKn-2, and BLKn+2.

[0065] like Figure 4A As shown, the BLKn erase and verify phase 402 may include a pre-programming phase 404, a pre-discharge phase 406, an erase pulse phase 408, an erase verify phase 410, and a recharge phase 412. In some embodiments, during the recharge phase 412, a voltage such as Vcc (e.g., the sixth voltage) may be applied to one or more word lines coupled to memory cells in the memory cell array, and a voltage such as Vss (e.g., the fifth voltage) may be applied to one or more select gate lines coupled to select gate transistors in the memory cells to turn off these select gate lines. In some cases, Vss may be lower than Vcc. An exemplary value for Vcc is 2.5V. An exemplary value for Vss is 0V.

[0066] In some embodiments, during the dummy read phase 424, the voltage of the word line 414 coupled to the memory cells in BLKn can be floating. In some cases, the word line 414 can be Figure 1 Example of word line 118 in FIG.

[0067] In some embodiments, during the dummy read phase 424, a voltage 466 (e.g., a first voltage), such as Vss, can be applied to a select gate line 416 (e.g., a first select gate line) coupled to one or more select gate transistors (e.g., a first select gate transistor) of BLKn to turn off the one or more select gate transistors of BLKn. In some cases, the select gate line 416 can be a top select gate (TSG) line, such as Figure 1 In some cases, the select gate line 416 may be a bottom select gate (BSG) line, e.g., Figure 1 SSG line 115 in.

[0068] In some embodiments, after performing the BLKn erase and verify phase 402, a read operation 426 on BLKn-2 can first be performed within a dummy read phase 424. For example, at time t1, a voltage 438 (e.g., a second voltage) such as Vbiashv can be applied to a select gate line (e.g., a second select gate line) coupled to one or more select gate transistors (e.g., a second select gate transistor) of BLKn-2 to turn on the one or more select gate transistors in BLKn-2 so that the channel hole potential of BLKn-2 can be reduced. In some cases, the select gate line can be a top select gate (TSG) line, such as, Figure 1 In some cases, the select gate line may be a bottom select gate (BSG) line, e.g., Figure 1 An exemplary range of voltage 438 may be between 2.2V and 3.5V.

[0069] In some embodiments, during the read operation 426, a voltage 440 (e.g., a fourth voltage), such as Vss, can be applied to a select gate line coupled to one or more select gate transistors of a memory cell block other than BLKn-2 (e.g., the second block) to turn off the one or more select gate transistors of the block.

[0070] In some embodiments, during the read operation 426 and at or after time t1, a voltage 434, such as Vbias, can be applied to the word line coupled to the memory cell of BLKn-2 to save time setting up the word line. In some cases, the word line can be Figure 1 An example of word line 118 in FIG. An exemplary range of voltage 434 may be between 1.8V and 3.8V.

[0071] In some implementations, during the read operation 426, the voltage 436 of the word lines coupled to the memory cells in blocks other than BLKn-2 can be floating.

[0072] In some embodiments, after performing the read operation 426, a read operation 428 can be performed on BLKn-1 in a dummy read phase 424. For example, at time t2, a voltage 446, such as Vbiashv, can be applied to a select gate line coupled to one or more select gate transistors of BLKn-1 to turn on the one or more select gate transistors of BLKn-1 so that the channel hole potential of BLKn-1 can be reduced. In some cases, the select gate line can be a top select gate (TSG) line, such as, Figure 1 In some cases, the select gate line may be a bottom select gate (BSG) line, e.g., Figure 1 An exemplary range of voltage 446 may be between 2.2V and 3.5V.

[0073] In some implementations, during read operation 428, a voltage 448, such as Vss, can be applied to a select gate line coupled to one or more select gate transistors of a memory cell block other than BLKn-1 to turn off the one or more select gate transistors of that block.

[0074] In some embodiments, during the read operation 428 and at or after time t2, a voltage 442 (e.g., a third voltage), such as Vbias, can be applied to the word line of the memory cell coupled to BLKn-1 to save time setting up the word line. In some cases, the word line can be Figure 1 An example of word line 118 in FIG. An exemplary range of voltage 442 may be between 1.8V and 3.8V.

[0075] In some implementations, during the read operation 428, the voltage 444 of the word lines coupled to the memory cells in blocks other than BLKn-1 can be floating.

[0076] In some embodiments, after performing the read operation 428, a read operation 430 can be performed on BLKn+1 in a dummy read phase 424. For example, at time t3, a voltage 454, such as Vbiashv, can be applied to a select gate line coupled to one or more select gate transistors of BLKn+1 to turn on the one or more select gate transistors of BLKn+1 so that the channel hole potential of BLKn+1 can be reduced. In some cases, the select gate line can be a top select gate (TSG) line, such as, Figure 1 In some cases, the select gate line may be a bottom select gate (BSG) line, e.g., Figure 1An exemplary range of voltage 454 may be between 2.2V and 3.5V.

[0077] In some implementations, during read operation 430, a voltage 456, such as Vss, can be applied to a select gate line coupled to one or more select gate transistors of a memory cell block other than BLKn+1 to turn off the one or more select gate transistors of that block.

[0078] In some embodiments, during the read operation 430 and at or after time t3, a voltage 450, such as Vbias, can be applied to the word line coupled to the memory cell of BLKn+1 to save time setting up the word line. In some cases, the word line can be Figure 1 An example of word line 118 in FIG. An exemplary range of voltage 450 may be between 1.8V and 3.8V.

[0079] In some implementations, during the read operation 430 , the voltage 452 of the word lines coupled to the memory cells in blocks other than BLKn+1 can be floating.

[0080] In some embodiments, after performing the read operation 430, a read operation 432 for BLKn+2 can be subsequently performed within a dummy read phase 424. For example, at time t4, a voltage 462, such as Vbiashv, can be applied to a select gate line coupled to one or more select gate transistors of BLKn+2 to turn on the one or more select gate transistors of BLKn+2 so that the channel hole potential of BLKn+2 can be reduced. In some cases, the select gate line can be a top select gate (TSG) line, such as, Figure 1 In some cases, the select gate line may be a bottom select gate (BSG) line, e.g., Figure 1 An exemplary range of voltage 462 may be between 2.2V and 3.5V.

[0081] In some implementations, during read operation 432, a voltage 464, such as Vss, can be applied to a select gate line coupled to one or more select gate transistors of a memory cell block other than BLKn+2 to turn off the one or more select gate transistors of that block.

[0082] In some embodiments, during the read operation 432 and at or after time t4, a voltage 458, such as Vbias, can be applied to the word line coupled to the memory cell of BLKn+2 to save time setting up the word line. In some cases, the word line can be Figure 1An example of word line 118 in FIG. An exemplary range of voltage 458 may be between 1.8V and 3.8V.

[0083] In some implementations, during the read operation 432, the voltage 460 of the word lines coupled to the memory cells in blocks other than BLKn+2 can be floating.

[0084] Figure 5 An example of voltages of components in a memory cell array during an erase operation 500 of a memory cell block in the memory cell array according to some aspects of the present disclosure is shown. Similar to the erase operation 400, the erase operation 500 is also performed on a memory cell block BLKn (eg, a target block). Figure 5 The erase operation 500 in Figure 4A and Figure 4B The difference between the erase operation 400 in FIG. 4 is the read operation performed after the BLKn erase and verify phase 402. Unlike the erase operation 400 in which read operations 426, 428, 430, and 432 are performed sequentially on BLKn-2, BLKn-1, BLKn+1, and BLKn+2, respectively, in the erase operation 500, read operations 526, 528, 530, and 532 are performed simultaneously on BLKn-2, BLKn-1, BLKn+1, and BLKn+2, respectively, during the dummy read phase 524.

[0085] In some implementations, during the dummy read phase 524, the voltage of the word line 414 coupled to the memory cells in BLKn can be floating.

[0086] In some implementations, during the dummy read phase 524, a voltage 466, eg, Vss, can be applied to the select gate line 416 coupled to one or more select gate transistors of BLKn to turn off the one or more select gate transistors of BLKn.

[0087] like Figure 5 As shown, the dummy read phase 524 can include read operations 526, 528, 530, and 532 that are performed simultaneously on BLKn-2, BLKn-1, BLKn+1, and BLKn+2, respectively. In some embodiments, the read operations within the dummy read phase 524 can be performed on more than four memory cell blocks proximate to BLKn. In some embodiments, the read operations within the dummy read phase 524 can be performed on a subset of the four memory cell blocks BLKn-1, BLKn+1, BLKn-2, and BLKn+2.

[0088] In some embodiments, after performing the BLKn erase and verify phase 402, read operations 526, 528, 530, and 532 can be simultaneously performed on BLKn-2, BLKn-1, BLKn+1, and BLKn+2, respectively, during a dummy read phase 524. For example, at time t1, a voltage 538, such as Vbiashv, can be applied to respective select gate lines coupled to one or more select gate transistors of each of BLKn-2, BLKn-1, BLKn+1, and BLKn+2 to turn on the one or more select gate transistors so that the respective channel hole potential of each of BLKn-2, BLKn-1, BLKn+1, and BLKn+2 can be reduced.

[0089] In some embodiments, during the dummy read phase 524, a voltage 540, e.g., Vss, can be applied to a select gate line coupled to one or more select gate transistors of a memory cell block other than BLKn-2, BLKn-1, BLKn, BLKn+1, and BLKn+2 to turn off the one or more select gate transistors of the block.

[0090] In some embodiments, during the dummy read phase 524 and at or after time t1, a voltage 534, such as Vbias, can be applied to the corresponding word lines coupled to the memory cells BLKn-2, BLKn-1, BLKn+1, and BLKn+2 to save time in setting up the corresponding word lines.

[0091] In some implementations, during the dummy read phase 524, the voltages 536 of the word lines coupled to memory cells in blocks other than BLKn-2, BLKn-1, BLKn, BLKn+1, and BLKn+2 may be floating.

[0092] Figure 6 An example 600 of a flow chart of a method for reducing erase disturb in a memory device according to some aspects of the present disclosure is shown. At 602, peripheral circuitry of a memory device erases one or more memory cells in a target block in a memory cell array during an erase operation on the target block.

[0093] At 604, the peripheral circuitry verifies whether one or more memory cells are erased during an erase operation on a target block.

[0094] At 606, the peripheral circuitry separately reads each of the one or more blocks in the memory cell array during an erase operation on the target block, wherein separately reading each of the one or more blocks includes: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

[0095] Figure 7 A block diagram of an exemplary system 700 having a memory device according to some aspects of the present disclosure is shown. System 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game controller, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 7 As shown, system 700 may include a host 708 and a memory system 702 having one or more memory devices 704 and a memory controller 706. Host 708 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 708 may be configured to send data to or receive data from memory device 704.

[0096] Memory device 704 can be any memory device disclosed in this disclosure. According to some embodiments, memory controller 706 is coupled to memory device 704 and host 708 and is configured to control memory device 704. Memory controller 706 can manage data stored in memory device 704 and communicate with host 708. In some embodiments, memory controller 706 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 706 is designed to operate in a high duty cycle environment, such as an SSD or an embedded MultiMediaCard (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. Memory controller 706 can be configured to control operations of memory device 704 (e.g., read operations, erase operations, and program operations). The memory controller 706 may also be configured to manage various functions regarding data stored or to be stored in the memory device 704, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 may also be configured to process error correction code (ECC) on data read from or written to the memory device 704. The memory controller 706 may also perform any other suitable functions, such as formatting the memory device 704.

[0097] The memory controller 706 may communicate with an external device (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0098] The memory controller 706 and the one or more memory devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of terminal electronic products. Figure 8AIn one example shown in FIG, the memory controller 706 and the single memory device 704 may be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a host computer (e.g., Figure 7 The memory card connector 804 is coupled to the host 708 in the memory card connector. Figure 8B In another example shown in FIG, the memory controller 706 and the plurality of memory devices 704 may be integrated into an SSD 806. The SSD 806 may also include a processor that interfaces the SSD 806 with a host (e.g., Figure 7 In some embodiments, the storage capacity and / or operating speed of the SSD 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0099] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims, but rather as descriptions of features that may be directed to specific embodiments. In the context of separate embodiments, certain features described in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any sub-combination in multiple embodiments. In addition, although the aforementioned features may be described as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variant of the sub-combination.

[0100] As used in this disclosure, unless the context clearly indicates otherwise, the terms "a" or "the" are used to include one or more than one. Unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure but not otherwise defined are used for descriptive purposes only and not for limiting purposes. Any use of section headings is intended to aid reading of this document and should not be construed as limiting; information related to the section heading may appear within or outside that particular section.

[0101] As used in this disclosure, the terms "about" or "approximately" can allow for a degree of variability in values ​​or ranges, for example, within 10%, within 5%, or within 1% of the stated value or limits of the stated range.

[0102] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or greater.

[0103] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly cited as limits of the range, but also all individual values ​​or subranges encompassed within the range, as if each value and subrange were explicitly cited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, and also include individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the range shown. Unless otherwise indicated, the statement "X to Y" has the same meaning as "about X to about Y." Similarly, unless otherwise indicated, the statement "X, Y, or Z" has the same meaning as "about X, about Y, or about Z."

[0104] Specific embodiments of the subject matter have been described. As will be apparent to those skilled in the art, other embodiments, alternatives, and permutations of the described embodiments are within the scope of the following claims. Although operations are described in a particular order in the drawings and claims, it is not required that the operations be performed in the particular order shown, or in a sequential order, or that all illustrated operations be performed (some operations may be considered optional) in order to achieve the desired results. In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and may be performed as deemed appropriate.

[0105] Furthermore, the separation or integration of the various system modules and components in the previously described embodiments is not required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0106] Therefore, the exemplary embodiments described above do not define or limit the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: during an erase operation on a target block in a memory cell array, erasing one or more memory cells in the target block; during the erase operation on the target block, verifying whether the one or more memory cells are erased; as well as During the erase operation on the target block, reading each of the one or more blocks in the memory cell array separately, wherein reading each of the one or more blocks separately comprises: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and A second voltage is applied to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

2. The method according to claim 1, wherein The one or more blocks include a first block adjacent to the target block and a second block adjacent to the target block, wherein the first block and the second block are located on two opposite sides of the target block.

3. The method according to claim 2, wherein: The one or more blocks include a third block adjacent to the first block and a fourth block adjacent to the second block.

4. The method according to claim 2 or 3, wherein: Reading each of the one or more blocks separately includes: Reading the first block and the second block includes: During a period in which the first voltage is applied to the first select gate line coupled to the first select gate transistor in the target block: applying the second voltage to a select gate line coupled to a select gate transistor in the first block; and The second voltage is applied to a select gate line coupled to select gate transistors in the second block.

5. The method according to any one of claims 2 to 4, wherein: Reading each of the one or more blocks in the memory cell array separately includes: Reading the first block, comprising: applying a third voltage to a word line coupled to at least one memory cell in the first block, wherein the third voltage is higher than a voltage of a word line coupled to at least one memory cell in the second block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the second block; and The second voltage is applied to a select gate line coupled to at least one select gate transistor in the first block, wherein the second voltage is higher than the fourth voltage.

6. The method according to claim 5, wherein: Reading each of the one or more blocks in the memory cell array separately further comprises: After reading the first block, reading the second block includes: applying the third voltage to the word line coupled to at least one memory cell in the second block, wherein the third voltage is higher than a voltage of the word line coupled to at least one memory cell in the first block; applying the fourth voltage to the select gate line coupled to at least one select gate transistor in the first block; and The second voltage is applied to the select gate line coupled to at least one select gate transistor in the second block.

7. The method according to claim 5 or 6, wherein: Reading the first block further includes: The fourth voltage is applied to a select gate line coupled to at least one select gate transistor in the target block, wherein the fourth voltage is lower than the third voltage.

8. The method according to any one of claims 5 to 7, wherein: The third voltage ranges from 1.8V to 3.8V, and the second voltage ranges from 2.2V to 3.5V.

9. The method according to any one of claims 1 to 8, wherein: The method further comprises: After erasing the one or more memory cells in the target block and before respectively reading each of the one or more blocks: applying a fifth voltage to a select gate line coupled to at least one select gate transistor in the memory cell array; and applying a sixth voltage to a word line coupled to at least one memory cell in the memory cell array, wherein The fifth voltage is lower than the sixth voltage.

10. The method according to any one of claims 1 to 9, wherein Reading each of the one or more blocks separately includes: After erasing the one or more memory cells in the target block and during the erase operation on the target block, each of the one or more blocks is read separately.

11. A memory device comprising: memory cell array; as well as a peripheral circuit coupled to the memory cell array and configured to perform operations comprising: during an erase operation on a target block in the memory cell array, erasing one or more memory cells in the target block; During the erase operation on the target block, verifying whether the one or more memory cells are erased; and During the erase operation on the target block, reading each of the one or more blocks in the memory cell array separately, wherein reading each of the one or more blocks separately comprises: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and A second voltage is applied to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage.

12. The memory device according to claim 11, wherein The one or more blocks include a first block adjacent to the target block and a second block adjacent to the target block, wherein the first block and the second block are located on two opposite sides of the target block.

13. The memory device according to claim 12, wherein: The one or more blocks include a third block adjacent to the first block and a fourth block adjacent to the second block.

14. The memory device according to claim 12 or 13, wherein: Reading each of the one or more blocks separately includes: Reading the first block and the second block includes: During a period in which the first voltage is applied to the first select gate line coupled to the first select gate transistor in the target block: applying the second voltage to a select gate line coupled to a select gate transistor in the first block; and The second voltage is applied to a select gate line coupled to select gate transistors in the second block.

15. The memory device according to any one of claims 12 to 14, wherein Reading each of the one or more blocks in the memory cell array separately includes: Reading the first block, comprising: applying a third voltage to a word line coupled to at least one memory cell in the first block, wherein the third voltage is higher than a voltage of a word line coupled to at least one memory cell in the second block; applying a fourth voltage to a select gate line coupled to at least one select gate transistor in the second block; and The second voltage is applied to a select gate line coupled to at least one select gate transistor in the first block, wherein the second voltage is higher than the fourth voltage.

16. The memory device according to claim 15, wherein Reading each of the one or more blocks in the memory cell array separately further comprises: After reading the first block, reading the second block includes: applying the third voltage to the word line coupled to at least one memory cell in the second block, wherein the third voltage is higher than a voltage of the word line coupled to at least one memory cell in the first block; applying the fourth voltage to the select gate line coupled to at least one select gate transistor in the first block; and The second voltage is applied to the select gate line coupled to at least one select gate transistor in the second block.

17. The memory device according to claim 15 or 16, wherein: Reading the first block further includes: The fourth voltage is applied to a select gate line coupled to at least one select gate transistor in the target block, wherein the fourth voltage is lower than the third voltage, the third voltage ranges from 1.8V to 3.8V, and the second voltage ranges from 2.2V to 3.5V.

18. The memory device according to any one of claims 11 to 17, wherein: The operations further include: After erasing the one or more memory cells in the target block and before respectively reading each of the one or more blocks: applying a fifth voltage to a select gate line coupled to at least one select gate transistor in the memory cell array; and A sixth voltage is applied to a word line coupled to at least one memory cell in the memory cell array, wherein the fifth voltage is lower than the sixth voltage.

19. The memory device according to any one of claims 11 to 18, wherein Reading each of the one or more blocks separately includes: After erasing the one or more memory cells in the target block and during the erase operation on the target block, each of the one or more blocks is read separately.

20. A memory system comprising: A memory device, the memory device comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and configured to perform operations comprising: during an erase operation on a target block in the memory cell array, erasing one or more memory cells in the target block; During the erase operation on the target block, verifying whether the one or more memory cells are erased; and During the erase operation on the target block, reading each of the one or more blocks in the memory cell array separately, wherein reading each of the one or more blocks separately comprises: applying a first voltage to a first select gate line coupled to a first select gate transistor in the target block; and applying a second voltage to a second select gate line coupled to a second select gate transistor in one of the one or more blocks, wherein the first voltage is lower than the second voltage; and A controller is coupled to the memory device and configured to send one or more signals to the memory device to initiate the operation.

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