Wireless transmitter with bias control

Abstract

Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly to wireless transmitters. One example apparatus generally includes: an in-phase direct current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to the output of the in-phase DC level converter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having an input coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; an in-phase mixer having an input coupled to the output of the in-phase V2I converter; and a quadrature mixer having an input coupled to the output of the quadrature V2I converter.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 521,108, filed on November 28, 2023, which claims the benefit of priority to U.S. provisional patent application serial number 63 / 485,996, filed on February 20, 2023, both of which are hereby incorporated by reference in their entirety. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to wireless transmitters. Background Art

[0004] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smartphones, wearable devices (like smart watches), internet servers, and the like. These various electronic devices provide information, entertainment, social interaction, protection, safety, productivity, transportation, manufacturing, and other services to human users. These various electronic devices rely on wireless communications for many of their functions. Wireless communication systems are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and the like. These systems may be able to support communication with multiple users by sharing available system resources (e.g., time, frequency, and power). Examples of such multiple access systems include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, and orthogonal frequency division multiple access (OFDMA) systems (e.g., long term evolution (LTE) systems or new radio (NR) systems). A wireless device may include a transmitter for processing signals for transmission via one or more antennas. Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no single aspect of which is solely responsible for its desired properties. Without limiting the scope of the present disclosure as expressed by the appended claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description," those skilled in the art will understand how the features of the present disclosure provide the advantages described herein.

[0006] Certain aspects of the present disclosure are directed to an apparatus for wireless communication. The apparatus generally includes: an in-phase direct current (DC) level shifter and a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter and a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; and an in-phase mixer having an input coupled to the output of the in-phase V2I converter and a quadrature mixer having an input coupled to the output of the quadrature V2I converter.

[0007] Certain aspects of the present disclosure are directed to an apparatus for wireless communication. The method generally includes: generating an in-phase level-shifted signal via an in-phase DC level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase V2I converter; converting the quadrature level-shifted signal into a quadrature current via a quadrature V2I converter; sensing a signal at a node of the in-phase V2I converter and the quadrature V2I converter via a bias control circuit; providing a bias signal to at least one of the in-phase DC level shifter or the quadrature DC level shifter based on the sensing; generating an up-converted in-phase signal via an in-phase mixer based on the in-phase current; and generating an up-converted quadrature signal via a quadrature mixer based on the quadrature current.

[0008] Certain aspects of the present disclosure are directed to an apparatus for wireless communication. The apparatus generally includes: an in-phase direct current (DC) level shifter and a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter and a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter and a quadrature mixer having an input coupled to an output of the quadrature V2I converter; a current sensing circuit having an input coupled to a positive differential output and a negative differential output of at least one of the in-phase mixer or the quadrature mixer; and a digital-to-analog converter (DAC) having an input coupled to the current sensing circuit and an output coupled to at least one of the in-phase V2I converter or the quadrature V2I converter.

[0009] Certain aspects of the present disclosure are directed to a method for wireless communication. The method generally includes: generating an in-phase level-shifted signal via an in-phase direct current (DC) level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase voltage-to-current (V2I) converter; converting the quadrature level-shifted signal into a quadrature current via a quadrature V2I converter; sensing a positive differential output current and a negative differential output current of at least one of an in-phase mixer or a quadrature mixer via a current sensing circuit, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current; generating an up-converted in-phase signal via the in-phase mixer based on the in-phase current; and generating an up-converted quadrature signal via the quadrature mixer based on the quadrature current.

[0010] To accomplish the foregoing and related objectives, one or more aspects include the features hereinafter fully described and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of only a few of the various ways in which the principles of the various aspects may be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the manner in which the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the content briefly summarized above may be given by reference to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only certain aspects of the present disclosure and, since the description may admit of other equally effective aspects, are not to be considered as limiting the scope of protection thereof.

[0012] Figure 1 is a schematic diagram of an example wireless communication network in which aspects of the present disclosure may be practiced.

[0013] Figure 2 is a block diagram of an example access point (AP) and example user terminals in which aspects of the present disclosure may be practiced.

[0014] Figure 3 is a block diagram of an example transceiver front end in which aspects of the present disclosure may be practiced.

[0015] Figure 4 An example multiple-input multiple-output (MIMO) transmitter is shown.

[0016] Figure 5A and Figure 5B An example transmitter chain is shown in accordance with certain aspects of the present disclosure.

[0017] Figure 5CCurrent-voltage (IV) characteristics associated with a transmitter chain, according to certain aspects of the present disclosure, are shown.

[0018] Figure 6 Example signal paths of a transmitter chain are shown in accordance with certain aspects of the present disclosure.

[0019] Figure 7 Local oscillator (LO) leakage calibration circuitry in accordance with certain aspects of the present disclosure is shown.

[0020] Figure 8 Mixer circuitry in accordance with certain aspects of the present disclosure is shown.

[0021] Figure 9 Shown are switches and resistive elements of a current sensing circuit according to certain aspects of the present disclosure.

[0022] Figure 10 Shown is swapping of converter inputs to reduce measurement errors during calibration, according to certain aspects of the present disclosure.

[0023] Figure 11A is a flow chart illustrating a calibration algorithm that may be executed via a controller according to certain aspects of the present disclosure.

[0024] Figure 11B is a flow chart illustrating harmonic rejection calibration according to certain aspects of the present disclosure.

[0025] Figure 12 and Figure 13 is a flow diagram illustrating example operations for wireless communications in accordance with certain aspects of the present disclosure.

[0026] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized in other aspects without specific recitation. DETAILED DESCRIPTION

[0027] Certain aspects of the present disclosure generally relate to wireless transmitters implemented with bias control. The transmitter may include a direct current (DC) level shifter that generates in-phase (I) and quadrature (Q) level-shifted signals. The level-shifted signals may be provided to a voltage-to-current (V2I) converter for generating I and Q currents to be provided to respective mixers for upconversion. In some aspects, the transmitter may include a bias control circuit configured to bias a source follower (SF) of the DC level shifter based on a drain-to-source voltage associated with a tail current source of the V2I converter, improving the linearity of the transmitter, as described in more detail herein. In some aspects, the transmitter may include a current sensing circuit configured to sense the output current of the mixer for calibrating the mixer (e.g., by controlling the V2I converter). The transmitter may also include a signal path implemented with circuitry for gain control. For example, each signal path may include a switch for redirecting current from a forward current path to a reverse current path for gain control, as described in more detail herein.

[0028] Example Wireless Communication

[0029] Figure 1 1 shows a wireless communication system 100 having an access point 110 and a user terminal 120 in which aspects of the present disclosure may be practiced. Figure 1 Only one access point 110 is shown. An access point (AP) is typically a fixed station that communicates with user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), a next-generation Node B (gNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, a user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet device, a personal computer, or the like.

[0030] Access point 110 can communicate with one or more user terminals 120 on the downlink and uplink at any given moment. The downlink (i.e., forward link) is the communication link from the access point to the user terminal, and the uplink (i.e., reverse link) is the communication link from the user terminal to the access point. A user terminal can also communicate peer-to-peer with another user terminal. System controller 130 can couple to the access point and provide coordination and control for the access point.

[0031] System 100 employs multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. Access point 110 may be equipped with a number (Nap ) antennas to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. u The selected user terminals 120 can receive downlink transmissions and send uplink transmissions. Each selected user terminal sends user-specific data to the access point and / or receives user-specific data from the access point. Typically, each selected user terminal can be equipped with one or more antennas (i.e., N ut ≥1). N u The selected user terminals may have the same number of antennas, or different numbers of antennas.

[0032] The wireless system 100 can be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 can be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., where the additional cost can be supported). The user terminal 120 or access point 110 can include a transmitter chain with a predistortion bias control circuit and, in some aspects, a current sensing circuit for calibrating one or more mixers, as described in more detail herein.

[0033] Figure 2 A block diagram shows an access point 110 and two user terminals 120m and 120x in a wireless system 100. The access point 110 is equipped with N ap The user terminal 120m is equipped with N antennas 224a to 224ap. ut,m antennas 252ma through 252mu, and user terminal 120x is equipped with N ut,x Antennas 252xa to 252xu. Access point 110 is a transmitting entity for downlink and a receiving entity for uplink. Each user terminal 120 is a transmitting entity for uplink and a receiving entity for downlink. As used herein, a "transmitting entity" is an independently operated device or apparatus capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated device or apparatus capable of receiving data via a frequency channel. In the following description, the subscript "dn" indicates downlink, the subscript "up" indicates uplink, and N up User terminals are selected for simultaneous transmission on the uplink, N dn User terminals are selected for simultaneous transmission on the downlink, N up May or may not be equal to N dn , and N up and Ndn It may be a static value or may change for each scheduling interval.Beam steering, beam forming, or some other spatial processing technique may be used at the access point and user terminal.

[0034] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes the traffic data for the user terminal based on the coding and modulation scheme associated with the rate selected for the user terminal. up} for processing (eg, encoding, interleaving, and modulation), and N ut,m One of the antennas provides a data symbol stream {s up The transceiver front end (TX / RX) 254 (also referred to as the radio frequency front end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and upconverts) the respective symbol streams to generate uplink signals. For example, the transceiver front end 254 may also route the uplink signals to the N-subnet for transmit diversity via an RF switch. ut,m Controller 280 may control routing within transceiver front end 254. Memory 282 may store data and program codes for user terminal 120 and may be connected to controller 280.

[0035] A number (N up ) user terminals 120 may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

[0036] At access point 110, N ap The antennas 224a through 224ap transmit on the uplink from all N up The access point's transceiver front end 222 also performs processing complementary to that performed by the user terminal's transceiver front end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is a stream of data symbols transmitted by the user terminal. up}. RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and / or to controller 230 for further processing.

[0037] On the downlink, at access point 110, TX data processor 210 receives data from data source 208 for N dn The TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. The TX data processor 210 may provide N dn One or more of the user terminals are to be ap The transceiver front end 222 receives and processes the symbol stream (e.g., converts to analog, amplifies, filters, and upconverts) to generate a downlink signal. For example, the transceiver front end 222 can also route the downlink signal to the N antennas for transmit diversity via an RF switch. ap Controller 230 may control routing within transceiver front end 222. Memory 232 may store data and program codes for access point 110 and may be connected to controller 230.

[0038] At each user terminal 120, N ut,m The antennas 252 receive downlink signals from the access point 110. For receive diversity at the user terminal 120, the transceiver front end 254 can select the signal received from one of the antennas 252 for processing. The signals received from multiple antennas 252 can be combined for enhanced receive diversity. The transceiver front end 254 of the user terminal also performs processing complementary to the processing performed by the transceiver front end 222 of the access point and provides a recovered downlink data symbol stream. The RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal. The transceiver front end 222 may include a transmitter chain with predistortion bias control circuitry and, in some aspects, includes current sensing circuitry for calibrating one or more mixers, as described in more detail herein.

[0039] Figure 3is an example transceiver front end 300 (such as Figure 2 2 and 3. FIGURE 3 illustrates a block diagram of a transceiver front end 222, 254 in FIGURE 3. Transceiver front end 300 includes a transmit (TX) path 302 (also referred to as a transmit chain) for transmitting signals via one or more antennas and a receive (RX) path 304 (also referred to as a receive chain) for receiving signals via the antennas. When TX path 302 and RX path 304 share antenna 303, the paths can connect to the antennas via interface 306.

[0040] Receive the in-phase (I) or quadrature (Q) baseband analog signal from the digital-to-analog converter (DAC) 308. The TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The DAC 308 may include current steering cells and may be configured to selectively disable one or more of the current steering cells to reduce power consumption, as described in more detail below. The BBF 310, mixer 312, and DA 314 may be included in a radio frequency integrated circuit (RFIC), while the PA 316 may be external to the RFIC.

[0041] BBF 310 filters the baseband signal received from DAC 308, and mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency conversion process produces the sum and difference frequencies of the LO frequency and the frequency of the signal of interest. The sum and difference frequencies are referred to as beat frequencies. The beat frequencies are typically in the RF range, so the signal output by mixer 312 is typically an RF signal, which is amplified by DA 314 and / or PA 316 before being transmitted via antenna 303.

[0042] RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. LNA 322, mixer 324, and BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may be the same RFIC that includes the TX path components, or may not be the same RFIC that includes the TX path components. RF signals received via antenna 303 may be amplified by LNA 322, and mixer 324 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signal output by mixer 324 may be filtered by BBF 326 before being converted to a digital I or Q signal by analog-to-digital converter (ADC) 328 for digital signal processing.

[0043] While it is desirable for the output of the LO to remain stable in frequency, tuning the LO to different frequencies typically requires the use of a variable frequency oscillator, which can involve a trade-off between stability and tunability. Contemporary systems may employ a frequency synthesizer with a voltage-controlled oscillator (VCO) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO frequency may be generated by a TX frequency synthesizer 318, which may be buffered or amplified by an amplifier 320 before being mixed with the baseband signal in mixer 312. Similarly, the receive LO frequency may be generated by an RX frequency synthesizer 330, which may be buffered or amplified by an amplifier 332 before being mixed with the RF signal in mixer 324. In some aspects, the transceiver front end 300 may include predistortion bias control circuitry and, in some aspects, current sensing circuitry for calibrating one or more mixers (such as mixer 312), as described in greater detail herein.

[0044] Example Wireless Transmitter

[0045] Certain aspects of the present disclosure generally relate to wireless transmitters that support wideband (WB) operation with improved linearity compared to conventional implementations. The wireless transmitters described herein can be used in any suitable wireless device, such as a base transmitter station (BTS) (e.g., a base station). Designing a BTS transmitter can involve simultaneous multi-user communications with strict specifications for adjacent channel transmissions. The BTS transmitter can support 1024-quadrature amplitude modulation (QAM) with a high signal-to-noise ratio (SNR) to meet strict noise, mismatch, and in-band emission specifications. The BTS transmitter may be subject to strict Federal Communications Commission (FCC) or other regulatory agency specifications regarding spectrum emission masks (SEM). The BTS transmitter can support non-contiguous user communications or radio access network (RAN) sharing of high linearity wideband support for front-end (FE) digital predistortion (DPD) linearization. The BTS transmitter can support multi-user (Mu)-multiple-input-multiple-output (MIMO) (MIMO and beamforming (BF)), including matching and tracking between transmitter chains.

[0046] Figure 4 An example MIMO transmitter 400 is shown. As shown, using various radiating elements 402, one or more communication beams can be generated toward one or more UEs (e.g., toward a direction labeled "desired beam direction"). In some aspects, a null beam can be generated toward an object 404, as shown. A null beam can refer to a transmission direction with reduced gain (e.g., compared to a desired beam direction). In some cases, a null beam can be used to reduce interference with one or more devices during transmission.

[0047] According to certain aspects of the present disclosure, Figure 5A and Figure 5B An example transmitter chain 500 is shown. Chain 500 may include a DAC 308 to provide in-phase (I) and quadrature (Q) signals to a filter 310 (e.g., an anti-aliasing filter). Filter 310 may be coupled to phase interpolators 509 and 532. Phase interpolators 509 and 532 may be used to perform phase adjustment. I and Q phase interpolators 509 may provide I and Q signals to respective in-phase (I) and quadrature (Q) direct current (DC) level shifters 506, and I and Q phase interpolators 532 may provide I signals with I and Q signals with Q to respective 45-degree phase offset (I45) and 45-degree phase offset (Q45) DC level shifters 534. The DC level shifters 506 and 534 generate DC level-shifted signals that are provided to respective voltage-to-current (V2I) converters 510 and 536. The V2I converters 510 and 536 can generate currents (e.g., I current, Q current, I45 current, and Q45 current) to be provided to the mixer 550 for upconversion. The mixer 550 can include an I mixer, a Q mixer, an I45 mixer, and a Q45 mixer, as shown. The mixer 550 can be implemented as a harmonic rejection mixer (HRM) for upconversion. As shown, the LO signal generator 517 can generate LO signals that can be provided to the delay-locked loop (DLL) 521 for generating the I LO signal, the Q LO signal, the I45 LO signal, and the Q45 LO signal to be provided to the mixer 550.

[0048] In some aspects, chain 500 can include a predistortion bias control circuit 502. Predistortion bias control circuit 502 can receive I and Q samples (e.g., labeled "I / Q samples") from V2I converter 510 and can bias DC level shifter 506 based on the I and Q samples, as described in greater detail herein. As described above, based on the I DC level shift signal and the Q DC level shift signal from DC level shifter 506, V2I converter 510 generates I and Q currents, respectively, that are provided to the I and Q mixers of mixer 550. Similarly, chain 500 can include a predistortion bias control circuit 504. Predistortion bias control circuit 504 can receive I and Q samples (e.g., labeled "I / Q samples") from V2I converter 536 and can bias DC level shifter 534 based on the I and Q samples. Based on the I45 DC level shifted signal and the Q45 DC level shifted signal from the DC level shifter 506 , the V2I converter 536 generates an I45 current and a Q45 current, respectively, which are provided to the I45 mixer and the Q45 mixer of the mixer 550 .

[0049] As shown, current sensing circuit 552 and current sensing circuit 530 can be coupled to the output of mixer 550, as shown. Current sensing circuits 552 and 530 can sense the output current of the mixer for calibration of mixer 550, as described in more detail herein. For example, current sensing circuits 552 and 530 can generate calibration signals that are provided to respective DACs 512 and 538. DACs 512 and 538 can output analog signals to respective V2I converters 510 and 536. The analog signals from DACs 512 and 538 can be used to sink current from mixer 550 via respective V2I converters 510 and 536, as described in more detail herein. For example, the output voltage from DAC 512 can be converted to a current using V2I converter 510 to bias mixer 550. Mixer 550 can be coupled to signal paths 505 and 507 coupled to port 508.

[0050] The mixer 550 can be coupled to a plurality of cross-coupled current buffers 526, 528. The current buffers 526, 528 are provided to an input / output (I / O) switch matrix 542 through load line tuning circuits 514, 540. The I / O switch matrix 542 can be coupled to I / O pins (e.g., also referred to herein as "transmitter port 508"). The mixer 550 operates based on eight phases (e.g., providing a differential I signal, a differential Q signal, a differential I45 signal, and a differential Q45 signal).

[0051] Figure 5B 1 shows an example implementation of a transmitter chain 500 according to certain aspects of the present disclosure. As shown, the chain 500 can be implemented for multiple transmitters (e.g., eight transmitters labeled "TX0" through "TX7"). Figure 5B As shown, the chain 500 may include a single-pole transimpedance amplifier (TIA) 518 (e.g., as part of a baseband filter (BBF), labeled “anti-aliasing filter”). The anti-aliasing filter with TIA 518 may correspond to the Figure 5A As shown, the chain 500 may include I and Q level shifters and V2I converter circuits 590 (e.g., corresponding to Figure 5A The chain 500 may also include an I and Q level shifter and V2I converter circuit 592 (e.g., corresponding to an I and Q DC level shifter 506 and an I and Q V2I converter 510). Figure 5A I and Q DC level shifters 534 and I and Q V2I converters 536).

[0052] To implement DC level shifter 506, circuit 590 may include a p-channel metal oxide semiconductor (PMOS) source follower (SF) stage comprising a PMOS transistor 580 coupled to an input PMOS transistor 586 and a PMOS SF stage comprising a PMOS transistor 581 coupled to an input PMOS transistor 587. To implement DC level shifter 534, circuit 592 may include a PMOS SF stage comprising a PMOS transistor 582 coupled to an input PMOS transistor 584 and a PMOS SF stage comprising a PMOS transistor 583 coupled to an input PMOS transistor 585. The input PMOS transistors receive differential signals from respective phase interpolators. The SF stage DC couples the phase interpolator output from a lower voltage domain (e.g., 1.2V) below a higher voltage domain (e.g., 1.8V) to respective mixer n-channel metal oxide semiconductor (NMOS) transconductance (Gm) cells (e.g., corresponding to V2I converters 510 and 536). The SF also acts as a buffer stage between the Gm unit and the TIA (e.g., TIA 518), and balances the tail device voltage at the slow (SS) and fast (FF) corners. As shown, each V2I converter can include a transistor (e.g., transistors 571, 573) having a gate coupled to the output of the respective SF stage of the DC level shifter. For example, the gate of transistor 573 can be coupled to a node between transistors 581, 587 (e.g., the DC level shifter output), as shown.

[0053] Chain 500 may include predistortion bias control circuits 502, 504, as described herein. The gates of the SF-stage PMOS transistors (e.g., PMOS transistors 580, 581) may be biased based on an average value of the drain-to-source voltage of the transistors used to implement the tail current source for the V2I circuit. For example, the gates of PMOS transistors 582, 583 may be biased via a sense amplifier 531 of bias control circuit 504. The sense amplifier 531 may receive the drain-to-source voltage (V) of the tail current source (e.g., tail device 520) for the I45 V2I circuit through respective resistor elements 562, 564 as shown. DS -I45) and the drain-to-source voltage (V DS-Q45). Thus, the positive input of the sense amplifier 531 can receive a voltage representing the average of the drain to source voltages associated with the tail current sources for the I45 signal and the Q45 signal. Since the common mode (CM) harmonics of the quadrature signals are out of phase, the sense amplifier can feed only the DC operating point to the SF or DC shifting stage. This quadrature sensing scheme is important for maintaining linearity. The sense amplifier 531 can drive the gate of the SF PMOS transistor so that the average of the tail device drain to source voltage is equal to the reference voltage (VDS-REF), thereby reducing CM harmonics. The operating bias of the sense amplifier 531 can be selected together with the DC level shifter stage so that the V2I converter current-voltage (IV) characteristic is opposite to the rest of the signal path, thereby creating an overall flat IV response in the operating power range, improving linearity, as shown with respect to Figure 5C Described in more detail.

[0054] Figure 5C FIGURE 5 illustrates the IV characteristics associated with chain 500 according to certain aspects of the present disclosure. A DC level shifter (e.g., Figure 5A The level shifter 534 shown provides an IV characteristic as shown in graph 561. For example, the level shifter and sense amplifier can be biased to have an IV expansion transfer function (TF) (e.g., associated with amplification gain expansion) and an IV compression TF (e.g., associated with amplification gain compression) as shown in graph 561. The associated V2I converter (e.g., Figure 5A 536 ) may have an IV expansion and compression TF as shown in graph 569 . Thus, the combined IV expansion and compression TF may be linear, as shown in graph 575 .

[0055] Return to Figure 5B , the gates of the PMOS transistors 580, 581 may be biased via the sense amplifier 533 of the bias control circuit 502. The sense amplifier 533 may receive the drain-to-source voltage (V) of the tail current source (e.g., tail device 560) for the IV2I circuit through respective resistor elements 563, 565. DS -I) and the drain-to-source voltage (V DS Thus, the positive input of the sense amplifier 533 can receive a voltage representing the average value of the drain-to-source voltage of the tail current source for the I signal and the Q signal, which is analogous to VDS-REF, based on which the gate voltages of the PMOS transistors 580 and 581 are controlled.

[0056] The PMOS SF stage also provides headroom for the tail devices (e.g., tail device 520). Although a PMOS SF stage is shown to facilitate understanding, in some cases an NMOS SF stage (e.g., driven by a PMOS stage) may be used. In some cases, a Gm cell degeneration (e.g., including greater than 15dB loop gain DPD bandwidth (BW)) may be used. In some aspects, split degeneration may be used to reduce the noise contribution of the tail device. Tail current source expansion (e.g., Figure 5C 561 in helps improve adjacent channel leakage ratio (ACLR). In some aspects, floating source degeneration (e.g., with 20dB wideband (WB) loop gain) can be used, which helps linearize the Gm unit to meet the ACLR specification.

[0057] like Figure 5B As shown, two signal paths 505, 507 may be provided for different frequency bands (e.g., one for the low / medium / high (LMH) band and another for the new radio (NR) / NR-unlicensed (U) band). Figure 5A ) have different controls that can be used to adjust the amount of current reaching a load (e.g., a balanced-to-unbalanced (balun) component) and, therefore, gain control. Compared to current-steering gain control circuits, the equipment used to implement cross-coupled current buffers can be smaller. Furthermore, unlike current-steering gain control circuits, cross-coupled current buffers may not inject current into the power supply, which reduces crosstalk.

[0058] Figure 6 An example signal path 600 (eg, corresponding to Figure 5B 505 or signal path 507). In some aspects, signal path 600 can be implemented as a gain control circuit. As shown, signal path 600 can include a forward current path 602 (e.g., from a first differential node 603 of the signal path to a balun 690), a return current path 604 (e.g., from the balun 690 to a second differential node 605 of the signal path), and transistors 606, 608, 610, 612. Differential nodes 603, 605 can be the differential outputs of mixer 550. Transistors 606, 608, 610, 612 can be tunable, allowing for gain control.

[0059] Transistor 606 can be coupled between differential node 603 and terminal 692 (e.g., referred to herein as the “first balanced terminal”) of balun 690, and transistor 612 can be coupled between differential node 605 and terminal 694 (e.g., referred to herein as the “second balanced terminal”) of balun 690. Transistor 608 can be coupled between differential node 603 and terminal 694, and transistor 610 can be coupled between terminal 692 and differential node 605. To control signal gain, transistors 608, 610 can be controlled (e.g., corresponding to the gain of the transistors 608 and 610). Figure 5A Cross-coupled current buffers 526 or 528 are shown to redirect at least a portion of the current from forward current path 602 to return current path 604, as shown. Thus, the redirected current bypasses balun 690 to adjust signal gain.

[0060] Terminal 696 of balun 690 (e.g., referred to herein as the “unbalanced terminal”) can be connected to a balun by switch 670 (e.g., corresponding to Figure 5A The I / O switch matrix 542 of FIG. 5 is coupled to the port 508. The port 508 may be for Figure 5B Common to the two signal paths 505, 507 shown. Figure 6 As shown, terminal 696 can be coupled to load line tuning circuit 672 (e.g., corresponding to Figure 5A load line tuning circuit 514 or 540).

[0061] Although Figure 5B Two signal paths 505, 507 are shown in FIG, but any number of signal paths can be used for any number of frequency bands or frequency band groupings. Each signal path can include a WB balun (e.g., balun 690), as shown. Signal paths 505, 507 can include thick oxide cascade structures (transistors 608, 610, 606, 612) to isolate the I / Q summing node (e.g., in the I / O switch matrix 542, just before port 508) from load and source impedance variations (e.g., using an on / off state machine for device breakdown protection). The integrated WB balun converts the differential signal to a single-ended (SE) output. The signal paths can be multiplexed to a driver amplifier (DA) (e.g., Figure 3314) is coupled to an input / output (I / O) pin (e.g., port 508) of the DA 314. On-chip per-phase mixer current calibration can be used to compensate for or at least adjust for local and global mismatches, as described in more detail herein. In some aspects, the switches of signal path 505 or 507 can be biased in saturation to activate the associated frequency band. The switches of the HRM (e.g., switches 591, 593) can be biased in the triode region. The BBF can be implemented as an anti-aliasing active filter (e.g., Figure 5A ), followed by a passive pole.

[0062] Some transceiver architectures are designed to meet the requirements of sideband transmission with low current consumption (e.g., using passive mixers and HRM). Some implementations may include an HRM DAC and an HRM LO. The passive mixer may include a tuned transformer that serves multiple purposes, including CM rejection, real impedance loading, and low swing across the passive components for good linearity. A DA may follow the passive mixer for power amplification.

[0063] The transceiver of the present disclosure can be designed to meet the fast radio burst (FRB) operating band unwanted emission (OBUE) and out-of-band (OOB) emission specifications. The transceiver may include an active mixer and an HRM. The active mixer may use source degeneration to linearize the Gm unit. As described, the active mixer differential output may be converted to a single-ended output by a balanced-unbalanced converter (e.g., an on-chip broadband balanced-unbalanced converter).

[0064] Figure 7 1 shows a local oscillator (LO) leakage calibration circuitry 700 according to certain aspects of the present disclosure. As shown, a plurality of DACs 710, 712, 714, 716 can be used to provide calibration currents for reducing mismatches associated with respective I mixers 702, Q mixers 704, I45 mixers 706, and Q45 mixers 708. The DACs 710, 712 (for I and Q) can correspond to Figure 5A The DAC 512 shown, and DACs 714, 716 (for I45 and Q45) may correspond to Figure 5ADAC 538 is shown. As shown, the outputs of mixers 702, 704, 706, 708 can be coupled to a balun 690. LO leakage can be caused by DC offset and LO feedthrough (LOFT). As shown, LOFT refers to the electrical coupling of the LO signal to the mixer output, which may also be subject to gain and phase adjustments, represented by the respective gain adjustments labeled "GI," "GQ," "GI45," and "GQ45," and the respective phase adjustment circuits labeled "Phi,I," "Phi,Q," "Phi,I45," and "Phi,Q45." In a multiphase mixer, the LO leakage through each phase may not be correlated. LO leakage can be calibrated by an I / Q DC Online Calibration (DCOC) block in the digital domain, which may only have calibration for I and Q phases.

[0065] When the leakage paths are uncorrelated, multiple distinct calibration settings may exist. Therefore, correlation between different leakage paths is important. In some cases, the DC offset can be corrected at the source (e.g., at the output of DAC 522). In some aspects, HRM is employed in high-performance transmitters to remove the third and fifth harmonics of the LO and 4FMOD (e.g., a frequency at four times the BB frequency). The amount of harmonic suppression depends on the amplitude and phase mismatch of the LO and BB signals. Certain aspects are directed to techniques for calibrating the amplitude and phase of the BB / LO signals.

[0066] Figure 8A mixer circuit system 800 is shown, according to certain aspects of the present disclosure, and includes an HRM 802 for upconverting the I signal, an HRM 804 for upconverting the Q signal, an HRM 806 for upconverting the I45 signal, and an HRM 808 for upconverting the Q45 signal. As shown, each HRM includes a bias current source (Ibias) for each differential path and a calibration current source (Ifine) connected in parallel with each bias current source (e.g., implemented by a high-resolution current DAC). For example, HRM 802 may include bias current sources 803 and 805, HRM 804 may include bias current sources 807 and 809, HRM 806 may include bias current sources 811 and 813, and HRM 808 may include bias current sources 815 and 817. Continuing with this example, calibration current sources 820, 822, 824, 826, 828, 830, 832, 834 may be coupled in parallel with respective bias current sources 803, 805, 807, 809, 811, 813, 815, 817 as shown. At least some of the calibration current sources 820, 822, 824, 826, 828, 830, 832, 834 may be adjustable. In some aspects, each of the calibration current sources 820, 822, 824, 826, 828, 830, 832, 834 may be coupled in parallel with respective bias current sources 803, 805, 807, 809, 811, 813, 815, 817. Figure 5A and Figure 5B The respective tail current sources of the depicted V2I circuits are coupled in parallel. For example, calibration current source 822 may be coupled in parallel with tail device 560 to provide calibration current (eg, along with bias current) to the respective mixers.

[0067] Current sensing circuit 831 (eg, corresponding to Figure 5ACurrent sensing circuits 552, 530 of the HRM can be coupled between differential outputs 890, 892 of the HRM and calibration ADC 833, as shown. Each of the bias current sources biases (e.g., sinks current Ibias) a respective BB input transistor, and each of the calibration current sources calibrates (e.g., sinks current Ifine) a respective BB input transistor, as shown. For example, HRM 802 can include a positive BB input (BBIP) transistor 850 (e.g., having a gate that receives a BBIP signal) and a negative BB input (BBIM) transistor 852 (e.g., having a gate that receives a BBIM signal). As shown, the sources of transistors 850, 852 can be coupled to respective current sources 803, 805. The drain of BBIP transistor 850 can be coupled to LO input transistors 854, 856, and the drain of BBIP transistor 852 can be coupled to LO input transistors 858, 860. LO input transistor 854 may have a gate receiving a positive LO input (LOIP) signal, and LO input transistor 856 may have a gate receiving a negative LO input (LOIM) signal. LO input transistor 860 may have a gate receiving the LOIP signal, and LO input transistor 858 may have a gate receiving the LOIM signal.

[0068] As shown, the drains of transistors 854, 858 may be coupled to the positive differential output 890 of the HRM's differential output pair. The drains of transistors 856, 860 may be coupled to the negative differential output 892 of the differential output pair.

[0069] Figure 9 1 shows a switch and a resistive element (labeled “R P ” and “R M ”). Resistor element R P and R M is selectively coupled between a voltage rail (e.g., a power supply node labeled "Vdd") and respective inputs of ADC 832. By closing switches 904, 908, the positive output 890 of the HRM can be coupled to R P and the first input of ADC833, and the negative output 892 of HRM can be coupled to R M and the second input of ADC 833. ADC 833 measures the P and R M The voltage at R , and calibrating the HRM (e.g., by adjusting Ifine absorbed by one or more of calibration current sources 820, 822, 824, 826, 828, 830, 832, 834) to P and R MThe voltages at 0 and 1 are set equal. A calibration code (e.g., representing the current setting of each of the calibration current sources) can be stored for use during mission mode. In some aspects, switch 912 can be coupled between the voltage rail and the first input of ADC 833.

[0070] In some aspects, the coupling to the ADC input can be swapped using the switches of the current sensing circuit 831. For example, the negative output 892 of the HRM can be coupled to the R by closing switches 906, 910. P and the first input of ADC 833, and the positive output 890 of the HRM can be coupled to R by closing switches 902, 914. M and the second input of ADC 833. By performing the swap, the difference between the input and the output due to mismatch (e.g., with the ADC, transmission line, or R P and R M associated) caused by calibration errors, as described in more detail herein.

[0071] To eliminate mismatch errors, two measurements (V1, V2) can be performed, where I p (e.g., positive output current of HRM) and I m (e.g., the negative output current of the HRM) is routed to a different resistor (R P and R M After DC offset calibration, the DC bias current for each phase (e.g., I, Q, I45, and Q45) is calculated by scaling I p and I m The two are balanced, such as Figure 10 、 Figure 11A and Figure 11B As described in more detail, each phase of the HRM can be calibrated to the same DC bias current, balancing Gm and improving harmonic rejection. As described, errors associated with ADC offset and any other mismatches in the measurement path can also be eliminated (or at least reduced).

[0072] Figure 10 1002 shows the swapping of ADC inputs for reducing measurement errors (eg, calibration errors) according to certain aspects of the present disclosure. As shown in schematic 1002, the positive output current I p Can be from R p absorbed, and the negative output current I m It can be from R m is absorbed so that the voltage V1′ can be measured via ADC 833. After the exchange as shown in schematic 1004, the positive output current I p Can be from R mabsorbed, and the negative output current I m Can be from R p absorbed so that the voltage V2′ can be measured via ADC 833.

[0073] The voltage V1 can be determined based on the following equation:

[0074] V1=V1'+V err =(I p R p -I m R m )+V err

[0075] Where V err is the error voltage associated with the mismatch between the resistive elements (e.g., as well as the transmission line and ADC mismatch). The voltage V2 can be determined based on the following equation:

[0076] V2=V2'+V err =(I p R m -I m R p )+V err ..

[0077] Assume R p =R, R m =R+ΔR, where ΔR represents the p With R m The mismatch between p Can be equal to

[0078] I bias +I offset +I fine

[0079] Among them I offset represents the bias current source of the HRM (e.g., Figure 8 The offset between the bias current sources 803 and 805 of the HRM 802. m Can be equal to

[0080] I bias -I fine

[0081] Therefore, V off Can be equal to

[0082] V2-V1=2R[I offset +2I fine ]+ΔR[I offset +2I fine ]

[0083] After calibration, the term [I offset +2I fine ] becomes zero, thus canceling ΔR. Measurement errors (including measurement path leakage and ADC offset) can also be cancelled (or at least reduced) in this way.

[0084] In some aspects, a first calibration may be performed for each HRM. For example, any mismatch between the differential outputs of a first HRM (e.g., HRM 802), followed by a second HRM (e.g., HRM 804), and so on may be calibrated, as described with respect to Figure 11A Once the differential output of each HRM is calibrated, any mismatch between the HRMs can be calibrated, as described in more detail. Figure 11B Described in more detail.

[0085] Figure 11A 1 is a flow chart illustrating a DC offset calibration algorithm that may be performed via a controller according to certain aspects of the present disclosure. As shown, at block 1102, the controller may measure V associated with each of the maximum calibration code and the minimum calibration code. off At block 1104, the controller may determine the measured V off For example, if the V associated with the calibration code off does not reach zero (i.e., may not be selected will cause V off = zero calibration), then at block 1106, you can select off The minimum value that can be achieved is associated with the calibration code (e.g., V off The minimum absolute value is marked as "min[abs(V off )]”). Then, the next TX chain (if any) can be calibrated. If V off If zero is reached, then a coarse calibration and a fine calibration may be performed. For example, for the coarse calibration at block 1108, a binary search (eg, a 4-step binary search) may be performed to reduce V off After the coarse calibration, fine calibration may be performed at block 1110 by performing a linear search (e.g., a 15-step linear search) around the calibration code derived from the binary search. As described, after performing the coarse and fine calibrations, the determined calibration code (e.g., min[abs(V off )]) may be saved at block 1112 and used for calibration during mission mode. Once each of the HRMs is calibrated (e.g., each of the I, Q, I45, Q45 HRMs), harmonic rejection calibration across the HRMs may begin, as described with respect to Figure 11B described.

[0086] Figure 11Bis a flow chart illustrating harmonic rejection calibration according to certain aspects of the present disclosure. As shown, at block 1120, the I channel voltage (V ich ) can be measured via calibration ADC 833, where V ich It is in R P For example, Figure 9 The calibration switch shown can be controlled to p Sinking I HRM positive output current (I ip ) or I HRM negative output current (I im )(For example, I for I HRM 802 p or I m ), while measuring the P V ich (For example, where V ich =I ip (or I im )x R P ). Similarly, at block 1122, the Q channel voltage (V qch ) can be obtained by p Sink Q HRM positive output current (I qp ) or Q HRM negative output current (I qm )(For example, I for Q HRM 804 p or I m ), while measuring the P V qch (For example, where V qch =I qp (or I qm )x RP) to measure. I can be tuned qp and / or I qm , making V qch Equal to V ich Similarly, at block 1124, the I-45 channel voltage (V i45ch ), and can measure and tune the Q-45 channel voltage (V q45ch ), as shown. For example, V i45ch This can be done by p Sink I45 HRM positive output current (I i45p ) or Q HRM negative output current (I i45m )(For example, I for I45HRM 806 p or I m ), while measuring the P V i45ch (For example, where V i45ch =I i45p (or I i45m)x R P ) to measure. I can be tuned i45p and / or I i45m , making V i45ch Equal to V qch At block 1126, Vq45ch may be obtained by p Absorbs the positive output current of Q45 HRM (I q45p ) or Q HRM negative output current (I q45m )(For example, I for Q45HRM 808 p or I m ), while in R P Measure V q45ch (For example, where V q45ch =I q45p (or I q45m )x R P ) to measure. I can be tuned q45p and / or I q45m , making V q45ch Equal to V i45ch .

[0087] The calibration techniques described herein eliminate (or at least reduce) errors introduced by measurement circuitry (e.g., resistors, transmission lines, and / or ADCs). Compared to some implementations, calibration of a multiphase high-performance mixer uses only a few additional components, and in some aspects, only a one-time calibration can be performed. Common circuitry can be used to correct for DC offset (e.g., LO leakage) and amplitude mismatch between BB signals (e.g., harmonic rejection calibration). After calibration (e.g., using DC offset and DCOC calibration), LO leakage levels of less than -62 dBc can be achieved.

[0088] Figure 12 is a flow diagram illustrating example operations 1200 for wireless communication. Operations 1200 may be performed by a transmitter chain, such as transmitter chain 500.

[0089] At block 1202, the transmitter chain generates an in-phase level-shifted signal via an in-phase DC level shifter (e.g., an IDC level shifter in level shifter 506). At block 1204, the transmitter chain generates a quadrature level-shifted signal via a quadrature DC level shifter (e.g., a quadrature DC level shifter in level shifter 506).

[0090] At block 1206, the transmitter chain converts the in-phase level-shifted signal into an in-phase current via an in-phase V2I converter (e.g., an I V2I converter in V2I converter 510). At block 1208, the transmitter chain converts the quadrature level-shifted signal into a quadrature current via a quadrature V2I converter (e.g., a quadrature V2I converter in V2I converter 510).

[0091] At block 1210, the transmitter chain senses signals at nodes of the in-phase V2I converter and the quadrature V2I converter via a bias control circuit (e.g., bias control circuit 502). At block 1212, the transmitter chain provides a bias signal to at least one of the in-phase DC level shifter or the quadrature DC level shifter based on the sensing.

[0092] At block 1214, the transmitter chain generates an upconverted in-phase signal based on the in-phase current via an in-phase mixer (e.g., the in-phase mixer of mixer 550, or mixer 802). At block 1216, the transmitter chain generates an upconverted quadrature signal based on the quadrature current via a quadrature mixer (e.g., the quadrature mixer in mixer 550, or mixer 804).

[0093] In some aspects, the in-phase DC level shifter may include a first source follower (e.g., including transistors 580, 586), the first source follower being configured to DC level shift the in-phase signal to generate an in-phase level-shifted signal. The quadrature DC level shifter may include a second source follower being configured to DC level shift the quadrature signal to generate a quadrature level-shifted signal. In some aspects, the in-phase V2I converter may include a first tail current source, and the quadrature V2I converter may include a second tail current source. The sensed signal may include a first VDS associated with the first tail current source and a second VDS associated with the second tail current source. A bias signal may be provided to a gate of a bias transistor of at least one of the first source follower or the second source follower.

[0094] At least one of the in-phase V2I converter or the quadrature V2I converter may include a tail current source (e.g., Figure 5B The sensed signal may include a first drain-to-source voltage (VDS) associated with the first source follower (e.g., at Figure 5B ) and a second VDS associated with the second source follower (e.g., Figure 5B The bias signal may be provided to a control input of the tail current source (eg, the gate of the associated transistor).

[0095] In some aspects, the transmitter chain senses a positive differential output current and a negative differential output current of at least one of the in-phase mixer or the quadrature mixer via a current sensing circuit. At least one of the in-phase current or the quadrature current can be generated based on the sensed positive differential output current and the sensed negative differential output current.

[0096] In some aspects, at least one of the in-phase mixer or the quadrature mixer can include a positive differential output and a negative differential output. When the first resistive element is coupled to the positive differential output, the transmitter chain can sense the first resistive element (e.g., Figure 9 The resistance element R P ). When the second resistive element is coupled to the negative differential output, the transmitter chain may sense a first voltage at the second resistive element (e.g., Figure 9 The resistance element R M ). The transmitter chain may bias at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage. In some aspects, the transmitter chain may sense a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output, and sense a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output. The transmitter chain may bias at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage.

[0097] In some aspects, the transmitter chain can route at least a portion of the current from the positive differential output to a first balanced terminal (e.g., terminal 692) of a first balun assembly (e.g., balun 690) via a first switch (e.g., transistor 606) of a first current path (e.g., current path 602). The transmitter chain can route at least a portion of the current from a second balanced terminal (e.g., terminal 694) of the balun assembly toward the negative differential output via a second switch (e.g., transistor 612) of a second current path (e.g., current path 604). The unbalanced terminal of the balun assembly can be coupled to a transmitter port (e.g., port 508). The transmitter chain can route at least another portion of the current from the positive differential output to the second current path via a third switch (e.g., transistor 608) or a fourth switch (e.g., transistor 610).

[0098] Figure 13 is a flow diagram illustrating example operations 1300 for wireless communication. Operations 1300 may be performed, for example, by a transmitter chain, such as transmitter chain 500.

[0099] At block 1302, the transmitter chain generates an in-phase level-shifted signal via an in-phase DC level shifter (e.g., the IDC level shifter of the level shifter 506). At block 1304, the transmitter chain generates a quadrature level-shifted signal via a quadrature DC level shifter (e.g., the Q DC level shifter of the level shifter 506).

[0100] At block 1306, the transmitter chain converts the in-phase level-shifted signal to an in-phase current via an in-phase V2I converter. At block 1308, the transmitter chain converts the quadrature level-shifted signal to a quadrature current via a quadrature V2I converter.

[0101] At block 1310, the transmitter chain senses a positive differential output current and a negative differential output current of at least one of an in-phase mixer (e.g., HRM 802) or a quadrature mixer (e.g., HRM 804) via a current sensing circuit (e.g., current sensing circuit 552). At least one of the in-phase current or the quadrature current may be generated based on the sensed positive differential output current and the sensed negative differential output current.

[0102] At block 1312, the transmitter chain generates an up-converted in-phase signal via an in-phase mixer based on the in-phase current. At block 1314, the transmitter chain generates an up-converted quadrature signal via a quadrature mixer based on the quadrature current.

[0103] In some aspects, at least one of the in-phase mixer or the quadrature mixer can include a positive differential output and a negative differential output. When the first resistive element is coupled to the positive differential output, the transmitter chain can sense the first resistive element (e.g., Figure 9 The resistance element R P ). When the second resistive element is coupled to the negative differential output, the transmitter chain may sense a first voltage at the second resistive element (e.g., Figure 9 The resistance element R M ). The transmitter chain may bias at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage. In some aspects, the transmitter chain may sense a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output, and sense a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output. The transmitter chain may bias at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage.

[0104] Aspect Examples

[0105] Aspect 1: A transceiver comprising: at least one mixer; a first signal path having a first balanced-to-unbalanced (balanced-unbalanced transformer) component; and a second signal path having a second balanced-unbalanced transformer component, wherein: the mixer is selectively coupled to the first signal path or the second signal path; and the first signal path and the second signal path are coupled to a node.

[0106] Aspect 2: The transceiver of aspect 1, wherein the node is coupled to an input of a driver amplifier (DA).

[0107] Aspect 3: The transceiver according to any of aspects 1-2, wherein the at least one mixer comprises a harmonic rejection mixer (HRM).

[0108] Aspect 4: A transceiver according to any of Aspects 1-3, wherein at least one mixer includes: a first differential harmonic rejection mixer (HRM) associated with an in-phase (I) signal; a second differential HRM associated with a quadrature (I) signal; a third differential HRM associated with a 45-degree offset I (I45) signal; and a fourth differential HRM associated with a 45-degree offset Q (Q45) signal.

[0109] Aspect 5: The transceiver according to any one of aspects 1-4, wherein the first signal path comprises a gain control stage.

[0110] Aspect 6: A transceiver according to Aspect 5, wherein the gain control stage includes: a first switch coupled between a first differential node of the first signal path and a first terminal of the first balanced-unbalanced transformer component; a second switch coupled between a second differential node of the first signal path and a second terminal of the first balanced-unbalanced transformer component; a third switch coupled between the first differential node of the first signal path and the second terminal of the first balanced-unbalanced transformer component; and a fourth switch coupled between the second differential node of the first signal path and the first terminal of the first balanced-unbalanced transformer component.

[0111] Aspect 7: The transceiver according to any of Aspects 1-6, further comprising: a calibration path circuit system coupled to the first differential output and the second differential output of the at least one mixer; and an analog-to-digital converter (ADC) coupled to the calibration path circuit system.

[0112] Aspect 8: A transceiver according to Aspect 7, wherein the calibration path circuit system includes a switch configured to selectively couple the first differential output to the first input of the ADC; couple the first differential output to the second input of the ADC; couple the second differential output to the first input of the ADC; or couple the second differential output to the second input of the ADC.

[0113] Aspect 9: The transceiver of aspect 8, wherein the calibration path circuitry further comprises: a first resistive element selectively coupled to the first input of the ADC and a power supply node; and a second resistive element selectively coupled to the second input of the ADC and a power supply node.

[0114] Aspect 10: An apparatus for wireless communication, comprising: an in-phase direct current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, the output of the bias control circuit being coupled to at least one of the in-phase DC level shifter or the quadrature DC level shifter; an in-phase mixer having an input coupled to the output of the in-phase V2I converter; and a quadrature mixer having an input coupled to the output of the quadrature V2I converter.

[0115] Aspect 11: An apparatus according to Aspect 10, wherein: the in-phase DC level shifter includes a first source follower circuit configured to perform DC level shifting on the in-phase signal; and the orthogonal DC level shifter includes a second source follower circuit configured to perform DC level shifting on the orthogonal signal.

[0116] Aspect 12: An apparatus according to Aspect 11, wherein: the in-phase V2I converter includes a first tail current source; the orthogonal V2I converter includes a second tail current source; and the bias control circuit is configured to: sense a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; and bias at least one of the first source follower circuit or the second source follower circuit based on the first VDS and the second VDS.

[0117] Aspect 13: An apparatus according to Aspect 12, wherein the bias control circuit includes an amplifier having a first input configured to receive an average of the first VDS and the second VDS, a second input configured to receive a reference voltage, and an output coupled to the gate of a bias transistor of at least one of the first source follower circuit or the second source follower circuit.

[0118] Aspect 14: The device according to any one of Aspects 11-13 further includes a phase interpolator, the phase interpolator including: a first output, which is coupled to the input of the first source follower circuit and is configured to generate an in-phase signal; and a second output, which is coupled to the input of the second source follower circuit and is configured to generate an orthogonal signal.

[0119] Aspect 15: The apparatus of any one of Aspects 10-14, further comprising: a current sensing circuit having an input coupled to the positive differential output and the negative differential output of at least one of the in-phase mixer or the quadrature mixer; and a digital-to-analog converter (DAC) having an input coupled to the current sensing circuit and an output coupled to at least one of the in-phase V2I converter or the quadrature V2I converter.

[0120] Aspect 16: An apparatus according to Aspect 15, wherein the current sensing circuit includes: a first resistive element selectively coupled to the positive differential output or the negative differential output, and a second resistive element selectively coupled to the positive differential output or the negative differential output; and an analog-to-digital converter (ADC) having a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

[0121] Aspect 17: An apparatus according to Aspect 16, wherein: the ADC is configured to: sense a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; and sense a second voltage at the second resistive element when the second resistive element is coupled to the negative differential output; and the DAC is configured to bias at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of an I V2I converter or a Q V2I converter.

[0122] Aspect 18: An apparatus according to Aspect 17, wherein: the ADC is configured to: sense a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; and sense a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; and the DAC is configured to bias at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of an I V2I converter or a Q V2I converter.

[0123] Aspect 19: The apparatus of any one of aspects 10-18, wherein the in-phase mixer and the quadrature mixer comprise harmonic rejection mixers.

[0124] Aspect 20: The apparatus according to Aspect 10 further includes: a first signal path coupled to a differential output pair of at least one of an in-phase mixer or a quadrature mixer; and a second signal path coupled to a differential output pair of at least one of the in-phase mixer or the quadrature mixer, wherein the first signal path and the second signal path are also coupled to a transmitter port of the apparatus.

[0125] Aspect 21: An apparatus according to Aspect 20, wherein the first signal path comprises: a first balanced-unbalanced (balanced-unbalanced transformer) component having an unbalanced terminal coupled to the transmitter port; a first switch coupled between a first differential output of the differential output pair and a first balanced terminal of the first balun component; and a second switch coupled between a second differential output of the differential output pair and a second balanced terminal of the first balun component.

[0126] Aspect 22: An apparatus according to Aspect 21, wherein the second signal path includes: a second balun component having an unbalanced terminal coupled to the transmitter port; a third switch coupled between the first differential output of the differential output pair and the first balanced terminal of the second balun component; and a fourth switch coupled between the second differential output of the differential output pair and the second balanced terminal of the second balun component.

[0127] Aspect 23: The apparatus of any of Aspects 21-22, wherein the first signal path further comprises: a third switch coupled between the first differential output and the second balanced terminal; and a fourth switch coupled between the second differential output and the first balanced terminal.

[0128] Aspect 24: The apparatus according to any one of aspects 10-23, further comprising a transceiver, the transceiver comprising an I mixer and a Q mixer.

[0129] Aspect 25: The apparatus according to aspect 24, wherein the transceiver is part of a base station.

[0130] Aspect 26: A method for wireless communication, comprising: generating an in-phase level-shifted signal via an in-phase direct current (DC) level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase voltage-to-current (V2I) converter; converting the quadrature level-shifted signal into a quadrature current via a quadrature V2I converter; sensing a signal at a node of the in-phase V2I converter and the quadrature V2I converter via a bias control circuit; providing a bias signal to at least one of the in-phase DC level shifter or the quadrature DC level shifter based on the sensing; generating an up-converted in-phase signal via an in-phase mixer based on the in-phase current; and generating an up-converted quadrature signal via a quadrature mixer based on the quadrature current.

[0131] Aspect 27: A method according to Aspect 26, wherein: the in-phase DC level shifter includes a first source follower; generating an in-phase level-shifted signal includes level-shifting the in-phase signal using the first source follower to generate an in-phase level-shifted signal; the orthogonal DC level shifter includes a second source follower; and generating a quadrature level-shifted signal includes level-shifting the quadrature signal using the second source follower to generate a quadrature level-shifted signal.

[0132] Aspect 28: A method according to Aspect 27, wherein: the in-phase V2I converter includes a first tail current source; the orthogonal V2I converter includes a second tail current source; and the sensed signal includes a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; and the bias signal is provided to the gate of the bias transistor of at least one of the first source follower or the second source follower.

[0133] Aspect 29: The method according to any one of Aspects 26-28 further includes: sensing the positive differential output current and the negative differential output current of at least one of the in-phase mixer or the quadrature mixer via a current sensing circuit, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current.

[0134] Aspect 30: A method according to any one of Aspects 26-29, wherein at least one of the in-phase mixer or the quadrature mixer includes a positive differential output and a negative differential output, the method further comprising: sensing a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; sensing a second voltage at the second resistive element when the second resistive element is coupled to the negative differential output; and biasing at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage.

[0135] Aspect 31: The method according to Aspect 30 further includes: sensing a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; sensing a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; and biasing at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage.

[0136] Aspect 32: The method according to any one of aspects 26-31, wherein the in-phase mixer and the quadrature mixer comprise harmonic rejection mixers.

[0137] Aspect 33: A method according to any of Aspects 26-32, wherein one of the in-phase mixer or the quadrature mixer includes a positive differential output and a negative differential output, the method further comprising: routing at least a portion of the current from the positive differential output to a first balanced terminal of a first balanced-unbalanced (balanced-unbalanced transformer) component via a first switch of a first current path; and routing at least a portion of the current from a second balanced terminal of the balun component to the negative differential output via a second switch of a second current path, wherein the unbalanced terminal of the balun component is coupled to a transmitter port.

[0138] Aspect 34: The method of Aspect 33, further comprising routing at least another portion of the current from the positive differential output to the second current path via a third switch.

[0139] Aspect 35: An apparatus for wireless communication, comprising: an in-phase direct current (DC) level shifter; a quadrature DC level shifter; an in-phase voltage-to-current (V2I) converter having an input coupled to an output of the in-phase DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; a quadrature mixer having an input coupled to an output of the quadrature V2I converter; a current sensing circuit having an input coupled to a positive differential output and a negative differential output of at least one of the in-phase mixer or the quadrature mixer; and a digital-to-analog converter (DAC) having an input coupled to the current sensing circuit and an output coupled to at least one of the in-phase V2I converter or the quadrature V2I converter.

[0140] Aspect 36: An apparatus according to Aspect 35, wherein the current sensing circuit includes: a first resistive element selectively coupled to the positive differential output or the negative differential output, and a second resistive element selectively coupled to the positive differential output or the negative differential output; and an analog-to-digital converter (ADC) having a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

[0141] Aspect 37: An apparatus according to Aspect 36, wherein: the ADC is configured to: sense a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; and sense a second voltage at the second resistive element when the second resistive element is coupled to the negative differential output; and the DAC is configured to bias at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of an IV2I converter or a Q V2I converter.

[0142] Aspect 38: An apparatus according to Aspect 37, wherein: the ADC is configured to: sense a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; and sense a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; and the DAC is configured to bias at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of an IV2I converter or a Q V2I converter.

[0143] Aspect 39: A method for wireless communication, comprising: generating an in-phase level-shifted signal via an in-phase direct current (DC) level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase voltage-to-current (V2I) converter; converting the quadrature level-shifted signal into a quadrature current via a quadrature V2I converter; sensing a positive differential output current and a negative differential output current of at least one of an in-phase mixer or a quadrature mixer via a current sensing circuit, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current; generating an up-converted in-phase signal via the in-phase mixer based on the in-phase current; and generating an up-converted quadrature signal via the quadrature mixer based on the quadrature current.

[0144] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or having advantages over other aspects of the disclosure. Similarly, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage, or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other—even if objects A and C are not directly in physical contact with each other. For example, a first object can be coupled to a second object even if the first object has never been in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of electrical devices and conductors that, when connected and configured, enable the functions described in this disclosure to be performed, without limitation to the type of electronic circuitry.

[0145] The apparatuses and methods described in the detailed description are shown in the drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). For example, these elements may be implemented using hardware.

[0146] One or more of the components, steps, features, and / or functions shown herein may be rearranged and / or combined into a single component, step, feature, or function, or may be embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from the features disclosed herein. The devices, equipment, and / or components shown herein may be configured to perform one or more of the methods, features, or steps described herein.

[0147] It is to be understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of exemplary processes. Based on design preferences, it is to be understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented unless expressly recited herein.

[0148] Provide the above description so that any person skilled in the art can put into practice the various aspects described herein.It will be apparent to those skilled in the art that various modifications to these aspects, and the general principles defined herein can be applied to other aspects.Therefore, claim is not intended to be limited to the various aspects shown herein, but to be given the full scope consistent with the language of claim, wherein unless explicitly stated so, otherwise the mentioning of the element in the singular form is not intended to mean "one and only one", but "one or more".Unless otherwise clearly stated, otherwise term "some" refers to one or more.The phrase of "at least one" mentioned in the item list refers to any combination of those items, including single members.As an example, "at least one of the following: a, b or c" is intended to at least contain: a, b, c, ab, ac, bc and abc and any combination with multiple identical elements (for example, aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc, or any other sorting of a, b and c). All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is expressly recited in the claims. No claim element is to be construed under 35 USC §112(f) unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”

[0149] It is to be understood that the claims are not limited to the precise configuration and components shown above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An apparatus for wireless communication, comprising: In-phase direct current (DC) level shifter; Quadrature DC level shifter; a non-inverting voltage-to-current (V2I) converter having an input coupled to an output of the non-inverting DC level converter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; a bias control circuit having inputs coupled to the in-phase V2I converter and the quadrature V2I converter, an output of the bias control circuit coupled to at least one of the in-phase DC level converter or the quadrature DC level converter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; as well as A quadrature mixer has an input coupled to the output of the quadrature V2I converter.

2. The device according to claim 1, wherein: The in-phase DC level shifter includes a first source follower circuit configured to DC level shift an in-phase signal; and The quadrature DC level shifter includes a second source follower circuit configured to DC level shift the quadrature signals.

3. The device according to claim 2, wherein: The in-phase V2I converter includes a first tail current source; The quadrature V2I converter includes a second tail current source; and The bias control circuit is configured to: sensing a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; as well as At least one of the first source follower circuit or the second source follower circuit is biased based on the first VDS and the second VDS.

4. The device according to claim 3, wherein The bias control circuit includes an amplifier having a first input configured to receive an average of the first VDS and the second VDS, a second input configured to receive a reference voltage, and an output coupled to a gate of a bias transistor of at least one of the first source follower circuit or the second source follower circuit.

5. The apparatus of claim 2 , further comprising a phase interpolator comprising: a first output coupled to an input of the first source follower circuit and configured to generate the in-phase signal; as well as A second output is coupled to the input of the second source follower circuit and is configured to generate the quadrature signal.

6. The apparatus according to claim 1, further comprising: a current sensing circuit having inputs coupled to the positive differential output and the negative differential output of at least one of the in-phase mixer or the quadrature mixer; as well as A digital-to-analog converter (DAC) has an input coupled to the current sensing circuit and an output coupled to the at least one of the in-phase V2I converter or the quadrature V2I converter.

7. The device according to claim 6, wherein The current sensing circuit includes: a first resistive element selectively coupled to the positive differential output or the negative differential output and a second resistive element selectively coupled to the positive differential output or the negative differential output; and An analog-to-digital converter (ADC) has a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

8. The apparatus according to claim 7, wherein: The ADC is configured as follows: sensing a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; as well as sensing a second voltage at the second resistive element when the second resistive element is coupled to the negative differential output; as well as A DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of the I V2I converter or the Q V2I converter.

9. The apparatus according to claim 8, wherein: The ADC is configured as follows: sensing a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; as well as sensing a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; as well as The DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of the I V2I converter or the Q V2I converter.

10. The device according to claim 1, wherein The in-phase mixer and the quadrature mixer include harmonic rejection mixers.

11. The apparatus according to claim 1 , further comprising: a first signal path coupled to a differential output pair of at least one of the in-phase mixer or the quadrature mixer; as well as A second signal path is coupled to the differential output pair of at least one of the in-phase mixer or the quadrature mixer, wherein the first and second signal paths are also coupled to a transmitter port of the device.

12. The device according to claim 11, wherein The first signal path includes: a first balanced-unbalanced (balun) component having an unbalanced terminal coupled to the transmitter port; a first switch coupled between a first differential output of the differential output pair and a first balanced terminal of the first balun assembly; and A second switch is coupled between a second differential output of the differential output pair and a second balanced terminal of the first balun component.

13. The device according to claim 12, wherein The second signal path includes: a second balun assembly having an unbalanced terminal coupled to the transmitter port; a third switch coupled between the first differential output of the differential output pair and a first balanced terminal of the second balun assembly; and A fourth switch is coupled between the second differential output of the differential output pair and a second balanced terminal of the second balun component.

14. The device according to claim 12, wherein The first signal path further comprises: a third switch coupled between the first differential output and the second balanced terminal; and A fourth switch is coupled between the second differential output and the first balanced terminal.

15. The apparatus of claim 1, further comprising a transceiver comprising the I mixer and the Q mixer.

16. The device according to claim 15, wherein The transceiver is part of a base station.

17. A method for wireless communication, comprising: generating an in-phase level-shifted signal via an in-phase direct current (DC) level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase voltage-to-current (V2I) converter; converting the quadrature level-shifted signals into quadrature currents via a quadrature V2I converter; sensing signals at nodes of the in-phase V2I converter and the quadrature V2I converter via a bias control circuit; providing a bias signal to at least one of the in-phase DC level shifter or the quadrature DC level shifter based on the sensing; generating an up-converted in-phase signal via an in-phase mixer based on the in-phase current; as well as An up-converted quadrature signal is generated via a quadrature mixer based on the quadrature current.

18. The method according to claim 17, wherein: The in-phase DC level shifter includes a first source follower; Generating the in-phase level-shifted signal includes level-shifting the in-phase signal using the first source follower to generate the in-phase level-shifted signal; The quadrature DC level shifter includes a second source follower; and Generating the quadrature level-shifted signal includes level-shifting the quadrature signal using the second source follower to generate the quadrature level-shifted signal.

19. The method according to claim 18, wherein: The in-phase V2I converter includes a first tail current source; The orthogonal V2I converter includes a second tail current source; and The sensed signal includes a first drain-to-source voltage (VDS) associated with the first tail current source and a second VDS associated with the second tail current source; as well as The bias signal is provided to a gate of a bias transistor of at least one of the first source follower or the second source follower.

20. The method according to claim 17, wherein Also includes: A positive differential output current and a negative differential output current of at least one of the in-phase mixer or the quadrature mixer are sensed via a current sensing circuit, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current.

21. The method according to claim 17, wherein At least one of the in-phase mixer or the quadrature mixer includes a positive differential output and a negative differential output, the method further comprising: sensing a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; sensing a second voltage at a second resistive element when the second resistive element is coupled to the negative differential output; and The at least one of the in-phase mixer or the quadrature mixer is biased based on the first voltage and the second voltage.

22. The method according to claim 21, further comprising: sensing a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; sensing a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; as well as The at least one of the in-phase mixer or the quadrature mixer is biased based on the third voltage and the fourth voltage.

23. The method according to claim 17, wherein The in-phase mixer and the quadrature mixer include harmonic rejection mixers.

24. The method according to claim 17, wherein One of the in-phase mixer or the quadrature mixer includes a positive differential output and a negative differential output, the method further comprising: routing at least a portion of the current from the positive differential output to a first balanced terminal of a first balanced-unbalanced (balun) component via a first switch of a first current path; and The at least a portion of the current is routed from a second balanced terminal of the balun assembly toward the negative differential output via a second switch of a second current path, wherein an unbalanced terminal of the balun assembly is coupled to a transmitter port.

25. The method according to claim 24, further comprising: At least another portion of the current is routed from the positive differential output to the second current path via a third switch.

26. An apparatus for wireless communication, comprising: In-phase direct current (DC) level shifter; Quadrature DC level shifter; a non-inverting voltage-to-current (V2I) converter having an input coupled to the output of the non-inverting DC level shifter; a quadrature V2I converter having an input coupled to an output of the quadrature V2I converter; an in-phase mixer having an input coupled to an output of the in-phase V2I converter; a quadrature mixer having an input coupled to an output of the quadrature V2I converter; a current sensing circuit having inputs coupled to the positive differential output and the negative differential output of at least one of the in-phase mixer or the quadrature mixer; as well as A digital-to-analog converter (DAC) has an input coupled to the current sensing circuit and an output coupled to the at least one of the in-phase V2I converter or the quadrature V2I converter.

27. The apparatus of claim 26, wherein: The current sensing circuit includes: a first resistive element selectively coupled to the positive differential output or the negative differential output and a second resistive element selectively coupled to the positive differential output or the negative differential output; and An analog-to-digital converter (ADC) has a first input selectively coupled to the first resistive element and a second input selectively coupled to the second resistive element.

28. The apparatus of claim 27, wherein: The ADC is configured as follows: sensing a first voltage at the first resistive element when the first resistive element is coupled to the positive differential output; as well as sensing a second voltage at the second resistive element when the second resistive element is coupled to the negative differential output; as well as The DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the first voltage and the second voltage using at least one of the IV2I converter or the Q V2I converter.

29. The apparatus of claim 28, wherein: The ADC is configured as follows: sensing a third voltage at the first resistive element when the first resistive element is coupled to the negative differential output; as well as sensing a fourth voltage at the second resistive element when the second resistive element is coupled to the positive differential output; as well as The DAC is configured to bias the at least one of the in-phase mixer or the quadrature mixer based on the third voltage and the fourth voltage using at least one of the IV2I converter or the Q V2I converter.

30. A method for wireless communication, comprising: generating an in-phase level-shifted signal via an in-phase direct current (DC) level shifter; generating a quadrature level-shifted signal via a quadrature DC level shifter; converting the in-phase level-shifted signal into an in-phase current via an in-phase voltage-to-current (V2I) converter; converting the quadrature level-shifted signals into quadrature currents via a quadrature V2I converter; sensing, via a current sensing circuit, a positive differential output current and a negative differential output current of at least one of an in-phase mixer or a quadrature mixer, wherein at least one of the in-phase current or the quadrature current is generated based on the sensed positive differential output current and the sensed negative differential output current; generating an up-converted in-phase signal via the in-phase mixer based on the in-phase current; and An up-converted quadrature signal is generated via the quadrature mixer based on the quadrature current.

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