Power semiconductor device and method for producing power semiconductor device

Abstract

A power semiconductor device (1) is specified, comprising a first electrode (2), a first semiconductor layer (3) of a first conductivity type, a drift layer (4) of the first conductivity type, a second semiconductor layer (5) of a second conductivity type different from the first conductivity type, and a second electrode (6), at least one of the first semiconductor layer (3) and the second semiconductor layer (5) comprises an oxide layer (24) which extends in an active region (9) of the power semiconductor device (1) surrounded by a termination region (8) of the power semiconductor device (1), and at least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a ramp structure (19). The invention further relates to a method for producing a power semiconductor component (1).

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing a power semiconductor device. Summary of the Invention

[0002] Embodiments of the present disclosure relate to a power semiconductor device with improved performance. Further embodiments of the present disclosure relate to a method for manufacturing such a power semiconductor device.

[0003] This is achieved by the subject-matter of the independent claims. Further embodiments are apparent from the dependent claims described below.

[0004] A power semiconductor device is described. Here and hereinafter, the term "power" refers, for example, to a power semiconductor module, a power semiconductor device, and / or a power semiconductor chip that is suitable for handling voltages and currents exceeding 100 V and / or exceeding 10 A (e.g., voltages up to 10 kV and amperes up to 10 kA).

[0005] According to an embodiment, a power semiconductor device includes a first electrode. The first electrode exemplarily extends in a lateral direction. For example, the first electrode is configured to make conductive contact with an external portion. Exemplarily, the first electrode includes or consists of metal.

[0006] The first electrode may include a first layer and a second layer stacked one above the other in a vertical direction perpendicular to the lateral direction. For example, the first layer may include a different metal than the second layer. The first layer may illustratively include molybdenum, while the second layer may illustratively include aluminum and / or other metals (e.g., copper, titanium, and / or nickel). Specifically, the first layer is configured to make conductive contact with the outside, while the second layer is a metallization layer. For example, the metallization layer may be applied using a sputtering process or an evaporation process.

[0007] According to an embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type. The first semiconductor layer illustratively extends in a lateral direction. For example, the first semiconductor layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material is silicon-based. The first semiconductor layer includes, for example, a first dopant of the first conductivity type.

[0008] According to an embodiment, a power semiconductor device includes a drift layer of a first conductivity type. The drift layer illustratively extends in a lateral direction. For example, the drift layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material includes or consists of the same material as the first semiconductor layer. The drift layer includes, for example, a first additional dopant of the first conductivity type. The first additional dopant of the drift layer is, for example, the same dopant as the dopant in the first semiconductor layer.

[0009] For example, the maximum doping concentration of the drift layer is lower than the maximum doping concentration of the first semiconductor layer. For example, the maximum doping concentration of the drift layer is lower than the maximum doping concentration of the first semiconductor layer by at least one order of magnitude.

[0010] According to an embodiment, a power semiconductor device includes a second semiconductor layer of a second conductivity type different from the first conductivity type. The second semiconductor layer illustratively extends in a lateral direction. For example, the second semiconductor layer includes or consists of a semiconductor material. Exemplarily, the semiconductor material includes or consists of the same material as the first semiconductor layer. The first semiconductor layer includes, for example, a second dopant of the second conductivity type.

[0011] For example, the first conductivity type is an n-type conductivity type, and the second conductivity type is a p-type conductivity type, or vice versa. For example, the first dopant is an n-type dopant, and the second dopant is a p-type dopant, or vice versa.

[0012] According to an embodiment, the power semiconductor device includes a second electrode. The second electrode illustratively extends in a lateral direction. For example, the second electrode is configured to make conductive contact with the outside. For example, the second electrode includes or consists of metal.

[0013] The second electrode may include a third layer and a fourth layer stacked vertically one above the other. For example, the third layer may include a different metal than the fourth layer. The third layer may illustratively include aluminum and / or other metals (e.g., copper, titanium, nickel, tungsten, platinum, and / or gold), while the fourth layer may illustratively include molybdenum. In particular, the third layer is a metallization layer, and the other layers are configured to make conductive contact with the outside.

[0014] For example, the first electrode is a cathode electrode of the power semiconductor device, and the second electrode is an anode electrode of the power semiconductor device, or vice versa.

[0015] For example, the first layer and the fourth layer do not exist in the power semiconductor device. For example, the first layer and the fourth layer are provided for processing the power semiconductor device, wherein the first electrode only includes the second layer, and the second electrode only includes the third layer.

[0016] According to an embodiment of the power semiconductor device, an oxide layer is arranged on at least one of the first semiconductor layer and the second semiconductor layer, the oxide layer extending in an active area of ​​the power semiconductor device surrounded by a termination region of the power semiconductor device. The termination region is a peripheral area of ​​the power semiconductor device, and the active area is a central area of ​​the power semiconductor device. The peripheral area completely surrounds the active area in a lateral direction.

[0017] The active region is located at the center of mass of the power semiconductor device and extends in a lateral direction in a direction to at least one edge of the power semiconductor device. The termination region extends in a lateral direction along an edge region of the power semiconductor device that delimits the active region.

[0018] For example, the oxide layer is arranged only on the first semiconductor layer or only on the second semiconductor layer. Alternatively, the oxide layer is arranged on both the first semiconductor layer and the second semiconductor layer.

[0019] The oxide layer extends within the active region, particularly from the termination region toward the centroid. Exemplarily, the oxide layer has a circular, elliptical, or polygonal (e.g., quadrilateral) shape in a plan view. In particular, the shape of the oxide layer in a plan view corresponds to the outer shape of the power semiconductor device (particularly the drift layer) in a plan view.

[0020] If the oxide layer is arranged on the first semiconductor layer, the oxide layer faces the first electrode. The oxide layer comprises, in particular, oxidized semiconductor material of the first semiconductor layer.

[0021] Exemplarily, the oxide layer is produced by locally applying a plasma-enhanced chemical vapor deposition (PECVD) process to the bottom surface of the first semiconductor layer. Specifically, the material of the oxide layer is applied to, and in particular, completely applied to, the bottom surface of the first semiconductor layer. Subsequently, a photoresist is exemplarily applied to, and in particular, completely applied to, the bottom surface of the material of the oxide layer. For example, the photoresist is structured, in particular, using a mask, to produce the oxide layer.

[0022] For example, the oxide layer protrudes beyond the first semiconductor layer in a vertical direction in a direction to the first electrode.

[0023] If the oxide layer is arranged on the second semiconductor layer, the oxide layer faces the second electrode. The oxide layer comprises, in particular, oxidized semiconductor material of the second semiconductor layer.

[0024] The oxide layer is exemplarily produced by locally applying a plasma-enhanced chemical vapor deposition (PECVD) process to the top surface of the first semiconductor layer. In particular, the material of the oxide layer is applied, in particular completely, to the top surface of the second semiconductor layer. Subsequently, a photoresist is exemplarily applied, in particular completely, to the top surface of the material of the oxide layer. For example, the photoresist is structured, in particular, using a mask, to produce the oxide layer.

[0025] For example, the oxide layer protrudes beyond the second semiconductor layer in a vertical direction in a direction to the second electrode.

[0026] The oxide layer has a height in the vertical direction of at most 1 μm.

[0027] For example, the power semiconductor described herein is a fast recovery diode, particularly a free-floating discrete fast recovery diode. Furthermore, the power semiconductor described herein can be a reverse-conducting integrated gate-commutated thyristor (RC-IGCT). The RC-IGCT includes a diode portion and a gate-commutated thyristor (GCT) portion, with a separation region disposed between the diode and GCT portions. The diode includes all elements of the active region described herein, and the separation region is formed by all elements of the termination region.

[0028] In summary, such a power semiconductor component having a combination of a first semiconductor layer and / or a second semiconductor layer and an oxide layer can particularly provide the following advantages.

[0029] Advantageously, the oxide layer reduces emitter injection efficiency in the termination region. Due to the presence of the oxide region, by significantly reducing emitter injection efficiency in the termination region, the termination region of the power semiconductor device is effectively electrically disconnected from operation in the on state. Advantageously, less heat is generated in the termination region, where cooling capacity is lower. Consequently, thermal stability is improved during high-frequency operation or during surge current events, enabling the power semiconductor device to operate at higher temperatures.

[0030] Due to the presence of the oxide layer in the active region (and in particular in the active region adjoining the termination region), the emitter injection efficiency can advantageously be reduced and particularly precisely predetermined.

[0031] According to another embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer, and the second electrode are stacked vertically one above the other along a stacking direction. Directly adjacent elements are, for example, in direct contact with one another. Exemplarily, the first layer of the first electrode faces away from the first semiconductor layer, while the second layer of the first electrode faces the first semiconductor layer. Exemplarily, the third layer of the second electrode faces the second semiconductor layer, while the fourth layer of the second electrode faces away from the second semiconductor layer.

[0032] According to another embodiment of the power semiconductor device, the first semiconductor layer includes a first sublayer facing the first electrode and a second sublayer facing the drift layer. For example, the maximum doping concentration of the first sublayer is higher than the maximum doping concentration of the second sublayer. For example, the maximum doping concentration of the first sublayer is at least one order of magnitude higher than the maximum doping concentration of the second sublayer.

[0033] According to another embodiment of the power semiconductor device, the second semiconductor layer includes a third sublayer facing the drift layer and a fourth sublayer facing the second electrode. For example, the maximum doping concentration of the fourth sublayer is higher than the maximum doping concentration of the third sublayer. For example, the maximum doping concentration of the fourth sublayer is at least one order of magnitude higher than the maximum doping concentration of the third sublayer.

[0034] According to another embodiment of the power semiconductor device, one of the first electrode and the second electrode extends over the active region and the termination region. In particular, only one of the first electrode and the second electrode extends over the active region and the termination region.

[0035] For example, the first electrode extends laterally to completely cover the first semiconductor layer. Specifically, the second layer of the first electrode completely (particularly in the active region and the termination region) covers the bottom surface of the first sublayer of the first semiconductor layer. Exemplarily, the first layer of the first electrode covers the second layer of the first electrode only in the active region. In other words, the first layer of the first electrode extends laterally only in the active region.

[0036] Alternatively, the second electrode extends laterally to completely cover the second semiconductor layer. Specifically, the third layer of the second electrode completely (particularly in the active region and the termination region) covers the top surface of the fourth sublayer of the second semiconductor layer. Exemplarily, the fourth layer of the second electrode covers the third layer of the second electrode only in the active region. That is, the fourth layer of the second electrode extends laterally only in the active region.

[0037] According to a further embodiment of the power semiconductor device, the other of the first electrode and the second electrode extends only over the active region.

[0038] If the first electrode extends in the lateral direction and completely covers the first semiconductor layer, ie covers the active area and the termination area, the second electrode extends only on the active area. In particular, the third and fourth layers of the second electrode have the same extent in the lateral direction.

[0039] If the second electrode extends in a lateral direction and completely covers the second semiconductor layer, ie covers the active area and the termination area, the first electrode extends only on the active area. In particular, the first layer and the second layer of the first electrode have the same extent in a lateral direction.

[0040] According to another embodiment of the power semiconductor device, the fourth sublayer extends laterally over the active region and the termination region. For example, the fourth sublayer overlaps the active region and at least partially overlaps the termination region in a plan view. If the second semiconductor layer has a bevel structure, the fourth sublayer overlaps the termination region by at least 20% or at least 50% in a plan view.

[0041] According to another embodiment of the power semiconductor device, the fourth sublayer extends only on the active region. In particular, the fourth sublayer overlaps only with the active region in a plan view, but does not overlap with the termination region.

[0042] This advantageously further reduces the emitter efficiency in the termination region.

[0043] According to an embodiment of the power semiconductor device, at least one of the first semiconductor layer and the second semiconductor layer has a sloped structure. Exemplarily, the first semiconductor layer and the second semiconductor layer each have a bottom surface and a top surface, both extending in a lateral direction, wherein the top surface and the bottom surface are connected to at least one side surface. The side surface of at least one of the first semiconductor layer and the second semiconductor layer is inclined relative to a vertical direction in a termination region.

[0044] For example, the inclined surface structure is arranged in the termination area. In particular, the inclined surface structure is only arranged in the termination area. That is to say, the inclined surface structure defines the extent of the termination area in the lateral direction.

[0045] According to another embodiment of the power semiconductor device, the second semiconductor layer tapers toward the second electrode in the termination region. The slope structure is arranged in the second semiconductor layer such that a side surface of the second semiconductor layer forms an angle less than 90° with a top surface of the drift layer.

[0046] Depending on the angle, ie depending on the steepness of the slope structure, the junction depth can be predetermined. This means that depending on the angle, the emitter efficiency in the termination region can be precisely preset.

[0047] According to another embodiment of the power semiconductor device, the first semiconductor layer tapers toward the first electrode in the termination region. The slope structure is arranged in the first semiconductor layer such that a side surface of the first semiconductor layer forms an angle less than 90° with a bottom surface of the drift layer.

[0048] Advantageously, the emitter efficiency in the termination region can be preset particularly precisely depending on the angle.

[0049] According to another embodiment of the power semiconductor device, the oxide layer is located on the first sublayer, in the active area and the termination area. Exemplarily, a bottom surface of the first sublayer and a bottom surface of the oxide layer are not in a common plane.

[0050] Exemplarily, the oxide layer extends to only partially cover the active region and completely cover the termination region.If the slope structure is arranged in the second semiconductor layer, the oxide layer completely covers the first electrode in the termination region.

[0051] Alternatively, if the slope structure is arranged in the first semiconductor layer, the oxide layer completely covers the second electrode in the termination region.

[0052] According to another embodiment of the power semiconductor device, the oxide layer is located between the first sublayer and the first electrode. Exemplarily, the bottom surface of the first sublayer and the bottom surface of the oxide layer are in direct contact with the first electrode, in particular the second layer.

[0053] According to another embodiment of the power semiconductor device, the oxide layer extends in a lateral direction from the termination region into the active region up to an extension distance. In particular, the oxide layer extends in a lateral direction from an interface between the termination region and the active region up to an extension distance in the active region in a lateral direction.

[0054] According to another embodiment of the power semiconductor device, the extension distance is at least 1 times and at most 7 times the height of the drift layer in the vertical direction. In particular, the extension distance is at least 3 times and at most 5 times the height of the drift layer.

[0055] This extension advantageously reduces the emitter efficiency at the interface between the termination regions in the active region.

[0056] According to another embodiment of the power semiconductor device, another oxide layer is located on the fourth sublayer and in the active region. Exemplarily, a top surface of the fourth sublayer and a top surface of the another oxide layer are not in a common plane.

[0057] If the slope structure is arranged in the second semiconductor layer, the further oxide layer only partially covers the second electrode in the active region. The termination region is free of the further oxide layer, for example.

[0058] Alternatively, if the slope structure is arranged in the first semiconductor layer, the further oxide layer only partially covers the first electrode in the active region. The termination region is free of the further oxide layer, for example.

[0059] According to another embodiment of the power semiconductor device, a further oxide layer is located between the fourth sublayer and the second electrode. Exemplarily, a top surface of the fourth sublayer and a top surface of the oxide layer are in direct contact with the second electrode, in particular the third layer.

[0060] According to another embodiment of the power semiconductor device, the further oxide layer extends in a lateral direction from the termination region into the active region to a further extension distance. In particular, the further oxide layer extends in a lateral direction from an interface between the termination region and the active region to a further extension distance in the active region in a lateral direction.

[0061] According to another embodiment of the power semiconductor device, the further extension distance is at least 1 times and at most 7 times the height of the drift layer in the vertical direction. In particular, the further extension distance is at least 3 times and at most 5 times the height of the drift layer.

[0062] The further extension distance may be equal to the extension distance. Alternatively, the further extension distance is different from the extension distance.

[0063] According to another embodiment, the power semiconductor device includes a passivation layer. For example, the passivation layer encapsulates layers of the power semiconductor device. In particular, portions of the first electrode and portions of the second electrode are free of the passivation layer. Exemplarily, the first layer of the first electrode and the fourth layer of the second electrode are free of the passivation layer.

[0064] The passivation layer comprises an electrically insulating material, such as a dielectric. For example, the passivation layer comprises a semi-insulating material at the surface of silicon. In addition to insulating the semiconductor surface from the surrounding environment, this material also serves to drain leakage current to one of the electrodes, particularly at elevated temperatures.

[0065] According to another embodiment of the power semiconductor device, the first electrode, the first semiconductor layer, the drift layer, the second semiconductor layer and the second electrode are surrounded by a passivation layer in the termination region. For example, the side surfaces of these layers and the electrodes are completely covered by the passivation layer.

[0066] Exemplarily, the inclined surface structure is completely embedded in the passivation layer, that is, the side surface forming the inclined surface structure is completely covered by the passivation layer.

[0067] Advantageously, due to the presence of the passivation layer, the power semiconductor device is protected from environmental influences.

[0068] According to a further embodiment of the power semiconductor device, the first semiconductor layer is constructed of several doping regions of the second conductivity type in the termination region.

[0069] These doped regions extend within the termination region. Exemplarily, each doped region has a circular, elliptical, or polygonal (e.g., quadrilateral) shape in plan view. In particular, the shape of the doped region in plan view corresponds to the outer shape of the power semiconductor device (particularly the drift layer) in plan view.

[0070] For example, the doped region is disposed in the semiconductor layer, and the oxide layer is not disposed on the semiconductor layer. If the first semiconductor layer includes the doped region, the oxide layer is disposed on the second semiconductor layer. If the second semiconductor layer includes the doped region, the oxide layer is disposed on the first semiconductor layer.

[0071] Exemplarily, the first sublayer includes a doped region, and / or the fourth sublayer includes a doped region.

[0072] According to another embodiment of the power semiconductor device, the first sublayer is separated into segments in a lateral direction by doped regions. For example, the segments are separated in a lateral direction by doped regions. This means that directly adjacent segments are not in physical contact with each other.

[0073] By means of a doped region, in particular a combination of an oxide layer and a doped region, the emitter efficiency can be particularly precisely predetermined and reduced.

[0074] Furthermore, this document describes a method for manufacturing a power semiconductor device, by which a power semiconductor device as described above can be manufactured or produced. Therefore, features related to the power semiconductor device are also disclosed in conjunction with this method, and vice versa.

[0075] According to an embodiment of the method, a semiconductor material having a drift layer is provided. Exemplarily, the semiconductor material is based on silicon. The semiconductor material is particularly provided as a wafer.

[0076] Exemplarily, the drift layer of the first conductivity type is produced during the pulling of the silicon ingot. In other words, it exists in the starting silicon wafer before production.

[0077] According to an embodiment of the method, a first semiconductor layer of a first conductivity type is fabricated on a first side of the drift layer. For example, a first dopant is incorporated into the wafer (e.g., the first side of the drift layer) by at least one of ion implantation or a deposition process, which may be followed by a diffusion process.

[0078] According to an embodiment of the method, a second semiconductor layer of a second conductivity type different from the first conductivity type is fabricated on a second side of the drift layer opposite the first side. For example, the second dopant is incorporated into the wafer (e.g., the second side of the drift layer) by at least one of ion implantation or a deposition process, followed by a subsequent diffusion process.

[0079] According to an embodiment of the method, a slope structure is produced in at least one of the first semiconductor layer and the second semiconductor layer in a termination region surrounding an active region of the power semiconductor device.

[0080] According to an embodiment of the method, an oxide layer is produced on at least one of the first semiconductor layer or the second semiconductor layer.

[0081] According to another embodiment of the method, the bevel structure is produced by a grinding process. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] The accompanying drawings are included to provide further understanding. In the accompanying drawings, elements of the same structure and / or function may be represented by the same reference numerals. It should be understood that the embodiments shown in the accompanying drawings are illustrative representations and are not necessarily drawn to scale.

[0083] Figures 1 to 3 are cross-sectional views of a power semiconductor device according to an exemplary embodiment, Figure 4 is a schematic plan view of a power semiconductor device according to an exemplary embodiment, and Figure 5 is an exemplary graph of hole density of a power semiconductor device under different exemplary embodiments. DETAILED DESCRIPTION

[0084] according to Figure 1 The power semiconductor device 1 of the exemplary embodiment includes a first electrode 2 and a second electrode 6. The first electrode includes a first layer 14 and a second layer 15, and the second electrode includes a third layer 16 and a fourth layer 17. The power semiconductor device 1 further includes a first semiconductor layer 3 of a first conductivity type and a second semiconductor layer 5 of a second conductivity type. The first semiconductor layer includes a first sublayer 10 and a second sublayer 11, and the second semiconductor layer includes a third sublayer 12 and a fourth sublayer 13. Furthermore, the power semiconductor device 1 includes a drift layer 4.

[0085] The first electrode 2 (particularly the first layer 14 and the second layer 15), the first semiconductor layer 3 (particularly the first sublayer 10 and the second sublayer 11), the drift layer 4, the second semiconductor layer 5 (particularly the third sublayer 12 and the fourth sublayer 13), and the second electrode 6 (particularly the third layer 16 and the fourth layer 17) are stacked one above the other in a stacking direction corresponding to the vertical direction. Each of these layers extends in a lateral direction perpendicular to the vertical direction. Furthermore, each of these layers is in direct contact with one another. The bottom surfaces of these layers face the first electrode 2, and the top surfaces of these layers face the second electrode 6.

[0086] The second layer 15 of the first electrode 2 completely covers the bottom surface of the first sublayer 10 of the first semiconductor layer 3. The first layer 14 of the first electrode 2 completely covers the bottom surface of the second layer 15 only in the active area 9 of the power semiconductor device 1. This means that the first layer 14 completely overlaps, and in particular completely coincides with, the active area 9 in a plan view and in a lateral direction.

[0087] In particular, the plan view is a view on the top surface of each element of the power semiconductor device 1 in the vertical direction.

[0088] The active region 9 is located at the center of mass of the power semiconductor device 1 and extends in a lateral direction around the center of mass. Figure 1 Only half of the power semiconductor device 1 is shown. By way of example, Figure 1 The left edge of includes the centroid.

[0089] The termination region 8 extends laterally along an edge region of the power semiconductor device 1 that delimits the active region 9. The termination region 8 is free of the first layer 14 of the first electrode 2. This means that the first layer 14 does not overlap the termination region 8 laterally in a plan view.

[0090] The third layer 16 of the second electrode 6 completely covers the top surface of the fourth sublayer 13 of the second semiconductor layer 5 only in the active region 9. The fourth layer 17 of the second electrode 6 completely covers the top surface of the third layer 16. That is, the third layer 16 and the fourth layer 17 completely overlap, and in particular completely overlap, the active region 9 in a lateral direction in a plan view.

[0091] The termination region 8 does not have the third layer 16 and the fourth layer 17 of the second electrode 6. That is, the third layer 16 and the fourth layer 17 do not overlap with the termination region 8 in the lateral direction in a plan view.

[0092] The second semiconductor layer 5 has a sloped structure 19 in the termination region 8. The side surface of the second semiconductor layer 5 (which connects the top and bottom surfaces of the second semiconductor layer 5) is inclined relative to the vertical direction. The side surface of the second semiconductor layer 5 is inclined only in the termination region 8. The angle between the side surface of the second semiconductor layer 5 and the bottom surface of the second semiconductor layer 5 is less than 90°, particularly less than 45°. In other words, the third sublayer 12 and the fourth sublayer 13 gradually narrow toward the second electrode 6 in the termination region 8.

[0093] An oxide layer 24 extending in the active region 9 and the termination region 8 is arranged on the first sublayer 10 of the first semiconductor layer 3. The oxide layer 24 faces the first electrode 2. The oxide layer 24 comprises the semiconductor material of the first semiconductor layer 3.

[0094] The bottom surface of the oxide layer 24 protrudes vertically beyond the bottom surface of the first sub-layer 10 to reach the first electrode 2. The first electrode 2 completely covers the bottom surface of the first sub-layer 10 and the bottom surface of the oxide layer 24.

[0095] The oxide layer 24 extends to only partially cover the active region 9 and completely cover the termination region 8. That is, the oxide layer 24 completely overlaps the termination region 8 in a plan view. The oxide layer 24 extends from the interface between the active region 9 and the termination region 8 into the active region 9 in the lateral direction to an extension distance 23. The extension distance 23 is at least 1 times and at most 7 times the height of the drift layer 4 in the vertical direction.

[0096] The power semiconductor device 1 further comprises a passivation layer 18. The passivation layer 18 encapsulates the layers of the power semiconductor device 1, wherein, in particular, a portion of the first electrode 2 and a portion of the second electrode 6 are free of the passivation layer 18.

[0097] and Figure 1 Compared to the exemplary embodiment of Figure 2The fourth sublayer 13 of the second semiconductor layer 5 of the exemplary embodiment includes an oxide layer 24. The oxide layer 24 extends only in the active region 9. That is, the oxide layer 24 completely overlaps with the active region 9 within the extension distance 23 in a plan view, and further, the oxide layer 24 does not overlap with the termination region 8 in a plan view.

[0098] The oxide layer 24 faces the second electrode 6. The oxide layer 24 includes the semiconductor material of the second semiconductor layer 5.

[0099] The top surface of the oxide layer 24 protrudes vertically beyond the top surface of the fourth sublayer 13 to reach the second electrode 6. The second electrode 6 completely covers the top surface of the fourth sublayer 13 and the top surface of the oxide layer 24.

[0100] like Figure 1 In the embodiment, the oxide layer 24 extends in the lateral direction from the interface between the active region 9 and the termination region 8 into the active region 9 up to an extension distance 23 .

[0101] according to Figure 4 The power semiconductor device 1 of the exemplary embodiment of the present invention has an oxide layer 24 and a further oxide layer 25. The oxide layer 24 on the first sublayer 10 corresponds to Figure 1 The oxide layer 24 in the fourth sub-layer 13 corresponds to another oxide layer 25 on the fourth sub-layer 13. Figure 2 The oxide layer 24 in the.

[0102] according to Figure 4 The power semiconductor device 1 of the exemplary embodiment is according to Figures 1 to 3 FIG1 is a plan view of a power semiconductor device 1. In the plan view, the top surfaces of the fourth layer 17 and the passivation layer 18 are freely accessible. The outer shape of the power semiconductor device 1 is circular.

[0103] The doped regions are not visible in this view, so they are indicated by dashed lines. The doped regions extend within the termination region 8, wherein each of the doped regions completely surrounds the active region 9 in the lateral direction. In particular, each of the doped regions has a circular shape in plan view, which corresponds to the outer shape of the power semiconductor device 1 in plan view.

[0104] In accordance with Figure 5 In the figure, the y-axis represents the hole density ρ, in cm -3 , and the x-axis represents the distance x from the center to the edge region of the power semiconductor device 1 in the drift layer 4 in the lateral direction, in μm.

[0105] Curve C1 corresponds to a typical power semiconductor device 1 that does not include the first semiconductor layer 3 having the oxide layer 24. Curve C2 corresponds to the typical power semiconductor device 1 that does not include the first semiconductor layer 3 having the oxide layer 24. Figure 1The power semiconductor device 1, curve C3 corresponds to Figure 2 power semiconductor device 1, and curve C4 corresponds to the Figure 3 A power semiconductor device 1.

[0106] Reference numerals 1Power semiconductor devices 2First electrode 3First semiconductor layer 4Drift layer 5Second semiconductor layer 6 Second electrode 7 doping region 8. Termination Zone 9 Active area 10 First sublayer 11 Second sublayer 12Third sublayer 13 Fourth sublayer 14 First Floor 15 Second Floor 16Third floor 17Fourth Floor 18 passivation layer 19 inclined structure 20 sections 21 Another doped region 23 extension distance 24 oxide layer 25 Another oxide layer

Claims

1. A power semiconductor device (1), comprising: - a first electrode (2), - a first semiconductor layer (3) of a first conductivity type, - a drift layer (4) of the first conductivity type, - a second semiconductor layer (5) of a second conductivity type different from the first conductivity type, and - a second electrode (6), wherein - an oxide layer (24) is arranged on at least one of the first semiconductor layer (3) and the second semiconductor layer (5), the oxide layer extending in an active region (9) of the power semiconductor device (1) surrounded by a termination region (8) of the power semiconductor device (1), and - At least one of the first semiconductor layer (3) and the second semiconductor layer (5) has a slope structure (19) in the termination region (8).

2. The power semiconductor device (1) according to claim 1, wherein: The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5) and the second electrode (6) are stacked one above the other in a vertical direction along a stacking direction.

3. The power semiconductor device (1) according to claim 1, wherein: - the first semiconductor layer (3) comprises a first sublayer (10) facing the first electrode (2) and a second sublayer (11) facing the drift layer (4), - the maximum doping concentration of the first sublayer (10) is higher than the maximum doping concentration of the second sublayer (11), - the second semiconductor layer (5) comprises a third sublayer (12) facing the drift layer (4) and a fourth sublayer (13) facing the second electrode (6), and - The maximum doping concentration of the fourth sublayer (13) is higher than the maximum doping concentration of the third sublayer (12).

4. The power semiconductor device (1) according to claim 1, wherein: - one of the first electrode (2) and the second electrode (6) extends over the active region (9) and the termination region (8), and - The other of the first electrode (2) and the second electrode (6) extends only over the active area (9).

5. The power semiconductor device (1) according to claim 3, wherein: - the fourth sublayer (13) extends in a lateral region over the active region (9) and the termination region (8), or - The fourth sublayer (13) extends only over the active region (9).

6. The power semiconductor device (1) according to any one of claims 1 to 5, wherein: At least one of the following: - the second semiconductor layer (5) tapers in the termination region (8) towards the second electrode (6), and - The first semiconductor layer (3) gradually narrows in the termination region (8) toward the first electrode (2).

7. The power semiconductor device (1) according to any one of claims 3 to 6, wherein: - the oxide layer (24) is located on the first sub-layer (10), in the active area (9) and in the termination area (8), and - The oxide layer (24) is located between the first sublayer (10) and the first electrode (2).

8. The power semiconductor device (1) according to any one of claims 1 to 7, wherein: - the oxide layer (24) extends in a lateral direction from the termination region (8) into the active region (9) up to an extension distance (23), and - The extension distance (23) is at least 1 times and at most 7 times the height of the drift layer (4) in the vertical direction.

9. The power semiconductor device (1) according to any one of claims 3 to 8, wherein: When the oxide layer (24) is arranged on the first semiconductor layer (3), - a further oxide layer (25) is located on the fourth sublayer (13) in the active area (9), and - The further oxide is a layer located between the fourth sublayer (13) and the second electrode (6).

10. The power semiconductor device (1) according to claim 9, wherein: - the further oxide layer (25) extends in a lateral direction from the termination region (8) into the active region (9) up to a further extension distance (23), and - the further extension distance (23) is at least 1 times and at most 7 times the height of the drift layer (4) in the vertical direction.

11. The power semiconductor device (1) according to any one of claims 1 to 10, wherein: - The first semiconductor layer (3) is constructed from a plurality of doped regions (7) of the second conductivity type in the termination region (8).

12. The power semiconductor device (1) according to claim 11, wherein: The first sublayer (10) is separated into a plurality of segments (20) in a lateral direction by the doped region (7).

13. The power semiconductor device (1) according to any one of claims 1 to 12, further comprising - a passivation layer (18), wherein The first electrode (2), the first semiconductor layer (3), the drift layer (4), the second semiconductor layer (5) and the second electrode (6) are surrounded by the passivation layer (18).

14. A method for manufacturing a semiconductor device, the method comprising: - providing a semiconductor material having a drift layer (4) of a first conductivity type, - producing a first semiconductor layer (3) of the first conductivity type on a first side of the drift layer (4), - producing a second semiconductor layer (5) of a second conductivity type different from the first conductivity type on a second side of the drift layer (4) opposite to the first side, - producing a slope structure (19) in at least the first semiconductor layer (3) and the second semiconductor layer (5) in a termination region (8) surrounding an active region (9) of the power semiconductor device (1), and - producing an oxide layer (24) on at least one of the first semiconductor layer (3) or the second semiconductor layer (5), wherein - The semiconductor device further comprises a first electrode (2) and a second electrode (6).

15. The method according to claim 14, wherein At least one - The bevel structure (19) is manufactured by a grinding process.

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