ZYNQ-based laser radar data acquisition system
By using photomultiplier tubes and ZYNQ programmable control devices for system control in the lidar data acquisition system, the problems of low integration and high power consumption in the existing technology are solved, efficient integration is achieved, the problem of high power consumption in the existing technology is reduced, efficient integration is achieved, the problem of high power consumption in the existing technology is reduced, efficient integration is achieved, the problem of high power consumption is reduced, efficient integration is achieved, the problem of high power consumption is reduced, efficient integration is achieved, the problem of high power consumption is reduced, efficient integration is achieved, the problem of high power consumption is reduced, efficient integration is achieved, the problem of high efficiency is reduced, efficient integration is achieved, the stability and sensitivity of the system are improved.
Patent Information
- Application Number
- CN202410333664.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2025-09-23
AI Technical Summary
Existing lidar data acquisition systems have low integration, high power consumption, and the photoelectric conversion unit is easily saturated, resulting in decreased sensitivity and shortened service life.
Photomultiplier tubes are used as photoelectric conversion units, and PMT voltage divider circuits, gating functions and high-voltage modules are designed. FPGA is combined for photon counting, ZYNQ programmable logic devices are used for system control, and data is transmitted via Ethernet.
The integration of the lidar data acquisition system is improved, power consumption is reduced, high-precision photon counting and system stability are achieved, and the service life of the photoelectric conversion unit is extended.
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Figure CN120686236A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of laser radar and discloses a ZYNQ-based laser radar data acquisition system. Background Art
[0002] Lidar is a remote sensing technology that uses laser beams to measure distance, speed and direction. It is a variant of radar technology that uses laser light sources instead of microwave signals.
[0003] LiDAR has been widely used in many fields such as autonomous driving, environmental monitoring, and earth observation.
[0004] The basic working principle of lidar is to calculate the distance of the target object by emitting laser pulses and measuring their return time. After the laser beam hits the target surface, the receiver captures the returning laser and determines the distance of the target by measuring the time delay of the laser. By rotating or adjusting the direction of the laser beam, lidar can also obtain the direction and speed information of the target.
[0005] LiDAR has the advantages of high precision, high resolution and long-range measurement, making it a key technology in self-driving cars. In this application, LiDAR can quickly and accurately detect the surrounding environment, identify obstacles, road signs and other vehicles, and provide critical information for the vehicle's safe navigation.
[0006] In addition, lidar also plays an important role in meteorology, urban planning, and environmental monitoring. In earth observation, lidar can be used to map topography and monitor glacier changes. In urban planning, lidar can generate high-precision three-dimensional maps to support urban planning and construction.
[0007] Overall, lidar, as an advanced remote sensing technology, is driving scientific and technological innovation in many fields, bringing higher levels of safety, efficiency and convenience to our lives and work.
[0008] The laser radar system mainly includes a laser transmitting unit, an optical receiving unit, a detection and acquisition unit, and a host computer control unit.
[0009] ZYNQ is a programmable system-on-chip (SoC) series from Xilinx. The ZYNQ series integrates high-performance programmable logic (PL) with a dual-core ARM Cortex-A series processor (Processing System, PS) on the same chip, providing a powerful hardware / software co-design platform. This integrated architecture allows developers to flexibly customize both hardware and software to achieve highly optimized system solutions. The ZYNQ series is widely used in embedded systems, communications, image processing, and high-performance computing, providing highly integrated and scalable processing capabilities.
[0010] To improve the integration of lidar data acquisition systems and reduce system power consumption, this paper uses a photomultiplier tube (PMT) as the core photoelectric conversion unit of the photon counter. Based on ZYNQ, a lidar data acquisition system is designed, consisting of a PMT front-end detection unit, a data acquisition unit, and a system control unit. An experimental platform is constructed to verify the functional correctness of the lidar data acquisition system. Summary of the Invention
[0011] The purpose of this invention is to improve the integration of the laser radar data acquisition system, reduce power consumption, and achieve high-precision photon counting. The system block diagram is as follows: Figure 1 As shown in the figure, a photomultiplier tube is selected to realize the conversion of optical signals into pulse electrical signals, and a hardware circuit is designed around the photomultiplier tube so that it can output a pulse signal with an amplitude of 2.2V and a width of 10ns. FPGA is used to complete photon counting, that is, to count the output pulses of the photomultiplier tube, and the counting results are stored in DDR and then transmitted to the host computer via Ethernet.
[0012] The specific steps of the implementation method of the ZYNQ-based laser radar data acquisition system provided by the present invention are as follows:
[0013] Preferably, the R9880U-210 photomultiplier tube of Hamamatsu Photonics of Japan is selected as the photoelectric conversion device, which is a metal package type, with a tube size of 16 mm in diameter, a circular photocathode surface area shape, a photocathode surface area size of 8 mm in diameter, a short wavelength of 230 nm, a long wavelength of 700 nm, a peak wavelength of 400 nm, a photocathode surface material of super bialkali (UBA), a window material of borosilicate glass, a multiplier electrode structure of a metal channel, a multiplier electrode stage of 10 levels, a maximum rated anode to cathode voltage of 1100 V, a maximum rated average anode current of 0.1 mA, a cathode brightness sensitivity minimum of 100 μA / lm, a cathode brightness sensitivity typical value of 135 μA / lm, and a cathode blue sensitivity index (CS 5-58) The typical value is 15.5, the typical value of cathode radiation sensitivity is 130mA / W, the minimum value of anode brightness sensitivity is 100A / lm, the typical value of anode brightness sensitivity is 270A / lm, and the typical value of anode gain is 2.0×10 6 The typical value of the anode dark current (after 30 minutes) is 1nA, the maximum value of the anode dark current (after 30 minutes) is 10nA, the typical value of the rise time is 0.57ns, the typical value of the transit time is 2.7ns, and the typical value of the transit time dispersion is 0.2ns.
[0014] PMT mainly consists of incident light input window, photocathode, dynode and anode.
[0015] The light signal hits the photocathode through the input window. The electrons on the photocathode are excited and leave the photocathode to enter the vacuum tube. After high voltage is applied between the photocathode, dynode and anode, the electrons begin to accelerate under the action of the internal electric field to reach the first dynode, and then knock out more electrons. This process is then repeated over and over again until a large number of electrons reach the anode. After being collected by the anode, they form output current, thus realizing the process of photoelectric conversion multiplication.
[0016] In order for the PMT to output a signal, a voltage needs to be applied between the photocathode and each dynode and the anode. The simplest method is to apply a high voltage between the photocathode and the anode, and then use a voltage divider circuit to obtain a certain voltage between each stage. The stepped voltage between adjacent dynodes is usually in the hundreds of volts.
[0017] When designing a PMT voltage divider circuit, follow the following design principles: divide the PMT inter-electrode voltage into three parts: the front-stage area, the middle-stage area, and the final-stage area.
[0018] In order to improve the efficiency of the first dynode in accepting electrons and enhance the electron emission capability of the next stage, the voltage of the front stage is designed to be high enough, and the voltage of the middle stage is evenly distributed. In order to avoid the space charge effect caused by the accumulation of a large number of electrons in the final stage, the inter-electrode voltage is designed to be higher.
[0019] When the laser starts working, the intensity of the emitted laser is very high. If this part of the echo signal directly enters the photomultiplier tube, it may instantly cause the photomultiplier tube to saturate. In this way, fatigue phenomena such as photocurrent decay and sensitivity decrease will occur in a short period of time, which will affect the service life of the PMT and even damage the PMT in severe cases.
[0020] To this end, we need to design the gating function of the PMT. By setting the time when the PMT starts detecting and ends detecting, we can ensure that the PMT starts detecting only after the laser pulse is emitted. The PMT voltage divider circuit is shown in the figure. It is mainly divided into two branches. The main branch is responsible for providing the electrical level of the photocathode, the second dynode DY2 to the tenth dynode DY10. The slave branch provides the electrical level for the first dynode under the control of the MOS tube.
[0021] Because the voltage applied to the PMT dynode is always negative, a P-channel field-effect transistor (FET) is selected as the level-controlled switch. The preferred P-channel FET is ON Semiconductor's FQD3P50. This P-channel enhancement-mode power MOSFET is manufactured using ON Semiconductor's proprietary planar stripe and DMOS technology. This advanced MOSFET technology is specifically tailored to reduce on-state resistance while providing excellent switching performance and high avalanche energy strength.
[0022] These devices are suitable for switch-mode power supplies, active power factor correction (PFC), and electronic rectifiers. The main branch of the PMT voltage divider circuit consists of a string of resistors. Here, we divide the voltage of the main branch into three sections: 1. The voltage from the photocathode to the first dynode DY1; 2. The intermediate dynodes adopt uniform voltage division; 3. The voltage between the last dynode and the anode is appropriately increased. In summary, the voltage distribution ratio between the three sections is roughly 4:1:2. The circuit design is as follows Figure 2 shown.
[0023] The PMT's high-voltage module uses XP-POWER's CA20N-5. The CA series is a high-performance, precision-regulated, high-voltage converter with high stability and low ripple, as well as a built-in voltage monitor output and an onboard precision voltage reference. Each model is programmed from 0 to 100% of the rated output via a DAC-compatible high-impedance programming input.
[0024] The voltage reference can be used to drive a 100% high-voltage output, or to adjust the output via an external potentiometer or voltage divider. The output voltage monitor is internally buffered and can provide a low-impedance (up to 1mA) signal to external circuits. The quasi-sine wave oscillator, internal transformer shielding, and isolated steel shell reduce EMI / RFI radiation to extremely low levels. The power module schematic is shown in the figure. Figure 3 shown.
[0025] Preferably, the DAC module uses ADI's high-speed dual-channel DAC chip AD9767, which has dual channels, a DA conversion bit number of 14 bits, an update rate of 125MSPS, and an output voltage range of -5V to +5V.
[0026] The DAC module principle design block diagram is as follows Figure 4 As shown, it mainly includes a high-speed dual-channel DAC chip AD9767, a low-pass filter, a first-stage operational amplifier (current to voltage conversion), a second-stage operational amplifier (voltage amplification) and a BNC interface.
[0027] Preferably, the operational amplifier circuit uses AD8065 from ADI, with an input bias current of 1pA, a -3dB bandwidth of 145MHz, a slew rate of 180V / μs, and a wide voltage range of 5V to 24V. The DAC module circuit is as follows: Figure 5 shown.
[0028] In order to realize photon counting, the present invention designs a photon counting amplifier circuit to amplify and identify the PMT output voltage signal.
[0029] The block diagram of the PMT photon counting circuit is as follows Figure 6 shown.
[0030] Preferably, the isolation circuit uses AD8045 from ADI, which is a high-bandwidth operational amplifier with stable unity gain. When the output voltage is 200mVp-p, the bandwidth under unity gain can reach 1GHz.
[0031] Preferably, the voltage amplifier circuit uses TI's OPA657, and when the output voltage is 200mV, the bandwidth can reach 275MHz.
[0032] The present invention designs an analog sampling circuit to convert analog signals into digital signals. The ADC module design block diagram is as follows: Figure 7 shown.
[0033] Preferably, the ADC acquisition circuit is AD9238 from ADI, the single-ended to differential circuit is AD8138 from ADI, and the isolation operational amplifier is AD8065 from ADI.
[0034] The ZYNQ control module is the main system control module, which is used for trigger signal generation, protocol communication, instruction parsing and photon counting;
[0035] Preferably, the ZYNQ chip uses Xilinx's XCZU4EV-2SFVC784I, with a system logic unit of 192K, a total RAM of 20.6Mb, a DSP of 728, and a maximum IO pin number of 252.
[0036] The present invention uses Verilog hardware programming language to complete the IP core design of a DAC module, an ADC module, a photon counting trigger module, a control module and a counting module.
[0037] The photon counting module uses two channels to alternately count one photon input signal, stores the two counting results in FIFO for buffering, and finally merges them into one data through an adder. The module adopts a design method that combines combinational logic and sequential logic. The state machine is strictly used to jump between each state. The counting function accuracy can reach 99%. The timing diagram of the present invention is shown in the figure. Figure 8 shown.
[0038] The present invention uses Gigabit Ethernet to transmit data to the host computer, and the transmission rate can reach 1Gbps. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 This is a system block diagram of the ZYNQ-based laser radar data acquisition system of the present invention.
[0040] Figure 2 It is the principle diagram of the PMT voltage divider circuit of the present invention.
[0041] Figure 3 It is a schematic diagram of the PMT power supply circuit of the present invention.
[0042] Figure 4 This is the principle design block diagram of the DAC module of the present invention.
[0043] Figure 5 This is a schematic diagram of the DAC module circuit of the present invention.
[0044] Figure 6 This is the block diagram of the photon counting circuit.
[0045] Figure 7 This is the design block diagram of the ADC module.
[0046] Figure 8 This is the timing diagram of the photon counting module. DETAILED DESCRIPTION
[0047] In order to make the objectives, technical solutions and technical features of the present invention clearer and more understandable, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0048] The ZYNQ-based laser radar data acquisition system designed by the present invention mainly consists of a photon counting hardware circuit, a ZYNQ data acquisition board and a host computer.
[0049] To avoid saturation of the photomultiplier tube, a filter needs to be placed in front of the photon counting module and covered with a black light shield.
[0050] The photon counting module outputs a pulse width of 10ns and an output amplitude of 5V under no-load conditions. In order for the ZYNQ data acquisition board to collect the signal, a 50-ohm load needs to be connected in parallel to divide the voltage. The final output voltage of the photon counting module is 2.2V and the pulse width is 10ns.
[0051] Use an SMA to BNC RF cable to connect the photon counting module to the ZYNQ data acquisition board.
[0052] Use the host computer to transmit the terminal instructions to the ZYNQ data acquisition board via Ethernet.
[0053] The ZYNQ control module parses the Ethernet instructions and obtains relevant configuration parameters and function instructions. Then, the system control module sends the configuration information to the DAC module, ADC module, photon counting trigger module, control module and photon counting module through the AXI bus.
[0054] Step 3: The DAC module outputs 5V to power the high-voltage power supply module of the PMT voltage divider circuit.
[0055] Step 4: The trigger module is set to a pulse signal with a specified frequency and a duty cycle of 1% to control the counting frequency of the photon counting module.
[0056] Step 5: The control module is used to set the time resolution and cumulative times of the photon counting module.
[0057] Step 6: The photon counting module is designed to use two channels to count the PMT output pulse signals in a ping-pong counting manner. The two counting results are cached through FIFO and then output and merged into one channel of data.
[0058] Step 7: The output data of the photon counting module is converted into AXI Stream format, buffered by AXI StreamData FIFO, and transmitted to the ARM end DDR4 through AXI Datamover.
[0059] Step 8: The present invention uses Ethernet to transmit data from DDR to the host computer, and the transmission rate can reach 1Gbps.
[0060] The above-described embodiments of the present invention do not limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the claims of the present invention.
Claims
1. A ZYNQ-based laser radar data acquisition system, characterized in that: Contains PMT front-end detection unit, data acquisition unit and system control unit; The photon counting probe is connected to a ZYNQ data acquisition card via an SMA-to-BNC cable. The photon counting probe converts incident light into an electrical signal, outputting a pulse signal with an amplitude of 2.2V and a width of 10ns. The FPGA on the ZYNQ data acquisition card processes the pulse signal output by the photon counting probe and accumulates photon counts, sending the calculated data to the ARM side of the ZYNQ data acquisition card. The ARM side is connected to a PC via Gigabit Ethernet, transmitting the data to the PC.
2. The ZYNQ-based laser radar data acquisition system according to claim 1, characterized in that: The superphoton counting probe and the ZYNQ data card are of an integrated design and are integrated on a circuit board. The ZYNQ-based lidar data acquisition system is a multi-channel design that can be connected to multiple photon counting probes and can perform simultaneous detection on multiple channels.
3. The ZYNQ-based laser radar data acquisition system according to claim 1, characterized in that: The photon counting probe has a gating function, which can solve the problem of rapid saturation of the photomultiplier tube when the laser just starts working.
4. The ZYNQ-based laser radar data acquisition system according to claim 1, characterized in that: The PMT front-end detection unit includes a high-voltage power supply circuit, a digital-to-analog conversion circuit, a photomultiplier tube voltage divider circuit, and a gate control circuit. The data acquisition unit includes an analog-to-digital conversion circuit and an FPGA circuit. The system control unit mainly includes a ZYNQ control circuit and a serial port circuit. The high-voltage power supply circuit is connected to the photomultiplier tube and is used to provide negative high voltage to each dynode of the photomultiplier tube, so that each dynode of the photomultiplier tube can normally realize photoelectron multiplication and enable the photomultiplier tube to output corresponding current. The analog-to-digital conversion circuit is connected to a high-voltage power supply and is used to drive the high-voltage power supply circuit to output a negative high voltage of a specified amplitude. The photomultiplier tube voltage divider circuit is mainly composed of resistors and capacitors to enable each dynode of the photomultiplier tube to reach the optimal operating voltage. The photomultiplier tube gating circuit is mainly composed of PMOS to prevent the photomultiplier tube from saturating when the laser starts working. The digital-to-analog conversion circuit is connected to the photon counting probe and is mainly used to convert analog signals into electrical signals and send them to the FPGA for sampling. The FPGA circuit is mainly a ZYNQ PL terminal, which is used to collect analog outputs of the photomultiplier tube and count the output pulses of the photomultiplier tube. The system control unit is mainly the ZYNQ PS terminal, which is used to control the entire data acquisition card. The serial port circuit is used for system debugging.
5. According to the ZYNQ-based laser radar data acquisition system of claim 4, its PMT front-end detection unit includes a high-voltage power supply circuit, preferably, an XP-POWER CA20N-5 model negative high-voltage power supply.
6. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the photomultiplier tube used in the PMT front-end detection unit is R9880U-210 from Hamamatsu Corporation.
7. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the gate control circuit adopts FQD3P50 from ON Semiconductor.
8. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the analog-to-digital conversion circuit adopts AD9767 and AD8065 of Analog Devices.
9. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the analog-to-digital conversion circuit adopts ADI's AD9238 and AD8138.
10. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the ZYNQ control circuit adopts Xilinx's XCZU4EV-2SFVC784I.
11. The ZYNQ-based laser radar data acquisition system according to claim 4, wherein the workflow includes the following steps. Step 1: The PC transmits instructions to the ZYNQ data acquisition card via Ethernet. After parsing the instructions, the ZYNQ data acquisition card configures the analog-to-digital conversion module IP core, photon counting IP core, and photon counting control module IP core of the data acquisition system. Step 2: The high-voltage power supply outputs a high voltage with an amplitude of -1000V and provides it to the photon counting probe. Step 3: The photon counting probe outputs a pulse signal with an amplitude of 2.2V and a width of 10ns. Step 4: The FPGA side of the ZYNQ data acquisition card counts the pulse signal Step 5: The FPGA side of the ZYNQ data acquisition card transmits the counting result to the DDR of the ARM side of the ZYNQ data acquisition card through the AXI bus. Step 6: The ARM side of the ZYNQ data acquisition card transmits the counting results to the PC side via Ethernet.
12. The FPGA photon counting control module according to claim 11 is written in Verilog hardware programming language, and mainly defines counter registers for implementing the time resolution time bin and cumulative number cnt_accum of the photon counting module.
13. The FPGA photon counting module of claim 11 is written in the Verilog hardware programming language and employs two counting channels for photon counting. While the photon counting working status signal is high, the two counting channels alternately count and buffer the counting results in two synchronous FIFOs with a data width of 16 bits and a depth of 2048. After the photon counting working status signal is low, the photon counting results stored in the two FIFOs are read out separately and then accumulated using an adder module. The entire photon counting module is implemented using a three-segment state machine.
14. The photon counting module of claim 13, further comprising a corresponding data accumulation module IP core for accumulating the counting results of each time bin in the photon counting control module of claim 12, and encapsulating the accumulated results using the AXI Stream protocol. The data accumulation module IP core also needs to output instructions for controlling the ARM-side DDR, including the address information written to the ARM-side DDR. The accumulation module IP core is written in the Veirlog hardware programming language and employs a one-stage state machine structure.
15. The data accumulation module according to claim 14, wherein the AXI Stream Data FIFO is used to cache data, and the AXI Datamover is used to transfer the data output by the AXI Stream Data FIFO to the DDR on the ZYNQ ARM side.
16. According to the ZYNQ-based lidar data acquisition system of claim 4, the data stored in the DDR of the ARM side is transmitted to the PC side through the LWIP TCP protocol, wherein the ZYNQ data acquisition card is the TCP client and the PC side is the TCP server.