Temperature control method and device

Abstract

The invention relates to the technical field of fiber lasers, and discloses a temperature control method and device.The first end of a programmable logic device FPGA receives signals of an upper computer, the second end of the programmable logic device FPGA is connected with the first end of a first digital power source, the third end of the programmable logic device FPGA is connected with the first end of a second digital power source, and the second end of the second digital power source is connected with the second end of a third digital power source; a fourth end of the programmable logic device FPGA is connected with a first end of the temperature acquisition device, a second end of the first digital power supply is connected with a first end of the TEC circuit, a second end of the second digital power supply is connected with a second end of the TEC circuit, a third end of the TEC circuit is connected with a first end of the frequency doubling crystal, and a fourth end of the frequency doubling crystal is connected with a second end of the temperature acquisition device. And the second end of the temperature acquisition device is connected with the second end of the frequency doubling crystal. The TEC device is controlled by non-PWM type continuous current output, temperature oscillation is reduced, and accurate temperature control is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of optical fiber lasers, and in particular to a temperature control method and device. Background Art

[0002] Frequency doubling technology is the core technology for fiber green lasers to achieve visible light band output. The infrared light of the fiber laser (such as 1064nm) is converted into green light (532nm) through a frequency doubling crystal (such as a nonlinear optical crystal), so the frequency doubling module is one of the core modules of the fiber green laser. The phase matching angle of the nonlinear crystal (such as LBO, BBO) in the frequency doubling module is highly sensitive to temperature. A temperature fluctuation of ±1°C can cause the green light output power to drop by more than 20%. Temperature changes directly affect the laser wavelength (typical drift is about 0.1nm / °C), and green light applications have extremely high requirements for wavelength stability. Temperature fluctuations must be controlled within ±0.005°C through temperature control. Maintaining a constant crystal temperature through a precision temperature control system is the key to achieving high-efficiency wavelength conversion. In addition, uneven temperature can also cause changes in the refractive index inside the crystal, resulting in a thermal lens effect, reducing beam quality and causing optical path deviation. If the frequency-doubling crystal is exposed to high-power laser irradiation for a long time and temperature control fails, resulting in local overheating, it may cause crystal cracking or optical coating ablation. Therefore, precise temperature control is extremely important for the frequency-doubling module.

[0003] The currently commonly used temperature control solutions, whether using a dedicated TEC temperature control chip or building a temperature control circuit, all use PWM signals to control the H-bridge circuit and high-frequency switching of high-speed switching elements (such as MOSFET and IGBT) to control the temperature. PWM temperature control adjusts the temperature through high-frequency switching, which will inevitably cause temperature fluctuations at the switching moment and is prone to electromagnetic interference (EMI), which may affect the normal operation of surrounding precision electronic equipment. During the high-frequency switching process, the switch tube repeatedly switches between the on / off state, generating a large amount of heat (accounting for 15-30% of the total system loss), reducing overall energy efficiency. High-frequency switching will also cause components to be subjected to long-term thermal stress and accelerate aging. In addition, the temperature control accuracy of conventional temperature control solutions is not high enough to meet the precise temperature control requirements of the green fiber laser frequency doubling module. Summary of the Invention

[0004] In view of this, the present invention provides a temperature control method and device to solve the problems of low temperature control accuracy in conventional temperature control solutions and the temperature oscillation easily caused by the PWM temperature control method.

[0005] In a first aspect, the present invention provides a temperature control device, comprising: a programmable logic device FPGA, a first digital power supply, a second digital power supply, a TEC circuit, and a temperature acquisition device, wherein:

[0006] A first end of the programmable logic device FPGA receives a host computer signal, a second end of the programmable logic device FPGA is connected to a first end of the first digital power supply, a third end of the programmable logic device FPGA is connected to a first end of the second digital power supply, a fourth end of the programmable logic device FPGA is connected to a first end of the temperature acquisition device, a second end of the first digital power supply is connected to a first end of the TEC circuit, a second end of the second digital power supply is connected to a second end of the TEC circuit, a third end of the TEC circuit is connected to a first end of a frequency doubling crystal, and a second end of the temperature acquisition device is connected to a second end of the frequency doubling crystal;

[0007] The temperature acquisition device is used to collect the temperature of the frequency doubling crystal and send the collected temperature to the programmable logic device FPGA in the form of an electrical signal. The programmable logic device FPGA adjusts the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature, controls the current size and direction of the TEC circuit, and dynamically adjusts the temperature of the frequency doubling crystal.

[0008] The present invention provides a temperature control device that uses two high-precision configurable digital power supplies connected to the two ends of the TEC circuit respectively, and uses non-PWM continuous current output to control the TEC device, avoiding PWM high-frequency noise interference, reducing temperature fluctuations, and achieving precise temperature control.

[0009] In an optional embodiment, the device further includes: a wavelength detection device and a power detection device, wherein:

[0010] The first end of the wavelength detection device and the first end of the power detection device are respectively connected to the third end of the frequency doubling crystal, the second end of the wavelength detection device is connected to the fifth end of the programmable logic device FPGA, and the second end of the wavelength detection device is connected to the sixth end of the programmable logic device FPGA.

[0011] By adding wavelength and power detection devices, the laser temperature point can be adjusted and calibrated, realizing the original optical requirements of the laser as the input of the temperature control system, and truly realizing closed-loop control of the laser temperature control system.

[0012] In an optional embodiment, the temperature acquisition device includes: a temperature sensor and an ADC analog-to-digital conversion chip, wherein:

[0013] The first end of the temperature sensor is connected to the second end of the frequency doubling crystal, the second end of the temperature sensor is connected to the first end of the ADC analog-to-digital conversion chip, and the second end of the ADC analog-to-digital conversion chip is connected to the fourth end of the programmable logic device FPGA.

[0014] In a second aspect, the present invention provides a temperature control method, which is applied to the temperature control device of the first aspect or any corresponding embodiment thereof, the method comprising:

[0015] The temperature of the frequency doubling crystal is collected by a temperature collection device, and the collected temperature is sent to the programmable logic device FPGA in the form of an electrical signal;

[0016] According to the difference between the collected temperature and the target temperature, the voltage signals output by the first digital power supply and the second digital power supply are adjusted to control the current size and direction of the TEC circuit and dynamically adjust the temperature of the frequency doubling crystal.

[0017] The present invention provides a temperature control method that uses two high-precision configurable digital power supplies connected to the two ends of the TEC circuit, respectively, and uses non-PWM continuous current output to control the TEC device, avoiding PWM high-frequency noise interference, reducing temperature fluctuations, and achieving precise temperature control.

[0018] In an optional embodiment, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes:

[0019] If the difference is greater than the first threshold, the rapid temperature rise phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm;

[0020] If the difference is not greater than the first threshold and not less than the second threshold, then entering the fine adjustment stage, using the segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply, and the first threshold is greater than the second threshold;

[0021] If the difference is smaller than the second threshold, the system enters a steady-state phase, and uses a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0022] In an optional embodiment, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes:

[0023] If the difference is greater than the first threshold value during the first test, the rapid temperature rise phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm;

[0024] When the difference is not greater than a third threshold, entering a fine adjustment stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the third threshold is less than the first threshold;

[0025] When the difference is less than a fourth threshold, entering a steady-state stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the fourth threshold is less than the second threshold;

[0026] When the difference is not less than a fifth threshold, the process returns to the fine adjustment stage and uses a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply. The fifth threshold is greater than the second threshold, and the fifth threshold is less than the third threshold.

[0027] In an optional embodiment, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature further includes:

[0028] If the difference is less than the second threshold value during the first test, the steady-state phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm;

[0029] When the difference is greater than a fifth threshold, the fine adjustment stage is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm;

[0030] When the difference is greater than a sixth threshold, entering a rapid temperature rise stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the sixth threshold is greater than the first threshold;

[0031] When the difference is less than the third threshold, the process returns to the fine adjustment stage and uses the segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0032] In an optional embodiment, adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm includes:

[0033] According to the temperature adjustment section entered, select the proportional coefficient, integral coefficient and differential coefficient of the corresponding temperature adjustment section;

[0034] Substituting the proportional coefficient, the integral coefficient and the differential coefficient into the PID operation formula to calculate the control amount;

[0035] The voltage signals output by the first digital power supply and the second digital power supply are adjusted according to the control amount.

[0036] In an optional implementation, the PID calculation formula is as follows:

[0037] Δu(k)=Kp*ΔTdiff(k)+Ki*Tdiff(k)+Kd*[ΔTdiff(k)-ΔTdiff(k-1)]

[0038] Among them, Δu(k) is the control quantity, Kp is the proportional coefficient, Ki is the integral coefficient, Kd is the differential coefficient, ΔTdiff(k)=Tdiff(k)-Tdiff(k-1), ΔTdiff(k-1)=Tdiff(k-1)-Tdiff(k-2), Tdiff(k), Tdiff(k-1), and Tdiff(k-2) are the differences between the current moment, the previous time, and the previous two times, respectively.

[0039] In an optional embodiment, the method further includes:

[0040] Utilize a wavelength detection device to detect the green light signal emitted by the frequency doubling crystal, and output corresponding wavelength information to the programmable logic device FPGA to calibrate the set temperature;

[0041] The power detection device is used to detect the green light signal emitted by the frequency doubling crystal, and output the corresponding power information to the programmable logic device FPGA to calibrate the set temperature.

[0042] By adding wavelength and power detection devices, the laser temperature point can be adjusted and calibrated, realizing the original optical requirements of the laser as the input of the temperature control system, and truly realizing closed-loop control of the laser temperature control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 is a principle block diagram of a temperature control device according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of a digital power supply hardware design according to an embodiment of the present invention;

[0046] Figure 3 is a schematic flow chart of a temperature control method according to an embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of the relationship between interval hysteresis parameters according to an embodiment of the present invention;

[0048] Figure 5 4 is a flow chart of FPGA temperature control according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0050] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0052] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0053] The present invention provides a temperature control device, such as Figure 1 As shown, it includes: a programmable logic device FPGA, a first digital power supply, a second digital power supply, a TEC circuit, and a temperature acquisition device. The temperature acquisition device includes: a temperature sensor and an ADC analog-to-digital conversion chip.

[0054] Specifically, the first end of the programmable logic device FPGA communicates with the host computer via the MCU and receives the host computer signal. The programmable logic device FPGA sets relevant parameters such as target temperature, temperature control accuracy, PID control coefficient, etc. according to the host computer signal.

[0055] The second terminal of the programmable logic device (FPGA) is connected to the first terminal of the first digital power supply, the third terminal of the programmable logic device (FPGA) is connected to the first terminal of the second digital power supply, and the fourth terminal of the programmable logic device (FPGA) is connected to the second terminal of the ADC analog-to-digital conversion chip. The second terminal of the first digital power supply is connected to the first terminal of the TEC circuit, and the second terminal of the second digital power supply is connected to the second terminal of the TEC circuit. The third terminal of the TEC circuit is connected to the first terminal of the frequency multiplication crystal. The first terminal of the temperature sensor is connected to the second terminal of the frequency multiplication crystal, and the second terminal of the temperature sensor is connected to the first terminal of the ADC analog-to-digital conversion chip.

[0056] In an embodiment of the present invention, a frequency doubling crystal is located within a frequency doubling cavity, and a temperature sensor is placed below the frequency doubling crystal. The temperature sensor is used to collect the temperature of the frequency doubling crystal and convert the temperature of the frequency doubling crystal into an analog electrical signal for output. The ADC analog-to-digital conversion chip converts the analog electrical signal output into a digital electrical signal and sends the digital electrical signal to a programmable logic device (FPGA). The programmable logic device (FPGA) collects signals and performs calculations, converting the electrical signal collected from the ADC analog-to-digital conversion chip into a corresponding temperature. Based on the difference between the collected temperature and the target temperature, a PID algorithm is used to adjust the voltage signals output by the first digital power supply and the second digital power supply, thereby controlling the current magnitude and direction of the TEC circuit, thereby dynamically adjusting the temperature and ultimately allowing the frequency doubling crystal to operate at a constant temperature.

[0057] Furthermore, the first and second digital power supplies are connected to the two ends of the TEC circuit, respectively. The digital power supplies can set their output voltages via a communication interface, with a minimum adjustable voltage step of 10mV. They can also set current limits and incorporate built-in current detection and compensation mechanisms. Therefore, the two digital power supplies can ensure extremely high output voltage and current stability to the greatest extent possible. In a TEC circuit, when current flows from the positive end to the negative end, side A heats up and side B cools down. If the current flows in the opposite direction, the effect is also reversed. By controlling the magnitude and direction of the current, the temperature can be adjusted. For example, a programmable logic device (FPGA) dynamically adjusts the voltage outputs of the two digital power supplies based on the actual and target temperatures. When the output voltage Vtec+ of the first digital power supply is greater than the output voltage Vtec- of the second digital power supply, current is input from the positive end, causing the TEC to heat. When the output voltage Vtec+ of the first digital power supply is less than the output voltage Vtec- of the second digital power supply, current is input from the negative end, causing the TEC to cool down. When the target temperature differs greatly from the actual temperature, the voltage difference between the two power supplies is increased, so that the TEC current is also larger, and the temperature can rise or fall quickly. When the target temperature is equal to the actual temperature, the two power supplies output a relatively constant small voltage difference, the TEC current is also constant, and the system is in a stable state.

[0058] A temperature control device proposed in this invention utilizes two high-precision, configurable digital power supplies connected to the ends of a TEC circuit. This device utilizes a non-PWM continuous current output to control the TEC device, achieving precise control of the TEC circuit's voltage and current while avoiding high-frequency PWM noise interference, minimizing temperature fluctuations, and achieving precise temperature control. Practical testing has shown that, combined with a high-precision sensor, the device can achieve a temperature control accuracy of 0.001°C.

[0059] In an optional embodiment, as Figure 1 As shown, the device further includes: a wavelength detection device and a power detection device. The first end of the wavelength detection device and the first end of the power detection device are respectively connected to the third end of the frequency doubling crystal, the second end of the wavelength detection device is connected to the fifth end of the programmable logic device FPGA, and the second end of the wavelength detection device is connected to the sixth end of the programmable logic device FPGA.

[0060] Specifically, the conventional fiber laser temperature control system is difficult to adjust and calibrate once it is produced and enters the terminal. However, after a long period of use and aging, the optical characteristics of the laser's optical components will inevitably drift over time. Coupled with changes in the use environment, its wavelength, power and other parameters will also change at the original set temperature point. For this reason, this application has added a wavelength detection device and a power detection device, which use the wavelength detection device and the power detection device to receive the green light signal emitted by the frequency doubling crystal, convert it into the corresponding wavelength and power information, and input it into the programmable logic device FPGA to calibrate the set temperature.

[0061] In the embodiments of the present invention, since the characteristics of the laser's optical components change slowly, the wavelength and power will not change dramatically over a short period of time as the temperature changes. Therefore, adjusting the set temperature point by detecting the wavelength and power does not need to be performed in real time. Calibration only needs to be performed once when the laser is powered on, or manually when a change is suspected and calibration is required. Real-time dynamic calibration is only required when the temperature is controlled near the set temperature point.

[0062] In an optional embodiment, the hardware design principle diagram of the first digital power supply and the second digital power supply is as follows: Figure 2 The module's power supply chip uses TI's TPS55289 programmable step-up / step-down power converter. This chip supports a wide input voltage range of 3 to 30V and a programmable output voltage range of 0.8 to 22V in 10mV steps, enabling precise output voltage control. This chip also implements current limiting and current detection compensation mechanisms for precise current control. The power supply chip supports a maximum current of 8A, which effectively meets the current design requirements of the temperature control system.

[0063] The present invention provides a temperature control method, which is applied to the temperature control device of the above embodiment, such as Figure 3 As shown, the temperature control method includes the following steps:

[0064] Step S1: Use a temperature acquisition device to acquire the temperature of the frequency doubling crystal, and send the acquired temperature to a programmable logic device FPGA in the form of an electrical signal.

[0065] Specifically, the frequency-doubling crystal is located within the frequency-doubling cavity, and a temperature sensor is placed beneath the crystal. The temperature sensor measures the crystal's temperature and converts it into an analog electrical signal for output. The ADC chip converts the analog signal into a digital signal and sends it to the FPGA.

[0066] Step S2, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature, controlling the current magnitude and direction of the TEC circuit, and dynamically adjusting the temperature of the frequency doubling crystal.

[0067] Specifically, the programmable logic device FPGA collects signals and performs calculations, converting the electrical signals collected from the ADC analog-to-digital conversion chip into the corresponding temperature. Based on the difference between the collected temperature and the target temperature, the PID algorithm is used to adjust the voltage signals output by the first digital power supply and the second digital power supply, and control the current size and direction of the TEC circuit, thereby achieving dynamic temperature adjustment and ultimately making the frequency doubling crystal operate at a constant temperature.

[0068] This invention provides a temperature control method that uses two high-precision, configurable digital power supplies connected to the two ends of a TEC circuit. This method utilizes a non-PWM continuous current output to control the TEC device. This method achieves precise control of the TEC circuit's voltage and current, avoids high-frequency PWM noise interference, minimizes temperature fluctuations, and achieves precise temperature control. Practical testing has shown that, combined with a high-precision sensor, the temperature control accuracy can reach 0.001°C.

[0069] In an optional embodiment, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes the following steps:

[0070] Step S201: If the difference is greater than the first threshold, the process enters a rapid temperature rise phase, and uses a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0071] In step S202 , if the difference is not greater than the first threshold and not less than the second threshold, the fine adjustment stage is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using the segmented PID algorithm, and the first threshold is greater than the second threshold.

[0072] Step S203, if the difference is less than the second threshold, enter the steady state segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0073] Specifically, the temperature control in this application uses a piecewise PID algorithm, which divides the temperature adjustment range into three segments: a rapid heating segment, a fine adjustment segment, and a steady state segment. In the rapid heating segment, a large overshoot is allowed, and the PID coefficients are a high proportional coefficient Kp_f, a low integral coefficient Ki_f, and a differential coefficient Kd_f of 0; in the fine adjustment segment, the PID coefficients are a low proportional coefficient Kp_u, a high integral coefficient Ki_u, and an increased differential coefficient Kd_u; in the steady state segment, the PID coefficients are a low proportional coefficient Kp_s, a decreased integral coefficient Ki_s, and a further increased differential coefficient Kd_s. The temperature value obtained by the programmable logic device FPGA collecting ADC data is processed by moving average filtering (the filtering time Tfilter parameter can be set) to obtain the current temperature Tmea. The difference Tdiff between the target temperature Tset and the current temperature Tmea is Tdiff = Tset - Tmea. Two temperature deviation threshold parameters, a first threshold Tseg_h and a second threshold Tseg_l, are set, and Tdiff is compared with the threshold parameters Tseg_h and Tseg_l to enter the corresponding temperature adjustment range. When Tdiff > Tseg_h, enter the rapid heating segment, and use the three parameters Kp_f, Ki_f, and Kd_f for PID operation to adjust the temperature and quickly approach the target temperature value; when Tseg_l ≤ Tdiff ≤ Tseg_h, enter the fine adjustment segment, and use the three parameters Kp_u, Ki_u, and Kd_u for PID operation to adjust the temperature for fine temperature adjustment; when Tdiff < Tseg_l, enter the steady state segment, and use the three parameters Kp_s, Ki_s, and Kd_s for PID operation to adjust the temperature, suppress noise interference, and maintain extremely small fluctuations to keep the temperature stable.

[0074] In an optional implementation manner, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes the following steps:

[0075] Step S211, if the difference is greater than the first threshold during the first test, enter the rapid heating segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0076] Step S212, when the difference is not greater than the third threshold, enter the fine adjustment segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply. The third threshold is less than the first threshold.

[0077] Step S213, when the difference to be measured is less than the fourth threshold, enter the steady state segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply. The fourth threshold is less than the second threshold.

[0078] Step S214, when the difference to be measured is not less than the fifth threshold, return to the fine adjustment segment again, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply. The fifth threshold is greater than the second threshold and less than the third threshold.

[0079] Specifically, the present application also sets four interval hysteresis parameters, namely the third threshold Tseg_h - Tseg_hh, the fourth threshold Tseg_l - Tseg_ll, the fifth threshold Tseg_l + Tseg_ll, and the sixth threshold Tseg_h + Tseg_hh, to avoid the problem that when the temperature is near the interval threshold, it will repeatedly jump in the temperature adjustment interval. Among them, the relationship of the four interval hysteresis parameters is as Figure 4 shown. The fourth threshold Tseg_l - Tseg_ll is less than the second threshold Tseg_l, the fifth threshold Tseg_l + Tseg_ll is greater than the second threshold Tseg_l, the fifth threshold Tseg_l + Tseg_ll is less than the third threshold Tseg_h - Tseg_hh, the third threshold Tseg_h - Tseg_hh is less than the first threshold Tseg_h, and the sixth threshold Tseg_h + Tseg_hh is greater than the first threshold Tseg_h.

[0080] This temperature control process is implemented in a field programmable gate array (FPGA), as Figure 5 shown: The actual temperature outputs an electrical signal through a temperature sensor and enters an ADC analog-to-digital conversion chip. The FPGA collects the ADC data, performs a moving average filtering process to obtain the current measured temperature Tmea. The FPGA calculates the value of Tdiff = Tset - Tmea based on the preset target temperature Tset, and at the same time, the values of Tdiff(k - 1) and Tdiff(k - 2) can be obtained. If the first measured temperature Tdiff > Tseg_h, enter the rapid heating segment; when Tdiff ≤ Tseg_h - Tseg_hh, enter the fine adjustment segment; when Tdiff < Tseg_l - Tseg_ll, enter the steady state segment; when Tdiff ≥ Tseg_l + Tseg_ll, return to the fine adjustment segment again. At the same time, the value of ΔTdiff(k) = Tdiff(k) - Tdiff(k - 1) can be calculated, and the value of ΔTdiff(k - 1) can be obtained.

[0081] In an optional implementation manner, adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature further includes the following steps:

[0082] Step S221, if the difference is less than the second threshold during the first test, enter the steady state segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0083] Step S222, when the difference is greater than the fifth threshold, enter the fine adjustment segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0084] Step S223, when the difference is greater than the sixth threshold, enter the rapid temperature rise segment, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply, where the sixth threshold is greater than the first threshold.

[0085] Step S224, when the difference is less than the third threshold, return to the fine adjustment segment again, and use the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

[0086] Specifically, this temperature control process is implemented in a programmable logic device FPGA, as Figure 5 shown: The actual temperature outputs an electrical signal through a temperature sensor and enters an ADC analog-to-digital conversion chip. The FPGA collects the ADC data, performs a moving average filtering process to obtain the current measured temperature Tmea. The FPGA calculates the value of Tdiff = Tset - Tmea based on the preset target temperature Tset, and at the same time can obtain the values of Tdiff(k - 1) and Tdiff(k - 2). If the first measured temperature Tdiff < Tseg_l, enter the steady state segment; when Tdiff > Tseg_l - Tseg_ll, enter the fine adjustment segment; when Tdiff > Tseg_h + Tseg_hh, enter the rapid temperature rise segment; when Tdiff < Tseg_h - Tseg_hh, return to the fine adjustment segment again. At the same time, the value of ΔTdiff(k) = Tdiff(k) - Tdiff(k - 1) can be calculated, and the value of ΔTdiff(k - 1) can be obtained.

[0087] In an optional implementation manner, using the piecewise PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply includes the following steps:

[0088] Step S2001, according to the entered temperature adjustment segment, select the proportional coefficient, integral coefficient, and differential coefficient corresponding to the temperature adjustment segment.

[0089] Step S2002, substitute the proportional coefficient, integral coefficient, and differential coefficient into the PID operation formula to calculate the control quantity.

[0090] Step S2003, adjust the voltage signals output by the first digital power supply and the second digital power supply according to the control quantity.

[0091] Specifically, based on the temperature adjustment range entered, the Kp, Ki, and Kd values ​​for the corresponding range are retrieved from the PID parameter table, and the value of ΔTdiff(k)-ΔTdiff(k-1) is simultaneously calculated. In the next clock cycle, the values ​​of P, I, and D are simultaneously calculated according to the formula P = Kp*ΔTdiff(k), I = Ki*Tdiff(k), and D = Kd*[ΔTdiff(k)-ΔTdiff(k-1)]. This allows the value of Δu(k) = P+I+D to be derived in the following clock cycle. The desired output current is then determined based on the experimentally obtained table of the relationship between Δu(k) and current, and the outputs of the two digital power supplies are controlled to achieve the desired current. By continuously looping, the set temperature can be quickly approached and ultimately maintained at a stable state, achieving high-precision temperature control and extremely high temperature stability.

[0092] In the embodiment of the present invention, the PID calculation formula is as follows:

[0093] Δu(k)=Kp*ΔTdiff(k)+Ki*Tdiff(k)+Kd*[ΔTdiff(k)-ΔTdiff(k-1)]

[0094] Among them, Δu(k) is the control quantity, Kp is the proportional coefficient, Ki is the integral coefficient, Kd is the differential coefficient, ΔTdiff(k)=Tdiff(k)-Tdiff(k-1), ΔTdiff(k-1)=Tdiff(k-1)-Tdiff(k-2), Tdiff(k), Tdiff(k-1), and Tdiff(k-2) are the differences between the current moment, the previous time, and the previous two times, respectively.

[0095] In an optional embodiment, the method further comprises the following steps:

[0096] Step S3: Utilize the wavelength detection device to detect the green light signal emitted by the frequency doubling crystal, and output the corresponding wavelength information to the programmable logic device FPGA to calibrate the set temperature.

[0097] Step S4: Utilize a power detection device to detect the green light signal emitted by the frequency doubling crystal, and output corresponding power information to the programmable logic device FPGA to calibrate the set temperature.

[0098] Specifically, the present invention also incorporates a wavelength detection device and a power detection device, thereby dynamically adjusting the set temperature according to fluctuations in wavelength and power, realizing the use of the original optical requirements of the laser as the input of the temperature control system, and truly realizing closed-loop control to ensure the stability of the wavelength and power of the green fiber laser, thereby ensuring the stability and reliability of the entire green fiber laser from a system perspective.

[0099] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A temperature control device, characterized in that: The device includes: a programmable logic device FPGA, a first digital power supply, a second digital power supply, a TEC circuit, and a temperature acquisition device, wherein: A first end of the programmable logic device FPGA receives a host computer signal, a second end of the programmable logic device FPGA is connected to a first end of the first digital power supply, a third end of the programmable logic device FPGA is connected to a first end of the second digital power supply, a fourth end of the programmable logic device FPGA is connected to a first end of the temperature acquisition device, a second end of the first digital power supply is connected to a first end of the TEC circuit, a second end of the second digital power supply is connected to a second end of the TEC circuit, a third end of the TEC circuit is connected to a first end of a frequency doubling crystal, and a second end of the temperature acquisition device is connected to a second end of the frequency doubling crystal; The temperature acquisition device is used to collect the temperature of the frequency doubling crystal and send the collected temperature to the programmable logic device FPGA in the form of an electrical signal. The programmable logic device FPGA adjusts the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature, controls the current size and direction of the TEC circuit, and dynamically adjusts the temperature of the frequency doubling crystal.

2. The temperature control device according to claim 1, characterized in that The device further comprises: a wavelength detection device and a power detection device, wherein, The first end of the wavelength detection device and the first end of the power detection device are respectively connected to the third end of the frequency doubling crystal, the second end of the wavelength detection device is connected to the fifth end of the programmable logic device FPGA, and the second end of the wavelength detection device is connected to the sixth end of the programmable logic device FPGA.

3. The temperature control device according to claim 1, characterized in that The temperature acquisition device includes: a temperature sensor and an ADC analog-to-digital conversion chip, wherein: The first end of the temperature sensor is connected to the second end of the frequency doubling crystal, the second end of the temperature sensor is connected to the first end of the ADC analog-to-digital conversion chip, and the second end of the ADC analog-to-digital conversion chip is connected to the fourth end of the programmable logic device FPGA.

4. A temperature control method, characterized in that: Applied to the temperature control device according to any one of claims 1 to 3, the method comprises: The temperature of the frequency doubling crystal is collected by a temperature collection device, and the collected temperature is sent to the programmable logic device FPGA in the form of an electrical signal; According to the difference between the collected temperature and the target temperature, the voltage signals output by the first digital power supply and the second digital power supply are adjusted to control the current size and direction of the TEC circuit and dynamically adjust the temperature of the frequency doubling crystal.

5. The temperature control method according to claim 4, characterized in that: Adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes: If the difference is greater than the first threshold, the rapid temperature rise phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm; If the difference is not greater than the first threshold and not less than the second threshold, then entering the fine adjustment stage, using the segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply, and the first threshold is greater than the second threshold; If the difference is smaller than the second threshold, the system enters a steady-state phase, and uses a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

6. The temperature control method according to claim 4, characterized in that: Adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature includes: If the difference is greater than the first threshold value during the first test, the rapid temperature rise phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm; When the difference is not greater than a third threshold, entering a fine adjustment stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the third threshold is less than the first threshold; When the difference is less than a fourth threshold, entering a steady-state stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the fourth threshold is less than the second threshold; When the difference is not less than a fifth threshold, the process returns to the fine adjustment stage and uses a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply. The fifth threshold is greater than the second threshold, and the fifth threshold is less than the third threshold.

7. The temperature control method according to claim 6, characterized in that: Adjusting the voltage signals output by the first digital power supply and the second digital power supply according to the difference between the collected temperature and the target temperature, further comprising: If the difference is less than the second threshold value during the first test, the steady-state phase is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm; When the difference is greater than a fifth threshold, the fine adjustment stage is entered, and the voltage signals output by the first digital power supply and the second digital power supply are adjusted using a segmented PID algorithm; When the difference is greater than a sixth threshold, entering a rapid temperature rise stage, and adjusting the voltage signals output by the first digital power supply and the second digital power supply using a segmented PID algorithm, wherein the sixth threshold is greater than the first threshold; When the difference is less than the third threshold, the process returns to the fine adjustment stage and uses the segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply.

8. The temperature control method according to any one of claims 6 to 7, characterized in that: Using a segmented PID algorithm to adjust the voltage signals output by the first digital power supply and the second digital power supply includes: According to the temperature adjustment section entered, select the proportional coefficient, integral coefficient and differential coefficient of the corresponding temperature adjustment section; Substituting the proportional coefficient, the integral coefficient and the differential coefficient into the PID operation formula to calculate the control amount; The voltage signals output by the first digital power supply and the second digital power supply are adjusted according to the control amount.

9. The temperature control method according to claim 8, characterized in that: The PID calculation formula is as follows: Δu(k)=Kp*ΔTdiff(k)+Ki*Tdiff(k)+Kd*[ΔTdiff(k)-ΔTdiff(k-1)] Among them, Δu(k) is the control quantity, Kp is the proportional coefficient, Ki is the integral coefficient, Kd is the differential coefficient, ΔTdiff(k)=Tdiff(k)-Tdiff(k-1), ΔTdiff(k-1)=Tdiff(k-1)-Tdiff(k-2), Tdiff(k), Tdiff(k-1), and Tdiff(k-2) are the differences between the current moment, the previous time, and the previous two times, respectively.

10. The temperature control method according to claim 5, characterized in that: The method further comprises: Utilize a wavelength detection device to detect the green light signal emitted by the frequency doubling crystal, and output corresponding wavelength information to the programmable logic device FPGA to calibrate the set temperature; The power detection device is used to detect the green light signal emitted by the frequency doubling crystal, and output the corresponding power information to the programmable logic device FPGA to calibrate the set temperature.

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