Knowledge graph-based operator code generation method and device

Abstract

The invention discloses an operator code generation method and device based on a knowledge graph. The method comprises the following steps: constructing a code knowledge graph according to an operator code library; performing hierarchical retrieval on the code knowledge graph according to a retrieval demand input by a user to obtain a reference operator code tree; generating a target operator code for each reference operator code tree; the generated target operator code is screened to obtain a final operator code matched with the retrieval requirement, and the final operator code is applied to the AI chip. According to the method, the code knowledge graph is constructed, the code knowledge graph is retrieved according to the retrieval requirement input by the user to obtain the reference operator code tree, and the special operator code applied to the AI chip is generated based on the reference code tree, so that participation of professionals is not needed in the code generation process, the operator development cost is reduced, the code quality is improved, and the user experience is improved. And the adaptability of the operator on a specific hardware architecture is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method and device for generating operator codes based on a knowledge graph. Background Art

[0002] Operator development is a crucial step in the software engineering of application-specific integrated circuit (ASIC) chips. It not only impacts the chip's computing power but also determines the efficiency of software and hardware collaboration. With the continuous breakthroughs in AI-related applications and the rapid evolution of related algorithms, efficient and rapid operator development is crucial for the successful implementation of these chips.

[0003] However, current operator development relies heavily on experienced manual coding and tuning, often requiring highly skilled engineers with deep hardware architecture knowledge and software engineering experience. This results in high labor costs and long development cycles. While some automated tools, such as MLIR and TVM, exist to help optimize operator code, these tools primarily rely on rule-based optimization, requiring extensive manual adjustments for complex operator development and adaptation. Generating operator code for ASIC chips, in particular, is difficult due to the lack of a rich code corpus for large-scale model training. Summary of the Invention

[0004] The present invention provides an operator code generation method based on knowledge graph to improve the efficiency and accuracy of operator code generation.

[0005] According to a first aspect of the present invention, a method for generating operator code based on a knowledge graph is provided, comprising: constructing a code knowledge graph based on an operator code library, wherein the code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of the graph nodes;

[0006] Performing a hierarchical search on the code knowledge graph according to a search requirement input by a user to obtain a reference operator code tree, wherein the reference operator code tree includes a target graph node related to the search requirement;

[0007] generating a target operator code for each of the reference operator code trees;

[0008] The generated target operator code is screened to obtain a final operator code that matches the search requirement, wherein the final operator code is applied to the AI ​​chip.

[0009] According to another aspect of the present invention, there is provided an operator code generation device based on a knowledge graph, comprising: a code knowledge graph construction module, configured to construct a code knowledge graph based on an operator code library, wherein the code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of the graph nodes;

[0010] A hierarchical retrieval module, configured to perform a hierarchical search on the code knowledge graph according to a retrieval requirement input by a user to obtain a reference operator code tree, wherein the reference operator code tree contains a target graph node related to the retrieval requirement;

[0011] A target operator code generation module, configured to generate a target operator code for each reference operator code tree;

[0012] A final operator code screening module is used to screen the generated target operator code to obtain a final operator code that matches the search requirement, wherein the final operator code is applied to the AI ​​chip.

[0013] According to another aspect of the present invention, an electronic device is provided, comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided. The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method described in any embodiment of the present invention when executed.

[0018] The technical solution of the embodiment of the present invention constructs a code knowledge graph, searches the code knowledge graph according to the search requirements input by the user to obtain a reference operator code tree, and generates proprietary operator code applied to the AI ​​chip based on the reference code tree. This eliminates the need for professional participation in the code generation process, reduces operator development costs, improves code quality, and enhances the adaptability of operators to specific hardware architectures.

[0019] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a flowchart of a method for generating operator code based on a knowledge graph according to the first embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of an application scenario of operator code generation provided by the first embodiment of the present invention;

[0023] Figure 3 This is a flowchart of a method for generating operator code based on a knowledge graph according to the second embodiment of the present invention;

[0024] Figure 4 1 is a schematic diagram of the structure of an operator code generation device based on a knowledge graph according to the third embodiment of the present invention;

[0025] Figure 5 It is a structural diagram of an electronic device provided by the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Example 1

[0029] Figure 1 A flowchart of a method for generating operator code based on a knowledge graph is provided for the first embodiment of the present invention. This embodiment is applicable to the case of generating dedicated code for an AI chip. The method can be executed by an operator code generating device based on a knowledge graph, which can be implemented in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0030] Step S101: construct a code knowledge graph based on the operator code library.

[0031] Optionally, a code knowledge graph is constructed based on the operator code library, including: extracting all operator file names contained in the operator code library, functional units under each operator file name, and function entities under each functional unit; dividing the function entities according to the operator code functions to obtain operator code fragments, and using the operator file name, functional unit and operator code fragment as node objects; using a large language model to analyze each node object to obtain node semantic information, and combining the node object with the matched node semantic information to construct a graph node; obtaining the connection relationship between each graph node, and connecting each graph node according to the connection relationship to construct a code knowledge graph, wherein the connection relationship includes ownership, inclusion, call and continuation.

[0032] Specifically, if Figure 2 The figure shows an application scenario diagram of operator code generation. The operator code generated in this embodiment is specifically a proprietary operator code applied to AI chips, and the process of generating proprietary operator code mainly involves the construction of code knowledge graphs, retrieval of code knowledge graphs, and generation of operator codes and other related stages. Among them, the construction process of the code knowledge graph is mainly based on the operator code library, and the generated code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of graph nodes. In this embodiment, the operator code knowledge graph structure is defined as G = {V, E}, where V represents the graph node set, E represents the edge set, the topological structure of G is a directed acyclic graph, and V is a set of node objects and semantics V = {V0, V1, ... V n}, where V i ={C i ,S i}, C i For node objects, including file names, functional units or operator code fragments, S i is the node semantic information. E represents the set of connection relationships between the operator code fragments E = {E0, E1, ... E m}, where E i ={j,k,Type}, j and k represent the edge from Vj to V k unidirectional connection, where Type is the edge type. In the operator code knowledge graph, we construct four edge types: Type∈{"includes", "owns", "continues", and "calls"}. "Includes" defines the relationship between the root node and the operator file name; "owns" defines the relationship between the operator file and the operator function implementation defined within the file; "continues" defines the sequential connection relationship between operator code snippets within the same operator function implementation; and "calls" defines the relationship between an operator code calling other functions.

[0033] In a specific implementation, the operator code library involved in the existing AI chip development will be analyzed in this embodiment. The operator code warehouse will include multiple file names, each file name will include multiple functional units, and each functional unit will specifically include function entities, that is, specific codes. In this embodiment, all operator file names, functional units, and function entities will be extracted from the operator code library, and the function entities will be segmented according to the operator code function to obtain operator code fragments, and the operator code fragments will be annotated according to the segmentation results. For example, it can be specifically<Block\> As a marking symbol, the function entity is segmented, and the operator code function can specifically include sub-function header declaration, input parameter processing, internal variable definition, data preloading, core calculation logic, etc. Of course, this embodiment is only an example, and does not limit the specific segmentation method of the function entity. The operator file name, functional unit directly extracted from the operator code library, and the operator code fragment obtained by segmentation are used as graph nodes V i The node object part C i In addition, in this implementation, a large language model is used to perform semantic analysis on each node object to extract the semantic information of function functions, parameter descriptions, and code fragment semantics. For example, for operator code fragments, the semantic fragments of these operator code fragments are grouped into a comment format starting with " / / " as a graph node V i Node semantic information S i Filling into the library, the method for file name or functional unit is roughly the same as this, and will not be repeated in this embodiment. i Combined acquisition i , S i} as a graph node. In this implementation, the connection relationships between the graph nodes are also obtained based on the functional units contained in the operator file name and the function entities contained in each functional unit, such as owning, containing, calling, and continuing. The specific meanings of each connection relationship have been explained above and will not be repeated here. The graph nodes are connected according to the connection relationship to construct a code knowledge graph.

[0034] Optionally, after constructing the code knowledge graph based on the operator code library, it also includes: calculating the mixed vector features of each graph node, where the mixed vector features include dense vector features and sparse vector features; marking the mixed vector features as attribute information of the graph nodes on the code knowledge graph.

[0035] It should be noted that in this embodiment, the hybrid vector language model bge-m3 is used to extract V i ={C i ,S i}, including dense vector features based on semantics and sparse vector features based on word segmentation. For example, when the node object in the graph node is an operator code fragment, the first step in calculating the mixed vector feature is to segment the input text, that is, C i ={TC0,TC1,…TC n}, S i ={TS i ,TS1,…TS m}, TC i and TS i Represent the code snippet and semantic information sequence after word segmentation. Then the two sequences are mixed by the bge-m3 model to calculate the vector, where the dense vector feature D C ∈R 1x768 ,D S ∈R 1x768 The feature dimension extracted is 768, corresponding to code snippets and semantic information respectively; the sparse vector is directly based on the word sequence {TC0, TC1, ...TC n}, {TS0, TS1, ... TS m} Get the weight W of each ci tune from the vocabulary i , i represents the position of each ci tune in the vocabulary. The acquired ci tune features are stored in the CSR format, which is a proprietary representation of sparse vectors. Of course, in this embodiment, only the graph nodes containing operator code fragments are used as an example for explanation. The calculation method of the mixed vector features of other types of graph nodes is roughly the same, and will not be repeated in this embodiment. In addition, in this embodiment, the acquired mixed vector features will be marked as attribute information in the code knowledge graph to facilitate subsequent code knowledge graph retrieval.

[0036] Step S102: Perform a hierarchical search on the code knowledge graph according to the search requirements input by the user to obtain a reference operator code tree.

[0037] Optionally, a hierarchical search is performed on the code knowledge graph according to the retrieval requirements input by the user to obtain a reference operator code tree, including: generating a query object according to the retrieval requirements input by the user, and calculating the query vector features of the query object, wherein the query object has the same format as the graph node; performing a first-level search on the code knowledge graph according to the query vector features, and obtaining an initial graph node without a parent node with a continuous connection relationship; performing a second-level search on the code knowledge graph according to the query vector features and the initial graph node to obtain a reference operator code tree, wherein the number of reference operator code trees is multiple.

[0038] Optionally, a secondary search is performed on the code knowledge graph based on the query vector features and the initial graph nodes to obtain a reference operator code tree, including: obtaining the subgraph nodes contained under each initial graph node from the code knowledge graph; filtering out target graph nodes similar to the query object from the subgraph nodes based on the query vector features; and constructing a reference operator code tree from the target graph nodes with connection relationships.

[0039] In this embodiment, based on the code knowledge graph constructed above, a hierarchical retrieval method is proposed, which is specifically divided into the retrieval of the first-level operator function header and the retrieval of the second-level operator code fragment. And according to the child node traversal of the last retrieved graph node Vi, the reference operator code tree Tree = {V i-sub ,E i-sub}, where V i-sub ={V i ,V i+1 ,…V n},E i-sub Is the child node combined with V i-sub The sub-node connection relationship within only includes two types of connections {"continue" and "call"}.

[0040] In a specific implementation, a query object is generated when a search requirement input by a user is received, and the query object has the same format as the graph node in the code knowledge graph. The search requirement input by the user can be a description of the generated code, for example, "write a sub, parameter, calculation process function", or it can be an incomplete code, for example, "write a sub, function (10 lines, complete)". Of course, this embodiment is only an example and does not limit the specific content of the search requirement input by the user. In this embodiment, the search requirement is parsed using the reasoning ability of the large language model to analyze the operator semantic description or code snippet. It is necessary to extract the function function related to the query operator, parameter description, and semantic description of the code snippet function. This information is constructed as a query object Q = {C Q ,S Q}, so the format of the query object Q is the same as that of the graph node Vi ={C i ,S i} have the same format for subsequent retrieval. Before retrieval, the query vector feature of the query object is calculated in this embodiment, and the query object Q is calculated as {C Q ,S Q The method of querying vector features is roughly the same as the method of calculating mixed vector features mentioned above, which is to calculate C Q The dense vector feature D CQ And the sparse vector S based on word segmentation CQ , and S Q The dense vector feature D SQ And the sparse vector feature S based on word segmentation SQ , and the D obtained above CQ 、S CQ 、D SQ and S SQ As the query vector feature. In this embodiment, the code knowledge graph will be searched at the first level according to the query vector feature. Specifically, the similarity is calculated based on the query vector feature, and the similarity in each dimension is weighted and fused to obtain the initial graph node whose similarity meets the requirements. Therefore, the first-level search in this embodiment specifically matches all the initial graph nodes in the code knowledge graph that do not have a "continuation" relationship parent node according to the user input search requirements, that is, first determine the operator function header information related to the query. Then, the code knowledge graph is searched at the second level according to the query vector feature and the initial graph node to obtain the reference operator code tree. Therefore, the second-level search in this embodiment specifically takes the initial graph node queried at the first level as the root node, and continues to match the most similar sub-graph node from all its child nodes, indicating that the current user input code fragment C Q The fragment C of the retrieved operator i Approximation; finally retrieve the subgraph node V i Traverse all subgraph nodes of the {“continue”, “call”} relationship to construct the reference operator code tree Tree = {V i-sub ,E i-sub}, prepare to generate code for the large model as enhanced knowledge, therefore, the target graph nodes related to the retrieval requirements are included in the reference operator code tree.

[0041] Step S103: Generate a target operator code for each reference operator code tree.

[0042] Optionally, a target operator code is generated for each reference operator code tree, including: determining the target graph nodes contained in each reference operator code tree, and obtaining generated code fragments corresponding to each target graph node using a cascade generation method; combining each generated code fragment in a cascade order to obtain the target operator code corresponding to the reference operator code tree.

[0043] Optionally, a cascade generation method is used to obtain the generated code snippet corresponding to each target graph node, including: obtaining the own code snippet of the target graph node at the current sequence position, the semantic information of the remaining target graph nodes at non-current sequence positions, and the set of code snippets generated before the current sequence position; using the own code snippet, the semantic information of the remaining target graph nodes and the set of code snippets as prompt words at the current sequence position; and using a large language model to obtain the generated code snippet corresponding to the target graph node at the current sequence position based on the prompt word at the current sequence position.

[0044] Specifically, if Figure 2 The number of reference operator code trees generated in this embodiment is shown as three, but in actual application, the number of reference operator code trees generated can also be other numbers, and in this embodiment, a specified number of reference operator code trees can be selected from them to generate code fragments. In this embodiment, the generation of code is described by selecting three reference operator code trees as an example. Among them, in this embodiment, a knowledge-enhanced prompt word project is constructed to be generated by a large model, and fragmented code generation is performed in a cascade generation manner. The code generated in the previous step will be used as part of the input to guide the generation of the next code. Finally, each reference operator code tree will generate a target operator code. For example, when determining the target graph nodes contained in each reference operator code tree and obtaining the generated code fragments corresponding to each target graph node in a cascade generation manner, the code fragments of the target graph node at the current sequence position, the semantic information of the other target graph nodes at non-current sequence positions, and the set of code fragments generated before the current sequence position are obtained, and the above-mentioned information is used as the prompt word at the current sequence position. The following formula (1) shows the content combination information of the prompt word:

[0045] P i =f(V i-sub , {E j-sub |j≠i}, {O j |j <i}) (1)

[0046] Among them, i marks the sequence number of the current cascade generation process; P i Represents the large model prompt word based on retrieval enhancement; V i-sub It is the code snippet corresponding to the target graph node at the current sequence position; j-sub |j≠i} represents the semantic information of the remaining target graph nodes at non-current sequence positions. Their role is to i-sub Providing contextual semantic information can significantly reduce the length of text compared to directly providing code snippets, and improve the ability of large models to understand the context of long texts; jThe set of code segments generated before the current sequence position, denoted as {Oj|j < i}, is used to compose the operator code content that has been generated currently, guiding the large model to continue writing code later, which can effectively limit the large model to generate segments only within the defined code logic. And after obtaining the prompt word at the current sequence position, the following formula (2) can be specifically used to obtain the generated code segment corresponding to the target graph node at the current sequence position: i-sub After obtaining the generated code segments corresponding to each sequence position in this embodiment, all the code segment sets {O0, O1, …, O

[0047] O i = LLM(P i ) (2)

[0048] } concatenated based on the current reference code tree will be combined into the complete target operator code O. Of course, in this embodiment, only one reference operator code tree is taken as an example to specifically illustrate the specific process of generating the target operator code. The method of generating the target operator code for other reference operator code trees is roughly the same, and will not be elaborated in this embodiment. For example, the target operator code 1 is generated by the reference operator code tree 1, the target operator code 2 is generated by the reference operator code tree 2, and the target operator code 3 is generated by the reference operator code tree 3. n} will be combined into the complete target operator code O. Of course, in this embodiment, only one reference operator code tree is taken as an example to specifically illustrate the specific process of generating the target operator code. The method of generating the target operator code for other reference operator code trees is roughly the same, and will not be elaborated in this embodiment. For example, the target operator code 1 is generated by the reference operator code tree 1, the target operator code 2 is generated by the reference operator code tree 2, and the target operator code 3 is generated by the reference operator code tree 3.

[0049] Step S104, screen the generated target operator code to obtain the final operator code that matches the retrieval requirement.

[0050] Optionally, screening the generated target operator code to obtain the final operator code that matches the retrieval requirement includes: automatically compiling and testing each target operator code using an automated compilation and testing process, and combining manual debugging to obtain the target operator code that passes the compilation and testing; scoring the target operator code that passes the compilation and testing according to the time and status of the compilation and testing, and taking the target operator code with the highest score as the final operator code that matches the retrieval requirement.

[0051] Among them, in this embodiment, after obtaining multiple target operator codes, an automated compilation and testing process will be used to compile and test each target operator code, and manual debugging will be combined to screen out the operator files that can pass the compilation and testing completely. Then, the final operator code will be screened out according to the scoring and voting mechanism. Therefore, the concept of ensemble learning is borrowed in the process of screening the final operator code, and the quality of the generated code and the system stability can be improved by selecting the best results from numerous candidates. And the final operator code obtained by screening in this embodiment is applied to the AI chip.

[0052] In the implementation mode of the present application, a code knowledge graph is constructed, and the code knowledge graph is searched according to the search requirements input by the user to obtain a reference operator code tree. Based on the reference code tree, proprietary operator code applied to the AI ​​chip is generated, thereby eliminating the need for professional participation in the code generation process, reducing the operator development cost, improving code quality, and enhancing the adaptability of the operator to a specific hardware architecture.

[0053] Example 2

[0054] Figure 3 The second embodiment of the present invention provides a flow chart of a method for generating operator codes based on a knowledge graph. This embodiment is based on the above embodiment. After screening the generated target operator codes to obtain the final operator codes that match the search requirements, the method further includes: detecting the final operator codes, such as Figure 3 As shown, the method includes:

[0055] Step S201: construct a code knowledge graph based on the operator code library.

[0056] Optionally, a code knowledge graph is constructed based on the operator code library, including: extracting all operator file names contained in the operator code library, functional units under each operator file name, and function entities under each functional unit; dividing the function entities according to the operator code functions to obtain operator code fragments, and using the operator file name, functional unit and operator code fragment as node objects; using a large language model to analyze each node object to obtain node semantic information, and combining the node object with the matched node semantic information to construct a graph node; obtaining the connection relationship between each graph node, and connecting each graph node according to the connection relationship to construct a code knowledge graph, wherein the connection relationship includes ownership, inclusion, call and continuation.

[0057] Optionally, after constructing the code knowledge graph based on the operator code library, it also includes: calculating the mixed vector features of each graph node, where the mixed vector features include dense vector features and sparse vector features; marking the mixed vector features as attribute information of the graph nodes on the code knowledge graph.

[0058] Step S202: Perform a hierarchical search on the code knowledge graph according to the search requirements input by the user to obtain a reference operator code tree.

[0059] Optionally, a hierarchical search is performed on the code knowledge graph according to the retrieval requirements input by the user to obtain a reference operator code tree, including: generating a query object according to the retrieval requirements input by the user, and calculating the query vector features of the query object, wherein the query object has the same format as the graph node; performing a first-level search on the code knowledge graph according to the query vector features, and obtaining an initial graph node without a parent node with a continuous connection relationship; performing a second-level search on the code knowledge graph according to the query vector features and the initial graph node to obtain a reference operator code tree, wherein the number of reference operator code trees is multiple.

[0060] Optionally, a secondary search is performed on the code knowledge graph based on the query vector features and the initial graph nodes to obtain a reference operator code tree, including: obtaining the subgraph nodes contained under each initial graph node from the code knowledge graph; filtering out target graph nodes similar to the query object from the subgraph nodes based on the query vector features; and constructing a reference operator code tree from the target graph nodes with connection relationships.

[0061] Step S203: Generate a target operator code for each reference operator code tree.

[0062] Optionally, a target operator code is generated for each reference operator code tree, including: determining the target graph nodes contained in each reference operator code tree, and obtaining generated code fragments corresponding to each target graph node using a cascade generation method; combining each generated code fragment in a cascade order to obtain the target operator code corresponding to the reference operator code tree.

[0063] Optionally, a cascade generation method is used to obtain the generated code snippet corresponding to each target graph node, including: obtaining the own code snippet of the target graph node at the current sequence position, the semantic information of the remaining target graph nodes at non-current sequence positions, and the set of code snippets generated before the current sequence position; using the own code snippet, the semantic information of the remaining target graph nodes and the set of code snippets as prompt words at the current sequence position; and using a large language model to obtain the generated code snippet corresponding to the target graph node at the current sequence position based on the prompt word at the current sequence position.

[0064] Step S204: Screen the generated target operator codes to obtain the final operator codes that match the search requirements.

[0065] Optionally, the generated target operator code is screened to obtain the final operator code that matches the retrieval requirement, including: using an automated compilation test process to automatically compile and test each target operator code, combined with manual debugging to obtain the target operator code that passes the compilation test; scoring the target operator code that passes the compilation test according to the time and status of the compilation test, and using the target operator code with the highest score as the final operator code that matches the retrieval requirement.

[0066] Step S205: Detect the final operator code.

[0067] Specifically, in this embodiment, after obtaining the final operator code, although the final operator code has been tested, its compatibility with the AI ​​chip still needs to be tested. Therefore, in this embodiment, the final operator code that has passed the test is run on the AI ​​chip to test its compatibility with the actual AI chip. If it is determined that the final operator code runs successfully on the AI ​​chip without any errors, the final operator code is determined to have passed the test.

[0068] It should be noted that in this embodiment, a test report will be generated after the final operator code is tested. The test report specifically includes relevant information such as the test results, test time, and test items of the final operator code. This embodiment does not limit the specific content included in the test report, and the monitoring report will be displayed in a visual form on the front-end interface.

[0069] It is worth mentioning that in this implementation, the operator code knowledge base and the calling relationships and data flow dependencies of the related function fragments therein are organized in the form of a directed acyclic graph. By performing semantic analysis and vector embedding on the operator code fragments, combined with a hierarchical retrieval mechanism, more accurate code search is achieved and operator code generation is performed using a large model, reducing the cycle and complexity of operator development. A multi-level code retrieval method is adopted, combining semantic parsing and hybrid embedding vectors, that is, dense vectors plus sparse vectors, to achieve efficient and accurate related code retrieval. Relevant operator code fragments are screened out by calculating similarity, and combined with a structured tree traversal strategy, the retrieved code is ensured to be not only accurate but also complete, providing a more reliable reference for subsequent code generation. In the code generation stage, the code generation capability of the large model is optimized by combining retrieval-enhanced prompt word engineering. Finally, through automated compilation testing, manual model evaluation, and voting screening mechanism, the optimal operator code is screened out from multiple generation schemes, ensuring the high quality and adaptability of the generated code and improving the reliability of automated development.

[0070] In the implementation mode of the present application, a code knowledge graph is constructed, and the code knowledge graph is searched according to the search requirements input by the user to obtain a reference operator code tree. Based on the reference code tree, proprietary operator code applied to the AI ​​chip is generated, thereby eliminating the need for professional participation in the code generation process, reducing the operator development cost, improving code quality, and enhancing the adaptability of the operator to a specific hardware architecture.

[0071] Example 3

[0072] Figure 4 The third embodiment of the present invention provides a schematic diagram of the structure of an operator code generation device based on a knowledge graph. Figure 4 As shown, the device includes: a code knowledge graph construction module 310, a hierarchical retrieval module 320, a target operator code generation module 330 and a final operator code screening module 340.

[0073] The code knowledge graph construction module 310 is used to construct a code knowledge graph based on the operator code library, wherein the code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of graph nodes;

[0074] A hierarchical retrieval module 320 is configured to perform a hierarchical search on the code knowledge graph according to the retrieval requirements input by the user to obtain a reference operator code tree, wherein the reference operator code tree includes target graph nodes related to the retrieval requirements;

[0075] A target operator code generation module 330 is configured to generate a target operator code for each reference operator code tree;

[0076] The final operator code screening module 340 is used to screen the generated target operator code to obtain the final operator code that matches the search requirement, wherein the final operator code is applied to the AI ​​chip.

[0077] Optionally, a code knowledge graph construction module is used to extract all operator file names, functional units under each operator file name, and function entities under each functional unit contained in the operator code library;

[0078] The function entity is split according to the operator code function to obtain the operator code fragment, and the operator file name, functional unit and operator code fragment are used as node objects;

[0079] A large language model is used to analyze each node object to obtain node semantic information, and the node object and the matched node semantic information are combined to construct a graph node;

[0080] The connection relationship between each graph node is obtained, and each graph node is connected according to the connection relationship to construct a code knowledge graph, where the connection relationship includes ownership, inclusion, call and continuation.

[0081] Optionally, the device further includes an attribute information marking module for calculating a mixed vector feature of each graph node, wherein the mixed vector feature includes a dense vector feature and a sparse vector feature;

[0082] The mixed vector features are marked as attribute information of graph nodes on the code knowledge graph.

[0083] Optionally, a hierarchical retrieval module is used to generate a query object based on the retrieval requirements input by the user and calculate the query vector features of the query object, where the query object has the same format as the graph node;

[0084] Perform a first-level search on the code knowledge graph based on the query vector features and obtain the initial graph nodes that do not have a parent node with a continuous connection relationship;

[0085] A secondary search is performed on the code knowledge graph based on the query vector features and the initial graph nodes to obtain a reference operator code tree, wherein the number of reference operator code trees is multiple.

[0086] Optional, hierarchical retrieval module, used to obtain the subgraph nodes contained under each initial graph node from the code knowledge graph;

[0087] Filter target graph nodes similar to the query object from subgraph nodes based on query vector features;

[0088] A reference operator code tree is constructed from target graph nodes with connection relationships.

[0089] Optionally, a target operator code generation module is used to determine the target graph nodes included in each reference operator code tree, and obtain the generated code fragment corresponding to each target graph node using a cascade generation method;

[0090] The generated code fragments are combined in a cascade order to obtain the target operator code corresponding to the reference operator code tree.

[0091] Optionally, a target operator code generation module is used to obtain the code snippet of the target graph node at the current sequence position, the semantic information of the remaining target graph nodes at non-current sequence positions, and the set of code snippets generated before the current sequence position;

[0092] The code snippet itself, the semantic information of other target graph nodes, and the code snippet set are used as the prompt words at the current sequence position;

[0093] A large language model is used to obtain the generated code snippet corresponding to the target graph node at the current sequence position based on the prompt word at the current sequence position.

[0094] Optionally, a final operator code screening module is used to automatically compile and test each target operator code using an automated compilation and testing process, and obtain target operator codes that pass the compilation and testing in combination with manual debugging;

[0095] The target operator code that passes the compilation test is scored according to the time and status of the compilation test, and the target operator code with the highest score is used as the final operator code that matches the retrieval requirements.

[0096] The knowledge graph-based operator code generation device provided in an embodiment of the present invention can execute the knowledge graph-based operator code generation method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0097] Example 5

[0098] Figure 5 The present invention is a block diagram of an electronic device 10 that can be used to implement an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0099] like Figure 5 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0100] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0101] The processor 11 can be a variety of general-purpose and / or specialized processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the operator code generation method based on the knowledge graph.

[0102] In some embodiments, the operator code generation method based on the knowledge graph can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the operator code generation method based on the knowledge graph described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the operator code generation method based on the knowledge graph by any other appropriate means (for example, by means of firmware).

[0103] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0105] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0106] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0107] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0109] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0110] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for generating operator code based on knowledge graph, characterized in that: include: Constructing a code knowledge graph based on the operator code library, wherein the code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of graph nodes; Performing a hierarchical search on the code knowledge graph according to a search requirement input by a user to obtain a reference operator code tree, wherein the reference operator code tree includes a target graph node related to the search requirement; generating a target operator code for each of the reference operator code trees; The generated target operator code is screened to obtain a final operator code that matches the search requirement, wherein the final operator code is applied to the AI ​​chip.

2. The method according to claim 1, characterized in that The construction of a code knowledge graph based on the operator code library includes: Extracting all operator file names, functional units under each operator file name, and function entities under each functional unit contained in the operator code library; The function entity is divided according to the operator code function to obtain the operator code fragment, and the operator file name, the functional unit and the operator code fragment are used as node objects; Analyzing each of the node objects using a large language model to obtain node semantic information, and combining the node object with the matched node semantic information to construct the graph node; The connection relationship between each graph node is obtained, and each graph node is connected according to the connection relationship to construct the code knowledge graph, wherein the connection relationship includes ownership, inclusion, call and continuation.

3. The method according to claim 1, characterized in that After constructing the code knowledge graph based on the operator code library, the following steps are also included: Calculating a mixed vector feature of each graph node, wherein the mixed vector feature includes a dense vector feature and a sparse vector feature; The mixed vector feature is marked on the code knowledge graph as the attribute information of the graph node.

4. The method according to claim 1, wherein The step of performing a hierarchical search on the code knowledge graph to obtain a reference operator code tree according to the search requirements input by the user includes: Generate a query object according to the search requirement input by the user, and calculate the query vector feature of the query object, wherein the query object has the same format as the graph node; Performing a first-level search on the code knowledge graph according to the query vector feature, and obtaining an initial graph node that has no parent node with a continuous connection relationship; A secondary search is performed on the code knowledge graph according to the query vector feature and the initial graph node to obtain the reference operator code tree, wherein the number of the reference operator code trees is multiple.

5. The method according to claim 4, characterized in that The performing a secondary search on the code knowledge graph according to the query vector feature and the initial graph node to obtain the reference operator code tree includes: Obtaining the subgraph nodes contained under each of the initial graph nodes from the code knowledge graph; Filtering target graph nodes similar to the query object from the subgraph nodes according to the query vector features; The target graph nodes having a connection relationship are used to construct the reference operator code tree.

6. The method according to claim 1, characterized in that Generating a target operator code for each reference operator code tree includes: Determining the target graph nodes included in each reference operator code tree, and obtaining generated code fragments corresponding to each target graph node using a cascade generation method; The generated code fragments are combined in a cascade order to obtain the target operator code corresponding to the reference operator code tree.

7. The method according to claim 6, characterized in that The method of obtaining the generated code fragment corresponding to each target graph node by adopting the cascade generation method includes: Obtain the code snippet of the target graph node at the current sequence position, the semantic information of the remaining target graph nodes at non-current sequence positions, and the set of code snippets generated before the current sequence position; Using the self code snippet, the semantic information of the remaining target graph nodes and the code snippet set as prompt words at the current sequence position; A large language model is used to obtain a generated code snippet corresponding to the target graph node at the current sequence position according to the prompt word at the current sequence position.

8. The method according to claim 1, characterized in that The step of screening the generated target operator code to obtain a final operator code that matches the search requirement includes: Automatic compilation and testing of each target operator code is performed using an automated compilation and testing process, and manual debugging is combined to obtain target operator code that passes the compilation and testing; The target operator code that passes the compilation test is scored according to the time and status of the compilation test, and the target operator code with the highest score is used as the final operator code that matches the search requirement.

9. An operator code generation device based on knowledge graph, characterized in that: include: A code knowledge graph construction module is used to construct a code knowledge graph based on the operator code library, wherein the code knowledge graph includes graph nodes, connection relationships between graph nodes, and attribute information of graph nodes; A hierarchical retrieval module, configured to perform a hierarchical search on the code knowledge graph according to a retrieval requirement input by a user to obtain a reference operator code tree, wherein the reference operator code tree contains a target graph node related to the retrieval requirement; A target operator code generation module, configured to generate a target operator code for each reference operator code tree; A final operator code screening module is used to screen the generated target operator code to obtain a final operator code that matches the search requirement, wherein the final operator code is applied to the AI ​​chip.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program to be executed by the at least one processor, where the computer program is executed by the at least one processor so as to enable the at least one processor to perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 8 when the processor executes the computer instructions.

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