Modeling method and device of insulated gate bipolar transistor, storage medium and program product

Abstract

Embodiments of the present application disclose a modeling method and device of an insulated gate bipolar transistor, a storage medium and a program product. The modeling method of the insulated gate bipolar transistor comprises: obtaining capacitance test data between a gate and a collector of the insulated gate bipolar transistor; constructing a dynamic capacitance segmented function of the insulated gate bipolar transistor in an opening stage and a closing stage according to a preset circuit model; and performing parameter extraction on the segmented function based on the capacitance test data to describe capacitance changes of the insulated gate bipolar transistor in the opening and / or closing process. The technical solution of the embodiments of the present application sets the modeling method of the insulated gate bipolar transistor, and realizes behavior change analysis of the insulated gate bipolar transistor in the switching process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics simulation, and particularly relates to a modeling method and device of an insulated gate bipolar transistor, a storage medium and a program product. BACKGROUND

[0002] Computer-aided design based on a simulation program with integrated circuit emphasis (SPICE) can perform a large number of virtual experiments and virtual tests to assist the development and design of circuit systems, so as to achieve higher cost efficiency and shorter development period. A high-precision device SPICE model is an important guarantee for improving the design efficiency and applicability of an application circuit. Figure 1 In the related art, modeling of an insulated gate bipolar transistor (IGBT) and fitting curves thereof are as shown in FIG. 1. Figure 1 C GE is a capacitance between a gate and an emitter in an IGBT device; C CE is a capacitance between a collector and the emitter in the IGBT device; C GC is a capacitance between the gate and the collector in the IGBT device; V CE is a voltage between the collector and the emitter in the IGBT device; V GE is a voltage between the gate and the emitter in the IGBT device; I CE is a current between the collector and the emitter in the IGBT device; generally, an existing modeling method considers that as long as DC I CE -V CE data and C-V CE data are perfectly fitted, the model can accurately match a switching waveform obtained by actual testing. In fact, unlike a unipolar device, the IGBT has a unique conductance modulation effect, so that a large number of hole carriers are injected from a collector region to a drift region in a conduction state, and a dynamic change characteristic of a reverse transmission capacitance is not as smooth as that under a test condition V GE = 0 V, but instead presents a more steep change trend. Therefore, the existing modeling method cannot well simulate the dynamic capacitance change characteristic of the IGBT device.

[0003] In a simulation design process, noise suppression and switching loss optimization are both related to improvement of a nonlinear characteristic of the capacitance. For example, smaller C GE and C GCBoth are the main factors leading to the aggravation of the device drain current voltage oscillation or the increase of overshoot. Thus, accurately modeling the dynamic capacitance nonlinear variation characteristics of the IGBT will be an important condition for predicting the switching performance of the IGBT in the application circuit. At present, the application of the IGBT in engineering is mostly based on extensive experience and limited manual data. Therefore, it is quite necessary to study the behavior of the IGBT device under normal switching conditions. SUMMARY

[0004] The application provides a modeling method, device, storage medium and program product of an insulated gate bipolar transistor, so as to realize analysis on the behavior change of the insulated gate bipolar transistor in a switching process.

[0005] According to an aspect of the application, a modeling method of an insulated gate bipolar transistor is provided, which comprises:

[0006] Obtaining capacitance test data between a gate and a collector of the insulated gate bipolar transistor;

[0007] Constructing a dynamic capacitance segmented function of the insulated gate bipolar transistor in an on stage and an off stage according to a preset circuit model;

[0008] Performing parameter extraction on the segmented function based on the capacitance test data, so as to describe the capacitance change of the insulated gate bipolar transistor in the on process and / or the off process.

[0009] Optionally, the preset circuit model comprises a first circuit model and a second circuit model; the first circuit model comprises the insulated gate bipolar transistor, a first voltage-controlled voltage source, a first capacitor, a second voltage-controlled voltage source, a second capacitor, a third capacitor and a first voltage source; the second circuit model comprises a first current source, a first resistor, a fourth capacitor and a second voltage source; the collector of the insulated gate bipolar transistor is connected with one end of the first voltage source, the other end of the first voltage source is connected with one end of the first capacitor and one end of the second capacitor, and a connection point is a first node; the other end of the first capacitor is connected with one end of the first voltage-controlled voltage source; the other end of the first voltage-controlled voltage source is connected with the gate of the insulated gate bipolar transistor and one end of the third capacitor, and a connection point is a second node; the other end of the third capacitor is connected with the emitter of the insulated gate bipolar transistor and one end of the second voltage-controlled voltage source; the other end of the second voltage-controlled voltage source is connected with the other end of the second capacitor; one end of the first current source is connected with one end of the second voltage source and one end of the fourth capacitor; the other end of the second voltage source is connected with one end of the first resistor; the other end of the first resistor is connected with the other end of the first current source and the other end of the fourth capacitor, and is grounded;

[0010] Constructing the dynamic capacitance segmented function of the insulated gate bipolar transistor in the on stage and the off stage according to the preset circuit model, comprising:

[0011] A first function is established according to the first circuit model and the second circuit model:

[0012] E GC = V 12 - f(V 12 ) / C0;

[0013] wherein, E GC is a first voltage-controlled voltage source; V 12 is a voltage between the first node and the second node; f(V 12 ) is a first sub-function, the first sub-function f(V 12 ) is determined according to the voltage V 12 between the first node and the second node; and C0 is a fourth capacitor;

[0014] A state of the insulated gate bipolar transistor is determined according to a current relationship in the first circuit model and the second circuit model.

[0015] A piecewise function is determined according to the first function and the state of the insulated gate bipolar transistor.

[0016] Optionally, the state of the insulated gate bipolar transistor is determined according to the current relationship in the first circuit model and the second circuit model, comprising:

[0017] When a difference between the current of the first current source and the current flowing through the second voltage source is greater than or equal to zero, it is determined that the insulated gate bipolar transistor is in an on state.

[0018] When the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, it is determined that the insulated gate bipolar transistor is in an off state; wherein the current of the first current source is equal to the current flowing through the first voltage source.

[0019] Optionally, the first sub-function f(V 12 ) is determined according to the voltage V 12 between the first node and the second node, comprising:

[0020] When the voltage V 12 between the first node and the second node is less than or equal to zero, the first sub-function f(V 12 ) is equal to 0.

[0021] When the voltage V 12 between the first node and the second node is greater than zero, the first sub-function is: wherein, C GC0 is a first capacitor; V CG is a voltage between a collector and a gate of the insulated gate bipolar transistor; and V CG *a first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is a first fitting coefficient;

[0022] determining the piecewise function according to the first function and the state of the insulated gate bipolar transistor, including:

[0023]

[0024] wherein E GC is a first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; C GC0 is a first capacitor; V CG is the voltage between the collector and the gate of the insulated gate bipolar transistor; V CG * a first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco is a first fitting coefficient; C0 is a fourth capacitor; V CG *′ a second adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; mjco' is a second fitting coefficient; I(G0) is the current of the first current source; I(V0) is the current flowing through the second voltage source.

[0025] Optionally, the capacitor test data between the gate and the collector of the insulated gate bipolar transistor is obtained, including:

[0026] a switch test circuit is built, and the first test data is tested and obtained; wherein the first test data includes the voltage between the collector and the emitter, the voltage between the gate and the emitter, and the gate current;

[0027] The capacitor test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the first test data.

[0028] Optionally, the capacitor test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the first test data, including:

[0029] The capacitor test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the following formula:

[0030]

[0031] wherein C GC.dynamic is the capacitor test data between the gate and the collector of the insulated gate bipolar transistor; I G is the gate current; C GE is a third capacitor; V GE is the voltage between the gate and the emitter; V CE is the voltage between the collector and the emitter.

[0032] Optionally, after calculating the capacitance test data between the gate and the collector of the insulated gate bipolar transistor according to the first test data, further comprising:

[0033] Processing the test data, converting the independent variable from a time variable to a voltage change variable between the collector and the gate.

[0034] According to another aspect of the present application, there is provided a modeling device of an insulated gate bipolar transistor, comprising:

[0035] A capacitance test data acquisition module is configured to acquire capacitance test data between the gate and the collector of the insulated gate bipolar transistor.

[0036] A piecewise function construction module is configured to construct a dynamic capacitance piecewise function of the insulated gate bipolar transistor in the on and off stages according to a preset circuit model.

[0037] A parameter extraction module is configured to perform parameter extraction on the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor in the on and / or off process.

[0038] According to another aspect of the present application, there is provided a computer readable medium, which stores computer instructions for causing a processor to implement the modeling method of the insulated gate bipolar transistor according to any of the embodiments of the present application.

[0039] According to another aspect of the present application, there is provided a computer program product, which comprises a computer program for implementing the modeling method of the insulated gate bipolar transistor according to any of the embodiments of the present application when executed by a processor.

[0040] The technical solution of the embodiments of the present application sets the modeling method of the insulated gate bipolar transistor, acquires the capacitance test data between the gate and the collector of the insulated gate bipolar transistor, constructs a dynamic capacitance piecewise function of the insulated gate bipolar transistor in the on and off stages according to a preset circuit model, performs parameter extraction on the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor in the on and / or off process, and analyzes the behavior change of the insulated gate bipolar transistor in the switching process. By establishing the piecewise function, the on and off processes of the insulated gate bipolar transistor are analyzed respectively, and the reliability of the behavior change analysis of the insulated gate bipolar transistor in the switching process is improved.

[0041] It is to be understood that the details described in this section are not intended to identify key or critical elements of the embodiments of the application or to limit the scope of the application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0043] Figure 1 is a modeling method of an insulated gate bipolar transistor in the related art and a fitting curve thereof;

[0044] Figure 2 is a flow chart of a modeling method of an insulated gate bipolar transistor according to an embodiment of the present application;

[0045] Figure 3 is a change of a capacitance between a gate and a collector of an insulated gate bipolar transistor under different test conditions according to an embodiment of the present application;

[0046] Figure 4 is a flow chart of another modeling method of an insulated gate bipolar transistor according to an embodiment of the present application;

[0047] Figure 5 is a structural schematic diagram of a first circuit model according to an embodiment of the present application;

[0048] Figure 6 is a structural schematic diagram of a second circuit model according to an embodiment of the present application;

[0049] Figure 7 is a flow chart of still another modeling method of an insulated gate bipolar transistor according to an embodiment of the present application;

[0050] Figure 8 is a structural schematic diagram of a modeling device of an insulated gate bipolar transistor according to an embodiment of the present application;

[0051] Figure 9 is a structural schematic diagram of a modeling device of an insulated gate bipolar transistor for implementing a modeling method of an insulated gate bipolar transistor according to an embodiment of the present application. DETAILED DESCRIPTION

[0052] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort should fall into the protection scope of the present application.

[0053] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a list of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products or devices.

[0054] Figure 2 is a flowchart of a modeling method of an insulated gate bipolar transistor according to an embodiment of the present application. The embodiments of the present application can be applicable to modeling of an insulated gate bipolar transistor, and the modeling method of the insulated gate bipolar transistor can be executed by a modeling device of the insulated gate bipolar transistor, which can be realized in the form of hardware and / or software. As shown in Figure 2 , the modeling method of the insulated gate bipolar transistor includes:

[0055] S110, obtaining capacitance test data between a gate and a collector of an insulated gate bipolar transistor.

[0056] Specifically, the capacitance between the gate and the collector of the insulated gate bipolar transistor can be represented by C GC . The obtained capacitance test data between the gate and the collector of the IGBT can be represented by C GC.dynamic . C GC is a key parasitic parameter affecting the switching characteristics of the IGBT, and the value of C GC changes dynamically with the voltage V CE between the collector and the emitter of the IGBT, the voltage V GE between the gate and the emitter, and the working phase (turning on or turning off). For example, a double-pulse test circuit can be built, the IGBT is driven by a pulse signal, and V GE and V CEData such as C is captured using an oscilloscope during the switching transient process. GC The dynamic changes. For example, a switch test circuit can be built to test and acquire relevant data to obtain C. GC Dynamically changing data. Figure 3 This refers to the capacitance variation between the gate and collector of an insulated-gate bipolar transistor under different test conditions provided by embodiments of the present invention. For example... Figure 3 As shown, Crss@100kHz represents the voltage V between the gate and emitter of the IGBT. GE C under test conditions of 0V GC Changes; C GC (turn-on) indicates that the IGBT is in the turn-on phase (C). GC Changes; C GC (turn-off) indicates the C value of the IGBT during the turn-off phase. GC Changes. From Figure 3 It can be seen that IGBT in V GE C under test conditions of 0V, during the turn-on and turn-off phases GC The changes are quite different. Therefore, in order to accurately describe the switching behavior of IGBTs, it is necessary to study the dynamic C. GC To perform accurate modeling.

[0057] S120. Construct the dynamic capacitance piecewise function of the insulated gate bipolar transistor during the turn-on and turn-off phases based on the preset circuit model.

[0058] Specifically, according to Figure 3 The test results shown indicate that dynamic C needs to be tested. GC Accurate modeling is crucial to accurately describe the switching behavior of the IGBT. For example, piecewise functions can be established to analyze the IGBT's turn-on and turn-off phases separately. The preset circuit model is a pre-defined model topology. This preset circuit model can include two circuit models: one for placing the DC IGBT model, setting the capacitance and voltage of different nodes in the DC IGBT model; and the other for identifying the moments when the model enters turn-on or turn-off during simulation.

[0059] S130. Extract parameters from the piecewise function based on capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process.

[0060] Specifically, according to the above steps, the capacitance test data and the dynamic capacitance segmented function of the IGBT in the opening stage and the turn-off stage can be obtained, and the segmented function is parameterized based on the capacitance test data to describe the capacitance change of the IGBT in the opening and / or turn-off process. The parameterization can be realized by software such as Integrated Circuit Characterization and Analysis Program (ICCAP) or Matrix Laboratory (MATLAB).

[0061] The technical scheme of the embodiment of the present application sets the modeling method of the IGBT, acquires the capacitance test data between the gate and the collector of the IGBT, constructs the dynamic capacitance segmented function of the IGBT in the opening stage and the turn-off stage according to the preset circuit model, parameterizes the segmented function based on the capacitance test data to describe the capacitance change of the IGBT in the opening and / or turn-off process, and realizes the behavior change analysis of the IGBT in the switching process. By establishing the segmented function, the opening and turn-off processes of the IGBT are analyzed respectively, and the reliability of the behavior change analysis of the IGBT in the switching process is improved.

[0062] Figure 4 is a flow chart of another modeling method of an IGBT provided by the embodiment of the present application. The embodiment of the present application is a detailed description of the technical features of the above-mentioned embodiment. Figure 5 is a structural schematic diagram of a first circuit model according to the embodiment of the present application. Figure 6 is a structural schematic diagram of a second circuit model according to the embodiment of the present application. As shown in Figure 5 and Figure 6 , the preset circuit model includes the first circuit model and the second circuit model. The first circuit model includes the IGBT, a first voltage-controlled voltage source E GC , a first capacitor C GC0 , a second voltage-controlled voltage source E CE , a second capacitor C CE0 , a third capacitor C GE , and a first voltage source V1; the second circuit model includes a first current source G0, a first resistor R0, a fourth capacitor C0, and a second voltage source V0; the collector of the IGBT is connected with one end of the first voltage source V1, the other end of the first voltage source V1 is connected with one end of the first capacitor C GC0 and one end of the second capacitor C CE0 , and the connection point is a first node 1; the other end of the first capacitor C GC0 is connected with the first voltage-controlled voltage source EGC one end of the first voltage-controlled voltage source E GC the other end of the third capacitor C GE is connected to the gate of the insulated gate bipolar transistor IGBT and the third capacitor C GE one end of the second voltage-controlled voltage source E CE the other end of the second capacitor C CE is connected to the emitter of the insulated gate bipolar transistor IGBT and the second voltage-controlled voltage source E CE0 one end of the second voltage source V0 and one end of the fourth capacitor C0; the other end of the second voltage source V0 is connected to one end of the first resistor R0; the other end of the first resistor R0 is connected to the other end of the first current source G0 and the other end of the fourth capacitor C0 and is grounded. The first circuit model and the second circuit model further comprise a third node 3 between the second voltage-controlled voltage source E CE , the third capacitor C GE and the emitter of the IGBT; a fourth node 4 between the first voltage-controlled voltage source E GC and the first capacitor C GC0 ; a fifth node 5 between the collector of the IGBT and the first voltage source V1; a sixth node 6 between the second voltage-controlled voltage source E CE and the second capacitor C CE0 ; a seventh node 7 at the connection point of one end of the first current source G0, one end of the second voltage source V0 and one end of the fourth capacitor C0; an eighth node 8 between the second voltage source V0 and the first resistor R0; a ninth node 9 at the connection point of the other end of the first resistor R0 and the other end of the first current source G0 and the other end of the fourth capacitor C0.

[0063] Specifically, a DC IGBT model is placed between the second node 2, the third node 3 and the fifth node 5; a constant third capacitor C GE is placed between the second node 2 and the third node 3 to represent the IGBT gate-emitter capacitance; the first voltage-controlled voltage source E GC is connected in series with a constant first capacitor C GC0 to represent the IGBT gate-collector capacitance; the second voltage-controlled voltage source E CE is connected in series with a constant second capacitor C CE0 to represent the IGBT collector-emitter capacitance. The first current source G0 in parallel with the RC circuit module in the second circuit model is used to identify the time when the model simulation enters the on stage / off stage. The first voltage source V1 and the second voltage source V0 are set to zero to detect the corresponding branch current and are called into the corresponding function expression.

[0064] As Figure 4 shown, the modeling method of the insulated gate bipolar transistor includes:

[0065] S210, obtaining the capacitance test data between the gate and the collector of the insulated gate bipolar transistor. S220, establishing a first function according to the first circuit model and the second circuit model:

[0066] E GC = V 12 -f(V 12 ) / C0;

[0067] wherein, E GC is a first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; f(V 12 ) is a first sub-function, the first sub-function f(V 12 ) is determined according to the voltage V 12 between the first node and the second node; and C0 is a fourth capacitance.

[0068] Specifically, C GC.dynamic may also represent a port equivalent capacitance. The derivation process of the port equivalent capacitance can be represented by the following formula:

[0069]

[0070] As can be seen from formula (3), the port equivalent capacitance C GC.dynamic is ultimately in the form of the first-order derivative of the first sub-function f(V 12 ).

[0071] In an optional embodiment of the present application, the first sub-function f(V 12 ) is determined according to the voltage V 12 between the first node and the second node, and includes:

[0072] When the voltage V 12 between the first node and the second node is less than or equal to zero, the first sub-function f(V 12 ) is equal to 0; when the voltage V 12 between the first node and the second node is greater than zero, the first sub-function is: wherein, C GC0 is a first capacitance; V CG is the voltage between the collector and the gate of the insulated gate bipolar transistor; V CG * is a first adjustment factor of the voltage between the collector and the gate of the insulated gate bipolar transistor; and mjco is a first fitting coefficient.

[0073] Specifically, when the voltage V 12 between the first node and the second node is less than or equal to zero, i.e., the voltage V GC between the gate and the collector of the IGBT is V 12 <0, the first sub-function f(V GC.dynamic ) = 0, and the port equivalent capacitance C GC0 is equal to the first capacitance C GC0 . The first capacitance C GC0 is the port equivalent capacitance when the bias voltage across the capacitance is 0V, to ensure the continuity of the function.

[0074] When the voltage V 12 between the first node and the second node is greater than zero, i.e., the voltage V GC >0 between the gate and the collector of the IGBT, the first sub-function is: where C GC0 is the first capacitance; V CG is the voltage between the collector and the gate of the IGBT; V CG * is the first adjustment factor of the voltage between the collector and the gate of the IGBT; and mjco is the first fitting coefficient. When the bias voltage across the capacitance is greater, the exponential function part is smaller, and the physical meaning is that the larger the bias voltage of the device, the wider the depletion region, and the smaller the capacitance. The first adjustment factor V CG * and the first fitting coefficient mjco can be obtained by parameter extraction software.

[0075] S230, determining the state of the IGBT according to the current relationship in the first circuit model and the second circuit model.

[0076] Specifically, the current I CE between the collector and the emitter in the IGBT model can be captured by setting the currents of the first node 1 and the fifth node 5 on the voltage source detection branch to zero, i.e., the current I(V1) flowing through the first voltage source V1, and setting the current I(G0) of the first current source to be equal to the current I(V1) flowing through the first voltage source V1. When the device is in an on state, the current I CE between the collector and the emitter gradually increases over time, which is represented in the second circuit model as the first current source G0 continuously charging the constant fourth capacitance C0 and generating a current on the first resistor R0, at this time I(G0) = I(V0) + I(C0), I(V0) being the current flowing through the second voltage source V0; when the device is turned off, the current generated by the first current source G0 gradually decreases, and the fourth capacitance C0 begins to discharge externally, generating a current flowing through the first resistor R0 on the branch between the seventh node 7 and the ninth node 9 and being detected by the second voltage source V0, at this time the loop satisfies: I(V0) = I(G0) + I(C0).

[0077] Therefore, the state of the IGBT device can be determined according to the magnitude relationship between the current of the first current source G0 and the current flowing through the second voltage source V0.

[0078] In an optional embodiment of the present application, the state of the IGBT is determined according to the current relationship in the first circuit model and the second circuit model, including: when the difference between the current of the first current source and the current flowing through the second voltage source is greater than or equal to zero, determining that the IGBT is in an open state; when the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, determining that the IGBT is in a closed state; wherein the current of the first current source is equal to the current flowing through the first voltage source.

[0079] Specifically, when the difference between the current I(G0) of the first current source and the current I(V0) flowing through the second voltage source V0 is greater than or equal to zero, it is determined that the IGBT is in an open state; when the difference between the current I(G0) of the first current source and the current I(V0) flowing through the second voltage source V0 is less than zero, it is determined that the IGBT is in a closed state.

[0080] S240, determining the piecewise function according to the first function and the state of the IGBT.

[0081] In an optional embodiment of the present application, the piecewise function is determined according to the first function and the state of the IGBT, including:

[0082]

[0083] Wherein, E GC is a first voltage-controlled voltage source; V 12 is the voltage between the first node and the second node; C GC0 is a first capacitor; V CG is the voltage between the collector and the gate of the IGBT; V CG * is a first adjustment factor of the voltage between the collector and the gate of the IGBT; mico is a first fitting coefficient; C0 is a fourth capacitor; V CG *′ is a second adjustment factor of the voltage between the collector and the gate of the IGBT; mico' is a second fitting coefficient; I(G0) is the current of the first current source; I(V0) is the current flowing through the second voltage source.

[0084] S250, parameter extraction is performed on the piecewise function based on the capacitance test data to describe the capacitance change of the IGBT in the process of opening and / or closing.

[0085] Specifically, the identification of the IGBT opening / closing process is realized by the current source parallel RC circuit module in the second circuit model, and then the C GC.dynamic The different characteristics of the opening / closing process are described respectively, avoiding the seesaw effect that the opening process is accurate and the closing process is inaccurate or the opening process is inaccurate and the closing process is accurate in the fitting process.

[0086] Figure 7 A flowchart of another modeling method of an insulated gate bipolar transistor is provided according to an embodiment of the present application. As shown in the figure, the modeling method of the insulated gate bipolar transistor comprises: Figure 7

[0087] S310, a switch test circuit is built, and first test data is tested and acquired; wherein the first test data comprises a voltage between the collector and the emitter, a voltage between the gate and the emitter, and a gate current.

[0088] Specifically, the switch test circuit can be a dynamic parameter test (DPT) circuit. The DPT circuit is a special test system for evaluating the electrical characteristics of electronic components (such as transistors or sensors, etc.) in a dynamic working state, and its core purpose is to simulate the signal change scene (such as high-frequency clock, pulse signal or load fluctuation, etc.) of the device in actual work, and accurately measure its dynamic parameters (such as switching delay, power consumption or frequency response, etc.). The DPT circuit can be composed of a power supply and power supply control module, a signal excitation generation module, a load simulation module, a measurement and data acquisition module, and an environment control module. The power supply and power supply control module can provide stable and adjustable power supply voltage, support voltage fluctuation simulation (such as ripple or transient change) in dynamic testing. The signal excitation generation module is used to generate input signals (such as clock, data pulse or analog signal, etc.) that meet the test conditions, control signal frequency, amplitude or edge time parameters. The load simulation module is used to simulate the load effect of the device in the actual circuit, including capacitance, resistance and current load, etc. The measurement and data acquisition module is used to collect the dynamic response signals of the device in real time, and convert them into analyzable data (such as voltage, current or timing waveform, etc.). The environment control module is used to control the test environment parameters to ensure that the test conditions meet the datasheet requirements.

[0089] After the switch test circuit is built, the bus voltage and current at the switch time are set according to the device voltage and current level or simulation requirements such as application scenarios, and the first test data is tested and acquired. The first test data includes the voltage V CE between the collector and the emitter, the voltage V GE between the gate and the emitter, and the gate current I G . The first test data also includes the current I​CE .

[0090] S320, calculate the capacitance test data between the gate and the collector of the insulated gate bipolar transistor according to the first test data.

[0091] Specifically, the following relationship can be obtained according to the switch test circuit:

[0092] I G =I GC +I GE (4);

[0093]

[0094] wherein, I GC is the current between the gate and the collector; I GE is the current between the gate and the emitter; C GE is the capacitance between the gate and the emitter; V GE is the voltage between the gate and the emitter; C GC.dynamic is the capacitance test data between the gate and the collector of the insulated gate bipolar transistor; I GC.dynamic is the current test data between the gate and the collector of the insulated gate bipolar transistor; V CE is the voltage between the collector and the emitter.

[0095] In the optional embodiment of the present application, the capacitance test data between the gate and the collector of the insulated gate bipolar transistor is calculated according to the following formula:

[0096]

[0097] wherein, C GC.dynamic is the capacitance test data between the gate and the collector of the insulated gate bipolar transistor; I G is the gate current; C GE is the third capacitance; V GE is the voltage between the gate and the emitter; V CE is the voltage between the collector and the emitter.

[0098] Specifically, the expression can be calculated by the above formula (4), formula (5) and formula (6). Through the formula, the capacitance test data C GC.dynamic between the gate and the collector of the insulated gate bipolar transistor can be obtained according to the measured first test data.

[0099] S330, process the test data, and convert the independent variable from the time variable to the voltage change between the collector and the gate.

[0100] Specifically, the test data is processed, and the independent variable is converted from a time variable to a voltage V between the collector and the gate CG The change amount is converted, and parameter extraction is facilitated.

[0101] S340, constructing a dynamic capacitance segmented function of the insulated gate bipolar transistor in the opening stage and the shutdown stage according to a preset circuit model.

[0102] S350, parameter extraction is performed on the segmented function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor in the opening and / or shutdown process.

[0103] Figure 8 It is a structure schematic diagram of a modeling device of an insulated gate bipolar transistor provided according to an embodiment of the present application. As shown in the figure, Figure 8 The modeling device of the insulated gate bipolar transistor comprises:

[0104] The capacitance test data acquisition module 100 is configured to acquire capacitance test data between the gate and the collector of the insulated gate bipolar transistor.

[0105] The segmented function construction module 200 is configured to construct a dynamic capacitance segmented function of the insulated gate bipolar transistor in the opening stage and the shutdown stage according to a preset circuit model.

[0106] The parameter extraction module 300 is configured to perform parameter extraction on the segmented function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor in the opening and / or shutdown process.

[0107] The modeling device of the insulated gate bipolar transistor of the embodiment of the present application is used to perform the modeling method of the insulated gate bipolar transistor of any embodiment of the present application, and has the corresponding beneficial effects.

[0108] Figure 9 It is a structure schematic diagram of a modeling device of an insulated gate bipolar transistor provided according to an embodiment of the present application. As shown in the figure, Figure 9As shown, the insulated-gate bipolar transistor modeling device 10 includes at least one processor 11, and memories, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., communicatively connected to the at least one processor 11, where the memories store computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer programs stored in the read-only memory (ROM) 12 or loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the insulated-gate bipolar transistor modeling device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0109] Various components in the insulated-gate bipolar transistor modeling device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc., an output unit 17, such as various types of displays, speakers, etc., a storage unit 18, such as a magnetic disk, an optical disk, etc., and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the insulated-gate bipolar transistor modeling device 10 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0110] The processor 11 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs various methods and processes described above, such as the insulated-gate bipolar transistor modeling method.

[0111] In some embodiments, the insulated-gate bipolar transistor modeling method can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the insulated-gate bipolar transistor modeling device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the insulated-gate bipolar transistor modeling method described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the insulated-gate bipolar transistor modeling method by any other appropriate means, such as by means of firmware.

[0112] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0113] Computer programs used to implement the processes of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer program, when executed, can cause instructions defined in the flow charts and / or block diagrams to be implemented. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.

[0114] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0115] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0116] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), blockchain network, and the Internet.

[0117] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and virtual private server (VPS) services.

[0118] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in different orders, as long as the desired results of the present disclosure are achieved, and the present disclosure is not limited herein.

[0119] The above detailed description does not limit the scope of the application. Various modifications, combinations, sub-combinations and alternatives can be made to the detailed description. Any modification, equivalent replacement and improvement etc. made within the spirit and principle of the application shall be included in the scope of the application.

Claims

1. A modeling method for an insulated-gate bipolar transistor, characterized in that, include: Obtain capacitance test data between the gate and collector of an insulated-gate bipolar transistor; The dynamic capacitance piecewise function of the insulated gate bipolar transistor during the turn-on and turn-off phases is constructed based on the preset circuit model. Based on the capacitance test data, parameters are extracted from the piecewise function to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process. The preset circuit model includes a first circuit model and a second circuit model; the first circuit model includes an insulated-gate bipolar transistor (IGBT), a first voltage-controlled voltage source (VDC), a first capacitor, a second VDC, a second capacitor, a third capacitor, and a first voltage source; the second circuit model includes a first current source, a first resistor, a fourth capacitor, and a second voltage source; the collector of the IGBT is connected to one end of the first voltage source, and the other end of the first voltage source is connected to one end of the first capacitor and one end of the second capacitor, with the connection point being a first node; the other end of the first capacitor is connected to one end of the first VDC; the other end of the first VDC is connected to the gate of the IGBT and one end of the third capacitor, with the connection point being a second node; the other end of the third capacitor is connected to the emitter of the IGBT and one end of the second VDC; the other end of the second VDC is connected to the other end of the second capacitor; one end of the first current source is connected to one end of the second voltage source and one end of the fourth capacitor; The other end of the second voltage source is connected to one end of the first resistor; the other end of the first resistor is connected to the other end of the first current source and the other end of the fourth capacitor and is grounded; The step of constructing the dynamic capacitance piecewise function of the insulated gate bipolar transistor during the turn-on and turn-off phases based on a preset circuit model includes: Based on the first circuit model and the second circuit model, establish the first function: ； in, This is the first voltage-controlled voltage source; This represents the voltage between the first node and the second node. The first sub-function, the first sub-function Based on the voltage between the first node and the second node Sure; This is the fourth capacitor; The state of the insulated gate bipolar transistor is determined based on the current relationship in the first circuit model and the second circuit model. The piecewise function is determined based on the first function and the state of the insulated gate bipolar transistor. First sub-function Based on the voltage between the first node and the second node Determined, including: When the voltage between the first node and the second node When less than or equal to zero, the first sub-function Equal to 0; When the voltage between the first node and the second node When the value is greater than zero, the first sub-function is: ;in, This is the first capacitor; This is the voltage between the collector and gate of an insulated-gate bipolar transistor. It is the first regulation factor for the voltage between the collector and gate of an insulated-gate bipolar transistor; The first fitting coefficient; Determining the piecewise function based on the first function and the state of the insulated gate bipolar transistor includes: ； in, This is the first voltage-controlled voltage source; This represents the voltage between the first node and the second node. This is the first capacitor; This is the voltage between the collector and gate of an insulated-gate bipolar transistor. It is the first regulation factor for the voltage between the collector and gate of an insulated-gate bipolar transistor; The first fitting coefficient; This is the fourth capacitor; It is a second regulation factor for the voltage between the collector and gate of an insulated-gate bipolar transistor; The second fitting coefficient; The current of the first current source; The current flowing through the second voltage source is denoted as .

2. The modeling method for an insulated gate bipolar transistor according to claim 1, characterized in that, Determining the state of the insulated gate bipolar transistor based on the current relationship in the first circuit model and the second circuit model includes: When the difference between the current of the first current source and the current flowing through the second voltage source is greater than or equal to zero, it is determined that the insulated gate bipolar transistor is in the on state. When the difference between the current of the first current source and the current flowing through the second voltage source is less than zero, the insulated gate bipolar transistor is determined to be in the off state; wherein, the current of the first current source is equal to the current flowing through the first voltage source.

3. The modeling method for an insulated gate bipolar transistor according to claim 1, characterized in that, The acquisition of capacitance test data between the gate and collector of an insulated gate bipolar transistor includes: A switch test circuit is built to test and acquire the first test data; wherein, the first test data includes the voltage between the collector and emitter, the voltage between the gate and emitter, and the gate current; Calculate the capacitance test data between the gate and collector of the insulated gate bipolar transistor based on the first test data.

4. The modeling method for an insulated gate bipolar transistor according to claim 3, characterized in that, The step of calculating the capacitance test data between the gate and collector of the insulated gate bipolar transistor based on the first test data includes: The capacitance test data between the gate and collector of the insulated-gate bipolar transistor is calculated using the following formula: ； in, This is the capacitance test data between the gate and collector of an insulated-gate bipolar transistor. This is the gate current; This is the third capacitor; This is the voltage between the gate and the emitter; This is the voltage between the collector and emitter.

5. The modeling method for an insulated gate bipolar transistor according to claim 3, characterized in that, After calculating the capacitance test data between the gate and collector of the insulated gate bipolar transistor based on the first test data, the method further includes: The test data is processed by converting the independent variable from a time variable into the voltage change between the collector and the gate.

6. A modeling apparatus for an insulated gate bipolar transistor, characterized in that, A modeling method for performing the insulated-gate bipolar transistor according to any one of claims 1-5, comprising: The capacitance test data acquisition module is used to acquire the capacitance test data between the gate and collector of an insulated gate bipolar transistor. The piecewise function construction module is used to construct the dynamic capacitance piecewise function of the insulated gate bipolar transistor in the turn-on and turn-off phases according to the preset circuit model. The parameter extraction module is used to extract parameters from the piecewise function based on the capacitance test data to describe the capacitance change of the insulated gate bipolar transistor during the turn-on and / or turn-off process.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the modeling method of the insulated gate bipolar transistor according to any one of claims 1-5.

8. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the modeling method for an insulated gate bipolar transistor according to any one of claims 1-5.

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