Reset controllable circuit without power dependence and use method

Abstract

The invention discloses a reset controllable circuit without power dependence and a use method, and relates to the technical field of circuit design, the reset controllable circuit comprises a watchdog chip U1 and a connection pin J1; the watchdog circuit further comprises a three-pin diode D1, a capacitor C1 and a capacitor C2. The two ends of the capacitor C1 and the two ends of the capacitor C2 are connected with a second pin and a third pin of the watchdog chip U1 respectively. A second pin of the three-pin diode D1 is respectively connected with a second pin of the watchdog chip U1 and a digital power supply of the watchdog chip U1, a first pin of the three-pin diode D1 is connected with a first pin of the connecting pin J1, and a third pin of the three-pin diode D1 is connected with an analog power supply of the watchdog chip U1; the problem that in the software debugging and program programming process, a product needs to be powered on and short-circuited with a contact pin is solved, the product debugging and program programming efficiency is improved, in the production process, human risks can be effectively eliminated, and the product reliability is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and more particularly to a reset controllable circuit without power dependence and a use method thereof. Background Art

[0002] In the process of embedded development, the watchdog is an important part of the hardware circuit and plays a vital role in software and hardware debugging, production and product reliability. The reset circuit design of the watchdog is particularly important. The circuit structure used in the existing technology is as follows: Figure 1 As shown, the pin at J1 is used to connect to the emulator J-LINK. When debugging the software and burning the program, you need to power on the product and then short-circuit the pin at JP1 with a shorting cap to make the first pin of U1 at a high level, making the watchdog invalid and preventing the debug interruption or program burning failure caused by the watchdog sending a reset signal.

[0003] However, this circuit structure has the following problems: software debugging and program burning are cumbersome operations, requiring the product to be powered on and the JP1 pin to be short-circuited, which is inefficient. In addition, during the production process, there is a possibility that the shorting cap at JP1 is forgotten, causing the watchdog to always fail, seriously affecting product reliability and posing a high risk. Summary of the Invention

[0004] The purpose of the present invention is to provide a reset controllable circuit that is not dependent on power supply and its use method, so as to solve the problem that the product needs to be powered on and the pins need to be short-circuited during software debugging and program burning, thereby improving the efficiency of product debugging and program burning, and effectively eliminating human risks in the production process and improving product reliability.

[0005] The above technical objectives of the present invention are achieved through the following technical solutions: In a first aspect, the present application provides a reset controllable circuit that is not dependent on power supply, including a watchdog chip U1 and a connecting pin J1, wherein: Pin 1 and pin 8 of the watchdog chip U1 are connected to one end of resistor R1 and one end of resistor R2 respectively. The other end of resistor R1 and the other end of resistor R2 are connected to pin 5 of connector J1. It also includes a three-pin diode D1, a capacitor C1 and a capacitor C2, where: The two ends of capacitor C1 and capacitor C2 are connected to the 2nd pin and 3rd pin of the watchdog chip U1 respectively; the 2nd pin of the three-pin diode D1 is connected to the 2nd pin of the watchdog chip U1 and the digital power supply of the watchdog chip U1 respectively, the 1st pin of the three-pin diode D1 is connected to the 1st pin of the connecting pin J1, and the 3rd pin of the three-pin diode D1 is connected to the analog power supply of the watchdog chip U1.

[0006] On the basis of the above technical solution, the present invention can also be improved as follows.

[0007] Furthermore, the reset controllable circuit further includes a resistor R3 , one end of the resistor R3 is connected to the 6th pin of the watchdog chip U1 , and the other end of the resistor R3 is connected to the digital power supply of the watchdog chip U1 .

[0008] Furthermore, the reset controllable circuit further includes a resistor R4 , one end of the resistor R4 is connected to the 7th pin of the watchdog chip U1 , and the other end of the resistor R4 is grounded.

[0009] Furthermore, the model of the three-pin diode D1 is BAT54C.

[0010] Furthermore, the model of the capacitor C1 is C0603-X7R-25-μ10-K; the model of the capacitor C2 is C0603-COG-25-1000-J.

[0011] Furthermore, the models of the resistor R1 and the resistor R2 are R0603-620R-F.

[0012] Furthermore, the models of the resistor R1 and the resistor R2 are R0603-620R-F.

[0013] In a second aspect, the present application provides a method for using a reset controllable circuit without power dependence, which is applied to any reset controllable circuit without power dependence in the first aspect, comprising the following specific steps: Before debugging the software or burning the program on the watchdog chip U1, connect the emulator through the connector pin J1; When the watchdog chip U1 needs to be reset during software debugging or program burning, a low-level pulse signal is sent to the 1st pin of the watchdog chip U1 through the 5th pin of the connecting pin J1.

[0014] In a third aspect, the present application provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the method of the second aspect is implemented when the processor executes the computer program.

[0015] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions enable a computer to execute the method of the second aspect.

[0016] Compared with the prior art, the present invention has at least the following beneficial effects: In this application, the SWD3.3V of the emulator is connected to the VDD3.3V and VDDA3.3V of the microcontroller through BAT54C. Since the two diodes of BAT54C are germanium diodes, the voltage drop is low to meet the power supply requirements of the microcontroller, and since the 1 pin of the watchdog chip is connected to the NJRST pin of the emulator, the normal state is high, which makes the watchdog chip in an invalid state, and it can be achieved without powering on to burn the program and no longer have the previous short-circuit operation; and when debugging the program, the microcontroller can be reset at any time by sending a low-level pulse signal to the 1 pin of the watchdog chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of this application, and do not constitute a limitation of the embodiments of the present invention. In the drawings: Figure 1 Schematic diagram of the circuit structure used in the prior art; Figure 2 Schematic diagram of a reset controllable circuit in an embodiment of the present application; Figure 3 This is a connection diagram of the actual use of the reset controllable circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0020] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0021] In the description of the embodiments of the present invention, "a plurality of" means at least two.

[0022] In the description of the embodiments of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0023] Example 1: Due to the cumbersome operation when debugging and burning the program, the product needs to be powered on and short-circuited. Figure 1 The JP1 pin in the PCB is inserted, resulting in low efficiency; and in the production process, there is a situation where the shorting cap at JP1 is forgotten to be removed, resulting in the watchdog always failing, seriously affecting product reliability and leading to higher risks. This embodiment provides a reset controllable circuit that is not dependent on power supply, such as Figure 2 As shown, it includes a watchdog chip U1 and a connecting pin J1, where: Pin 1 and pin 8 of the watchdog chip U1 are connected to one end of the resistor R1 and one end of the resistor R2 respectively. The other end of the resistor R1 and the other end of the resistor R2 are connected to pin 5 of the connector J1.

[0024] The reset controllable circuit also includes a three-pin diode D1, a capacitor C1 and a capacitor C2, as shown in FIG. Figure 2 As shown, where: The two ends of capacitor C1 and capacitor C2 are connected to the 2nd pin and 3rd pin of the watchdog chip U1 respectively; the 2nd pin of the three-pin diode D1 is connected to the 2nd pin of the watchdog chip U1 and the digital power supply of the watchdog chip U1 respectively, the 1st pin of the three-pin diode D1 is connected to the 1st pin of the connecting pin J1, and the 3rd pin of the three-pin diode D1 is connected to the analog power supply of the watchdog chip U1.

[0025] Specifically, the principle of the reset controllable circuit is shown in Figure 2 , Figure 2 SWD3.3V is the 3.3V of the emulator J-LINK, and is connected to the digital power supply VDD3.3V and analog power supply VDDA3.3V of the microcontroller respectively using BAT54C. Since the voltage drop of the two diodes of BAT54C is about 0.2V-0.3V, the voltage of VDDA and VDD is 3.0V-3.1V when power is off, which meets the power supply requirements of the microcontroller.

[0026] further, Figure 2NJRST in the figure is connected to the reset pin of the J-LINK emulator. It is normally high to disable the watchdog chip. You can also directly control the reset of the microcontroller by sending a low-level pulse signal to pin 1 of the watchdog chip.

[0027] In summary, the connection diagram of the above reset controllable circuit in actual use can be found in Figure 3 ,like Figure 3 As shown in the figure, after connecting to the emulator, the watchdog chip becomes invalid, and the program can be burned without powering on the product. During software debugging, the reset of the microcontroller can be controlled at any time by sending a low-level pulse signal to pin 1 of the watchdog chip.

[0028] Optionally, the reset controllable circuit further includes a resistor R3 , one end of the resistor R3 is connected to the 6th pin of the watchdog chip U1 , and the other end of the resistor R3 is connected to the digital power supply of the watchdog chip U1 .

[0029] Optionally, the reset controllable circuit further includes a resistor R4, one end of the resistor R4 is connected to the 7th pin of the watchdog chip U1, and the other end of the resistor R4 is grounded.

[0030] Specifically, if Figure 2 As shown, the model of the three-pin diode D1 is BAT54C; the model of the capacitor C1 is C0603-X7R-25-μ10-K; the model of the capacitor C2 is C0603-COG-25-1000-J; the model of the resistor R1 and the resistor R2 is R0603-620R-F; the model of the resistor R1 and the resistor R2 is R0603-620R-F.

[0031] Example 2: This example provides a method for using a reset controllable circuit that is independent of power supply. The reset controllable circuit includes a watchdog chip U1 and a connection pin J1, wherein: The 1st and 8th pins of the watchdog chip U1 are connected to one end of the resistor R1 and one end of the resistor R2 respectively. The other end of the resistor R1 and the other end of the resistor R2 are connected to the 5th pin of the connector J1. The reset control circuit also includes a three-pin diode D1, a capacitor C1 and a capacitor C2. Figure 2 As shown, where: The two ends of capacitor C1 and capacitor C2 are connected to the second and third pins of the watchdog chip U1 respectively; the second pin of the three-pin diode D1 is connected to the second pin of the watchdog chip U1 and the digital power supply of the watchdog chip U1 respectively, the first pin of the three-pin diode D1 is connected to the first pin of the connector J1, and the third pin of the three-pin diode D1 is connected to the analog power supply of the watchdog chip U1; the method of using the reset controllable circuit includes the following specific steps: S1, before debugging the software or burning the program on the watchdog chip U1, connect the emulator through the connecting pin J1.

[0032] Among them, the SWD3.3V of the emulator is connected to the VDD3.3V and VDDA3.3V of the microcontroller through BAT54C. Since the two diodes of BAT54C are germanium diodes, the voltage drop is low, which meets the power supply requirements of the microcontroller. In addition, since the 1st pin of the watchdog chip (watchdog chip U1) is connected to the NJRST pin of the emulator, the normal state is high, and the watchdog chip is in an invalid state, it can be achieved without powering on and burning the program and there is no longer the previous short-circuit operation.

[0033] S2, when the watchdog chip U1 needs to be reset during software debugging or program burning, a low-level pulse signal is sent to the 1st pin of the watchdog chip U1 through the 5th pin of the connecting pin J1.

[0034] Specifically, when debugging the program, the microcontroller can be reset at any time by sending a low-level pulse signal to pin 1 of the watchdog chip.

[0035] In this embodiment, the reset controllable circuit may further include a resistor R3, one end of the resistor R3 is connected to the 6th pin of the watchdog chip U1, and the other end of the resistor R3 is connected to the digital power supply of the watchdog chip U1; the reset controllable circuit also includes a resistor R4, one end of the resistor R4 is connected to the 7th pin of the watchdog chip U1, and the other end of the resistor R4 is grounded.

[0036] Among them, in the above-mentioned reset controllable circuit, the model of the three-pin diode D1 is BAT54C; the model of the capacitor C1 is C0603-X7R-25-μ10-K; the model of the capacitor C2 is C0603-COG-25-1000-J; the model of the above-mentioned resistor R1 and resistor R2 is R0603-620R-F; the model of the above-mentioned resistor R1 and resistor R2 is R0603-620R-F.

[0037] In actual use, the connection diagram of the reset controllable circuit is shown in Figure 3 During the program burning process, the emulator is connected to the computer, and the first pin of the watchdog chip U1 is in the normal high level, the watchdog chip is invalid, and the program is burned without power and there is no short circuit operation before; and during the program burning, due to Figure 2SWD3.3V is the 3.3V of the emulator J-LINK, and is connected to the digital power supply VDD3.3V and analog power supply VDDA3.3V of the microcontroller using BAT54C. Since the voltage drop of the two diodes of BAT54C is about 0.2V-0.3V, the voltage of VDDA and VDD is 3.0V-3.1V when not powered on, which meets the power supply requirements of the microcontroller and achieves the purpose of the product being completed without powering on. Figure 2 NJRST in the figure is connected to the reset pin of the J-LINK emulator. It is normally high to disable the watchdog chip. You can also directly control the reset of the microcontroller by sending a low-level pulse signal to pin 1 of the watchdog chip.

[0038] Example 3: An embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method of Example 2 is implemented.

[0039] Working principle: Connect the SWD3.3V of the emulator to the VDD3.3V and VDDA3.3V of the microcontroller through BAT54C. Since the two diodes of BAT54C are germanium diodes, the voltage drop is low to meet the power supply requirements of the microcontroller. And since the 1 pin of the watchdog chip is connected to the NJRST pin of the emulator, it is normally high, making the watchdog chip in an invalid state, so that the program can be burned without power and the previous short-circuit operation is no longer required. When debugging the program, the microcontroller can be reset at any time by sending a low-level pulse signal to the 1 pin of the watchdog chip.

[0040] Example 4: The embodiment of the present application provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions enable the computer to execute the method of Example 2.

[0041] Working principle: Connect the SWD3.3V of the emulator to the VDD3.3V and VDDA3.3V of the microcontroller through BAT54C. Since the two diodes of BAT54C are germanium diodes, the voltage drop is low to meet the power supply requirements of the microcontroller. And since the 1 pin of the watchdog chip is connected to the NJRST pin of the emulator, it is normally high, making the watchdog chip in an invalid state, so that the program can be burned without power and the previous short-circuit operation is no longer required. When debugging the program, the microcontroller can be reset at any time by sending a low-level pulse signal to the 1 pin of the watchdog chip.

[0042] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0043] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0044] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0045] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0046] Those skilled in the art will understand that all or part of the steps in implementing the above facts and methods can be completed by instructing relevant hardware through a program, and the program involved or the program can be stored in a computer-readable storage medium. When the program is executed, it includes the following steps: the corresponding method steps are then brought out, and the storage medium can be ROM / RAM, a disk, an optical disk, etc.

[0047] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A reset controllable circuit without power dependence, characterized in that: Includes watchdog chip U1 and connection pin J1, where: Pin 1 and pin 8 of the watchdog chip U1 are connected to one end of the resistor R1 and one end of the resistor R2, respectively. The other end of the resistor R1 and the other end of the resistor R2 are connected and connected to pin 5 of the connecting pin J1. It also includes a three-pin diode D1, a capacitor C1 and a capacitor C2, where: The two ends of the capacitor C1 and the capacitor C2 are respectively connected to the 2nd pin and the 3rd pin of the watchdog chip U1; the 2nd pin of the three-pin diode D1 is respectively connected to the 2nd pin of the watchdog chip U1 and the digital power supply of the watchdog chip U1, the 1st pin of the three-pin diode D1 is connected to the 1st pin of the connecting pin J1, and the 3rd pin of the three-pin diode D1 is connected to the analog power supply of the watchdog chip U1.

2. The reset controllable circuit without power dependence according to claim 1, characterized in that: The reset controllable circuit further includes a resistor R3 , one end of the resistor R3 is connected to the sixth pin of the watchdog chip U1 , and the other end of the resistor R3 is connected to the digital power supply of the watchdog chip U1 .

3. The reset controllable circuit without power dependence according to claim 1, characterized in that: The reset controllable circuit further includes a resistor R4 , one end of the resistor R4 is connected to the seventh pin of the watchdog chip U1 , and the other end of the resistor R4 is grounded.

4. A reset controllable circuit without power dependence according to any one of claims 1 to 3, characterized in that: The model of the three-pin diode D1 is BAT54C.

5. The reset controllable circuit without power dependence and the method of using the same according to claim 1, characterized in that: The model of the capacitor C1 is C0603-X7R-25-μ10-K; the model of the capacitor C2 is C0603-COG-25-1000-J.

6. The reset controllable circuit without power dependence according to claim 1, characterized in that: The resistor R1 and the resistor R2 have models R0603-620R-F.

7. The reset controllable circuit without power dependence according to claim 1, characterized in that: The model of the resistor R3 is R0603-10K-F; the model of the resistor R4 is R0603-100K-F.

8. A method for using a reset controllable circuit without power dependence, applied to a reset controllable circuit without power dependence according to any one of claims 1 to 7, characterized in that: The specific steps include: Before debugging the software or burning the program on the watchdog chip U1, connect the emulator through the connector pin J1; When the watchdog chip U1 needs to be reset during software debugging or program burning, a low-level pulse signal is sent to the 1st pin of the watchdog chip U1 through the 5th pin of the connecting pin J1.

9. An electronic device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method of claim 8 is implemented.

10. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer instructions that cause a computer to execute the method of claim 8 .

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