Static random access memory using micro-electro-mechanical systems

Abstract

The invention relates to a static random access memory using micro-electro-mechanical systems. An SRAM cell includes electromechanical transistors each having a source terminal, a gate terminal, a drain terminal, and a cantilever beam connected to the source terminal, the cantilever beam deflecting in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal. The SRAM cell also includes a bistable latch having a first storage node and a second storage node complementary to the first storage node. The first electromechanical transistor and the second electromechanical transistor are connected to the bistable latch. A word line is connected to gate terminals of the first and second electromechanical transistors. The first and second electromechanical transistors are operable to enable read from and write to the first and second storage nodes via the bit line and complementary bit line in response to the word line being asserted.

Description

[0001] This application claims the benefit of Indian Provisional Patent Application No. 202411022045, filed on March 22, 2024, titled “STATIC RANDOM ACCESS MEMORY USING MICRO-ELECTROMECHANICAL SYSTEMS,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to static random access memory. Background Art

[0003] Static random access memory (SRAM) is a type of semiconductor memory widely used in portable devices, system-on-chip (SOC) circuits, and high-performance very large-scale integration (VLSI) circuits. SRAM is considered non-volatile memory because, unlike some other types of memory, such as dynamic RAM (DRAM), SRAM does not require periodic refreshing. Instead, SRAM retains data as long as power is supplied. Summary of the Invention

[0004] In general, this disclosure describes SRAM cells that use microelectromechanical systems (MEMS) structures instead of semiconductor transistors, such as complementary metal oxide semiconductor (CMOS) transistors. In the example of a 6T SRAM cell, each of the six transistors of the SRAM cell can be replaced with a MEMS structure.

[0005] The MEMS structure can be an electromechanical transistor comprising a source terminal, a gate terminal, and a drain terminal, and a cantilever beam connected to the source terminal, the cantilever beam being suspended above the gate terminal and the drain terminal. When a potential difference exists between the source terminal and the drain terminal, the potential difference generates an electrostatic force that pulls the cantilever beam downward to contact the drain terminal. By contacting both the source terminal and the drain terminal, the cantilever beam forms an electrical short circuit between the source terminal and the drain terminal, thereby allowing current to flow between the source terminal and the drain terminal.

[0006] In some aspects, the technology described herein relates to a static random access memory (SRAM) cell comprising: a set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: a source terminal; a gate terminal; a drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node, the second storage node being complementary to the first storage node. , wherein the drain terminal of a first electromechanical transistor in the group of electromechanical transistors is connected to a first storage node, and wherein the drain terminal of a second electromechanical transistor in the group of electromechanical transistors is connected to a second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line; wherein the source terminal of the first electromechanical transistor is connected to a bit line; wherein the source terminal of the second electromechanical transistor is connected to a complementary bit line; and wherein the first electromechanical transistor and the second electromechanical transistor are operable to enable reading from and writing to the first storage node and the second storage node via the bit line and the complementary bit line in response to the word line being asserted.

[0007] In some aspects, the technology described herein relates to a static random access memory (SRAM) device comprising: a plurality of word lines; a plurality of bit lines; a plurality of complementary bit lines; a plurality of drive circuits operable to drive the plurality of word lines; a plurality of SRAM cells, wherein each of the plurality of SRAM cells comprises: a set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: a source terminal; a gate terminal; a drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node. point, the second storage node is complementary to the first storage node, wherein the drain terminal of the first electromechanical transistor in the group of electromechanical transistors is connected to the first storage node, and wherein the drain terminal of the second electromechanical transistor in the group of electromechanical transistors is connected to the second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line among a plurality of word lines; wherein the source terminal of the first electromechanical transistor is connected to a bit line among a plurality of bit lines; wherein the source terminal of the second electromechanical transistor is connected to a complementary bit line among a plurality of complementary bit lines; and wherein the first electromechanical transistor and the second electromechanical transistor are capable of operating to enable reading from and writing to the first storage node and the second storage node via the bit line and the complementary bit line in response to the word line being asserted by a corresponding drive circuit among a plurality of drive circuits.

[0008] In some aspects, the technology described herein relates to a method of operating a memory device, the method comprising: driving, by a driver circuit of the memory device, a word line of an SRAM cell connected to a plurality of SRAM cells of the memory device to a supply voltage; driving, by a write driver circuit of the memory device, a bit line of an SRAM cell connected to a ground voltage to write a bit value of 0 to the SRAM cell; and in response to the word line being driven to the supply voltage, generating, by an electromechanical transistor of the SRAM cell, an electrostatic force between a source terminal connected to the bit line and a gate terminal connected to the word line, the electromechanical transistor having a source terminal, a gate terminal, and a drain terminal connected to a storage node of the SRAM cell, the electrostatic force pulling downwardly a cantilever beam connected to the source terminal to connect the drain terminal to the source terminal, thereby writing the bit value of 0 to the storage node.

[0009] The details of one or more examples of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A An example electromechanical transistor used as a mechanical relay switch is illustrated.

[0011] Figure 1B Example Figure 1A The unit symbol for an electromechanical transistor.

[0012] Figure 1C is used Figure 1A Schematic diagram of an inverter built with electromechanical transistors.

[0013] Figure 2 is a schematic diagram illustrating an example SRAM cell using electromechanical transistors according to aspects of the present disclosure.

[0014] Figure 3 is a schematic diagram illustrating an example SRAM device having an SRAM cell using electromechanical transistors according to aspects of the present disclosure.

[0015] Figure 4 is a flowchart illustrating example operation of a memory device according to aspects of the present disclosure.

[0016] Figure 5 is a flowchart illustrating example operation of a memory device according to aspects of the present disclosure. DETAILED DESCRIPTION

[0017] The present disclosure describes a static random access memory (SRAM) cell that uses microelectromechanical systems (MEMS) structures as transistors. Using MEMS structures instead of semiconductor transistors (such as complementary metal oxide semiconductor (CMOS) transistors) can improve the performance and reliability of SRAM.

[0018] MEMS structures are micromechanical and electromechanical components that combine silicon-based microelectronics with mechanical systems and are typically manufactured using microfabrication processes. MEMS structures can be used for microscale sensing, control, actuation, and other applications.

[0019] Memory is used in many different types of electronic designs. One type of memory is SRAM. SRAM is non-volatile because, unlike some other types of memory, it doesn't need to be periodically refreshed. Instead, it retains its data as long as power is supplied.

[0020] SRAM cells typically use CMOS transistors to store bit values ​​and enable read and write operations. However, there are potential technical disadvantages to using CMOS transistors in SRAM cells. CMOS transistors can have relatively large sizes, relatively large power requirements, and relatively high switching times. Furthermore, CMOS transistors can be susceptible to single-event upsets, which can make them unsuitable for space or high-altitude applications.

[0021] According to aspects of the present disclosure, a cell of an SRAM may use a MEMS structure as a transistor, such as in place of a CMOS transistor. The MEMS structure may be in the form of an electromechanical transistor comprising a source terminal, a gate terminal, a drain terminal, and a cantilever beam connected to the source terminal, the cantilever beam being suspended above the gate terminal and the drain terminal. When there is a potential difference between the source terminal and the gate terminal, the potential difference generates an electrostatic force that pulls the cantilever beam downward to contact the drain terminal. By contacting both the source terminal and the drain terminal, the cantilever beam forms an electrical short circuit between the source terminal and the drain terminal, thereby allowing current to flow between the source terminal and the drain terminal.

[0022] Using MEMS structures to replace CMOS transistors in SRAM cells offers certain technical advantages. MEMS transistors can be smaller than CMOS transistors, which can reduce the size of SRAM cells using MEMS transistors. MEMS transistors can also have faster switching times and lower power consumption than CMOS transistors. Furthermore, due to their low ionizing radiation resistance, MEMS transistors can be less susceptible to single-event upsets than CMOS transistors, which can make MEMS transistors more suitable for use in flight systems in space or high-altitude applications.

[0023] Figure 1A An example electromechanical transistor is shown used as a mechanical relay switch. Such an electromechanical transistor can be used to replace semiconductor transistors, such as complementary metal oxide semiconductor (CMOS) transistors in static random access memory (SRAM).

[0024] like Figure 1A As shown, electromechanical transistor 104 is a MEMS or nanoelectromechanical system (NEMS) transistor that includes a source terminal 108, a gate terminal 110, and a drain terminal 112 electrically isolated by an isolation layer 114 atop a substrate 116. In some examples, source terminal 108, gate terminal 110, and drain terminal 112 are made of silicon. In some examples, substrate 116 can be a silicon substrate.

[0025] Electromechanical transistor 104 also includes a cantilever beam 106. Cantilever beam 106 is a structural element that extends horizontally and is supported at only one end by a support portion 102 of cantilever beam 106. Cantilever beam 106 can be a mechanical cantilever beam and can be made of silicon, polysilicon, silicon nitride, silicon dioxide, or any other suitable material. Cantilever beam 106 contacts source terminal 108 via support portion 102 of cantilever beam 106 and is suspended from source terminal 108 over and through gate terminal 110 and drain terminal 112.

[0026] The source terminal 108 and the gate terminal 110 are voltage controlled. When there is no potential difference between the source terminal 108 and the gate terminal 110, there is no mechanical action in the electromechanical transistor 104.

[0027] When a potential difference exists between the source terminal 108 and the gate terminal 110, the potential difference causes an electrostatic force to be generated between the source terminal 108 and the gate terminal 110. The generated electrostatic force may deflect the cantilever beam 106, such as pulling the cantilever beam 106 downward toward the drain terminal 112, and thus may cause the cantilever beam 106 to contact the drain terminal 112. That is, the cantilever beam 106 may deflect (e.g., bend) downward toward the drain terminal 112 in response to the electrostatic force to contact the drain terminal 112, thereby connecting the source terminal 108 to the drain terminal 112.

[0028] Because the cantilever beam 106 has contacted the source terminal 108, the cantilever beam 106 may form an electrical short between the source terminal 108 and the drain terminal 112 by contacting the drain terminal 112. The electrical short may enable current to flow between the source terminal 108 and the drain terminal 112. When the potential difference between the source terminal 108 and the gate terminal 110 disappears, the electrostatic force between the source terminal 108 and the gate terminal 110 may also disappear, which may cause the cantilever beam 106 to deflect away and no longer contact the drain terminal 112.

[0029] In some examples, because cantilever beam 106 is suspended by gate terminal 110 and drain terminal 112, when a potential difference exists between gate terminal 110 and drain terminal 112, the potential difference causes an electrostatic force to be generated between gate terminal 110 and drain terminal 112. The generated electrostatic force can cause cantilever beam 106 to deflect, such as pulling cantilever beam 106 downward toward drain terminal 112, and thus can cause cantilever beam 106 to contact drain terminal 112. When the potential difference between gate terminal 110 and drain terminal 112 disappears, the electrostatic force between gate terminal 110 and drain terminal 112 can also disappear, which can cause cantilever beam 106 to deflect away and no longer contact drain terminal 112.

[0030] Figure 1B Example Figure 1ATABLE 1 shows the unit symbol of the electromechanical transistor 104. Operational outputs of the electromechanical transistor 104 depending on the potential difference applied between the source terminal 108 and the gate terminal 110 are shown in Table 1.

[0031] Table 1

[0032] Source gate drain 0 0 Z 0 1 0 1 0 1 1 1 Z

[0033] As can be seen, when source terminal 108 is in a high voltage state and gate terminal 110 is in a low voltage state (denoted as 1 for source terminal 108 and 0 for gate terminal 110), or when source terminal 108 is in a low voltage state and gate terminal 110 is in a high voltage state (denoted as 0 for source terminal 108 and 1 for gate terminal 110), there is a potential difference between source terminal 108 and gate terminal 110. When there is a potential difference between source terminal 108 and gate terminal 110, the electrostatic force generated by the potential difference deflects cantilever beam 106 and pulls cantilever beam 106 downward to contact drain terminal 112, thereby electrically shorting source terminal 108 and drain terminal 112. The electrical short between source terminal 108 and drain terminal 112 causes drain terminal 112 to assume the voltage state of source terminal 108.

[0034] Figure 1C is used Figure 1A Schematic diagram of an inverter constructed with an electromechanical transistor 104. Figure 1C As shown in FIG, the inverter 130 may be formed by an electromechanical transistor 104A and an electromechanical transistor 104B, each of which is Figure 1A 1. Electromechanical transistors 104A and 104B may replace an N-type metal oxide semiconductor (NMOS) transistor and a P-type metal oxide semiconductor (PMOS) transistor that together form a CMOS inverter.

[0035] The electromechanical transistor includes a source terminal 108A, a gate terminal 110A, and a drain terminal 112A. The electromechanical transistor 104B includes a source terminal 108B, a gate terminal 110B, and a drain terminal 112B. The drain terminal 112A of the electromechanical transistor 104A is connected to the drain terminal 112B of the electromechanical transistor 104B in the inverter 130, and both the drain terminal 112A and the drain terminal 112B are connected to the output terminal 120. The source terminal 108A of the electromechanical transistor 104A is connected to a high voltage source (Vhi) 122, and the source terminal 108B of the electromechanical transistor 104B is connected to a low voltage source (Vlow) 124. The gate terminal 110A of the electromechanical transistor 104A and the gate terminal 110B of the electromechanical transistor 104B are each connected to the input terminal 118.

[0036] When an input 0 is applied to inverter 130 via input 118, there is no potential difference between source terminal 108B and gate terminal 110B of electromechanical transistor 104B. However, there is a potential difference between source terminal 108A and gate terminal 110A of electromechanical transistor 104A, which pulls the cantilever beam of electromechanical transistor 104A downward, electrically shorting source terminal 108A and drain terminal 112A. The short circuit between source terminal 108A of electromechanical transistor 104A, which is connected to high voltage 122, and drain terminal 112A of the electromechanical transistor causes drain terminal 112A to output a 1 at output 120.

[0037] When an input of 1 is applied to inverter 130 via input 118, there is no potential difference between source terminal 108A and gate terminal 110A of electromechanical transistor 104A. However, there is a potential difference between source terminal 108B and gate terminal 110B of electromechanical transistor 104B, which pulls the cantilever beam of electromechanical transistor 104B downward, electrically shorting source terminal 108B to drain terminal 112B. The short circuit between source terminal 108B of electromechanical transistor 104B, which is connected to low voltage 124, and drain terminal 112B of the electromechanical transistor causes drain terminal 112B to output a 0 at output 120.

[0038] According to aspects of the present invention, a static random access memory (SRAM) cell may include an electromechanical transistor (such as a Figure 1A and Figure 1B ) and an inverter constructed from electromechanical transistors (such as, Figure 1C 104 to replace the CMOS structure and inverter in the SRAM. The SRAM cell can use the electromechanical transistor 104 to store bit values ​​and enable read and write operations of the SRAM cell in a manner that improves the performance and reliability of the SRAM cell.

[0039] Figure 2 is a schematic diagram illustrating an example SRAM cell using electromechanical transistors according to aspects of the present disclosure. Figure 2 A 6T SRAM cell is illustrated, but the techniques of the present disclosure are equally applicable to building any other type of SRAM cell.

[0040] like Figure 2 As shown in FIG, SRAM cell 200 includes a set of electromechanical transistors 204A to 204E (“electromechanical transistors 204”) (each of which is Figures 1A to 1CAn example of an electromechanical transistor 104 is shown in FIG. 2 ), which replaces a transistor in the SRAM cell 200, such as a complementary metal oxide semiconductor (CMOS) transistor. Such an electromechanical transistor may be a MEMS or NEMS transistor.

[0041] Electromechanical transistor 204A includes a source terminal 208A, a gate terminal 210A, and a drain terminal 212A. Source terminal 208A is connected to a bit line (BL) 244 for the SRAM cell 200, and gate terminal 210A is connected to a word line (WL) 250 for the SRAM cell 200. Electromechanical transistor 204B includes a source terminal 208B, a gate terminal 210B, and a drain terminal 212B. Source terminal 208B is connected to a complementary bit line (BL') 246 (also known as a bit inversion line) for the SRAM cell 200, and gate terminal 210B is connected to a word line 250 for the SRAM cell 200. As can be seen, SRAM cell 200 uses electromechanical transistors 204A and 204B instead of CMOS pass-gate transistors connected to bit line 244, complementary bit line 246, and word line 250.

[0042] The drain terminal 112A of the electromechanical transistor 204A and the drain terminal 112B of the electromechanical transistor 204B are connected to a bistable latch 232 that stores a single bit of information in the SRAM cell 200. The bistable latch 232 includes a pair of cross-coupled inverters 230A and 230B, each of which is a Figure 1C 1. In an example of inverters 130, they are cross-connected to each other so that the two inverters 230A and 230B are connected in a loop with the output of one inverter being fed to the other inverter, and vice versa.

[0043] Inverter 230A includes an electromechanical transistor 204C and an electromechanical transistor 204D. Electromechanical transistor 204C includes a source terminal 208C, a gate terminal 210C, and a drain terminal 212C. Electromechanical transistor 204D includes a source terminal 208D, a gate terminal 210D, and a drain terminal 212D. In inverter 230A, gate terminal 210C of electromechanical transistor 204C is connected to gate terminal 210D of electromechanical transistor 204D, and drain terminal 212C of electromechanical transistor 204C is connected to drain terminal 212D of electromechanical transistor 204D. Source terminal 208D of electromechanical transistor 204D is connected to supply voltage (VDD) 234. Source terminal 208C of electromechanical transistor 204C is connected to ground potential (GND) 236.

[0044] Inverter 230B includes an electromechanical transistor 204E and an electromechanical transistor 204F. Electromechanical transistor 204E includes a source terminal 208E, a gate terminal 210E, and a drain terminal 212E. Electromechanical transistor 204F includes a source terminal 208F, a gate terminal 210F, and a drain terminal 212F. In inverter 230B, gate terminal 210E of electromechanical transistor 204E is connected to gate terminal 210F of electromechanical transistor 204F, and drain terminal 212E of electromechanical transistor 204E is connected to drain terminal 212F of electromechanical transistor 204F. Source terminal 208F of electromechanical transistor 204F is connected to VDD 234. Source terminal 208E of electromechanical transistor 204E is connected to GND 236.

[0045] As described above, inverters 230A and 230B are cross-connected to each other in bistable latch 232. To cross-connect inverters 230A and 230B, gate terminals 210C and 210D in inverter 230A are connected to drain terminals 212E and 212F in inverter 230B, and gate terminals 210E and 210F in inverter 230B are connected to drain terminals 212C and 212D in inverter 230A.

[0046] The bistable latch 232 includes a storage node (Q) 240 and a complementary storage node (Q') 242, each of which is operable to store a bit value. The storage node 240 and the complementary storage node 242 are complementary because when the storage node 240 stores a bit value of 0, the complementary storage node 242 stores a bit value of 1, and when the storage node 240 stores a bit value of 1, the complementary storage node 242 stores a bit value of 0.

[0047] To control reading and writing of bistable latch 232, drain terminal 212A of electromechanical transistor 204A is connected to drain terminals 212C and 212D in inverter 130A. Similarly, drain terminal 212B of electromechanical transistor 204B is connected to drain terminals 212E and 212F in inverter 230B.

[0048] When the voltage of word line 250 is asserted (i.e., switched to a system high voltage such as a supply voltage), electromechanical transistors 204A and 204B are turned on, thereby enabling SRAM cell 200 to perform a read operation from and a write operation to bi-stable latch 232. That is, electromechanical transistors 204A and 204B are operable to enable reading from and writing to storage node 240 and complementary storage node 242 via bit line 244 and complementary bit line 246 in response to word line 250 being asserted.

[0049] Because word line 250 is connected to gate terminals 210A and 210B, a high voltage on word line 250 can cause gate terminals 210A and 210B to each emit a high voltage level. To read the values ​​stored in storage node 240 and complementary storage node 242 from bi-stable latch 232, word line 250 is asserted, and gate terminals 210A and 210B correspondingly have a high voltage. Because storage node 240 and complementary storage node 242 are connected to drain terminal 212A of electromechanical transistor 204A and drain terminal 212B of electromechanical transistor 204B, respectively, the values ​​stored in storage node 240 and complementary storage node 242 can result in a potential difference between drain terminal 212A and gate terminal 210A of electromechanical transistor 204A or between drain terminal 212B and gate terminal 210B of electromechanical transistor 204B.

[0050] In an example where the bi-stable latch 232 stores a bit value of 1 (i.e., the bit value stored in the storage node 240 is 1 and the bit value stored in the complementary storage node 242 is 0), the complementary storage node 242 storing the bit value of 0 may cause a potential difference between the drain terminal 212B and the gate terminal 210B of the electromechanical transistor 204B because the bit value of 0 stored in the complementary storage node 242 causes the drain terminal 212B connected to the complementary storage node 242 to be in a low voltage state. The potential difference may cause a cantilever beam (not shown) in the electromechanical transistor 204B to pull downward, resulting in an electrical short between the drain terminal 212B and the source terminal 208B, which allows the complementary storage node 242 to be accessed by the complementary bit line 246.

[0051] In an example where the bi-stable latch 232 stores a bit value of 0 (i.e., the bit value stored in the storage node 240 is 0 and the bit value stored in the complementary storage node 242 is 1), the storage node 240 storing the bit value of 0 may cause a potential difference between the drain terminal 212A and the gate terminal 210A of the electromechanical transistor 204A because the bit value of 0 stored in the storage node 240 causes the drain terminal 212A connected to the storage node 240 to be in a low voltage state. The potential difference may cause a cantilever beam (not shown) in the electromechanical transistor 204A to pull downward, resulting in an electrical short between the drain terminal 212A and the source terminal 208A, which allows the storage node 240 to be accessed by the bit line 244.

[0052] When the voltage of word line 250 is asserted (i.e., switched to a system high voltage), electromechanical transistors 204A and 204B are turned on, and SRAM cell 200 may also perform a write operation to bi-stable latch 232. To write a value of 1 to bi-stable latch 232 (i.e., write a 1 to storage node 240 and a 0 to Q' 242), assuming that storage node 240 is initialized to 0 and complementary storage node 242 is initialized to 1, bit line 244 is asserted to 1 (e.g., driven to a high voltage, such as a supply voltage) and complementary bit line 246 is de-asserted to 0 (e.g., driven to a low voltage, such as ground potential). Since there is no potential difference between source terminal 208A and gate terminal 210A, both bit line 244 and word line 250 being asserted to 1 turns off electromechanical transistor 204A.

[0053] Due to the potential difference between source terminal 208B and gate terminal 210B, complementary bit line 246 is deasserted to 0 and word line 250 is asserted to 1, turning on electromechanical transistor 204B. The potential difference causes a cantilever beam (not shown) in electromechanical transistor 204B to pull downward, creating an electrical short between drain terminal 212B and source terminal 208B, which causes complementary storage node 242 to be set to store a bit value of 0. Drain terminals 212E and 212F of inverter 230B are cross-connected to gate terminals 210C and 210D of inverter 230A. The value of 0 at gate terminal 210D causes a potential difference between source terminal 208D and gate terminal 210D in electromechanical transistor 204D. The potential difference causes a cantilever beam (not shown) in electromechanical transistor 204D to pull downward, creating an electrical short between drain terminal 212D and source terminal 208D. Because source terminal 208D is connected to VDD 234, drain terminal 212D assumes a high voltage. Thus, storage node 240 is set to store a bit value of one.

[0054] To write a value of 0 into the bi-stable latch 232 (i.e., write a 0 to the storage node 240 and a 1 to the complementary storage node 242), assuming that the storage node 240 is initialized to 1 and the complementary storage node 242 is initialized to 0, the bit line 244 is de-asserted to 0 (e.g., driven to a low voltage, such as ground potential) and the complementary bit line 246 is asserted to 1 (e.g., driven to a high voltage, such as a supply voltage). Since there is no potential difference between the source terminal 208B and the gate terminal 210B, both the complementary bit line 246 and the word line 250 being asserted to 1 turns off the electromechanical transistor 204B.

[0055] Due to the potential difference between source terminal 208A and gate terminal 210A, bit line 244 is deasserted to 0 and word line 250 is asserted to 1, turning on electromechanical transistor 204A. The potential difference causes a cantilever beam (not shown) in electromechanical transistor 204A to pull downward, creating an electrical short between drain terminal 212A and source terminal 208A, which causes storage node 240 to be set to store a bit value of 0. Drain terminals 212C and 212D of inverter 230A are cross-connected to gate terminals 210E and 210F of inverter 230B. The value of 0 at gate terminal 210F causes a potential difference between source terminal 208F and gate terminal 210F in electromechanical transistor 204F. The potential difference causes a cantilever beam (not shown) in electromechanical transistor 204F to pull downward, creating an electrical short between drain terminal 212F and source terminal 208F. Since source terminal 208F is connected to VDD 234, drain terminal 212F assumes a high voltage. Thus, complementary storage node 242 is set to store a bit value of one.

[0056] Figure 3 is a schematic diagram illustrating an example SRAM device having an SRAM cell using electromechanical transistors according to aspects of the present disclosure. The SRAM device 360 ​​may be a memory device used as a data storage device in an integrated circuit. Figure 3 As shown in FIG, the SRAM device 360 ​​includes SRAM cells 300A to 300P (“SRAM cells 300”), each of which is a SRAM cell including an electromechanical transistor. Figure 2 The SRAM device 360 ​​further includes a row decoder 362, a column decoder 364, driver circuits 370A-370D ("driver circuits 370"), sense amplifiers 372A-372D ("sense amplifiers 372"), and write driver circuits 374A-374D ("write driver circuits 374"). The SRAM device 360 ​​may also include Figure 3 Additional components and circuits not shown. Figure 3 A 4×4 array of SRAM cells 300 is illustrated, but the techniques of this disclosure are equally applicable to any other number and / or configuration of SRAM cells in the SRAM device 360 ​​.

[0057] Row decoder 362 is implemented via circuitry and is connected to driver circuits 370. Each of driver circuits 370 is connected to a corresponding one of word lines 350A to 350H ("word lines 350"), each of which is Figure 22, and each driver circuit is operable to drive a voltage to the corresponding word line. Row decoder 362 may receive an address signal 366 indicating a memory address (e.g., a physical memory address), such as from a processing circuit of a computing device. Row decoder 362 may determine which word line to activate from word lines 350 based on the physical memory address using any suitable technique. Thus, row decoder 362 may use a driver circuit in driver circuit 370 connected to the selected word line to drive the selected word line to a system high voltage (e.g., a supply voltage) to assert the selected word line.

[0058] Column decoder 364 is implemented via circuitry and is implemented via bit lines 344A-344H ("bit lines 344") (each of these bit lines is Figure 2 244) and via complementary bit lines 346A through 346H ("complementary bit lines 346") (each of these complementary bit lines is Figure 2 Column decoder 364 may also receive an address signal 366 indicating a memory address and may select one of bit lines 344 and one of complementary bit lines 346 to read from and write to the SRAM cell based on the memory address.

[0059] To select an SRAM cell for writing a bit value to the SRAM cell, the column decoder 364 may select a corresponding write driver circuit connected to the bit line and complementary bit line for the SRAM cell from the write driver circuit 374 to drive appropriate voltages to the bit line and complementary bit line for the SRAM cell to write the bit value to the SRAM cell. To select an SRAM cell for reading a bit value stored in the SRAM cell, the column decoder may connect a corresponding sense amplifier from the sense amplifier 372 to the bit line and complementary bit line for the SRAM cell to sense the bit value stored in the SRAM cell.

[0060] For example, if the memory address indicated by address signal 366 addresses an SRAM cell including SRAM cell 300C, row decoder 362 may determine to assert word line 350A based on the memory address, such as by driving word line 350A to a system high voltage using driver circuit 370A. Column decoder 364 may select bit line 344C and complementary bit line 346C to read from and write to SRAM cell 300C based on the memory address.

[0061] The SRAM device 360 ​​can use a write driver circuit 374 to write data to the SRAM cell 300. The write driver circuit 374 can receive an input data signal 368 indicating input data to be written to the SRAM cell 300, and can write the input data to the SRAM cell addressed by the memory address indicated by the address signal 366. Each write driver circuit is connected to a bit line and a complementary bit line. For example, write driver circuit 374A is connected to bit line 344A and complementary bit line 346A, write driver circuit 374B is connected to bit line 344B and complementary bit line 346B, write driver circuit 374C is connected to bit line 344C and complementary bit line 346C, and write driver circuit 374D is connected to bit line 344D and complementary bit line 346D.

[0062] In the example of writing a bit value of 1 to the SRAM cell 300L, the row decoder 362 may use the driver circuit 370C to assert the word line 350C connected to the SRAM cell 300L. The column decoder 364 may also select the bit line 344D and the complementary bit line 346D for writing to the SRAM cell 300L. The SRAM device 360 ​​may use the write driver circuit 374D to write the bit value of 1 to the storage node of the SRAM cell 300L and the bit value of 0 to the complementary storage node of the SRAM cell 300L. To write the bit value of 1 to the storage node of the SRAM cell 300L and the bit value of 0 to the complementary storage node of the SRAM cell 300L, the driver circuit 374D may drive the bit line 344D to a high voltage (e.g., a supply voltage) to assert the bit line 344D to 1 and may drive the complementary bit line 346D to a low voltage (e.g., a ground potential) to de-assert the complementary bit line 346D to 0.

[0063] In the example of writing a bit value of 0 to the SRAM cell 300L, the row decoder 362 may use the driver circuit 370C to assert the word line 350C connected to the SRAM cell 300L. The column decoder 364 may also select the bit line 344D and the complementary bit line 346D for writing to the SRAM cell 300L. The SRAM device 360 ​​may use the write driver circuit 374D to write the bit value of 0 to the storage node of the SRAM cell 300L and the bit value of 1 to the complementary storage node of the SRAM cell 300L. To write the bit value of 0 to the storage node of the SRAM cell 300L and the bit value of 1 to the complementary storage node of the SRAM cell 300L, the driver circuit 374D may drive the bit line 344D to a low voltage (e.g., ground potential) to de-assert the bit line 344D to 0 and may drive the complementary bit line 346D to a high voltage (e.g., a supply voltage) to assert the complementary bit line 346D to 1.

[0064] The SRAM device 360 ​​can read data from the SRAM cell 300 using sense amplifiers 372. Each of the sense amplifiers 372 is associated with a corresponding pair of bit lines and a complementary bit line, and each of the sense amplifiers 372 can be a differential amplifier that amplifies a voltage difference between the corresponding pair of bit lines and the complementary bit line. In the example of the SRAM device 360, sense amplifier 372A is associated with bit line 344A and complementary bit line 346A, sense amplifier 372B is associated with bit line 344B and complementary bit line 346B, sense amplifier 372C is associated with bit line 344C and complementary bit line 346C, and sense amplifier 372D is associated with bit line 344D and complementary bit line 346D.

[0065] To read the bit value stored in the SRAM cell, the SRAM device 360 ​​may precharge the bit line 344 and the complementary bit line 346 to a high voltage level, such as a supply voltage. The row decoder 362 may then use appropriate driver circuits to assert the word line connected to the SRAM cell. The column decoder 364 may connect corresponding sense amplifiers to the bit line and complementary bit line for the SRAM cell. The sense amplifier may detect the voltage differential between the connected bit line and the complementary bit line and amplify the voltage differential to a logical high (e.g., a supply voltage) or a logical low (e.g., a ground potential), and the SRAM device 360 ​​may send an output data signal 376 indicating the output of the sense amplifier.

[0066] For example, to read the value stored in SRAM cell 300N, after SRAM device 360 ​​precharges bit line 344 and complementary bit line 346 to a high voltage level, row decoder 362 may use driver circuit 370D to assert word line 350D connected to SRAM cell 300N. Column decoder 364 may connect sense amplifier 372B to bit line 344B and complementary bit line 346B. Sense amplifier 372B may sense and amplify the voltage difference between bit line 344B and complementary bit line 346B connected to SRAM cell 300N. If sense amplifier 372B senses that the voltage of bit line 344B is greater than the voltage of bit line 346B, sense amplifier 372B may output a logic high (e.g., 1), and SRAM device 360 ​​may indicate in output data signal 376 that SRAM cell 300N is storing a 1. If sense amplifier 372B senses that the voltage of bit line 344B is less than the voltage of bit line 346B, sense amplifier 372B may output a logic low (e.g., 0), and SRAM device 360 ​​may indicate in output data signal 376 that SRAM cell 300N is storing a 0. Accordingly, SRAM device 360 ​​may send output data signal 376 to processing circuitry of, for example, a computing device.

[0067] Figure 4is a flow chart illustrating an example operation of a memory device. Figure 2 and Figure 3 right Figure 4 Provide a description.

[0068] like Figure 4 As shown in FIG, a driver circuit 370A in a driver circuit 370 of a memory device 360 ​​may drive a word line 350A in a word line 350 connected to an SRAM cell 300B in a plurality of static random access memory (SRAM) cells 300 of the memory device 360 ​​to a supply voltage (402). A write driver circuit in a write driver circuit 374 of the memory device 360 ​​may drive a bit line 344B connected to an SRAM cell 300B in the plurality of SRAM cells 300 to a ground voltage to write a bit value 0 to the SRAM cell 300B (404). The electromechanical transistor 204A of the SRAM cell 300B can generate an electrostatic force between the source terminal 208A connected to the bit line 344B and the gate terminal 210A connected to the word line 350A in response to the word line 350A being driven to the supply voltage. The electromechanical transistor 204A has a source terminal 208A, a gate terminal 210A, and a drain terminal 212A connected to the storage node 240 of the SRAM cell 300B. The electrostatic force pulls the cantilever beam connected to the source terminal 208A downward to connect the drain terminal 212A to the source terminal 208A, thereby writing a bit value of 0 to the storage node 240 (406).

[0069] Figure 5 is a flow chart illustrating an example operation of a memory device. Figure 2 and Figure 3 right Figure 4 Provide a description.

[0070] like Figure 5 As shown in FIG, a driver circuit 370A in a driver circuit 370 of a memory device 360 ​​may drive a word line 350A in a word line 350 connected to an SRAM cell 300B in a plurality of static random access memory (SRAM) cells 300 of the memory device 360 ​​to a supply voltage (502). The memory device 360 ​​may connect a sense amplifier 372B in a sense amplifier 372 to a bit line 344B and a complementary bit line 346B, wherein the bit line 344B and the complementary bit line 346B are connected to the SRAM cell 300B (504).

[0071] In response to word line 350A being driven to a supply voltage, electromechanical transistor 204A of SRAM cell 300B may generate an electrostatic force between drain terminal 212A of storage node 240 connected to storage bit value 0 of SRAM cell 300B and gate terminal 210A connected to word line 350A through the electromechanical transistor of the SRAM cell. Electromechanical transistor 204A has source terminal 208A connected to bit line 344B, gate terminal 210A, and drain terminal 212A. The electrostatic force pulls down the cantilever beam connected to source terminal 208A to connect drain terminal 212A to source terminal 208A, thereby lowering the voltage level of bit line 344B (506). Sense amplifier 372B may amplify the voltage difference between bit line 344B and complementary bit line 346B to determine the bit value stored in storage node 240 (508).

[0072] The technology of this disclosure may also be described in the following clauses.

[0073] Clause 1. A static random access memory (SRAM) cell, comprising: a set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: a source terminal; a gate terminal; a drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node, the second storage node being complementary to the first storage node, wherein the first electromechanical transistor in the set of electromechanical transistors is connected to the source terminal. The drain terminal of the body transistor is connected to the first storage node, and the drain terminal of the second electromechanical transistor in the set of electromechanical transistors is connected to the second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line; wherein the source terminal of the first electromechanical transistor is connected to a bit line; wherein the source terminal of the second electromechanical transistor is connected to a complementary bit line; and wherein the first electromechanical transistor and the second electromechanical transistor are capable of operating to enable reading from and writing to the first storage node and the second storage node via the bit line and the complementary bit line in response to the word line being asserted.

[0074] Clause 2. The SRAM cell of Clause 1, wherein the bi-stable latch comprises a pair of cross-coupled inverters, the pair of cross-coupled inverters comprising a plurality of electromechanical transistors in the set of electromechanical transistors.

[0075] Clause 3. An SRAM cell according to clause 2, wherein: a first inverter of the pair of cross-coupled inverters includes a third electromechanical transistor and a fourth electromechanical transistor of the set of electromechanical transistors; a second inverter of the pair of cross-coupled inverters includes a fifth electromechanical transistor and a sixth electromechanical transistor of the set of electromechanical transistors; the source terminal of the third electromechanical transistor and the source terminal of the fifth electromechanical transistor are connected to the ground potential; the source terminal of the fourth electromechanical transistor and the source terminal of the sixth electromechanical transistor are connected to the supply voltage; the gate terminal of the third electromechanical transistor is connected to the gate terminal of the fourth electromechanical transistor; the gate terminal of the fifth electromechanical transistor is connected to the gate terminal of the fourth electromechanical transistor connected to the gate terminal of the sixth electromechanical transistor; the drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor are connected to the first storage node; the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor are connected to the second storage node; the gate terminal of the third electromechanical transistor and the gate terminal of the fourth electromechanical transistor are cross-connected to the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor; and the gate terminal of the fifth electromechanical transistor and the gate terminal of the sixth electromechanical transistor are cross-connected to the drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor.

[0076] Item 4. The SRAM cell of any one of Items 1 to 3, wherein each electromechanical transistor in the set of electromechanical transistors is a microelectromechanical system (MEMS) transistor.

[0077] Item 5. An SRAM cell according to any one of items 1 to 4, wherein to write a bit value of 0 to the first storage node, the bit line being driven to a low voltage causes a potential difference between the source terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor and enable the drain terminal of the first electromechanical transistor to write the bit value of 0 to the first storage node.

[0078] Item 6. An SRAM cell according to any one of items 1 to 5, wherein to write a bit value of 0 to the second storage node, the complementary bit line being driven to a low voltage causes a potential difference between the source terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enable the drain terminal of the second electromechanical transistor to write the bit value of 0 to the second storage node.

[0079] Item 7. An SRAM cell according to any one of items 1 to 6, wherein in order to read the bit value 0 from the first storage node, the bit value 0 in the first storage node causes a potential difference between the drain terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor, and enabling the bit line to read the bit value 0 from the first storage node.

[0080] Clause 8. An SRAM cell according to any one of clauses 1 to 7, wherein in order to read a bit value of 0 from the second storage node, the bit value of 0 in the second storage node causes a potential difference between the drain terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enabling the complementary bit line to read the bit value of 0 from the second storage node.

[0081] Clause 9. The SRAM cell of any one of clauses 1 to 8, wherein the SRAM cell is a 6T SRAM cell.

[0082] Clause 10. The SRAM cell of any one of Clauses 1 to 9, wherein the SRAM cell is included in a plurality of SRAM cells of an SRAM device.

[0083] Item 11. A static random access memory (SRAM) device, the static random access memory (SRAM) device comprising: a plurality of word lines; a plurality of bit lines; a plurality of complementary bit lines; a plurality of drive circuits operable to drive the plurality of word lines; a plurality of SRAM cells, wherein each of the plurality of SRAM cells comprises: a set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: a source terminal; a gate terminal; a drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node, the second storage node being complementary to the first storage node, wherein The drain terminal of the first electromechanical transistor in the group of electromechanical transistors is connected to the first storage node, and the drain terminal of the second electromechanical transistor in the group of electromechanical transistors is connected to the second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line among the multiple word lines; wherein the source terminal of the first electromechanical transistor is connected to a bit line among the multiple bit lines; wherein the source terminal of the second electromechanical transistor is connected to a complementary bit line among the multiple complementary bit lines; and wherein the first electromechanical transistor and the second electromechanical transistor are capable of operating to enable reading from and writing to the first storage node and the second storage node via the bit line and the complementary bit line in response to the word line being asserted by a corresponding drive circuit among the multiple drive circuits.

[0084] Clause 12. The SRAM device of Clause 11, wherein the bi-stable latch comprises a pair of cross-coupled inverters, the pair of cross-coupled inverters comprising a plurality of electromechanical transistors in the set of electromechanical transistors.

[0085] Clause 13. The SRAM device of clause 12, wherein: a first inverter of the pair of cross-coupled inverters comprises a third electromechanical transistor and a fourth electromechanical transistor of the set of electromechanical transistors; a second inverter of the pair of cross-coupled inverters comprises a fifth electromechanical transistor and a sixth electromechanical transistor of the set of electromechanical transistors; the source terminal of the third electromechanical transistor and the source terminal of the fifth electromechanical transistor are connected to the ground potential; the source terminal of the fourth electromechanical transistor and the source terminal of the sixth electromechanical transistor are connected to the supply voltage; the gate terminal of the third electromechanical transistor is connected to the gate terminal of the fourth electromechanical transistor; the gate terminal of the fifth electromechanical transistor is connected to the gate terminal of the fourth electromechanical transistor The gate terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor are connected to the first storage node; the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor are connected to the second storage node; the gate terminal of the third electromechanical transistor and the gate terminal of the fourth electromechanical transistor are cross-connected to the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor; and the gate terminal of the fifth electromechanical transistor and the gate terminal of the sixth electromechanical transistor are cross-connected to the drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor.

[0086] Clause 14. The SRAM device of any one of Clauses 11 to 13, wherein each electromechanical transistor in the set of electromechanical transistors is a microelectromechanical system (MEMS) transistor.

[0087] Item 15. An SRAM device according to any one of items 11 to 14, wherein to write a bit value of 0 to the first storage node, the bit line being driven to a low voltage causes a potential difference between the source terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor and enable the drain terminal of the first electromechanical transistor to write the bit value of 0 to the first storage node.

[0088] Item 16. An SRAM device according to any one of items 11 to 15, wherein to write a bit value of 0 to the second storage node, the complementary bit line being driven to a low voltage causes a potential difference between the source terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enable the drain terminal of the second electromechanical transistor to write the bit value of 0 to the second storage node.

[0089] Clause 17. An SRAM device according to any one of clauses 11 to 16, wherein in order to read the bit value 0 from the first storage node, the bit value 0 in the first storage node causes a potential difference between the drain terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor and enable the bit line to read the bit value 0 from the first storage node.

[0090] Clause 18. An SRAM device according to any one of clauses 11 to 17, wherein in order to read the bit value 0 from the second storage node, the bit value 0 in the second storage node causes a potential difference between the drain terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force, the electrostatic force pulling the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enable the complementary bit line to read the bit value 0 from the second storage node.

[0091] Clause 19. The SRAM device of any one of Clauses 11 to 18, wherein each SRAM cell of the plurality of SRAM cells is a 6T SRAM cell.

[0092] Item 20. A method of operating a memory device, the method comprising: driving, by a drive circuit of the memory device, a word line of an SRAM cell connected to a plurality of SRAM cells of the memory device to a supply voltage; driving, by a write drive circuit of the memory device, a bit line of an SRAM cell connected to the plurality of SRAM cells to a ground voltage to write a bit value of 0 to the SRAM cell; and in response to the word line being driven to the supply voltage, generating, by an electromechanical transistor of the SRAM cell, an electrostatic force between a source terminal connected to the bit line and a gate terminal connected to the word line, the electromechanical transistor having the source terminal, the gate terminal, and a drain terminal connected to a storage node of the SRAM cell, the electrostatic force pulling downward a cantilever beam connected to the source terminal to connect the drain terminal to the source terminal, thereby writing the bit value of 0 to the storage node.

[0093] Various examples of the disclosure have been described. These and other examples are within the scope of the following claims.

Claims

1. A static random access memory (SRAM) cell, comprising: A set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: source terminal; gate terminal; drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node, the second storage node being complementary to the first storage node, wherein the drain terminal of a first electromechanical transistor in the set of electromechanical transistors is connected to the first storage node, and wherein the drain terminal of a second electromechanical transistor in the set of electromechanical transistors is connected to the second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line; wherein said source terminal of said first electromechanical transistor is connected to a bit line; wherein said source terminal of said second electromechanical transistor is connected to a complementary bit line; and Wherein the first and second electromechanical transistors are operable to enable reading from and writing to the first and second storage nodes via the bit line and the complementary bit line in response to the word line being asserted. 2 . The SRAM cell of claim 1 , wherein the bistable latch comprises a pair of cross-coupled inverters, the pair of cross-coupled inverters comprising a plurality of electromechanical transistors in the set of electromechanical transistors.

3. The SRAM cell according to claim 2, wherein: a first inverter of the pair of cross-coupled inverters comprising a third electromechanical transistor and a fourth electromechanical transistor of the set of electromechanical transistors; a second inverter of the pair of cross-coupled inverters comprising a fifth electromechanical transistor and a sixth electromechanical transistor of the set of electromechanical transistors; the source terminal of the third electromechanical transistor and the source terminal of the fifth electromechanical transistor being connected to the ground potential; the source terminal of the fourth electromechanical transistor and the source terminal of the sixth electromechanical transistor being connected to the supply voltage; the gate terminal of the third electromechanical transistor being connected to the gate terminal of the fourth electromechanical transistor; the gate terminal of the fifth electromechanical transistor being connected to the gate terminal of the sixth electromechanical transistor; The drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor are connected to the first storage node; the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor being connected to the second storage node; the gate terminal of the third electromechanical transistor and the gate terminal of the fourth electromechanical transistor being cross-connected to the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor; and The gate terminal of the fifth electromechanical transistor and the gate terminal of the sixth electromechanical transistor are cross-connected to the drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor.

4. The SRAM cell of claim 1 , wherein to write a bit value of 0 to the first storage node, the bit line being driven to a low voltage causes a potential difference between the source terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force that pulls the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor and enable the drain terminal of the first electromechanical transistor to write the bit value of 0 to the first storage node.

5. The SRAM cell of claim 1 , wherein to write a bit value of 0 to the second storage node, the complementary bit line being driven to a low voltage causes a potential difference between the source terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force that pulls the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enable the drain terminal of the second electromechanical transistor to write the bit value of 0 to the second storage node.

6. The SRAM cell of claim 1 , wherein to read a bit value of 0 from the first storage node, the bit value of 0 in the first storage node causes a potential difference between the drain terminal of the first electromechanical transistor and the gate terminal of the first electromechanical transistor, the potential difference generating an electrostatic force that pulls the cantilever beam of the first electromechanical transistor downward to connect the drain terminal of the first electromechanical transistor to the source terminal of the first electromechanical transistor and enable the bit line to read the bit value of 0 from the first storage node.

7. The SRAM cell of claim 1 , wherein to read a bit value of 0 from the second storage node, the bit value of 0 in the second storage node causes a potential difference between the drain terminal of the second electromechanical transistor and the gate terminal of the second electromechanical transistor, the potential difference generating an electrostatic force that pulls the cantilever beam of the second electromechanical transistor downward to connect the drain terminal of the second electromechanical transistor to the source terminal of the second electromechanical transistor and enable the complementary bit line to read the bit value of 0 from the second storage node.

8. A static random access memory (SRAM) device, comprising: multiple word lines; a plurality of bit lines; a plurality of complementary bit lines; a plurality of driver circuits operable to drive the plurality of word lines; a plurality of SRAM cells, wherein each SRAM cell of the plurality of SRAM cells comprises: A set of electromechanical transistors, wherein each electromechanical transistor in the set of electromechanical transistors comprises: source terminal; gate terminal; drain terminal; and a cantilever beam connected to the source terminal, wherein the cantilever beam is operable to deflect in response to an electrostatic force generated by a potential difference between the source terminal and the drain terminal to connect the drain terminal to the source terminal; and a bistable latch connected to a supply voltage and a ground potential, the bistable latch having a first storage node and a second storage node, the second storage node being complementary to the first storage node, wherein the drain terminal of a first electromechanical transistor in the set of electromechanical transistors is connected to the first storage node, and wherein the drain terminal of a second electromechanical transistor in the set of electromechanical transistors is connected to the second storage node; wherein the gate terminal of the first electromechanical transistor and the gate terminal of the second electromechanical transistor are connected to a word line of the plurality of word lines; wherein the source terminal of the first electromechanical transistor is connected to a bit line among the plurality of bit lines; wherein the source terminal of the second electromechanical transistor is connected to a complementary bit line of the plurality of complementary bit lines; and wherein the first and second electromechanical transistors are operable to enable reading from and writing to the first and second storage nodes via the bit line and the complementary bit line in response to the word line being asserted by a corresponding drive circuit of the plurality of drive circuits. 9 . The SRAM device of claim 8 , wherein the bi-stable latch comprises a pair of cross-coupled inverters, the pair of cross-coupled inverters comprising a plurality of electromechanical transistors in the set of electromechanical transistors.

10. The SRAM device according to claim 9, wherein: a first inverter of the pair of cross-coupled inverters comprising a third electromechanical transistor and a fourth electromechanical transistor of the set of electromechanical transistors; a second inverter of the pair of cross-coupled inverters comprising a fifth electromechanical transistor and a sixth electromechanical transistor of the set of electromechanical transistors; the source terminal of the third electromechanical transistor and the source terminal of the fifth electromechanical transistor being connected to the ground potential; the source terminal of the fourth electromechanical transistor and the source terminal of the sixth electromechanical transistor being connected to the supply voltage; the gate terminal of the third electromechanical transistor being connected to the gate terminal of the fourth electromechanical transistor; the gate terminal of the fifth electromechanical transistor being connected to the gate terminal of the sixth electromechanical transistor; The drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor are connected to the first storage node; the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor being connected to the second storage node; the gate terminal of the third electromechanical transistor and the gate terminal of the fourth electromechanical transistor being cross-connected to the drain terminal of the fifth electromechanical transistor and the drain terminal of the sixth electromechanical transistor; and The gate terminal of the fifth electromechanical transistor and the gate terminal of the sixth electromechanical transistor are cross-connected to the drain terminal of the third electromechanical transistor and the drain terminal of the fourth electromechanical transistor.

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