Page buffer, memory device, and operation method of page buffer

Abstract

The invention relates to a page buffer, a memory device including the page buffer, and an operation method of the page buffer. A memory device includes a memory cell array, a page buffer, and a bit line operation controller. The memory cell array includes memory cells. The page buffer is connected to the memory cells through bit lines. The page buffer is configured to perform a sensing operation of sensing program data stored in the memory cell. The bit line operation controller is configured to control the page buffer to perform a page buffer lower drive operation before the sensing operation. The page buffer includes a latch circuit, a sense amplifier circuit, and a page buffer control switch. The latch circuit is configured to store program data. The sense amplifier circuit is configured to perform a sensing operation. The page buffer control switch is configured to connect the bit line and the sense amplifier circuit to each other.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0038369 filed on March 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to an electronic device, and more particularly, to a page buffer associated with a sensing operation, a memory device including the page buffer, and an operating method of the page buffer. Background Art

[0004] A storage device is a device that stores data under the control of a host device, such as a computer or smartphone. A storage device may include a memory device that stores data and a memory controller that controls the memory device. Memory devices are categorized as either volatile or nonvolatile.

[0005] A memory device may include a page buffer for sensing data stored in a memory cell. The page buffer may perform a sensing operation by controlling the voltage of a bit line connected to the memory cell. The page buffer adjusts the voltage level of a page buffer control signal before the sensing operation, thereby shortening the bit line settling time required to set the bit line voltage to a target level. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a memory device is provided, comprising: a memory cell array including memory cells; a page buffer connected to the memory cells through bit lines, the page buffer being configured to perform a sensing operation for sensing programming data stored in the memory cells; and a bit line operation controller being configured to control the page buffer to perform a page buffer down-drive operation prior to the sensing operation, wherein the page buffer comprises: a latch circuit configured to store programming data; a sense amplifier (amp) circuit configured to perform the sensing operation; and a page buffer control switch configured to connect the bit lines to the sense amplifier circuit, wherein the page buffer down-drive operation is an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch, and wherein the target voltage level is determined based on a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation.

[0007] According to an embodiment of the present disclosure, a page buffer is provided, comprising: a page buffer control switch connected between a bit line connected to a memory cell and a common sense node, the page buffer control switch being configured to be controlled according to a page buffer control signal; first and second switches connected in series between a power supply node and a sense node; a third switch connected between the sense node and the common sense node, the third switch being configured to be controlled according to a sense amplifier (amp) sense signal; fourth and fifth switches connected in series between the sense node and a ground node; and a latch circuit configured to store data sensed from the memory cell, wherein the first switch and the fifth switch are controlled according to data stored in the latch circuit, the second switch is controlled according to a sense amplifier precharge signal, and the fourth switch is controlled according to a sense amplifier discharge signal, wherein before a sensing operation on the memory cell, a page buffer control signal having a target voltage level is applied to the page buffer control switch, and wherein the target voltage level is determined according to a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation.

[0008] According to an embodiment of the present disclosure, a method for operating a memory device is provided, the method comprising: performing a page buffer drive-down operation before a sensing operation for sensing data stored in a memory cell, and performing the sensing operation by applying a read voltage to a word line connected to the memory cell. In one embodiment, performing the page buffer drive-down operation comprises: determining a target voltage level of a page buffer control signal based on a read voltage level of the read voltage, and applying the page buffer control signal having the target voltage level to a page buffer control switch, the page buffer control switch connecting a bit line connected to the memory cell to a latch circuit for storing data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

[0010] In the accompanying drawings, for clarity of explanation, dimensions may be exaggerated. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. It will be understood that when an element or layer, etc. is referred to as being "on," "connected to," or "coupled to" another element or layer, etc., it can be directly on, connected to, or coupled to another element or layer, etc., or there may be intermediate elements or layers, etc. On the contrary, when an element or layer, etc. is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element or layer, etc., there are no intermediate elements or layers, etc. The same reference numerals always indicate the same elements.

[0011] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0013] Figure 3 is a diagram illustrating a bit line shielding operation according to an embodiment of the present disclosure.

[0014] Figure 4 is a timing diagram illustrating a first sensing operation according to an embodiment of the present disclosure.

[0015] Figure 5A is a timing diagram illustrating a second sensing operation according to an embodiment of the present disclosure.

[0016] Figure 5B is a timing diagram illustrating a second sensing operation according to an embodiment of the present disclosure.

[0017] Figure 6 is a diagram illustrating a bit line stabilization time in a sensing operation according to an embodiment of the present disclosure.

[0018] Figure 7 is a diagram illustrating a bit line stabilization time in a sensing operation according to an embodiment of the present disclosure.

[0019] Figure 8A is a diagram illustrating the probability that a memory cell will be read as a programmed cell according to a read level, according to an embodiment of the present disclosure.

[0020] Figure 8B is a diagram illustrating the probability that a memory cell will be read as a programmed cell according to a read level, according to an embodiment of the present disclosure.

[0021] Figure 9 is a diagram illustrating the probability that a memory cell will be read as a programmed cell in a first sensing operation according to an embodiment of the present disclosure.

[0022] Figure 10 is a diagram illustrating the probability that a memory cell will be read as a programmed cell in a second sensing operation according to an embodiment of the present disclosure.

[0023] Figure 11 is a diagram illustrating a setting operation of a page buffer control signal according to an embodiment of the present disclosure.

[0024] Figure 12 is a diagram illustrating a page buffer down driving operation and a sensing operation according to an embodiment of the present disclosure.

[0025] Figure 13 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions disclosed herein are only shown for the purpose of describing the embodiments of the concepts according to the present disclosure. The embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein.

[0027] Various embodiments provide a page buffer, a memory device including the page buffer, and a method for operating the page buffer, which adjusts a voltage level of a page buffer control signal before a sensing operation, thereby shortening a bit line stabilization time and performing a sensing operation.

[0028] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0030] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the read / write circuit 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells.

[0031] Each of the memory cells of the memory device 100 may be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0032] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a read / write circuit 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0033] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

[0034] The address decoder 121 may be connected to the memory cell array 110 through row lines RL. The row lines RL may include a drain select line, a word line, a source select line, and a common source line.

[0035] The address decoder 121 may operate under the control of the control logic 130. The address decoder 121 may receive an address ADDR from the control logic 130.

[0036] The address decoder 121 can decode the block address in the received address ADDR. The address decoder 121 can select at least one memory block from the memory blocks BLK1 to BLKz based on the decoded block address. The address decoder 121 can decode the row address in the received address ADDR. The address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. The address decoder 121 can apply the operating voltage Vop supplied by the voltage generator 122 to the selected word line.

[0037] In a program operation, the address decoder 121 may apply a program voltage to a selected word line and a pass voltage having a level lower than the program voltage to unselected word lines. In a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage to unselected word lines. In a read operation, the address decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a level higher than the read voltage to unselected word lines. In an erase operation, the address decoder 121 may apply a ground voltage to the word line of the selected memory block.

[0038] According to an embodiment of the present disclosure, an erase operation of the memory device 100 may be performed in units of memory blocks. An address ADDR input to the memory device 100 in the erase operation may include a block address.

[0039] According to an embodiment of the present disclosure, the address decoder 121 may decode the column address in the received address ADDR and transmit the decoded column address to the read / write circuit 123. For example, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0040] The voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage supplied to the memory device 100. The voltage generator 122 may operate under the control of the control logic 130.

[0041] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0042] In an embodiment, the voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage. The voltage generator 122 may generate various voltages required by the memory device 100. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of unselect read voltages.

[0043] To generate a plurality of operating voltages Vop having different voltage levels, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage. The voltage generator 122 may generate the plurality of operating voltages Vop by selectively enabling the plurality of pumping capacitors under the control of the control logic 130. The plurality of operating voltages generated by the voltage generator 122 may be supplied to the memory cell array 110 by the address decoder 121.

[0044] The read / write circuit 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm may be connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may operate under the control of the control logic 130.

[0045] The first to mth page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 124. In a program operation, the first to mth page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0046] During a program operation, when a program voltage is applied to a selected word line, the first to mth page buffers PB1 to PBm can transfer data DATA received through data input / output circuit 124 to the selected memory cells via bit lines BL1 to BLm. The memory cells of the selected page can be programmed based on the transferred data DATA. The threshold voltage of the memory cells connected to the bit line to which a program enable voltage (e.g., a ground voltage) is applied can be increased. The threshold voltage of the memory cells connected to the bit line to which a program inhibit voltage (e.g., a power supply voltage) is applied can remain unchanged. During a program verification operation, the first to mth page buffers PB1 to PBm can read the data DATA stored in the selected memory cells from the memory cells via bit lines BL1 to BLm.

[0047] In an embodiment, the first to mth page buffers PB1 to PBm may be connected to selected memory cells through bit lines BL1 to BLm and perform a sensing operation to sense program data stored in the selected memory cells. Each page buffer may include a latch circuit to store program data, a sense amplifier (amp) circuit to perform a sensing operation, and a page buffer control switch to connect the bit line and the sense amplifier circuit to each other.

[0048] In a read operation, the read / write circuit 123 may read data DATA from memory cells of a selected page through the bit lines BL1 to BLm and store the read data DATA in the first to mth page buffers PB1 to PBm.

[0049] In an erase operation, the read / write circuit 123 may float the bit line BL. In an embodiment, the read / write circuit 123 may include a column selection circuit.

[0050] The data input / output circuit 124 may be connected to the first to mth page buffers PB1 to PBm through data lines DL. The data input / output circuit 124 may operate under the control of the control logic 130.

[0051] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. During a program operation, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During a read operation, the data input / output circuit 124 may output data DATA transmitted from the first to mth page buffers PB1 to PBm included in the read / write circuit 123 to the external controller.

[0052] In a read operation or a verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit VRYBIT generated by the control logic 130, and output a pass signal PASS or a fail signal FAIL to the control logic 130 by comparing the sensing voltage VPB received from the read / write circuit 123 with the reference voltage generated by the reference current.

[0053] The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the read / write circuit 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may control the overall operation of the memory device 100. The control logic 130 may operate in response to a command CMD transmitted from an external device.

[0054] The control logic 130 can control the peripheral circuit 120 by generating a plurality of signals in response to a command CMD and an address ADDR. For example, the control logic 130 can generate an operation signal OPSIG, an address ADDR, a read / write circuit control signal PBSIGNALS, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 can output the operation signal OPSIG to the voltage generator 122, the address ADDR to the address decoder 121, the read / write circuit control signal PBSIGNALS to the read / write circuit 123, and the enable bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 can determine whether the verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL output by the sensing circuit 125.

[0055] The control logic 130 may include a page buffer control information storage device 131 and a bit line operation controller 132. In an embodiment, the page buffer control information storage device 131 may be implemented as hardware, software, or a combination of hardware and software. For example, the page buffer control information storage device 131 may be a page buffer control information storage circuit that operates according to an algorithm and / or a processor that executes page buffer control information storage code. In an embodiment, the bit line operation controller 132 may be implemented as hardware, software, or a combination of hardware and software. For example, the bit line operation controller 132 may be a bit line operation controller circuit that operates according to an algorithm and / or a processor that executes bit line operation controller code.

[0056] The page buffer control information storage device 131 may store setting information regarding the page buffer control signal. The setting information may include an offset voltage level for the page buffer control signal, the offset voltage level corresponding to the read voltage level of the read voltage applied to the word line connected to the selected memory cell. The setting information may include the probability that a memory cell connected to a bit line adjacent to the bit line connected to the selected memory cell will be read as a programmed cell by the read voltage level. The setting information may include the lower drive group to which the read voltage level belongs based on the offset voltage level. The magnitude of the offset voltage level may be inversely proportional to the probability that the memory cell will be read as a programmed cell.

[0057] The bit line operation controller 132 may control the page buffer to perform a page buffer down drive operation prior to a sensing operation. The page buffer down drive operation may be an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch. The target voltage level may be determined based on a read voltage level of a read voltage applied to a word line connected to a selected memory cell during a sensing operation. For example, the target voltage level may be determined based on a default voltage level and an offset voltage level of the page buffer control signal.

[0058] The bit line operation controller 132 may determine a target voltage level based on the setup information and control the page buffer to perform a page buffer down-drive operation when performing a word line down-drive operation on the word line. The bit line operation controller 132 may terminate the page buffer down-drive operation before the word line setup operation for setting the potential of the word line to the read voltage level is completed. The word line down-drive operation may be an operation of applying a down-drive voltage lower than the read voltage level to the word line before a sensing operation.

[0059] The bit line operation controller 132 may control the page buffer to perform the next sensing operation by changing the read voltage level after performing the sensing operation. The page buffer may disable the sense amplifier circuit in the next sensing operation according to the result of the sensing operation. In the next sensing operation, the page buffer may apply a shielding voltage to the bit line.

[0060] Figure 2 is a diagram illustrating a page buffer according to an embodiment of the present disclosure.

[0061] Reference Figure 2The page buffer PB may include a page buffer control switch 210, a sense amplifier (amp) circuit 220, and a latch circuit 230. The page buffer control switch 210 may connect the bit line BL and the sense amplifier circuit 220 to each other. The sense amplifier circuit 220 may perform a sensing operation to sense program data stored in a memory cell connected to the bit line BL. The latch circuit 230 may store the program data sensed by the sense amplifier circuit 220.

[0062] exist Figure 2 In the embodiment, the page buffer control switch 210 can be connected between the bit line BL connected to the memory cell and the common sensing node CSO and controlled according to the page buffer control signal PB_SENSE. The page buffer down-driving operation can be an operation of applying the page buffer control signal PB_SENSE having a target voltage level to the page buffer control switch 210 before the sensing operation. The target voltage level can be determined based on the read voltage level of the read voltage applied to the word line connected to the memory cell in the sensing operation, such as Figure 11 When a lower driving voltage lower than the read voltage level is applied to the word line, the page buffer control signal PB_SENSE may maintain a target voltage level. Before the potential of the word line reaches the read voltage level, the page buffer control signal PB_SENSE may change from the target voltage level to a default voltage level.

[0063] The sense amplifier circuit 220 may include first to fifth switches S1 to S5 .

[0064] The first and second switches S1 and S2 can be connected in series between the power supply node VCORE and the sense node SO. The first switch S1 can be controlled according to the programming data stored in the latch circuit 230. The second switch S2 can be controlled according to the sense amplifier precharge signal SA_PRECH_N. The third switch S3 can be connected to the sense node SO and the common sense node CSO and controlled according to the sense amplifier sense signal SA_SENSE. The fourth and fifth switches S4 and S5 can be connected in series between the sense node SO and the ground node. The fourth switch S4 can be controlled according to the sense amplifier discharge signal SA_DISCH. The sense amplifier discharge signal SA_DISCH can be deactivated in the first sensing operation as the initial sensing operation and activated in the second sensing operation as the subsequent next sensing operation. The fifth switch S5 can be controlled according to the programming data stored in the latch circuit 230.

[0065] In an embodiment, since the sense amplifier discharge signal SA_DISCH is always activated in the next sensing operation except for the initial sensing operation, the sense amplifier circuit 220 can be enabled or disabled according to the result of the previous sensing operation stored in the latch circuit 230. For example, when the data value stored in the latch circuit 230 is 1, the potential of the sense node SO can be discharged to the ground level, and the sense amplifier circuit 220 can be disabled. When the data value stored in the latch circuit 230 is 0, the potential of the sense node SO is not discharged to the ground level, and the sense amplifier circuit 220 can be enabled. The enabled sense amplifier circuit 220 can perform the sensing operation normally.

[0066] Figure 3 is a diagram illustrating a bit line shielding operation according to an embodiment of the present disclosure.

[0067] Reference Figure 3 Before the first sensing operation (i.e., "First Sense"), the data in the latch circuit LAT may be initialized to 0, and the data on the sense node SO may be initialized to 1. Vread_1 may be applied as a read voltage to the word line connected to the memory cell. The sense amplifier circuit SA may be enabled or disabled based on the data QS in the latch circuit LAT. For example, when the data QS in the latch circuit LAT is 0, the sense amplifier circuit SA may be enabled. When the data QS in the latch circuit LAT is 1, the sense amplifier circuit SA may be disabled. The sense amplifier circuit SA may reflect the data sensed from the memory cell on the sense node SO. For example, when the memory cell is read as an erased cell using Vread_1 as the read voltage, the data on the sense node SO may be set to 0. When the memory cell is read as a programmed cell, the data on the sense node SO may be set to 1. When the data on the sense node SO is 0, the data QS in the latch circuit LAT may retain the current value. When the data on the sense node SO is 1, the data QS in the latch circuit LAT may be set to 1.

[0068] exist Figure 3 In the first sensing operation, since the memory cell is read as a programming cell with Vread_1 as the read voltage, the data of the sensing node SO may be set to 1, and the data QS of the latch circuit LAT may be set to 1.

[0069] Before the second sensing operation (i.e., <Second Sense>), the data on the sense node SO may be initialized to 1. The latch circuit LAT may store the result 1 of the first sensing operation as data. Vread_2 may be applied as a read voltage to the word line connected to the memory cell. Because the data QS of the latch circuit LAT is 1, the sense amplifier circuit SA may be disabled. While the sense amplifier circuit SA is disabled, a bit line shielding operation may be performed, applying a shielding voltage to the bit line BL. The shielding voltage may include ground voltage GND. In other words, in the second sensing operation, where the read voltage level changes from Vread_1 to Vread_2, a shielding voltage may be applied to the bit line BL based on the result of the first sensing operation.

[0070] In another embodiment, when a memory cell is read as an erased cell in a first sensing operation using Vread_1 as the read voltage, the data on the sense node SO may be set to 0, and the data QS of the latch circuit LAT may be set to 0. Prior to a second sensing operation, the data on the sense node SO may be initialized to 1. The latch circuit LAT may store the result of the sensing operation, 0, as data. Vread_2 may be applied as the read voltage to the word line connected to the memory cell. Since the data QS of the latch circuit LAT is 0, the sense amplifier circuit SA may be enabled. The sense amplifier circuit SA may perform the second sensing operation similarly to the first sensing operation.

[0071] Figure 4 is a timing diagram illustrating a first sensing operation (ie, first sensing) according to an embodiment of the present disclosure.

[0072] Reference Figure 4 At ta0 (i.e., time point ta0), the page buffer control signal PB_SENSE, the sense amplifier sensing signal SA_SENSE, and the sense amplifier precharge signal SA_PRECH_N may be in an activated state. The sense amplifier discharge signal SA_DISCH may be in an inactivated state. The data of the sense node SO may be set to 1. The setting signal SET of the latch circuit may be in an inactivated state. The data QS of the latch circuit may be initially set to 0. Figure 2 At ta0, the first and second switches S1 and S2 are activated. Therefore, the sensing node SO can be precharged to the power supply voltage level and the data can be set to 1.

[0073] At ta1, the sense amplifier precharge signal SA_PRECH_N may be changed from an active state to a deactivated state. Accordingly, the potential of the sense node SO may follow the potential of the bit line BL.

[0074] In the ta1 to ta2 phase, when the memory cell connected to the bit line BL is read as a programmed cell, the potential of the sensing node SO may remain unchanged and the data may be set to 1. When the memory cell connected to the bit line BL is read as an erased cell, the potential of the sensing node SO may be discharged and the data may be set to 0.

[0075] At ta2, the sense amplifier sense signal SA_SENSE may change from an active state to an inactive state. The set signal SET of the latch circuit may change from an inactive state to an active state. When the set signal SET of the latch circuit is activated, the data of the sense node SO may be stored as the data QS of the latch circuit.

[0076] At ta3 , the sense amplifier sense signal SA_SENSE may change from a deactivated state to an activated state.

[0077] Figure 5A is a timing diagram illustrating a second sensing operation (ie, second sensing) according to an embodiment of the present disclosure.

[0078] Reference Figure 5A , at tb0 (ie, time point tb0), the page buffer control signal PB_SENSE, the sense amplifier sensing signal SA_SENSE, the sense amplifier precharge signal SA_PRECH_N, and the sense amplifier discharge signal SA_DISCH may be in an active state. In the case of the second sensing operation, with reference to Figure 4 Unlike the first sensing operation described above, the sense amplifier discharge signal SA_DISCH may be continuously in an active state. The data of the sense node SO may be set to 1. The set signal SET of the latch circuit may be in an inactive state. The data QS of the latch circuit may be set to the result of the first sensing operation. Figure 5A In the case of , when the memory cell is read as an erased cell, the data QS of the latch circuit may be set to 0.

[0079] When the memory cell is read as an erased cell in the first sensing operation, the second sensing operation may be performed with reference to FIG. 1 , except that the sense amplifier discharge signal SA_DISCH is in an active state. Figure 4 The first sensing operation described is performed identically.

[0080] Figure 5B is a timing diagram illustrating a second sensing operation according to an embodiment of the present disclosure.

[0081] Reference Figure 5B, at tc0 (ie, time point tc0), the page buffer control signal PB_SENSE, the sense amplifier sensing signal SA_SENSE, the sense amplifier precharge signal SA_PRECH_N, and the sense amplifier discharge signal SA_DISCH may be in an active state. In the case of the second sensing operation, with reference to Figure 4 Unlike the first sensing operation described above, the sense amplifier discharge signal SA_DISCH may be continuously in an active state. The setting signal SET of the latch circuit may be in an inactive state. The data QS of the latch circuit may be set to the result of the first sensing operation. Figure 5B In the case of , when the memory cell is read as a program cell in the first sensing operation, the data QS of the latch circuit may be set to 1.

[0082] Reference Figure 2 , the sense amplifier discharge signal SA_DISCH is in an active state, and the data QS of the latch circuit is 1. Therefore, both the fourth and fifth switches S4 and S5 may be activated, and the sensing node SO may be connected to the ground node. Accordingly, the potential of the sensing node SO may be discharged to the ground voltage level, and the data of the sensing node SO may be set to 0.

[0083] Since the sensing node SO is electrically connected to the bit line BL when the sense amplifier sensing signal SA_SENSE is in an active state, the potential of the bit line BL may also be discharged to the ground voltage level, and a bit line shielding operation may be performed.

[0084] Figure 6 is a diagram illustrating a bit line stabilization time in a sensing operation according to an embodiment of the present disclosure.

[0085] Reference Figure 6 , shows waveforms of the word line potential, bit line potential, cell current, and sense current when the read voltage Vread applied to the word line in a sensing operation is higher than the threshold voltage Vt of the memory cell (i.e., Cell Vt). Since the read voltage Vread is higher than the threshold voltage Vt of the memory cell Cell, the memory cell can be read as an erased cell.

[0086] To shorten the word line stabilization time required to set the potential of the word line to the read voltage level, a lower drive voltage may be applied to the word line. This may cause an undershoot, where the cell current drops excessively, and the sense current following the cell current may also undershoot. This undershoot of the sense current may increase the bit line stabilization time required to set the potential of the bit line to the target level.

[0087] In case 1, the page buffer down drive operation PB UD of applying a page buffer control signal having a target voltage level lower than a default voltage level to the page buffer control switch may not be performed. The bit line stabilization may be completed at time c1.

[0088] In case 2, a page buffer down-drive operation (PBUD) can be performed. The page buffer down-drive operation (PBUD) can terminate before word line stabilization is complete. When the page buffer down-drive operation (PBUD) terminates, the page buffer control signal can return from the target voltage level to the default voltage level. Consequently, the gate voltage of the page buffer control switch may temporarily and suddenly increase, potentially forcibly causing an overshoot in the cell current. Due to the overshoot, the cell current may be released in an undershoot state, and bit line stabilization can terminate at time c2.

[0089] In reference Figure 6 In the described embodiment, when a memory cell is read as an erased cell, the time to terminate the bit line stabilization can be shortened from tp1 to c2 when performing the page buffer down drive operation PB UD.

[0090] Figure 7 is a diagram illustrating a bit line stabilization time in a sensing operation according to an embodiment of the present disclosure.

[0091] Reference Figure 7 , shows waveforms of a word line potential, a bit line potential, a cell current, and a sense current when a read voltage Vread applied to a word line in a sensing operation is lower than a threshold voltage Vt of a memory cell. Since the read voltage Vread is lower than the threshold voltage Vt of the memory cell, the memory cell can be read as a programmed cell.

[0092] To shorten the word line stabilization time required to set the word line potential to the read voltage level, a lower drive voltage can be applied to the word line. Since the read voltage Vread is lower than the memory cell's threshold voltage Vt, the cell current (-0nA) and sense current (-4nA) are very small and have little effect on the read result.

[0093] On the other hand, when the page buffer down drive operation (PB UD) is performed, the potential of the bit line follows the voltage of the page buffer control switch. Therefore, when the bit line voltage is low, the rise of the bit line voltage may be suppressed. Since the rise of the bit line voltage is delayed, noise may be caused in adjacent bit lines through parasitic capacitance for a longer time, and the bit line stabilization time may be reduced.

[0094] In reference Figure 7 In the described embodiment, when a memory cell is read as a programming cell, the end time of the bit line stabilization time can be delayed from d1 to tp2 when performing the page buffer down drive operation PB UD. In other words, when a memory cell is read as a programming cell, excessive page buffer down drive operations may destabilize the bit line, and the bit line stabilization time may be increased.

[0095] Therefore, according to Figure 11 The strength of the driving operation under the page buffer is adjusted based on the probability that the memory cells connected to the adjacent bit lines will be read as programmed cells, which will be described later, so that in embodiments, the bit line stabilization time can be optimally shortened.

[0096] Figure 8A is a diagram illustrating the probability that a memory cell will be read as a programmed cell according to a read level, according to an embodiment of the present disclosure.

[0097] Reference Figure 8A , assuming that the memory cell is a three-level cell storing three bits of data. The number of data bits stored by the memory cell is not limited to this embodiment.

[0098] The threshold voltage distribution of memory cells can be divided according to first to seventh read levels R1 to R7. When reading the least significant bit (LSB) data stored in a memory cell, a first sensing operation (e.g., a first read) can be performed according to the seventh read level R7, and a second sensing operation (e.g., a second read) can be performed according to the third read level R3. In the first sensing operation, the probability that a memory cell will be read as a programmed cell (e.g., a PGM cell) can be 1 / 8. In the first sensing operation, the probability that a memory cell will be read as an erased cell (e.g., an ERA cell) can be 7 / 8. In the second sensing operation, the probability that a memory cell will be read as a programmed cell can be 5 / 8. In the second sensing operation, the probability that a memory cell will be read as an erased cell can be 3 / 8.

[0099] Figure 8B is a diagram illustrating the probability that a memory cell will be read as a programmed cell according to a read level, according to an embodiment of the present disclosure.

[0100] Reference Figure 8B ,as Figure 8A As described above, the least significant bit (LSB) of the memory cell can be read. However, as shown in FIG. Figure 3 and Figure 5B As described above, when a memory cell is read as a programmed cell in a sensing operation, a bit line shielding operation of applying a shielding voltage to a bit line connected to the corresponding memory cell may be performed in a subsequent next sensing operation.

[0101] Therefore, the first sensing operation can be performed according to the seventh read level R7, the memory cells read as programming cells can be shielded by the seventh read level, and the bit line shielding operation can be performed. In the next sensing operation, the shielded memory cells can be read as bit line shielding cells instead of programming cells.

[0102] Therefore, excluding the shielded memory cells, the probability that the memory cells will be read as programmed cells according to the third read level R3 in the second sensing operation may be 4 / 8.

[0103] Figure 9 is a diagram illustrating the probability that a memory cell will be read as a programmed cell in a first sensing operation according to an embodiment of the present disclosure.

[0104] Reference Figure 9 In the case where the first sensing operation is an initial sensing operation, the bit line shielding unit is not present when the memory cell is read. Therefore, in the case of a first sensing operation in which the least significant bit (LSB) data stored in the memory cell is sensed according to the seventh read level R7, the probability that the memory cell will be read as a programmed cell can be 1 / 8. In the case of a first sensing operation in which the center significant bit (CSB) data stored in the memory cell is sensed according to the sixth read level R6, the probability that the memory cell will be read as a programmed cell can be 2 / 8. In the case of a first sensing operation in which the most significant bit (MSB) data stored in the memory cell is sensed according to the fifth read level R5, the probability that the memory cell will be read as a programmed cell can be 3 / 8.

[0105] Figure 10 is a diagram illustrating the probability that a memory cell will be read as a programmed cell in a second sensing operation according to an embodiment of the present disclosure.

[0106] Reference Figure 10 In the case of a second sensing operation performed as the next sensing operation after the first sensing operation as the initial sensing operation, the bit line shielding unit is present when the memory cell is read. Therefore, in the case of the second sensing operation in which the least significant bit (LSB) data stored in the memory cell is sensed according to the third read level R3, the probability that the memory cell will be read as a programmed cell can be 4 / 8. In the case of a second sensing operation in which the center significant bit (CSB) data stored in the memory cell is sensed according to the fourth read level R4, the probability that the memory cell will be read as a programmed cell can be 2 / 8. In the case of a second sensing operation in which the most significant bit (MSB) data stored in the memory cell is sensed according to the first read level R1, the probability that the memory cell will be read as a programmed cell can be 4 / 8.

[0107] Figure 11 is a diagram illustrating a setting operation of a page buffer control signal according to an embodiment of the present disclosure.

[0108] Reference Figure 11The setting information of the page buffer control signal may include an offset voltage level of the page buffer control signal, the offset voltage level corresponding to the read voltage level of the read voltage. The setting information may include a probability that a memory cell connected to a bit line adjacent to a bit line connected to the selected memory cell will be read as a programmed cell by the read voltage level. The setting information may include the lower drive group (UD) to which the read voltage level belongs based on the offset voltage level. The magnitude of the offset voltage level may be inversely proportional to the probability that the memory cell will be read as a programmed cell.

[0109] For example, the target voltage level of the page buffer control signal can be determined based on the default voltage level of the page buffer control signal and the offset voltage level. The offset voltage level can be determined based on the probability that the memory cells connected to the bit line adjacent to the bit line will be read as programmed cells by reading the voltage level.

[0110] exist Figure 11 In the embodiment of the present invention, when the read level of the read voltage Vread is the seventh read level V7, the probability that the memory cell connected to the adjacent bit line will be read as a programmed cell by the seventh read level R7 in the sensing operation may be 1 / 8. The level of the offset voltage Voffset may be -0.3 V. Therefore, the level of the target voltage Vtar of the page buffer control signal may be 0.9 V.

[0111] Figure 12 is a diagram illustrating a page buffer down driving operation and a sensing operation according to an embodiment of the present disclosure.

[0112] Reference Figure 12 , the sensing operation performed from td2 (ie, time point td2) to td6 (ie, time point td6) can be performed as described with reference to Figure 4 In another embodiment, when the sensing operation performed from td2 to td6 is the next sensing operation instead of the initial sensing operation, the sensing operation may be performed as described in reference to FIG. Figure 5A and Figure 5B The sensing operation is performed as described above.

[0113] The down driving operation may be performed from td0 to td2, which is a period of time before the sensing operation is performed. The down driving operation may include a word line down driving operation and a page buffer down driving operation.

[0114] The word line lower driving operation may be an operation of applying a lower driving voltage Vud to the word line before the sensing operation, the lower driving voltage Vud having a level lower than that of the read voltage Vread.

[0115] The page buffer down drive operation may be an operation of applying a page buffer control signal having a target voltage Vtar level to the page buffer control switch. The page buffer down drive operation may be terminated before the word line down drive operation is terminated. The level of the target voltage Vtar may be determined based on a read voltage level of a read voltage Vread applied to a word line connected to a memory cell in a sensing operation, as described with reference to FIG. Figure 11 As stated.

[0116] Figure 13 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0117] Reference Figure 13 , in step S1301, the memory device may determine a target voltage level of a page buffer control signal based on a level of a read voltage applied to a word line connected to a memory cell.

[0118] In step S1303, the memory device may perform a page buffer down drive operation using a page buffer control signal having a target voltage level. The page buffer down drive operation may be an operation of applying a page buffer control signal having a target voltage level to a page buffer switch before a sensing operation.

[0119] In step S1305 , the memory device may perform a sensing operation using a read voltage having a read voltage level.

[0120] According to an embodiment of the present disclosure, a page buffer, a memory device including the page buffer, and an operating method thereof may be provided to adjust a voltage level of a page buffer control signal before a sensing operation, thereby shortening a bit line stabilization time and performing a sensing operation.

[0121] Although the present disclosure has been shown and described with reference to specific examples of its embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the examples of the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0122] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described but may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure and the present disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0123] On the other hand, examples of embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many modifications are possible within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A memory device comprising: a memory cell array comprising memory cells; a page buffer connected to the memory cell through a bit line, the page buffer performing a sensing operation for sensing program data stored in the memory cell; as well as A bit line operation controller controls the page buffer to perform a page buffer down drive operation before the sensing operation. in, The page buffer includes: a latch circuit for storing the programming data; A sense amplifier circuit, i.e., a sense amp circuit, performs the sensing operation; and a page buffer control switch connecting the bit line to the sense amplifier circuit, The page buffer down driving operation is an operation of applying a page buffer control signal having a target voltage level to the page buffer control switch, and The target voltage level is determined based on a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation.

2. The memory device according to claim 1 , further comprising: A page buffer control information storage device stores setting information on the page buffer control signal.

3. The memory device according to claim 2, wherein The setting information includes an offset voltage level of the page buffer control signal, the offset voltage level corresponding to the read voltage level.

4. The memory device according to claim 3, wherein The target voltage level is determined based on a default voltage level of the page buffer control signal and the offset voltage level.

5. The memory device according to claim 3, wherein The setup information includes a probability that memory cells connected to a bit line adjacent to the bit line will be read as programmed cells according to the read voltage level. The memory device according to claim 5 , wherein: The magnitude of the offset voltage level is inversely proportional to the probability that the memory cell will be read as the programmed cell.

7. The memory device according to claim 3, wherein: The setting information includes a lower driving group to which the read voltage level belongs according to the offset voltage level.

8. The memory device according to claim 2, wherein: The bit line operation controller determines the target voltage level based on the setting information, and controls the page buffer to perform the page buffer down drive operation when performing a word line down drive operation on the word line.

9. The memory device according to claim 8, wherein The bit line operation controller terminates the page buffer down driving operation before a word line setting operation of setting the potential of the word line to the read voltage level is completed.

10. The memory device according to claim 8, wherein The word line lower driving operation is an operation of applying a lower driving voltage having a level lower than the read voltage level to the word line before the sensing operation.

11. The memory device according to claim 1, wherein When the read voltage level changes after performing the sensing operation, the page buffer performs a next sensing operation.

12. The memory device according to claim 11, wherein The page buffer disables the sense amplifier circuit in the next sensing operation according to a result of the sensing operation.

13. The memory device according to claim 11, wherein The page buffer applies a shielding voltage to the bit line in the next sensing operation according to a result of the sensing operation.

14. A page buffer comprising: a page buffer control switch connected between a bit line connected to the memory cell and a common sensing node, and controlled according to a page buffer control signal; A first switch and a second switch are connected in series between the power supply node and the sensing node; a third switch connected between the sensing node and the common sensing node, and controlled according to a sensing signal of a sensing amplifier, i.e., a sensing amp sensing signal; a fourth switch and a fifth switch connected in series between the sensing node and the ground node; as well as a latch circuit storing data sensed from the memory cell, in, controlling the first switch and the fifth switch according to data stored in the latch circuit, controlling the second switch according to a sense amplifier precharge signal, controlling the fourth switch according to the sense amplifier discharge signal, Before a sensing operation on the memory cell, applying the page buffer control signal having a target voltage level to the page buffer control switch, and The target voltage level is determined according to a read voltage level of a read voltage applied to a word line connected to the memory cell in the sensing operation.

15. The page buffer according to claim 14, wherein: The target voltage level is determined based on a default voltage level and an offset voltage level of the page buffer control signal, and The offset voltage level is determined according to a probability that memory cells connected to a bit line adjacent to the bit line will be read as programmed cells according to the read voltage level.

16. The page buffer according to claim 14, wherein: When a lower driving voltage lower than the read voltage level is applied to the word line, the page buffer control signal maintains the target voltage level, and changes from the target voltage level to a default voltage level before the potential of the word line reaches the read voltage level.

17. The page buffer according to claim 14, wherein: According to a result of the sensing operation, a shielding voltage is applied to the bit line in a next sensing operation in which the read voltage level is changed.

18. The page buffer according to claim 17, wherein: The sense amplifier discharge signal is disabled in the sensing operation and enabled in the next sensing operation.

19. A method of operating a memory device, comprising: performing a page buffer down driving operation before a sensing operation of sensing data stored in a memory cell; as well as performing the sensing operation by applying a read voltage to a word line connected to the memory cell, The step of executing the page buffer down-driving operation includes: determining a target voltage level of a page buffer control signal based on a read voltage level of the read voltage; and The page buffer control signal having the target voltage level is applied to a page buffer control switch, which connects a bit line connected to the memory cell to a latch circuit storing the data.

20. The method according to claim 19, wherein In determining the target voltage level, the target voltage level is determined based on a default voltage level and an offset voltage level of the page buffer control signal, and The offset voltage level is determined according to a probability that memory cells connected to a bit line adjacent to the bit line will be read as programmed cells according to the read voltage level.

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