Semiconductor device and operation method thereof
By accurately erasing and verifying the memory cell pairs or erased areas of semiconductor devices and applying different voltages, the problem of widening of the storage bit threshold voltage distribution is solved, and the performance and verification accuracy of the device are improved.
Patent Information
- Application Number
- CN202410338704.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2025-09-23
AI Technical Summary
During the erase operation of a semiconductor device, the threshold voltage distribution of the storage bits tends to widen, resulting in degradation of device performance.
By performing independent erasure verification on the memory cell pairs or the memory bits of the target erasure area, different voltages are applied to the memory bits that succeeded and failed erasure according to the verification results to perform the m+1th erasure operation to prevent the memory bits that have been successfully erased from being erased again.
It effectively suppresses the threshold voltage of the storage bit from moving in a negative direction, improves the threshold voltage distribution, and improves the performance of the semiconductor device and the accuracy of erase verification.
Smart Images
Figure CN120690264A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to an operating method of a semiconductor device. Background Art
[0002] As consumer spending continues to rise, users are demanding higher performance from electronic devices, driving the rapid development of memory technology. Non-volatile flash memory devices, using polysilicon floating gates as their cells, are gaining an increasingly important position in the memory field thanks to their advantages, including low cost, low power consumption, high reliability, and fast access speeds.
[0003] During an erase operation, in order to ensure that all storage bits (or storage cells) are erased, it is necessary to repeatedly verify whether the storage bits have been successfully erased (erase verify, EV for short). If any storage bit fails to be erased, all storage bits need to be erased again, which will cause the storage bits that have been successfully erased (pass erase verify, pass EV for short) to repeatedly undergo the erase process. The threshold voltage of the successfully erased storage bits may move more negatively, thereby widening the threshold voltage distribution of the storage bits. This problem needs to be solved urgently. Summary of the Invention
[0004] The present application provides an operating method for a semiconductor device, which can effectively improve the problem of widening of the threshold voltage distribution of storage bits when the semiconductor device performs an erase operation.
[0005] In a first aspect, the present application provides an operating method for a semiconductor device, comprising: performing an erasure verification on the mth erasure operation of two storage bits of at least one memory cell pair, obtaining a verification result of the mth erasure operation of the memory cell pair, wherein m is an integer greater than 0, each of the memory bits corresponds to a control gate line, and the control gate line is connected to the corresponding memory bit; in response to the verification result of the mth erasure operation of the memory cell pair, applying a first voltage to the control gate line corresponding to the storage bit that has been successfully erased, and applying a second voltage to the control gate line corresponding to the storage bit that has failed to be erased, so as to perform an m+1th erasure operation.
[0006] Optionally, the operating method of the semiconductor device includes: performing erase verification on the mth erase operation of the target erase area, obtaining a verification result of the mth erase operation of the target erase area, the target erase area includes at least one storage cell row, each of the storage cell row includes two storage bit rows, each of the storage bit rows corresponds to a control gate line, and the control gate line is connected to each of the storage bits in the corresponding storage bit row; in response to the verification result of the mth erase operation of the target erase area being: at least one storage bit row is successfully erased and at least one storage bit row fails to be erased, performing the m+1th erase operation on the target erase area; wherein, performing the m+1th erase operation on the target erase area includes: applying a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applying a second voltage to the control gate line corresponding to the storage bit row that fails to be erased.
[0007] Optionally, each of the memory cell rows corresponds to a word line; wherein, performing the m+1th erasing operation on the target erasing area includes: applying a third voltage to the word line of the target erasing area, and the absolute value of the difference between the first voltage and the third voltage is smaller than the absolute value of the difference between the second voltage and the third voltage.
[0008] Optionally, when all storage bits in the storage bit row are successfully erased, it is determined that the storage bit row is successfully erased; when at least one storage bit in the storage bit row fails to be erased, it is determined that the storage bit row is failed to be erased.
[0009] Optionally, the operating method of the semiconductor device further includes: performing an mth erasing operation on the target erasing area before performing erasure verification on the mth erasing operation on the target erasing area; wherein, when m=1, performing an mth erasing operation on the target erasing area in response to an erase start signal; when m is greater than 1, in response to obtaining the verification result of the m-1th erasing operation on the target erasing area: at least one storage bit row is successfully erased, and at least one storage bit row fails to be erased, performing an mth erasing operation on the target erasing area.
[0010] Optionally, the erasure verification of the mth erasure operation on the target erase area includes: performing erasure verification on the mth erasure operation of each of the memory cell rows in sequence to obtain an erasure verification result of the mth erasure operation of each of the memory bit rows in each of the memory cell rows; wherein the two memory bit rows in each of the memory cell rows are the first memory bit row and the second memory bit row, respectively, and the erasure verification of the mth erasure operation on each of the memory cell rows includes: applying a turn-on voltage to the control gate line corresponding to the first memory bit row in each of the memory cell rows, and applying a check voltage to the control gate line corresponding to the second memory bit row in each of the memory cell rows, to obtain an erasure verification result of the mth erasure operation of the first memory bit row; applying a turn-on voltage to the control gate line corresponding to the second memory bit row in each of the memory cell rows, and applying a check voltage to the control gate line corresponding to the first memory bit row in each of the memory cell rows, to obtain an erasure verification result of the mth erasure operation of the second memory bit row.
[0011] Optionally, the operating method of the semiconductor device further includes: latching the erasure verification result of the mth erasure operation of the storage bit row that is successfully erased through a latch; or latching the erasure verification result of the mth erasure operation of the storage bit row that is failed to be erased through a latch.
[0012] Optionally, the erase verification result of the mth erase operation of the storage bit row that is successfully erased by latching the latch includes: when it is determined that the storage bit row is erased successfully, the latch corresponding to the erase verification result of the mth erase operation of the storage bit row is set from the initial state bit to the first state bit; the erase verification result of the mth erase operation of the storage bit row that is failed to be erased by latching the latch includes: when it is determined that the storage bit row is erased failed, the latch corresponding to the erase verification result of the mth erase operation of the storage bit row is set from the initial state bit to the first state bit.
[0013] Optionally, the operating method of the semiconductor device further includes: latching an erasure verification result of the mth erasure operation of each storage bit row by a latch.
[0014] Optionally, latching the erasure verification result of the mth erasure operation of each storage bit by the latch includes: when it is determined that the erasure of the storage bit row is successful, setting the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row from the initial state bit to the first state bit; when it is determined that the erasure of the storage bit row fails, setting the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row from the initial state bit to the second state bit.
[0015] Optionally, the semiconductor device further includes a control circuit, and the m+1th erasing operation on the target erasure area includes: the control circuit applies a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applies a second voltage to the control gate line corresponding to the storage bit row that fails to be erased, according to the status bit of the latch.
[0016] In a second aspect, the present application provides a semiconductor device, comprising: at least one memory cell row, each memory cell row comprising two memory bit rows, each memory cell row comprising at least one memory cell pair, each memory cell pair comprising two memory bits, the two memory bits being respectively located in two adjacent memory bit rows; a plurality of control gate lines corresponding one-to-one to the plurality of memory bit rows, each control gate line being electrically connected to each memory bit in the corresponding memory bit row; an erase verification module for performing erase verification on the mth erase operation of the target erase area to obtain a verification result of the mth erase operation of the target erase area; a control circuit for applying a first voltage to the control gate line corresponding to the successfully erased memory bit row and a second voltage to the control gate line corresponding to the failed erase memory bit row based on the verification result of the mth erase operation of the target erase area: at least one memory bit row is successfully erased and at least one memory bit row is failed to be erased.
[0017] According to the semiconductor device and its operating method provided by the present application, the operating method of the semiconductor device includes: performing erase verification on the mth erase operation of two storage bits of at least one memory cell pair, obtaining the verification result of the mth erase operation of the memory cell pair, wherein m is an integer greater than 0, each of the memory bits corresponds to a control gate line, and the control gate line is connected to the corresponding memory bit; in response to the verification result of the mth erase operation of the memory cell pair, applying a first voltage to the control gate line corresponding to the erased storage bit, and applying a second voltage to the control gate line corresponding to the erased storage bit to perform the m+1th erase operation. The operating method of the semiconductor device can effectively improve the problem of widening of the threshold voltage distribution of the memory cell when the NORD memory performs an erase operation. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0019] Figure 1 A schematic structural diagram of a storage unit pair provided in some embodiments of the present application.
[0020] Figure 2 An equivalent circuit diagram of a memory cell pair provided in some embodiments of the present application.
[0021] Figure 3 Schematic diagram of a circuit module of a semiconductor device provided in some embodiments of the present application.
[0022] Figure 4 A schematic flow chart of a method for operating a semiconductor device according to some embodiments of the present application.
[0023] Figure 5 A schematic flow chart of a method for operating a semiconductor device according to some embodiments of the present application.
[0024] Figure 6 A schematic diagram of a process for performing erase verification on the mth erase operation of each memory cell row provided in some embodiments of the present application.
[0025] Description of reference numerals:
[0026] Target erase area A1; memory cell pair 11; memory bit 21; first control gate line CGL1; second control gate line CGL2; word line WL; first bit line BL1; second bit line BL2; control circuit CG Driver; word line driver WL Driver; bit line driver BL Driver; erase verification module M1; sense amplifier SA; DETAILED DESCRIPTION
[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.
[0028] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.
[0029] Figure 1 A schematic diagram of the structure of a storage unit pair provided in some embodiments of the present application; Figure 2 An equivalent circuit diagram of a memory cell pair provided in some embodiments of the present application; Figure 3 Schematic diagram of a circuit module of a semiconductor device provided in some embodiments of the present application. Figure 4 Schematic diagram of a process flow of a semiconductor device operating method provided in some embodiments of the present application. Figures 1-4 As shown, in the first aspect, an embodiment of the present application provides an operating method for a semiconductor device, which can suppress the threshold voltage of the storage bit that has been successfully erased from moving to the negative direction when the NORD memory performs an erase operation, thereby improving the problem of widening of the threshold voltage distribution of the storage bit.
[0030] Reference Figure 4 As shown, in some embodiments of the present application, the operating method of the semiconductor device includes:
[0031] Step S01: performing an erase verification on two storage bits 21 of at least one memory cell pair 11 for an m-th erase operation, obtaining a verification result of the m-th erase operation of the memory cell pair 11, wherein m is an integer greater than 0, each of the storage bits 21 corresponds to a control gate line CGL, and the control gate line is connected to the corresponding storage bit 21;
[0032] Step S02: In response to the verification result of the mth erasing operation of the storage unit pair 11, a first voltage is applied to the control gate line corresponding to the successfully erased storage bit 21, and a second voltage is applied to the control gate line corresponding to the failed erased storage bit 21 to perform the m+1th erasing operation.
[0033] In the operating method of the semiconductor device provided in the present application, an m+1th erasing operation is performed, in response to the verification result of the mth erasing operation of the memory cell pair 11, a first voltage is applied to the control gate line corresponding to the successfully erased storage bit 21, and a second voltage is applied to the control gate line corresponding to the failed erased storage bit 21, respectively. The first voltage is different from the second voltage, that is, when the m+1th erasing operation is performed, the voltage applied to the control gate line corresponding to the successfully erased storage bit 21 and the voltage applied to the control gate line corresponding to the failed erased storage bit 21 are different. The second voltage can be understood as an erasing voltage. Therefore, by making the first voltage not meet the erase voltage standard, the successfully erased storage bit 21 can be prevented from being effectively erased again during the m+1th erasing operation, thereby preventing the threshold voltage of the storage bit 21 that has been successfully erased in the mth erasing operation from shifting further negatively during the m+1th erasing operation, thereby improving the problem of a widening threshold voltage distribution of the storage bit 21, and thereby improving the performance of the semiconductor device.
[0034] In some embodiments of the present application, the semiconductor device includes at least one memory cell row, each memory cell row includes two memory bit rows, each memory cell row includes at least one memory cell pair 11, each memory cell pair 11 includes two memory bits 21, and the two memory bits 21 are respectively located in two adjacent memory bit rows. In the direction of the control gate line, there is no restriction on the connection method between adjacent memory cell pairs 11 and the bit lines. For example, they can share a bit line or be connected to different bit lines, which is not limited in the relevant embodiments.
[0035] Reference Figure 2 As shown, in some embodiments of the present application, the bit lines include a first bit line BL1 and a second bit line BL2.
[0036] In the related art, in an actual semiconductor device architecture, each memory cell row often includes multiple memory cell pairs 11. That is, each memory cell row includes two memory bit rows, and each memory bit row includes multiple memory cell pairs 11. Taking a single memory bit row as an example, multiple memory cell pairs 11 in a memory bit row are electrically connected to the same control gate line and are applied with the same erase voltage during an erase operation.
[0037] Figure 5 A schematic flow chart of a method for operating a semiconductor device provided in some embodiments of the present application. Figure 1-Figure 5 As shown, in some embodiments of the present application, the operating method of the semiconductor device includes:
[0038] Step S011: performing an erase verification on the mth erase operation of the target erase area A1 to obtain a verification result of the mth erase operation of the target erase area A1, wherein the target erase area A1 includes at least one memory cell row, each memory cell row includes two memory bit rows, each memory bit row corresponds to a control gate line, and the control gate line is connected to each memory bit 21 in the corresponding memory bit row;
[0039] Step S012: In response to the verification result of the m-th erasing operation on the target erasing area A1 being: at least one storage bit row is successfully erased and at least one storage bit row is failed to be erased, the target erasing area A1 is subjected to the m+1-th erasing operation; wherein, the m+1-th erasing operation on the target erasing area A1 includes: applying a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applying a second voltage to the control gate line corresponding to the storage bit row that fails to be erased.
[0040] In the operating method of the semiconductor device provided in the present application, performing the m+1th erasing operation on the target erasing area A1 includes: applying a first voltage to the control gate line corresponding to the storage bit row that has been successfully erased, and applying a second voltage to the control gate line corresponding to the storage bit row that has failed to be erased. That is, during the m+1th erasing operation, the voltage applied to the control gate line corresponding to the storage bit row that has been successfully erased is different from the voltage applied to the control gate line corresponding to the storage bit row that has failed to be erased. The second voltage can be understood as an erasing voltage. Therefore, by making the first voltage not meet the erase voltage standard, the storage bit row that has been successfully erased can be prevented from being effectively erased again during the m+1th erasing operation. This can prevent the threshold voltage of each storage bit 21 in the storage bit row that has been successfully erased in the mth erasing operation from shifting further toward the negative direction during the m+1th erasing operation, thereby improving the problem of a widening threshold voltage distribution of the storage bit 21, thereby improving the performance of the semiconductor device.
[0041] It should be noted that in the related art, when the two storage bit rows belonging to the same storage cell row perform the current erase operation, the two control gate lines corresponding to the two storage bit rows of the same storage cell row will be applied with the same erase voltage. This makes it so that even if all the storage bits 21 in one storage bit row of the same storage cell row have been successfully erased in the previous erase operation, the corresponding control gate line will still be applied with an erase voltage, thereby causing the threshold voltage distribution of all the storage bits 21 in the storage bit row to widen. The operating method of the semiconductor device provided in the present application can perform independent erase verification on a single storage bit row of the same storage cell row, thereby more accurately avoiding the threshold voltage of each storage bit 21 in the storage bit row that has been successfully erased in the mth erase operation from moving further negatively in the m+1th erase operation, thereby greatly improving the accuracy of erase verification and improving the performance of the semiconductor device.
[0042] In some embodiments of the present application, each of the memory cell rows corresponds to a word line WL; wherein, the m+1th erasing operation on the target erasing area A1 includes: applying a third voltage to the word line WL of the target erasing area A1, and the absolute value of the difference between the first voltage and the third voltage is smaller than the absolute value of the difference between the second voltage and the third voltage.
[0043] In the operating method of the semiconductor device provided in this application, during the (m+1)th erase operation, a third voltage (e.g., a positive voltage of 8V to 10V) is applied to the word line WL corresponding to the selected memory cell row, a first voltage is applied to the control gate line corresponding to the successfully erased memory bit row in the selected memory cell row, and a second voltage (e.g., a negative voltage of -6V to -10V, corresponding to the erase voltage) is applied to the control gate line corresponding to the failed erased memory bit row in the selected memory cell row. One of the bit lines is pulled down to ground at 0V. The voltage on the control gate of the memory bit 21 in the failed erased memory bit row is pulled down by the capacitor, and electrons in the floating gate layer are tunneled through the sidewall of the floating gate to the word line WL under the action of the electric field directed from the word line WL to the floating gate, thereby completing the (m+1)th operation. Electrons on the floating gate can tunnel, and the absolute value of the voltage difference between the second voltage and the third voltage needs to be greater than a threshold value (such as 15V). Therefore, the present application makes the absolute value of the difference between the first voltage (such as 0V to 5V) and the third voltage smaller than the absolute value of the difference between the second voltage and the third voltage, so that when the m+1th erasing operation is performed, it is difficult for electrons on the floating gate of the storage bit 21 in the storage bit row that has been successfully erased to tunnel, thereby avoiding the threshold voltage of each storage bit 21 in the storage bit row that has been successfully erased in the mth erasing operation from moving more negatively in the m+1th erasing operation, thereby improving the problem of widening the threshold voltage distribution of the storage bit 21, thereby improving the performance of the semiconductor device.
[0044] Specifically, in some embodiments of the present application, when all storage bits 21 in the storage bit row are successfully erased, the storage bit row is determined to be successfully erased; when at least one storage bit 21 in the storage bit row fails to be erased, the storage bit row is determined to be failed to be erased.
[0045] Specifically, in the operating method of the semiconductor device provided in the present application, each of the memory cell rows often includes multiple memory cell pairs 11, and the multiple memory cell pairs 11 in each memory bit row are electrically connected to the same control gate line and are applied with the same voltage when performing a certain erase operation. Therefore, when all the memory bits 21 in the memory bit row are successfully erased, the memory bit row is determined to be successfully erased; when at least one memory bit 21 in the memory bit row fails to be erased, the judgment principle of determining that the memory bit row has failed to be erased can better meet actual work requirements and improve the efficiency of erase verification.
[0046] In some embodiments of the present application, the operating method of the semiconductor device further includes: before performing erase verification on the mth erase operation on the target erase area A1, performing the mth erase operation on the target erase area A1; wherein, when m=1, in response to an erase start signal, performing the mth erase operation on the target erase area A1; when m is greater than 1, in response to obtaining the verification result of the m-1th erase operation on the target erase area A1: at least one storage bit row is successfully erased, and at least one storage bit row fails to be erased, performing the mth erase operation on the target erase area A1.
[0047] Figure 6 A schematic diagram of a process for performing erase verification on the mth erase operation of each memory cell row provided in some embodiments of the present application. Figure 6 As shown, in some embodiments of the present application, performing erasure verification on the m-th erasure operation of the target erasure area A1 includes:
[0048] performing erasure verification on the mth erasure operation of each of the memory cell rows in sequence to obtain an erasure verification result of the mth erasure operation of each of the memory bit rows in each of the memory cell rows;
[0049] The two storage bit rows in each of the storage cell rows are respectively a first storage bit row and a second storage bit row, and performing erasure verification on the m-th erasure operation of each of the storage cell rows includes:
[0050] Step S0111: applying a turn-on voltage to a control gate line corresponding to a first storage bit row in each of the memory cell rows, and applying a check voltage to a control gate line corresponding to a second storage bit row in each of the memory cell rows, to obtain an erase verification result of the mth erase operation on the first storage bit row;
[0051] Step S0112: Apply a turn-on voltage to the control gate line corresponding to the second storage bit row in each of the memory cell rows, and apply a check voltage to the control gate line corresponding to the first storage bit row in each of the memory cell rows to obtain an erase verification result of the mth erase operation of the second storage bit row.
[0052] Specifically, in the operating method of the semiconductor device provided in the present application, the two storage bit rows in each of the storage cell rows are divided into a first storage bit row and a second storage bit row, and a conduction voltage and a check voltage are applied to the first storage bit row and the second storage bit row, respectively, to obtain an erase verification result of the mth erase operation of the first storage bit row, thereby clarifying whether each storage bit 21 in the first storage bit row is successfully erased. Then, a check voltage and a conduction voltage are applied to the first storage bit row and the second storage bit row, respectively, to obtain an erase verification result of the mth erase operation of the second storage bit row, thereby clarifying whether each storage bit 21 in the second storage bit row is successfully erased, so as to accurately apply a first voltage to the control gate line corresponding to the storage bit row that has been successfully erased, and apply a second voltage to the control gate line corresponding to the storage bit row that has failed to be erased, thereby avoiding the threshold voltage of each storage bit 21 in the storage bit row that has been successfully erased in the mth erase operation from moving further negatively in the (m+1)th erase operation, thereby improving the problem of widening the threshold voltage distribution of the storage bit 21, thereby improving the performance of the semiconductor device.
[0053] In some embodiments of the present application, the turn-on voltage is 3V to 5V; and the check voltage is 0V.
[0054] In some embodiments of the present application, the erasure verification of the mth erasure operation on each of the memory cell rows also includes: applying the turn-on voltage to the word line WL corresponding to each of the memory cell rows, and applying a fourth voltage (such as 0.6V) to the bit line corresponding to each of the memory cell rows.
[0055] In some embodiments of the present application, the control gate line corresponding to the first storage bit row is the first control gate line CGL1 , and the control gate line corresponding to the second storage bit row is the second control gate line CGL2 .
[0056] In some embodiments of the present application, the operating method of the semiconductor device further includes: latching, by a latch, an erase verification result of the mth erase operation on the successfully erased storage bit row. That is, the latch only latches the erase verification result of the mth erase operation on the successfully erased storage bit row, thereby minimizing the number of latch state bit flips.
[0057] Correspondingly, in some embodiments of the present application, the erasure verification result of the mth erasure operation of the storage bit row that is successfully latched by the latch includes: when it is determined that the storage bit row is successfully erased, the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row is set from the initial state bit to the first state bit.
[0058] In other embodiments of the present application, the operating method of the semiconductor device further includes: latching, by a latch, an erase verification result of the mth erase operation on the storage bit row that failed to be erased. That is, the latch only latches the erase verification result of the mth erase operation on the storage bit row that failed to be erased, thereby minimizing the number of state bit flips of the latch.
[0059] Correspondingly, in some embodiments of the present application, the erasure verification result of the mth erasure operation of the storage bit row that fails to be latched by the latch includes: when it is determined that the erasure of the storage bit row fails, the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row is set from the initial state bit to the first state bit.
[0060] In other embodiments of the present application, the operating method of the semiconductor device further includes: latching, by a latch, an erase verification result of the mth erase operation of each storage bit row. That is, the latch latches the erase verification results of the mth erase operation of the storage bit row for erase failure and erase success, respectively.
[0061] Correspondingly, in some embodiments of the present application, when it is determined that the storage bit row is erased successfully, the latch corresponding to the erase verification result of the mth erase operation of the storage bit 21 is set from the initial state bit to the first state bit; when it is determined that the storage bit row is erased unsuccessfully, the latch corresponding to the erase verification result of the mth erase operation of the storage bit row is set from the initial state bit to the second state bit.
[0062] In some embodiments of the present application, the semiconductor device further includes a control circuit CG Driver, and the m+1th erasing operation on the target erasure area A1 includes: the control circuit CG Driver applies a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applies a second voltage to the control gate line corresponding to the storage bit row that fails to be erased, according to the status bit of the latch.
[0063] In some embodiments of the present application, the control circuit CG Driver includes a control gate driver.
[0064] Combine Figure 1-Figure 3As shown, in a second aspect, an embodiment of the present application provides a semiconductor device, which includes: at least one memory cell row, each memory cell row including two memory bit rows, each memory cell row including at least one memory cell pair 11, each memory cell pair 11 including two memory bits 21, and the two memory bits 21 are respectively located in two adjacent memory bit rows; a plurality of control gate lines corresponding one-to-one to the plurality of memory bit rows, each of the control gate lines being electrically connected to each of the memory bits 21 in the corresponding memory bit row; an erase verification module M1 for performing erase verification on the mth erase operation of the target erase area A1 to obtain a verification result of the mth erase operation of the target erase area A1; a control circuit CG Driver for applying a first voltage to the control gate line corresponding to the successfully erased memory bit row and applying a second voltage to the control gate line corresponding to the failed erased memory bit row based on the verification result of the mth erase operation of the target erase area A1: at least one memory bit row is successfully erased and at least one memory bit row is failed to be erased.
[0065] The semiconductor device provided in the present application can effectively improve the problem of widening of the threshold voltage distribution of the storage bit 21 when the NORD memory performs an erase operation.
[0066] In some embodiments of the present application, the erasure verification module M1 includes the latch.
[0067] In the semiconductor device provided by the present application, the latch is used to latch the status bit of each storage bit row, so as to determine whether each storage bit row is successfully erased according to the status bit of each storage bit row after the erase verification operation is completed.
[0068] In some embodiments of the present application, the semiconductor device further includes: a word line driver WL Driver, for applying an electrical signal to the word line WL; a bit line driver BL Driver, for applying an electrical signal to the bit line; a sensitive amplifier SA, the sensitive amplifier SA is connected to the bit line, and is used to compare the current currently passing through the bit line with the standard current to determine whether each of the storage bit rows has been erased into place, and the erase verification module M1 is used to receive a signal indicating whether each of the storage bit rows has been erased into place, and can change the status bit of the latch according to the signal.
[0069] In summary, an embodiment of the present application provides a semiconductor device and an operating method thereof, which obtains a verification result of the m-th erasure operation of the memory cell pair by performing an erase verification on the m-th erase operation of two storage bits of at least one memory cell pair, wherein m is an integer greater than 0, and each of the memory bits corresponds to a control gate line, and the control gate line is connected to the corresponding memory bit; in response to the verification result of the m-th erase operation of the memory cell pair, a first voltage is applied to the control gate line corresponding to the successfully erased storage bit, and a second voltage is applied to the control gate line corresponding to the failed erased storage bit, so as to perform the m+1-th erase operation. The operating method of the semiconductor device can effectively improve the problem of widening of the threshold voltage distribution of the storage bits when the NORD memory performs an erase operation.
[0070] The semiconductor device and its operating method provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A method for operating a semiconductor device, characterized in that: The operating method of the semiconductor device comprises: Performing an erasure verification on an m-th erasure operation of two storage bits of at least one memory cell pair to obtain a verification result of the m-th erasure operation of the memory cell pair, wherein m is an integer greater than 0, each of the storage bits corresponds to a control gate line, and the control gate line is connected to the corresponding storage bit; In response to the verification result of the mth erasing operation of the memory cell pair, a first voltage is applied to the control gate line corresponding to the successfully erased storage bit, and a second voltage is applied to the control gate line corresponding to the failed erased storage bit to perform the (m+1)th erasing operation.
2. The method for operating a semiconductor device according to claim 1, wherein: The operating method of the semiconductor device comprises: Performing an erase verification on an m-th erase operation of a target erase area to obtain a verification result of the m-th erase operation of the target erase area, wherein the target erase area includes at least one memory cell row, each memory cell row includes two memory bit rows, each memory bit row corresponds to a control gate line, and the control gate line is connected to each memory bit in the corresponding memory bit row; In response to a verification result of the mth erasing operation on the target erasing area being: at least one storage bit row is successfully erased and at least one storage bit row is failed to be erased, performing an m+1th erasing operation on the target erasing area; The performing the (m+1)th erasing operation on the target erasing area includes applying a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applying a second voltage to the control gate line corresponding to the storage bit row that is failed to be erased.
3. The method for operating a semiconductor device according to claim 2, wherein: Each of the memory cell rows corresponds to a word line; The performing the (m+1)th erasing operation on the target erasing area includes applying a third voltage to the word line of the target erasing area, wherein the absolute value of the difference between the first voltage and the third voltage is smaller than the absolute value of the difference between the second voltage and the third voltage.
4. The method for operating a semiconductor device according to claim 2, wherein: When all storage bits in the storage bit row are successfully erased, it is determined that the storage bit row is successfully erased; when at least one storage bit in the storage bit row fails to be erased, it is determined that the storage bit row is failed to be erased.
5. The method for operating a semiconductor device according to claim 4, wherein: The operating method of the semiconductor device further comprises: performing an mth erasing operation on the target erasing area before performing erasing verification on the mth erasing operation on the target erasing area; wherein, When m=1, in response to the erase start signal, the target erase area is erased for the mth time; When m is greater than 1, in response to obtaining the verification result of the m-1th erasing operation on the target erasing area: at least one storage bit row is successfully erased and at least one storage bit row is failed to be erased, the target erasing area is subjected to the mth erasing operation.
6. The method for operating a semiconductor device according to claim 2, wherein: The performing erasure verification on the mth erasure operation of the target erasure area includes: performing erasure verification on the mth erasure operation of each of the memory cell rows in sequence to obtain an erasure verification result of the mth erasure operation of each of the memory bit rows in each of the memory cell rows; The two storage bit rows in each of the storage cell rows are respectively a first storage bit row and a second storage bit row, and performing erasure verification on the m-th erasure operation of each of the storage cell rows includes: Applying a conduction voltage to a control gate line corresponding to a first storage bit row in each of the memory cell rows, and applying a check voltage to a control gate line corresponding to a second storage bit row in each of the memory cell rows, so as to obtain an erase verification result of the mth erase operation of the first storage bit row; A turn-on voltage is applied to the control gate line corresponding to the second storage bit row in each of the memory cell rows, and a check voltage is applied to the control gate line corresponding to the first storage bit row in each of the memory cell rows to obtain an erase verification result of the mth erase operation of the second storage bit row.
7. The method for operating a semiconductor device according to claim 6, wherein: The operating method of the semiconductor device further includes: Latching the erasure verification result of the mth erasure operation of the successfully erased storage bit row by a latch; or, The erasure verification result of the mth erasure operation of the storage bit row that fails to be erased is latched by a latch.
8. The method for operating a semiconductor device according to claim 7, wherein: The latching the erasure verification result of the mth erasure operation of the storage bit row that is successfully erased by the latch comprises: when it is determined that the erasure of the storage bit row is successful, setting the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row from an initial state bit to a first state bit; The erasure verification result of the mth erasure operation of the storage bit row that fails to be erased is latched by the latch, including: when it is determined that the storage bit row fails to be erased, the latch corresponding to the erasure verification result of the mth erasure operation of the storage bit row is set from the initial state bit to the first state bit.
9. The method for operating a semiconductor device according to claim 6, wherein: The operating method of the semiconductor device further includes: latching an erasure verification result of the mth erasure operation of each storage bit row by a latch.
10. The method for operating a semiconductor device according to claim 9, wherein: The erasure verification result of the mth erasure operation of latching each of the storage bits by the latch includes: When it is determined that the storage bit row is erased successfully, the latch corresponding to the erase verification result of the mth erase operation of the storage bit is set from the initial state bit to the first state bit; when it is determined that the storage bit row is erased unsuccessfully, the latch corresponding to the erase verification result of the mth erase operation of the storage bit row is set from the initial state bit to the second state bit.
11. The method for operating a semiconductor device according to claim 8 or 10, wherein: The semiconductor device further includes a control circuit, and performing the (m+1)th erasing operation on the target erasing area includes: The control circuit applies a first voltage to the control gate line corresponding to the storage bit row that is successfully erased, and applies a second voltage to the control gate line corresponding to the storage bit row that is failed to be erased, according to the state bit of the latch.
12. A semiconductor device, characterized in that: The semiconductor device comprises: At least one memory cell row, each memory cell row including two memory bit rows, each memory cell row including at least one memory cell pair, each memory cell pair including two memory bits, the two memory bits being located in two adjacent memory bit rows respectively; a plurality of control gate lines corresponding one-to-one to the plurality of storage bit rows, each of the control gate lines being electrically connected to each of the storage bits in the corresponding storage bit row; an erasure verification module, configured to perform erasure verification on the mth erasure operation of the target erasure area and obtain a verification result of the mth erasure operation of the target erasure area; A control circuit applies a first voltage to a control gate line corresponding to a successfully erased storage bit row and applies a second voltage to a control gate line corresponding to a failed erased storage bit row, based on a verification result of the mth erase operation on the target erase area: at least one storage bit row is successfully erased and at least one storage bit row is failed to be erased.