Formation method of semiconductor structure, semiconductor structure and electronic device

Abstract

The invention discloses a semiconductor structure forming method, a semiconductor structure and an electronic device, and the method comprises the steps: forming a mask lamination layer on a substrate in a shape-preserving manner, the mask lamination layer comprises a mask layer and a mask protection layer located on the mask layer, and the thickness of the mask layer is greater than the depth of a zero layer mark located in a substrate of the substrate; forming a channel structure in a device region of the substrate by taking the mask lamination layer as a mask, and removing the mask lamination layer outside the zero layer mark in the process of forming the channel structure; and a zero-layer mark filling layer with the top surface flush with the top surface of the epitaxial layer on the substrate is formed on the mask layer positioned on the zero-layer mark under the protection of the mask protection layer on the mask layer, so that the planarization process of the zero-layer mark is completed in the process of forming the channel structure. According to the semiconductor structure and the manufacturing method thereof, additional backfilling and mechanical grinding treatment on the zero-layer mark before or after the channel structure is formed are avoided, the manufacturing process is simplified, damage to the substrate is avoided, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Art

[0002] As semiconductor device sizes continue to shrink, in order to reduce short-channel effects (SCE) and improve semiconductor device performance, semiconductor processes are gradually transitioning from planar MOSFETs to more efficient three-dimensional transistors, such as fin field-effect transistors (FinFETs). Compared to planar MOSFETs, the gate structure in FinFETs has better control over the channel and can effectively suppress short-channel effects.

[0003] At the same time, the shortening of device channel lengths has led to increasingly smaller device line widths. If well implantation is performed after fin formation, the smaller fin line widths are more susceptible to damage during the ion implantation process. Therefore, well implantation is typically performed on the substrate before fin formation. This fabrication process requires the formation of a zero mark in the substrate, which serves as an alignment mark for the photolithography process during the well implantation process.

[0004] Because the zero mark is a deep pit, if it is not backfilled and mechanically smoothed to a flat surface, it will form a complex sandwich structure during the subsequent active area film deposition process. The fin formation process will etch it into an uneven, bumpy structure, which is prone to harboring dirt and grime. The irregular residual film material is also prone to causing defects such as shedding. However, the planarization process for the zero mark in related technologies is not only complex and reduces the fabrication efficiency of the semiconductor structure, but also damages the substrate and the zero mark, thereby adversely affecting the performance of the semiconductor structure. Summary of the Invention

[0005] In order to solve the problems of the prior art, the embodiments of the present application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. The technical solution is as follows:

[0006] In one aspect, a method for forming a semiconductor structure is provided, comprising:

[0007] Providing a base, including a substrate and an epitaxial layer conformally formed on the substrate, wherein a zero layer mark is formed in the substrate, and the substrate includes a device area;

[0008] Conformally forming a mask stack on the substrate, the mask stack comprising a mask layer and a mask protection layer located on the mask layer, wherein the thickness of the mask layer is greater than the depth of the zero layer mark;

[0009] Using the mask stack as a mask, forming a channel structure in a device region of the substrate, the channel structure comprising a trench formed on the substrate and penetrating the epitaxial layer and a channel material layer formed in the trench;

[0010] In the process of forming the channel structure, the mask stack located outside the zero layer mark is removed, and the mask layer located at the zero layer mark forms a zero layer mark filling layer with a top surface flush with the top surface of the epitaxial layer under the protection of the mask protection layer.

[0011] In an exemplary embodiment, forming a channel structure in the device region of the substrate using the mask stack as a mask includes:

[0012] Using the mask stack as a mask, forming an initial trench exposing the substrate on the device region; the initial trench penetrates the mask stack and the epitaxial layer;

[0013] removing the mask protection layer outside the zero-layer mark area to expose a first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect a second portion of the mask layer;

[0014] performing a channel material forming process, wherein an initial channel material layer is formed in the initial trench during the channel material forming process, and the first portion of the mask layer is partially removed, so that a top surface of the remaining first portion is flush with a top surface of the second portion, and after the first portion is partially removed, the mask protection layer on the second portion is removed to expose the second portion of the mask layer;

[0015] Etching the exposed mask layer until the top surface of the mask layer located at the zero layer mark is flush with the top surface of the epitaxial layer, and the remaining mask layer located at the zero layer mark forms the zero layer mark filling layer;

[0016] The initial channel material layer is planarized.

[0017] In an exemplary embodiment, forming an initial trench exposing the substrate in the device region using the mask stack as a mask includes:

[0018] covering the mask stack with a first planarization layer;

[0019] forming an anti-reflection layer and a patterned photoresist layer in sequence on the first planarization layer, wherein the patterned photoresist layer has a pattern defining the groove, and the pattern is located above the device area;

[0020] etching the anti-reflection layer, the first planarization layer, the mask stack, and the epitaxial layer in sequence along the pattern of the grooves until the substrate is exposed;

[0021] The patterned photoresist layer and the remaining anti-reflective layer are removed.

[0022] In an exemplary embodiment, removing the mask protection layer outside the zero-layer mark area to expose the first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect the second portion of the mask layer includes:

[0023] Etching back the remaining first planarization layer to expose the mask protection layer outside the zero-layer mark area, and retaining a planarization material layer of a preset thickness in the zero-layer mark area;

[0024] Performing an etching process to remove the exposed mask protection layer to expose the covered first portion of the mask layer;

[0025] The planarization material layer is removed to expose the covered mask protection layer.

[0026] In an exemplary embodiment, removing the mask protection layer outside the zero-layer mark area to expose the first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect the second portion of the mask layer includes:

[0027] removing the remaining first planarization layer to expose the mask protection layer;

[0028] coating a second planarization layer on the mask protection layer;

[0029] Etching back the second planarization layer to expose the mask protection layer outside the zero layer mark area, and retaining a planarization material layer of a preset thickness in the zero layer mark area;

[0030] Performing an etching process to remove the exposed mask protection layer to expose the covered first portion of the mask layer;

[0031] The planarization material layer is removed to expose the covered mask protection layer.

[0032] In an exemplary embodiment, the thickness of the planarization material layer is greater than 100 angstroms.

[0033] In an exemplary embodiment, performing a channel material forming process includes:

[0034] Partially removing the first portion of the mask layer in a direction perpendicular to the substrate, so that a top surface of the remaining first portion is flush with a top surface of the second portion of the mask layer;

[0035] Filling an initial channel material layer in the initial trench, wherein a top surface of the initial channel material layer is higher than a top surface of the epitaxial layer;

[0036] The mask protection layer located on the second portion of the mask layer is removed to expose the second portion of the mask layer.

[0037] In an exemplary embodiment, performing a channel material forming process includes:

[0038] Filling an initial channel material layer in the initial trench, wherein a top surface of the initial channel material layer is higher than a top surface of the epitaxial layer;

[0039] Partially removing the first portion of the mask layer in a direction perpendicular to the substrate, so that a top surface of the remaining first portion is flush with a top surface of the second portion of the mask layer;

[0040] The mask protection layer located on the second portion of the mask layer is removed to expose the second portion of the mask layer.

[0041] In an exemplary embodiment, the partially removing the first portion of the mask layer in a direction perpendicular to the substrate includes:

[0042] A plasma etching process or a wet etching process is adopted to partially remove the first portion of the mask layer in a direction perpendicular to the substrate.

[0043] In an exemplary embodiment, the mask stack further includes a liner formed on the epitaxial layer, and the mask layer is located on the liner; and the planarizing process of the initial channel material layer includes:

[0044] planarizing the initial channel material layer, stopping at the liner;

[0045] The liner layer outside the zero layer mark is removed.

[0046] In an exemplary embodiment, the liner layer is formed of a material including silicon oxide, the mask layer is formed of a material including silicon nitride, and the mask protection layer is formed of a material including plasma-enhanced oxide.

[0047] In an exemplary embodiment, etching the exposed mask layer until the top surface of the mask layer located at the zero-layer mark is flush with the top surface of the epitaxial layer includes:

[0048] performing main etching on the exposed mask layer and stopping at the liner layer;

[0049] The remaining exposed mask layer is over-etched so that the top surface of the remaining mask layer on the zero-layer mark is flush with the top surface of the epitaxial layer, and the remaining mask layer forms the zero-layer mark filling layer.

[0050] In an exemplary embodiment, the main etching is performed by using a plasma etching process or a wet etching process, and the over etching is performed by using a plasma etching process or a wet etching process.

[0051] In an exemplary embodiment, the depth of the zero layer mark in the substrate is greater than 600 angstroms, and the thickness of the mask layer in the mask stack is greater than 650 angstroms.

[0052] In an exemplary embodiment, N-type conductive ions are implanted into the device region, a material forming the channel material layer includes silicon germanium, and the channel material layer is used to form a fin structure disposed on the device region.

[0053] In another aspect, a semiconductor structure is provided, formed using any of the aforementioned methods for forming a semiconductor structure, comprising:

[0054] a substrate having a zero layer mark formed therein, the substrate including a device area;

[0055] an epitaxial layer conformally formed on the substrate;

[0056] a trench located in the device region and penetrating the epitaxial layer;

[0057] a channel material layer located in the trench, wherein a top surface of the channel material layer is flush with a top surface of the epitaxial layer; the trench and the channel material layer constitute a channel structure;

[0058] A liner located inside the zero layer mark and a mask layer covering the liner, wherein the top surface of the mask layer is flush with the top surface of the epitaxial layer, and the mask layer covering the liner forms a zero layer mark filling layer.

[0059] In an exemplary embodiment, N-type conductive ions are implanted into the device region, a material forming the channel material layer includes silicon germanium, and the channel material layer is used to form a fin structure disposed on the device region.

[0060] In an exemplary embodiment, the liner layer is formed of a material including silicon oxide, and the mask layer is formed of a material including silicon nitride.

[0061] In an exemplary embodiment, the depth of the zero layer mark is greater than 600 angstroms.

[0062] On the other hand, an electronic device is provided, comprising a semiconductor structure formed by any one of the aforementioned methods for forming a semiconductor structure.

[0063] The embodiment of the present application forms a mask stack conformally on a substrate, wherein the mask stack includes a mask layer and a mask protection layer located on the mask layer, and the thickness of the mask layer is greater than the depth of the zero-layer mark located in the substrate of the substrate, and then forms a channel structure in the device area of ​​the substrate using the mask stack as a mask. During the formation of the channel structure, the mask stack located outside the zero-layer mark is removed, and the mask layer located at the zero-layer mark forms a zero-layer mark filling layer with a top surface flush with the top surface of the epitaxial layer on the substrate under the protection of the mask protection layer thereon, thereby achieving the simultaneous completion of the zero-layer mark flattening process during the channel structure formation process, avoiding additional backfilling and mechanical smoothing treatment of the zero-layer mark before or after the channel structure is formed, which not only simplifies the preparation process and improves the preparation efficiency of the semiconductor structure, but also avoids damage to the substrate and the zero-layer mark during the additional backfilling and mechanical smoothing treatment process, which is beneficial to improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0065] Figures 1a to 1d It is a cross-sectional view of a semiconductor structure during the formation process of a semiconductor structure in the prior art;

[0066] Figures 2a to 2d is a cross-sectional view of a semiconductor structure during another semiconductor structure formation process in the prior art;

[0067] Figures 3 to 14 is a structural cross-sectional view of a method for forming a semiconductor structure provided by an embodiment of the present application during the process of forming the semiconductor structure; DETAILED DESCRIPTION

[0068] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0069] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0071] Taking a fin field effect transistor as an example, the planarization process for the zero layer mark in the related art is described below in combination with a method for forming a semiconductor structure in the prior art.

[0072] See also Figures 1a to 1d , which shows a method for forming a semiconductor structure in the prior art. Specifically, Figure 1aAs shown, a substrate 110 having a zero layer mark 111 is provided, and an epitaxial layer 120 is conformally formed on the substrate 110; then, as shown in FIG. Figure 1b As shown, an oxide layer, a silicon nitride layer and a filling material layer are sequentially deposited in the zero-layer mark area; then, as shown Figure 1c As shown, chemical mechanical polishing of the zero-layer mark area is performed; then, as shown Figure 1d As shown, the oxide layer and silicon nitride layer in the zero-layer mark area are removed, and the filling material layer is retained. Then, the fin channel 130 is formed in the device area of ​​the substrate. During the formation of the fin channel 130, a covering mask layer is first formed on the epitaxial layer 120, and then the mask layer is used as a mask to perform trench etching of the fin channel 130, fill the trench with channel material, and then remove the remaining mask layer.

[0073] See also Figures 2a to 2d , which shows another method for forming a semiconductor structure in the prior art. Specifically, Figure 2a As shown, a substrate 210 having a zero layer mark 211 is provided, and an epitaxial layer 220 is conformally formed on the substrate 210; then, as shown in FIG. Figure 2b As shown, a fin channel 230 is formed in the device region of the substrate 210; after the fin channel 230 is formed, the following steps are performed. Figure 2c As shown, an oxide layer, a silicon nitride layer and a filling material layer are sequentially deposited in the zero-layer mark area; then, as shown Figure 2d , chemical mechanical polishing of the zero-layer mark area is performed, after which the oxide layer and silicon nitride layer of the zero-layer mark can be removed, leaving the filling material layer.

[0074] It can be seen that the planarization process for the zero-layer mark in the existing technology, whether it is placed before or after the fin channel is formed, involves relatively complex processes such as the deposition of three film layers and chemical mechanical polishing. Not only is the process complicated, which reduces the preparation efficiency of the semiconductor structure, but the chemical mechanical polishing process is also prone to damage the zero-layer mark, thereby affecting the accuracy of the overlay (OVL) of the subsequent process; in addition, the side digging in the subsequent silicon nitride layer etching process will cause the problem of uneven zero-layer mark interface, which in turn has an adverse effect on the performance of the prepared semiconductor structure.

[0075] In view of this, an embodiment of the present application provides a method for forming a semiconductor structure, by providing a substrate, the substrate including a substrate and an epitaxial layer formed conformally on the substrate, a zero layer mark formed in the substrate, and the substrate including a device area, then conformally forming a mask stack on the substrate, the mask stack including a mask layer and a mask protection layer located on the mask layer, and the thickness of the mask layer is greater than the depth of the zero layer mark, then using the mask stack as a mask to form a channel structure in the device area of ​​the substrate, during the formation of the channel structure, the mask stack located outside the zero layer mark is removed, and The mask layer located at the zero layer mark forms a zero layer mark filling layer whose top surface is flush with the top surface of the epitaxial layer on the substrate under the protection of the mask protection layer thereon, thereby realizing the simultaneous completion of the zero layer mark flattening process during the channel structure formation process, avoiding additional backfilling and mechanical polishing of the zero layer mark before or after the channel structure is formed, which not only simplifies the preparation process and improves the preparation efficiency of the semiconductor structure, but also avoids damage to the substrate and the zero layer mark during the additional backfilling and mechanical polishing process, thereby improving the performance of the semiconductor structure.

[0076] The following combination Figures 3 to 14 , the method for forming the semiconductor structure provided in the embodiment of the present application is described in detail.

[0077] See Figure 3 , providing a substrate 300.

[0078] The base 300 includes a substrate 310 and an epitaxial layer 320 conformally formed on the substrate 310 . A zero mark 311 is formed in the substrate 310 . The substrate 310 also has a device region 312 .

[0079] Specifically, the substrate 310 may be a bulk semiconductor or a silicon on insulator (SOI) substrate, etc., which may be doped (for example, doped with a p-type dopant or an n-type dopant) or undoped. The SOI substrate is a semiconductor material layer formed on an insulator layer, which may be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc., and the insulator layer is disposed on a silicon substrate or a glass substrate. In a specific implementation, the semiconductor material of the substrate 310 may include one or more of silicon, germanium, a compound semiconductor, and an alloy semiconductor, wherein the compound semiconductor may be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, and the alloy semiconductor may be one or more of silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenic phosphide.

[0080] A zero layer mark 311 is formed in the substrate 310, which serves as an alignment mark for subsequent photolithography alignment. The zero layer mark 311 is a groove extending from a surface of the substrate 310 to the interior of the substrate 310. Exemplarily, the depth of the zero layer mark 311 can be greater than 600 angstroms.

[0081] Among them, the number and position of the zero layer marks 311 within the substrate 310 can be set according to actual needs. For example, multiple zero layer marks 311 can be formed in the substrate 310. The multiple zero layer marks 311 can be dispersed and arranged on the surface of the substrate 310, or can be dispersed and arranged only in a partial area.

[0082] Conductive ions of a preset type are implanted into the device region 312 of the substrate 310 so that the device region 312 can serve as a well region of a corresponding transistor. In an embodiment of the present application, N-type conductive ions are implanted into the device region 312 so that the device region 312 is used to form a PMOS transistor; in other examples, the conductive ions implanted into the device region 312 can be P-type conductive ions so that the device region 312 is used to form an NMOS transistor. It is understood that the substrate 310 may include multiple device regions 312, and the multiple device regions 312 can be used to form different types of transistors, for example, a first type transistor and a second type transistor, the first type transistor can be an NMOS transistor, and the second type transistor can be a PMOS transistor. Exemplarily, the above-mentioned transistor can be a fin field-effect transistor.

[0083] The epitaxial layer 320 may be an epitaxial silicon layer.

[0084] In a specific implementation, the formation process of the base 300 can be: forming a photoresist layer (not shown in the figure) on the substrate 310; patterning the photoresist layer, and the opening of the patterned photoresist layer exposes the position for forming the zero layer mark 311; etching the substrate 310 with the patterned photoresist layer as a mask to form a groove, and the groove serves as the zero layer mark 311 for alignment in the subsequent photolithography process; removing the remaining photoresist layer; using the zero layer mark 311 as an alignment mark, performing well ion implantation based on the photolithography process to form a device area 312 in the substrate 310; conformally forming an epitaxial layer 320 on the side of the substrate 310 where the zero layer mark is formed, and the epitaxial layer 320 covers the side surface of the substrate 310 and conformally grows along the side wall and bottom wall of the zero layer mark 311, thereby retaining the shape characteristics of the zero layer mark 311 in the epitaxial layer 320.

[0085] In the embodiment of the present application, for the convenience of explanation, the region having the shape characteristics of the zero layer mark 311 and conformally formed on the corresponding zero layer mark 311 is referred to as a zero layer mark region.

[0086] See Figure 4A mask stack 330 is conformally formed on the substrate 300 . The mask stack 330 includes a mask layer 331 and a mask protection layer 332 located on the mask layer 331 . The thickness H1 of the mask layer 331 is greater than the depth H2 of the zero layer mark 311 .

[0087] Specifically, a mask layer 331 is formed on the epitaxial layer 320 of the substrate 300, conformally covering the epitaxial layer 320. To simultaneously planarize the zero-layer mark during the subsequent formation of the channel structure, the thickness H1 of the mask layer 331 needs to be greater than the depth H2 of the zero-layer mark. For example, if the depth H2 of the zero-layer mark is greater than 600 angstroms, the thickness H1 of the mask layer 331 is greater than 650 angstroms. Next, a mask protection layer 332 is formed on the mask layer 331, conformally covering the mask layer 331.

[0088] The mask layer 331 may be formed of silicon nitride, and the mask protection layer 332 may be formed of plasma-enhanced oxide (PEOX), such as plasma-enhanced silicon oxide. The mask layer 331 and the mask protection layer 332 may be formed sequentially using a chemical vapor deposition process.

[0089] In some exemplary embodiments, in order to avoid adverse effects on the substrate 300 in subsequent processes, such as Figure 4 As shown, the mask stack 330 may further include a liner 333. That is, before forming the mask layer 331, a liner 333 is first formed on the epitaxial layer 320 to conformally cover the epitaxial layer 320. Then, a conformally covering mask layer 331 and a mask protection layer 332 are sequentially formed on the liner 333. The liner 333 may be made of silicon oxide (e.g., SiO2) and may be formed by thermal growth or chemical vapor deposition (e.g., low-pressure chemical vapor deposition). Taking SiO2 as an example, the formation process may generally include furnace thermal oxidation, nitrogen doping, thermal annealing, and other steps. Si-N bonds are introduced into the SiO2 surface through ion implantation and thermal annealing, or through high-temperature furnace nitridation of the SiO2 surface and thermal annealing, thereby improving the reliability of the SiO2 and the bonding strength with the silicon nitride mask layer 331.

[0090] See Figure 5 Using the mask stack 330 as a mask, an initial trench 340 exposing the substrate 310 is formed on the device region 312 .

[0091] Among them, the initial trench 340 penetrates the mask stack 330 and the epitaxial layer 320, that is, the initial trench 340 can include a mask trench located in the mask stack 330 and a trench located in the epitaxial layer 320, and the trench located in the epitaxial layer 320 is subsequently used as a trench in the channel structure formed in the device area 312.

[0092] In some exemplary embodiments, the process of forming the initial trench 340 exposing the substrate 310 on the device region 312 may be as follows: Figures 6a to 6d shown.

[0093] See also Figure 6a , a first planarization layer 610 is covered on the mask stack 330 .

[0094] The first planarization layer 610 fills the zero-layer mark area and covers the top surface of the mask protection layer 332. The first planarization layer 610 may be formed of a spin-on carbon (SOC) material.

[0095] In a specific implementation, a chemical vapor deposition method or a physical vapor deposition method may be used to cover the mask stack 330 with the first planarization layer 610 . The first planarization layer 610 fills the zero-layer mark area and overflows to cover the upper surface of the mask protection layer 332 .

[0096] See also Figure 6b An anti-reflection layer 620 and a patterned photoresist layer 630 are sequentially formed on the first planarization layer 610 . The patterned photoresist layer 630 has a pattern defining a trench in a channel structure to be formed, and the pattern is located above the device region 312 .

[0097] The anti-reflection layer 620 may be formed of a Si-ARC (silicon-based anti-reflection coating) material. The Si-ARC material is rich in silicon, which helps to increase the hardness of the anti-reflection layer 620 and thus improve the accuracy of subsequent pattern transfer.

[0098] See also Figure 6c The anti-reflection layer 620 , the first planarization layer 610 , the mask stack 330 and the epitaxial layer 320 are sequentially etched along the pattern of the trenches until the substrate 310 is exposed.

[0099] In a specific implementation, the patterned photoresist 630 is used as an etching mask, and a dry etching process or a wet etching process is adopted to sequentially etch part of the anti-reflective layer 620, part of the first planarization layer 610, part of the mask stack 330 and part of the epitaxial layer 320 to expose the substrate 310, and an opening exposing the substrate 310 is formed on the device area 312 of the substrate 310.

[0100] See also Figure 6d , the patterned photoresist layer 630 and the remaining anti-reflective layer 620 are removed.

[0101] Specifically, an ashing process or a wet etching process may be used to remove the patterned photoresist layer 630 and the remaining anti-reflection layer 620 , thereby forming a through initial trench 340 in the mask stack 330 and the epitaxial layer 320 on the device region 312 of the substrate 310 .

[0102] It should be noted that, since a certain thickness of planarizing material layer is required in the subsequent process to protect part of the mask protection layer 332 in the zero-layer marking area, so that the part of the mask protection layer 332 can be used to protect the part of the mask layer 331 covered thereunder in the subsequent process, when removing the patterned resist layer 630 and the remaining anti-reflection layer 620, the remaining first planarizing layer 610 may also not be removed to further simplify the process; of course, when removing the patterned resist layer 630 and the remaining anti-reflection layer 620, the remaining first planarizing layer 610 may also be removed, and the subsequent process may re-apply the planarizing material layer when a certain thickness is required. The specific selection can be made according to the needs of the subsequent process, which will be explained in detail later in the embodiments of the present application.

[0103] See Figure 7 , remove the mask protection layer 332 outside the zero-layer mark area to expose the first portion 331a of the mask layer 331, and retain the mask protection layer 332b in the zero-layer mark area to protect the second portion 331b of the mask layer.

[0104] In a specific embodiment, Figure 6d As shown, the mask protection layer 332 has the remaining first planarization layer 610, then the mask protection layer 332a outside the zero layer mark area is removed, and the mask protection layer 332b in the zero layer mark area is retained. Figures 8a to 8c shown.

[0105] See also Figure 8a , the remaining first planarization layer 610 is etched back to expose the mask protection layer 332a outside the zero-layer mark area, and a planarization material layer 810 of a preset thickness is retained in the zero-layer mark area.

[0106] Since the planarization material layer 810 will be used to protect the portion of the mask protection layer 332b covered thereunder in the subsequent process, the retained preset thickness should not be too small, otherwise the purpose of protecting the portion of the mask protection layer 33b2 covered thereunder will not be achieved. At the same time, the retained preset thickness should not be too large, because a too large thickness will increase the difficulty of removal in the subsequent process. For example, the preset thickness of the planarization material layer 810 is greater than 100 angstroms.

[0107] See also Figure 8b , an etching process is performed to remove the exposed mask protection layer 332 a to expose the first portion 331 a of the covered mask layer 331 .

[0108] In this step, since the mask protection layer 332b in the zero-layer marking area is protected by the planarization material layer 810 of a preset thickness, when the exposed mask protection layer 332a is etched, the protected mask protection layer 332b will not be etched, so that only the first part 331a of the mask layer 331, that is, the mask layer covered by part of the mask protection layer 332a, is exposed, while the second part 332b of the mask layer 332, that is, the mask layer covered by part of the mask protection layer 332b, is not exposed.

[0109] Referring to FIG8 c , the planarization material layer 810 is removed to expose the covered mask protection layer 332 b .

[0110] By removing the planarization material layer 810 , the mask protection layer 332 b covered by the planarization material layer 810 can be exposed, so that the mask protection layer 332 b located in the zero-layer mark area can be used to protect the mask layer 331 b located in the zero-layer mark area from being etched when the exposed mask layer 331 a is subsequently etched.

[0111] The planarization material layer 810 may be removed by an ashing process or a wet removal process.

[0112] In another specific embodiment, when the patterned photoresist layer 630 and the remaining anti-reflective layer 620 are removed, the remaining first planarization layer 610 is also removed. Then, a second planarization layer (not shown in the figure) can be coated on the mask protection layer 332, thereby obtaining a similar Figure 6d The structural diagram shown in FIG. 1 , wherein the material of the second planarization layer can be a spin-on carbon SOC material; then similarly Figure 8a , the second planarization layer can be etched back to expose the mask protection layer 332a outside the zero-layer mark area, and retain a planarization material layer of a preset thickness in the zero-layer mark area; then similarly Figure 8b , an etching process may be performed to remove the exposed mask protection layer 332a to expose the first portion 331a of the covered mask layer; and then similarly Figure 8c , the planarization material layer is removed to expose the covered mask protection layer 332b.

[0113] See Figure 9 , a channel material formation process is performed, during which the initial channel material layer 341 is filled in the initial trench 340, and the first portion 331a of the mask layer is partially removed, and the top surface of the remaining first portion 331a is flush with the top surface of the second portion 331b. After the first portion 331a is partially removed, the mask protection layer 332b on the second portion 331b is removed to expose the second portion 331b of the mask layer 331.

[0114] In the embodiment of the present application, the mask layer 311 is etched for the first time during the channel material formation process. Specifically, because a portion of the mask protection layer 332b is retained on the mask layer located in the zero-layer mark area, i.e., the second portion 331b of the mask layer, when the first etching partially removes the first portion 331a of the mask layer, the second portion 331b of the mask layer located in the zero-layer mark area is not damaged and is retained. After the first etching partially removes the first portion 331a of the mask layer, the mask protection layer 332b on the second portion 331b is removed. This can expose the mask layer in the zero-layer mark area, i.e., the second portion 331b of the mask layer, i.e., expose the entire remaining mask layer, thereby preparing for the subsequent second etching of the mask layer to form a zero-layer mark filling layer whose top surface is flush with the top surface of the epitaxial layer 320.

[0115] In the embodiment of the present application, when performing the channel material formation process, the initial channel material layer 341 may be formed before partially removing the first portion 331 a of the mask layer, or after partially removing the first portion 331 of the mask layer.

[0116] Based on this, in some specific embodiments, the channel material forming process can be performed as follows: Figures 10a to 10b shown.

[0117] See also Figure 10a , the first portion 331 a of the mask layer is partially removed in a direction perpendicular to the substrate 300 , so that the top surface of the remaining first portion 331 a is flush with the top surface of the second portion 331 b of the mask layer.

[0118] Specifically, the mask layer 331 can be etched in a direction perpendicular to the substrate 300. Since the second part 331b of the mask layer is protected by the remaining mask protection layer 332b, only the first part 331a of the mask layer will be etched. When the top surface of the remaining first part 331a is flush with the bottom outer side of the remaining mask protection layer 332b, it indicates that the top surface of the remaining first part 331a is flush with the top surface of the second part 331b, and the etching is stopped at this time.

[0119] In a specific implementation, a plasma etching process or a wet etching process may be used to partially remove the first portion 331 a .

[0120] The wet etching process may adopt phosphoric acid (HPO) wet etching.

[0121] Among them, the plasma etching process can adopt a radical surface treatment (RST) process with a high etching selectivity of silicon nitride to silicon oxide / silicon. The RST process not only has a higher etching selectivity, but also causes less damage to silicon and is easier to precisely control, which is beneficial to improving the performance of semiconductor structures. Among them, the radicals can include, for example, fluorine radicals, fluorine-containing radicals, hydrated radicals, nitrogen / hydrogen radicals, hydrogen sulfide radicals, and / or a gas mixture of another gas to generate radicals. The radicals can be generated using plasma, and the plasma can include nitrogen-based (N2) plasma, hydrogen-based (H2) plasma, argon-based (Ar) plasma, and / or another type of plasma. The plasma can be generated by inductive coupling, capacitive coupling, transformer coupling, and / or another plasma generation technique.

[0122] Specifically, when the material of the mask layer 330 is silicon nitride, the etching selectivity of the RST process for silicon nitride can reach 56.6, which is much higher than the etching selectivity of 1.0 for silicon. Taking the radicals including hydrogen radical H* and fluorine radical F* as an example, the etching of silicon nitride using the RST process involves the following chemical reactions:

[0123] Si3N4 + 12H* + 12F* → 3SiF4 + 4NH3;

[0124] SiF4 + 2HF + 2NH3 → (NH4)2SiF6;

[0125] Among them, the silicon nitride in the mask layer reacts with hydrogen radicals and fluorine radicals to generate ammonia gas and gaseous by-product silicon tetrafluoride. Then, the silicon tetrafluoride reacts with ammonia gas and hydrogen fluoride gas to generate by-product ammonium hexafluorosilicate (NH4)2SiF6, and the ammonium hexafluorosilicate is further peeled off under the bombardment of radicals.

[0126] See Figure 10b , an initial channel material layer 341 is filled in the initial trench, and the top surface of the initial channel material layer 341 is higher than the top surface of the epitaxial layer 320.

[0127] In some examples, the device region 312 is used to form a PMOS transistor, and the material of the initial channel material layer 341 is a semiconductor material containing germanium, such as silicon germanium Si 1-x Ge x , where the molar ratio of Ge atoms can be less than 60% (x < 0.6), for example, in Si 1- x Ge x , the molar ratio of Ge atoms can be between 40% and 50% (0.4 < x < 0.5), so as to improve the carrier mobility of the PMOS transistor.

[0128] In a specific implementation, an epitaxial growth process can be used to epitaxially grow a channel material in the initial trench to form an initial channel material layer 341. Taking silicon germanium as an example, before growing the silicon germanium channel layer by the epitaxial growth process, SiCoNi is usually used to pre-clean the surface to remove the natural silicon oxide layer on the surface to ensure the size and morphology of the subsequently formed silicon germanium channel layer. During the SiCoNi process, the mask protection layer 332b located on the second portion 331b can be partially or completely removed.

[0129] Next, the mask protection layer 332b on the second portion 331b of the mask layer is removed to expose the second portion 331b of the mask layer, thereby forming the aforementioned Figure 9 The structural cross-section view shown.

[0130] In a specific implementation, during the process of forming the initial trench material layer 341, the mask protection layer 332b located on the second part 331b of the mask layer can be partially or completely removed. If it is partially removed, the remaining part can be removed again to completely remove the mask protection layer 332b located on the second part 331b of the mask layer, exposing the covered second part 331b of the mask layer.

[0131] In some other specific embodiments, the channel material forming process may be performed as follows: Figures 11a to 11b shown.

[0132] See also Figure 11a , an initial channel material layer 341 is filled in the initial trench, and a top surface of the initial channel material layer 341 is higher than a top surface of the epitaxial layer 320 .

[0133] See next Figure 11b , the first portion 331 a of the mask layer is partially removed in a direction perpendicular to the substrate 300 , so that the top surface of the remaining first portion 331 a is flush with the top surface of the second portion 331 b of the mask layer.

[0134] Next, the mask protection layer 332b located on the second portion 331b of the mask layer is removed to expose the second portion 331b of the mask layer, thereby forming the aforementioned Figure 9 The structural cross-section view shown.

[0135] The mask protection layer 332b located on the second portion 331b of the mask layer may be removed by using a dry etching process or a wet etching process.

[0136] See Figure 12 The exposed mask layer is etched until the top surface of the mask layer at the zero layer mark 111 is flush with the top surface of the epitaxial layer 320 , and the remaining unetched mask layer at the zero layer mark 111 forms a zero layer mark filling layer 1210 .

[0137] After the remaining mask layer is completely exposed, the exposed mask layer is etched a second time until the top surface of the mask layer at the zero layer mark 111 is flush with the top surface of the epitaxial layer 320 , thereby forming a zero layer mark filling layer 1210 at the zero layer mark 11 .

[0138] In some exemplary embodiments, when etching the exposed mask layer until the top surface of the mask layer located at the zero layer mark is flush with the top surface of the epitaxial layer, the following steps may be performed: main etching is performed on the exposed mask layer 331 and stopped at the liner 333; over etching is performed on the remaining exposed mask layer 331 so that the top surface of the remaining mask layer on the zero layer mark 111 is flush with the top surface of the epitaxial layer 320.

[0139] Specifically, the main etching process may be performed by using a plasma etching process or a wet etching process. The plasma etching process may be a free radical surface treatment RST process, and the wet etching process may be a phosphoric acid (HPO) wet etching process.

[0140] Specifically, a plasma etching process or a wet etching process can be used for over-etching. The plasma etching process can be a free radical surface treatment (RST) process, and the wet etching process can be a phosphoric acid (HPO) wet etching process. For example, the RST process can be used for main etching, and the phosphoric acid wet etching can be used for over-etching.

[0141] See Figure 13 , the initial channel material layer 341 is planarized.

[0142] Specifically, the initial channel material layer 341 can be planarized to remove the portion of the initial channel material layer 341 located above the epitaxial layer 320, and the remaining initial channel material layer 341 fills the groove 1310 on the epitaxial layer 320, and the top surface of the remaining initial channel material layer 341 is flush with the top surface of the epitaxial layer 320. The remaining initial channel material layer 341 can be referred to as the channel material layer 1320, and the channel material layer 1320 and the groove 1310 constitute the channel structure 1330 of an embodiment of the present application.

[0143] In some exemplary embodiments, the channel material layer 1320 is used to form a fin structure disposed on the device region 132 , thereby forming a fin field-effect transistor.

[0144] In some exemplary embodiments, the planarization process for the initial channel material layer 341 may be performed as follows: Figure 14 As shown, the initial channel material layer 341 is planarized and stops at the liner 333 .

[0145] Specifically, a chemical mechanical polishing process may be used to planarize the initial channel material layer 341 and stop at the liner 333 , thereby removing excess initial channel material layer on the liner 333 .

[0146] Next, the liner 333 outside the zero layer mark 111 is removed, so that the above-mentioned Figure 13 The structural cross-section view shown.

[0147] Specifically, a dry etching process or a wet etching process can be used to remove the liner 333 outside the zero layer mark 111, thereby retaining the liner 333 located at the zero layer mark 111, and the liner 333 located at the zero layer mark 111 is covered by the zero layer mark filling layer 1210.

[0148] The embodiment of the present application utilizes a zero-layer mark filling and a mask stack similar to that used to form a channel structure, and realizes protection of the mask layer in the zero-layer mark area through the channel structure formation process. Further, by adjusting the thickness of the mask layer (such as the silicon nitride layer) and the specific two-step mask layer etching method, the zero-layer mark flattening process is finally achieved during the channel structure formation process, thereby avoiding the additional cumbersome zero-layer mark filling, zero-layer mark mechanical polishing and zero-layer mark area oxide layer / silicon nitride layer removal processes, greatly simplifying the semiconductor structure formation process, improving the preparation efficiency of the semiconductor structure, and avoiding damage to the zero-layer mark during the additional backfilling and mechanical polishing process, thereby improving the performance of the semiconductor structure.

[0149] The present application also provides a semiconductor structure formed based on the aforementioned formation method, the semiconductor structure comprising:

[0150] a substrate having a zero layer mark formed therein and including a device region;

[0151] an epitaxial layer conformally formed on a substrate;

[0152] A trench located on the device region and penetrating the epitaxial layer;

[0153] a channel material layer located in the trench, wherein a top surface of the channel material layer is flush with a top surface of the epitaxial layer; the trench and the channel material layer constitute a channel structure;

[0154] A liner located inside the zero layer mark and a mask layer covering the liner, wherein the top surface of the mask layer is flush with the top surface of the epitaxial layer, and the mask layer covering the liner forms a zero layer mark filling layer.

[0155] In some exemplary embodiments, N-type conductive ions are implanted into the device region of the substrate, the channel material layer is formed of a material including silicon germanium, and the channel material layer is used to form a fin structure disposed on the device region.

[0156] In some exemplary embodiments, the liner layer is formed of a material including silicon oxide, and the mask layer is formed of a material including silicon nitride.

[0157] In some exemplary embodiments, the depth of the zero layer mark is greater than 600 angstroms.

[0158] The semiconductor structure of the embodiment of the present application completes the planarization process of the zero layer mark while forming the channel structure. Since it avoids the additional tedious processes of zero layer mark filling, zero layer mark mechanical polishing, and zero layer mark area oxide layer / silicon nitride layer removal, it can avoid damage to the zero layer mark during the additional backfilling and mechanical polishing process, thereby improving the performance of the semiconductor structure.

[0159] Correspondingly, an embodiment of the present application further provides an electronic device, which includes any one of the aforementioned semiconductor structures in the embodiment of the present application.

[0160] Because semiconductor structures have superior performance, the electronic device employing such a semiconductor structure correspondingly improves the performance of the electronic device. The electronic device may be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, camera, camcorder, voice recorder, MP3, MP4, PSP, or the like. It may also be an intermediate product incorporating the semiconductor structure, such as a device motherboard incorporating the semiconductor device.

[0161] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a base, including a substrate and an epitaxial layer conformally formed on the substrate, wherein a zero layer mark is formed in the substrate, and the substrate includes a device area; Conformally forming a mask stack on the substrate, the mask stack comprising a mask layer and a mask protection layer located on the mask layer, wherein the thickness of the mask layer is greater than the depth of the zero layer mark; Using the mask stack as a mask, forming a channel structure in a device region of the substrate, the channel structure comprising a trench formed on the substrate and penetrating the epitaxial layer and a channel material layer formed in the trench; In the process of forming the channel structure, the mask stack located outside the zero layer mark is removed, and the mask layer located at the zero layer mark forms a zero layer mark filling layer with a top surface flush with the top surface of the epitaxial layer under the protection of the mask protection layer.

2. The forming method according to claim 1, wherein: The forming of a channel structure in the device region of the substrate using the mask stack as a mask comprises: Using the mask stack as a mask, forming an initial trench exposing the substrate on the device region; the initial trench penetrates the mask stack and the epitaxial layer; removing the mask protection layer outside the zero-layer mark area to expose a first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect a second portion of the mask layer; performing a channel material forming process, wherein an initial channel material layer is formed in the initial trench during the channel material forming process, and the first portion of the mask layer is partially removed, so that a top surface of the remaining first portion is flush with a top surface of the second portion, and after the first portion is partially removed, the mask protection layer on the second portion is removed to expose the second portion of the mask layer; Etching the exposed mask layer until the top surface of the mask layer located at the zero layer mark is flush with the top surface of the epitaxial layer, and the remaining mask layer located at the zero layer mark forms the zero layer mark filling layer; The initial channel material layer is planarized.

3. The forming method according to claim 2, wherein: The forming of an initial trench exposing the substrate in the device region using the mask stack as a mask comprises: covering the mask stack with a first planarization layer; forming an anti-reflection layer and a patterned photoresist layer in sequence on the first planarization layer, wherein the patterned photoresist layer has a pattern defining the groove, and the pattern is located above the device area; etching the anti-reflection layer, the first planarization layer, the mask stack, and the epitaxial layer in sequence along the pattern of the grooves until the substrate is exposed; The patterned photoresist layer and the remaining anti-reflective layer are removed.

4. The forming method according to claim 3, wherein: The removing of the mask protection layer outside the zero-layer mark area to expose the first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect the second portion of the mask layer includes: Etching back the remaining first planarization layer to expose the mask protection layer outside the zero-layer mark area, and retaining a planarization material layer of a preset thickness in the zero-layer mark area; Performing an etching process to remove the exposed mask protection layer to expose the covered first portion of the mask layer; The planarization material layer is removed to expose the covered mask protection layer.

5. The forming method according to claim 3, wherein: The removing of the mask protection layer outside the zero-layer mark area to expose the first portion of the mask layer, and retaining the mask protection layer in the zero-layer mark area to protect the second portion of the mask layer includes: removing the remaining first planarization layer to expose the mask protection layer; coating a second planarization layer on the mask protection layer; Etching back the second planarization layer to expose the mask protection layer outside the zero layer mark area, and retaining a planarization material layer of a preset thickness in the zero layer mark area; Performing an etching process to remove the exposed mask protection layer to expose the covered first portion of the mask layer; The planarization material layer is removed to expose the covered mask protection layer.

6. The forming method according to claim 4 or 5, characterized in that: The thickness of the planarization material layer is greater than 100 angstroms.

7. The forming method according to claim 2, wherein: The performing of the channel material forming process comprises: Partially removing the first portion of the mask layer in a direction perpendicular to the substrate, so that a top surface of the remaining first portion is flush with a top surface of the second portion of the mask layer; Filling an initial channel material layer in the initial trench, wherein a top surface of the initial channel material layer is higher than a top surface of the epitaxial layer; The mask protection layer located on the second portion of the mask layer is removed to expose the second portion of the mask layer.

8. The forming method according to claim 2, wherein: The performing of the channel material forming process comprises: Filling an initial channel material layer in the initial trench, wherein a top surface of the initial channel material layer is higher than a top surface of the epitaxial layer; Partially removing the first portion of the mask layer in a direction perpendicular to the substrate, so that a top surface of the remaining first portion is flush with a top surface of the second portion of the mask layer; The mask protection layer located on the second portion of the mask layer is removed to expose the second portion of the mask layer.

9. The forming method according to claim 7 or 8, characterized in that: Partially removing the first portion of the mask layer in a direction perpendicular to the substrate includes: A plasma etching process or a wet etching process is adopted to partially remove the first portion of the mask layer in a direction perpendicular to the substrate.

10. The forming method according to claim 2, wherein: The mask stack further includes a liner formed on the epitaxial layer, and the mask layer is located on the liner; the planarizing process of the initial channel material layer includes: planarizing the initial channel material layer, stopping at the liner; The liner layer outside the zero layer mark is removed.

11. The forming method according to claim 10, wherein: The liner layer is formed of a material comprising silicon oxide, the mask layer is formed of a material comprising silicon nitride, and the mask protection layer is formed of a material comprising plasma-enhanced oxide.

12. The forming method according to claim 10, wherein: The etching process of the exposed mask layer until the top surface of the mask layer located at the zero layer mark is flush with the top surface of the epitaxial layer comprises: performing main etching on the exposed mask layer and stopping at the liner layer; The remaining exposed mask layer is over-etched so that the top surface of the remaining mask layer on the zero-layer mark is flush with the top surface of the epitaxial layer, and the remaining mask layer forms the zero-layer mark filling layer.

13. The forming method according to claim 12, wherein: The main etching is performed by adopting a plasma etching process or a wet etching process, and the over etching is performed by adopting a plasma etching process or a wet etching process.

14. The forming method according to claim 1, wherein: The depth of the zero layer mark in the substrate is greater than 600 angstroms, and the thickness of the mask layer in the mask stack is greater than 650 angstroms.

15. The forming method according to claim 1, wherein: N-type conductive ions are implanted into the device region. The channel material layer is formed of germanium silicon. The channel material layer is used to form a fin structure disposed on the device region.

16. A semiconductor structure, characterized in that Formed by any forming method as claimed in claim 1-15, comprising: a substrate having a zero layer mark formed therein, the substrate including a device area; an epitaxial layer conformally formed on the substrate; a trench located in the device region and penetrating the epitaxial layer; a channel material layer located in the trench, wherein a top surface of the channel material layer is flush with a top surface of the epitaxial layer; the trench and the channel material layer constitute a channel structure; A liner located inside the zero layer mark and a mask layer covering the liner, wherein the top surface of the mask layer is flush with the top surface of the epitaxial layer, and the mask layer covering the liner forms a zero layer mark filling layer.

17. The forming method according to claim 16, wherein: N-type conductive ions are implanted into the device region. The channel material layer is formed of germanium silicon. The channel material layer is used to form a fin structure disposed on the device region.

18. The forming method according to claim 16, wherein: The liner layer is formed of a material including silicon oxide, and the mask layer is formed of a material including silicon nitride.

19. The forming method according to claim 16, wherein: The depth of the zero layer mark is greater than 600 angstroms.

20. An electronic device, characterized in that: The electronic device includes a semiconductor structure formed by the forming method according to any one of claims 1 to 15 .

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