Three-dimensional gradient heat dissipation structure and its preparation method

Abstract

This invention provides a three-dimensional gradient heat dissipation structure and its fabrication method. The three-dimensional gradient heat dissipation structure of this invention includes: a chip; an interposer layer on which the chip is flip-chip mounted; heat sinks disposed within the interposer layer, one end of which extends to the side of the interposer layer near the chip and is coupled to the chip, and the other end of which extends to the side of the interposer layer away from the chip; and a manifold cover plate disposed on the side of the interposer layer away from the chip. Microchannels are formed within the manifold cover plate and are connected to the ends of the heat sinks away from the chip. An interface layer is disposed between the interposer layer and the manifold cover plate. By embedding the heat sinks, interface layer, and manifold cover plate synergistically, a three-dimensional heat transfer network is constructed, effectively improving heat dissipation efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more specifically, to a three-dimensional gradient heat dissipation structure and its fabrication method. Background Technology

[0002] As the semiconductor industry rapidly evolves towards high-density integration and high-performance computing, advanced packaging technologies such as 2.5D / 3D IC packaging, system-in-package (SiP), and chiplets integrate computing and storage functional units at high density through chip stacking and heterogeneous integration. While improving packaging density and high-performance computing, these technologies face severe heat dissipation challenges. These challenges are mainly reflected in the following three aspects.

[0003] I. Inefficient thermal paths lead to a surge in thermal resistance. Traditional packaging relies on printed circuit boards (PCBs) as the primary heat dissipation carrier. However, the core material of the substrate, epoxy resin, has a thermal conductivity of approximately 15 W / mK, which is orders of magnitude different from that of the chip (silicon, 148 W / mK) and the metal interconnect layer (copper, 401 W / mK), resulting in excessively high interface thermal resistance. Taking a typical flip-chip ball grid array (FCBGA) package as an example, heat must pass sequentially through the chip's active layer → thermal interface material (TIM) → heat sink → PCB → external heat sink. The cumulative thermal resistance at each interface leads to a total thermal efficiency loss of over 40%, and even a vicious cycle where the chip generates heat easily but dissipates it poorly.

[0004] Second, uneven heat density distribution leads to localized overheating. When a multi-chip module (MCM) is operating, the heat flux density of different functional units varies significantly. For example, the heat flux density in areas such as the GPU core and high-speed interfaces can exceed 500 W / cm² (more than five times that of the surrounding areas), easily forming localized hot spots. Traditional homogeneous heat dissipation materials (such as copper and aluminum) cannot achieve directional heat dissipation, causing a sharp rise in junction temperature in the hot spot areas (exceeding 125 ℃ in some areas). This not only degrades chip performance but also accelerates material aging and shortens package lifespan.

[0005] Third, the conflict between miniaturization and heat dissipation efficiency has become increasingly prominent. In everyday consumer electronics (such as AR glasses and foldable phones) and automotive electronics, the packaging thickness requirement has been reduced to below 1.2 mm. However, traditional heat dissipation structures (such as metal heat sinks and heat pipes) require at least 0.5 mm of space, making it difficult to achieve both space utilization and heat dissipation efficiency. For example, data from a 3DIC packaging project shows that the additional metal heat sink layer added to meet heat dissipation requirements directly resulted in the overall thickness exceeding the standard by 25%, making it impossible to pass the size verification of the end product.

[0006] To address these issues, the industry has attempted various improvement solutions. For example, the top-heating technology used in the AOS GTPAK package improves heat dissipation efficiency by exposing the drain pad, reducing thermal resistance by 30% compared to traditional TOLL packaging. However, it is only suitable for discrete power devices and cannot adapt to the complex thermal networks of interposers and chip stacks in 2.5D / 3D packages. Double-sided heat dissipation structures establish heat dissipation channels on both sides of the metal substrate, improving heat dissipation capacity by 50% compared to single-sided structures. However, this requires a redesigned packaging architecture, has poor compatibility with existing production lines, and increases costs by 40%. High thermal conductivity TIM materials reduce thermal resistance by 60% compared to traditional TIM adhesives (<10 W / mK), but rely on vacuum reflow soldering and strict gold plating processes, resulting in a mass production yield of less than 70%, hindering large-scale application. Micro-groove heat sinks improve efficiency by increasing the heat dissipation area by 30%, but the trench structure reduces TIM usage, exacerbating stress concentration and doubling the failure risk in reliability testing. Therefore, existing technologies cannot simultaneously solve the problems of high thermal resistance, concentrated hot spots, and limited space in the package. Summary of the Invention

[0007] In view of the problems existing in the packaging in the prior art described above, this application provides a three-dimensional gradient heat dissipation structure and its preparation method to solve the problems of high thermal resistance, concentrated hot spots and limited space in the packaging that cannot be solved simultaneously in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a three-dimensional gradient heat dissipation structure, comprising: a chip; an interposer layer on which the chip is flip-chip disposed; a heat sink disposed within the interposer layer, one end of which extends to the side of the interposer layer near the chip and is coupled to the chip, and the other end of which extends to the side of the interposer layer away from the chip; and a manifold cover disposed on the side of the interposer layer away from the chip, wherein a microchannel is formed within the manifold cover, and the microchannel is connected to the end of the heat sink away from the chip.

[0009] Optionally, an interface layer is provided between the intermediary layer and the manifold cover.

[0010] Optionally, the thermal conductivity of the interface layer gradually increases from the intermediate layer toward the manifold cover.

[0011] Optionally, the interface layer is composed of 60%-80% silver flakes, 20%-40% epoxy resin, and 5%-15% graphene.

[0012] Optionally, the heat dissipation column comprises a tungsten-copper-silver alloy material, which is composed of 40%-60% tungsten skeleton, 30%-60% copper-silver alloy and 5%-15% graphene.

[0013] Optionally, a groove is formed on the side of the manifold cover away from the chip.

[0014] Optionally, the cross-sectional shape of the trench is trapezoidal, the heat conduction direction from the chip to the manifold cover is defined as the vertical direction, and the plane passing through the center of the trench along the vertical direction is the cross-section.

[0015] Optionally, the inner wall of the trench is formed with a protective coating.

[0016] Optionally, a barrier layer may also be included, located around the heat dissipation column near the interlayer.

[0017] Optionally, it further includes: a filler layer, a first filler layer located between the interposer layer and the manifold cover, and a second filler layer located between the chip and the interposer layer.

[0018] This application also provides a method for fabricating a three-dimensional gradient heat dissipation structure, comprising the following steps: providing an interposer layer, etching blind vias on the interposer layer; filling the blind vias with a composite material to form heat dissipation pillars; bonding a flip chip to one side of the interposer layer to fabricate a manifold cover plate, forming microchannels within the manifold cover plate; and bonding the manifold cover plate to the side of the interposer layer away from the chip.

[0019] Optionally, before bonding the manifold cover to the side of the interposer layer away from the chip, an interface layer is further formed on the side of the interposer layer away from the chip, the interface layer being located before the interposer layer and the manifold cover.

[0020] Optionally, fabricating the manifold cover also includes forming a groove on the side of the manifold cover away from the chip.

[0021] Optionally, after etching a blind via on the intermediate layer, the process further includes depositing a barrier layer within the sidewalls of the blind via.

[0022] As described above, the three-dimensional gradient heat dissipation structure and its preparation method provided by the present invention have at least the following beneficial technical effects: by embedding heat dissipation columns, interface layers, and manifold cover plates in synergy, a three-dimensional heat transfer network is constructed, which greatly improves heat dissipation efficiency; the heat dissipation columns are made of tungsten-copper-silver composite material, which combines the high strength of tungsten, the excellent thermal conductivity of copper and silver, and the low interfacial thermal resistance of graphene, thereby improving heat transfer efficiency while reducing production costs; the heat dissipation columns, interface layers, and microchannels are designed with a non-uniform distribution, with a relatively dense distribution in high-density areas and a relatively uniform distribution in low-density areas, which is a targeted distribution that effectively and quickly dissipates heat. Attached Figure Description

[0023] Figure 1 The diagram shown is a schematic of the three-dimensional gradient heat dissipation structure provided by the present invention.

[0024] Figure 2 The diagram shows a structure in which a blind hole is formed on the intermediate layer.

[0025] Figure 3 The diagram shows a structure in which heat dissipation pillars are formed on the interlayer.

[0026] Figure 4 The diagram shows the structure that forms the interface layer.

[0027] Figure 5 The diagram shows a structural schematic for manufacturing a manifold cover.

[0028] Reference numerals: 1. Chip; 11. Logic chip; 12. Memory chip; 13. Microbump; 2. Interposer layer; 201. Blind via; 3. Heat sink; 31. Barrier layer; 4. Manifold cover; 5. Microchannel; 6. Trench; 61. Protective coating; 7. Interface layer; 71. Silver paste layer; 72. Indium-based thin film; 81. First filler layer; 82. Second filler layer. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0031] Example 1

[0032] This embodiment provides a three-dimensional gradient heat dissipation structure, such as Figure 1 As shown, the three-dimensional gradient heat dissipation structure of this embodiment includes a chip 1, an interposer layer 2, heat sinks 3, and a manifold cover plate 4. The chip 1 is flip-chip mounted on the interposer layer 2. The heat sinks 3 are disposed within the interposer layer 2. One end of the heat sinks 3 extends to the side of the interposer layer 2 near the chip 1 and is coupled to the chip 1. The other end of the heat sinks 3 extends towards the side of the interposer layer 2 away from the chip 1. The manifold cover plate 4 is disposed on the side of the interposer layer 2 away from the chip 1. A microchannel 5 is formed within the manifold cover plate 4. The microchannel 5 is disposed opposite to the end of the heat sinks 3 away from the chip 1.

[0033] like Figure 1 As shown, chip 1 is a flip chip, with dimensions ranging from 5×5 mm to 20×20 mm, which can be flexibly selected according to integration requirements. Optionally, chip 1 is provided with microbumps 13, which are distributed in an array. Specifically, the diameter of the microbumps 13 is between 30-80 μm, and the distance between two adjacent microbumps 13 is 50-150 μm. The microbumps 13 enable communication between chip 1 and the interposer layer 2. Specifically, the interposer layer 2 includes silicon substrates, organic substrates, and composite substrates, etc. Generally, the dimensions of the interposer layer 2 are designed according to the actual scenario, with a length and width between 40×60 mm and 100×100 mm, and a thickness between 50-300 μm. Generally, multiple chips 1 are disposed on one interposer layer 2. Specifically, 2-8 chips 1 are integrated on one interposer layer 2 to form a heterogeneous or homogeneous integrated system.

[0034] In this embodiment, a silicon substrate is selected as the interposer layer 2, and two chips are disposed on the interposer layer 2, including a logic chip 11 and a memory chip 12. Specifically, the logic chip 11 adopts CMOS technology and integrates a computing and control unit; the memory chip 12 includes DRAM (Dynamic Random Access Memory), adopts a stacked structure (4-16 layers), and the material includes a silicon substrate, polysilicon gate, and metal interconnects. The two chips communicate with each other through the redistribution layer (not shown in the figure) of the interposer layer 2. The diameter of the microbumps 13 on the chip 1 is 30 μm, the spacing between two adjacent microbumps 13 is 50 μm, and the length and width of the interposer layer 2 are 40×60 mm, and the thickness is 100 μm. In this embodiment, the chip 1 has a front and a back side, and the side with the microbumps 13 is defined as the front side of the chip.

[0035] The heat sink 3 is located within the interposer layer 2. Specifically, the heat sink 3 has an array structure and is vertically embedded inside the interposer layer 2; the top of the heat sink 3 extends to the side of the interposer layer 2 closest to the chip 1. Optionally, the heat sink 3 is arranged in a uniformly distributed array structure with a spacing of 150 μm between adjacent heat sink 3; alternatively, the heat sink 3 is arranged in a non-uniformly distributed array structure, with the array density gradient corresponding to the heat flux density difference of the chip 1: the core area of ​​the logic chip 11 is a high-density area, where the heat sink 3 is closely arranged, with a spacing of 100-150 μm; the area of ​​the memory chip 12 and the chip edge area are low-density areas, where the heat sink 3 is sparsely arranged, with a spacing of 150-300 μm. Specifically, the cross-section of the heat sink 3 is circular with rounded corners to reduce stress concentration, and the radius is between 20-100 μm. Specifically, the height of the heat sink 3 is less than or equal to the thickness of the interposer layer 2. Generally, the height of the heat sink 3 is between 60-200 μm. In this embodiment, the height of the heat dissipation column 3 is 80±5 μm, and the diameter is 50 μm. Specifically, the heat dissipation column 3 is made of a high thermal conductivity composite material. Specifically, the thermal conductivity of the heat dissipation column 3 is required to be ≥220 W / mK, and the bending strength is required to be 480 MPa.

[0036] Specifically, in this embodiment, the heat dissipation column 3 is made of a tungsten-copper-silver alloy material, which consists of 40%-60% tungsten skeleton, 30%-60% copper-silver alloy, and 5%-15% graphene. The tungsten skeleton provides the composite material with bending strength, which is far greater than that of copper alloy. By controlling the ratio of tungsten, copper, and silver, combined with the two-dimensional constraint effect of graphene, the thermal expansion coefficient of the composite material is better matched with that of chip 1. Specifically, in this embodiment, the tungsten-copper-silver alloy material consists of 60% tungsten skeleton, 30% copper-silver alloy, and 10% graphene.

[0037] Optionally, the three-dimensional gradient heat dissipation structure further includes a barrier layer 31 located around the heat dissipation pillar near the intermediate layer. The barrier layer 31 surrounds the heat dissipation pillar 3 and is an annular barrier layer. The barrier layer 31 is a key auxiliary layer that ensures the bonding strength between the high thermal conductivity composite material and the intermediate layer 2, prevents material diffusion, and improves the stability of the electroplating process. Specifically, the barrier layer 31 is made of titanium-tungsten alloy. Generally, the thickness of the barrier layer 31 is between 20-30 nm. In this embodiment, the thickness of the barrier layer 31 is 20 nm.

[0038] The front side of chip 1 includes microbumps 13 and reserved non-circuit contact areas. Generally, the non-circuit contact areas are covered with thermal interface material. The contact between heat sink 3 and chip 1 includes: direct thermal coupling between heat sink 3 and the thermal interface material on the front side of chip 1, and electrical connection between heat sink 3 and microbumps 13 of chip 1. Direct thermal coupling between heat sink 3 and the thermal interface material on the front side of chip 1 forms a heat conduction path from the active layer of chip 1 to the thermal interface material to heat sink 3; electrical connection between heat sink 3 and microbumps 13 of chip 1 enables electrical conduction between heat sink 3 and chip 1, while also utilizing the high thermal conductivity of heat sink 3 to directly dissipate the heat generated by the operation of microbumps 13.

[0039] The manifold cover 4 is disposed on the side of the interposer 2 away from the chip 1, and a microchannel 5 is formed within the manifold cover 4. The microchannel 5 is connected to the end of the heat sink 3 away from the chip 1. Generally, the manifold cover is a specially designed cover that integrates fluid distribution and heat dissipation functions. The thickness of the manifold cover 4 is between 200-500 μm, and the material of the manifold cover 4 includes: metal (pure copper) and metal alloys (copper-molybdenum alloy, aluminum-copper composite plate), ceramics and their composite materials (including aluminum nitride, silicon carbide), etc. In this embodiment, the material of the manifold cover 4 is copper-molybdenum alloy.

[0040] Generally, the distribution shape of the microchannels 5 includes tree-like, spiral, mesh-like, and other distributions. In this embodiment, the distribution of the microchannels 5 is tree-like. Generally, the width of the main channel is between 300-80 μm, and the width of the sub-channels is between 50-300 μm. In this embodiment, through fluid dynamics optimization, the width of the main channel is 500 μm, and the width of the sub-channels is 100 μm. Figure 1 The diagram shown is a cross-sectional view for illustrative purposes only; the relationship between the main channel and the sub-channels is not shown. Generally, the coolant in microchannel 5 includes: an aqueous ethylene glycol solution and a fluorinated liquid. The coolant is evenly distributed from the inlet of the microchannel to each branch channel, and then converges to the outlet. At a pressure of 0.1 MPa, the flow rate reaches 10 mL / min·cm², and it can remove 300 W / cm² of heat. 2 .

[0041] Optionally, a groove 6 is formed on the side of the manifold cover 4 away from the chip 1. Specifically, the groove 6 extends from the end of the manifold cover 4 away from the chip 1 towards the end closer to the chip 1. The groove 6 improves the heat dissipation efficiency of the manifold cover 4 by increasing the heat dissipation area, enhancing phase change heat transfer, and optimizing fluid flow. Specifically, the direction of heat conduction from the chip 1 to the manifold cover 4 is defined as the vertical direction, and the plane passing through the center of the groove 6 along the vertical direction is defined as the cross-section. The cross-sectional shape of the groove 6 is trapezoidal, and the side of the trapezoid closer to the chip 1 is narrower, while the side away from the chip 1 is wider. The depth of the groove 6 is along the vertical direction, and the width of the groove is perpendicular to the vertical direction. Specifically, in this embodiment, the depth-to-width ratio of the groove 6 is approximately 3:1. The depth of the groove 6 is between 50-90 μm, the upper base width of the groove 6 is between 20-40 μm, and the lower base width is between 30-60 μm. In this embodiment, the trench 6 has a depth of 60±5 μm, a width of 30±5 μm for the upper base, and a width of 50±5 μm for the lower base. The trapezoidal heat dissipation trench 6 can effectively increase the heat dissipation area. Optionally, the trenches 6 are uniformly arrayed, with a spacing of 150 μm between adjacent trenches. Optionally, the trenches 6 are non-uniformly distributed in an array structure, corresponding to the difference in heat flux density of chip 1, with the array density showing a gradient distribution: in high-density areas, the trenches 6 are closely arranged, with a specific trench spacing of 100-150 μm; in low-density areas, the trenches 6 are arranged in a coefficient manner, with a specific trench spacing of 200-300 μm.

[0042] Optionally, a protective coating 61 is formed on the inner wall of the trench 6. Specifically, the protective coating 61 includes metal and alloy coatings (nickel-phosphorus alloy coatings, titanium coatings, etc.), ceramic coatings, and diamond-based carbon coatings. In this embodiment, a diamond-based carbon coating is used, with a thickness between 50-1000 nm. The protective coating 61 has both high hardness and chemical inertness, preventing corrosion by coolants (such as solutions containing ethylene glycol).

[0043] Optionally, the three-dimensional gradient heat dissipation structure provided in this embodiment further includes an interface layer 7, which is located between the intermediate layer 2 and the manifold cover plate 4. Specifically, the interface layer 7 is arrayed between the intermediate layer 2 and the manifold cover plate 4. The interface layer 7 corresponds one-to-one with the position of the heat dissipation pillars 3, forming directional heat dissipation channels. Specifically, the interface layer 7 includes a silver paste layer 71 and an indium-based thin film 72. The interface layer 7 closer to the chip 1 is the silver paste layer 71, and the interface layer 7 farther from the chip 1 is the indium-based thin film 72. The thickness of the silver paste layer 71 is between 5 μm and 20 μm. In this embodiment, the thickness of the silver paste layer 71 is 10 μm. The silver paste layer 71 is composed of 60%-80% silver flakes, 20%-40% epoxy resin, and 5%-15% graphene. The silver flakes are micron-sized silver flakes with a particle size between 1 and 5 μm. The silver sheet serves as the primary heat source, epoxy resin provides adhesion, and graphene acts as a thermal conductivity enhancer. By adjusting the content of graphene in the silver paste layer 71, a gradient change in the thermal conductivity of the silver paste layer 71 can be achieved.

[0044] The indium-based thin film 72, near the chip 1, includes an indium tin alloy layer and an indium silver-graphene gradient layer. Generally, the thickness of the indium tin alloy layer is between 5 μm and 20 μm, and the thickness of the indium silver-graphene gradient layer is also between 5 μm and 20 μm. In this embodiment, the thickness of both the indium tin alloy layer and the indium silver-graphene gradient layer is 15 μm. Specifically, in this embodiment, the thermal conductivity of the interface layer 7 gradually increases from the intermediate layer 2 towards the manifold cover plate 4. This is achieved by gradually increasing the graphene content in the indium silver-graphene gradient layer; specifically, the graphene content in the interface layer 7 near the intermediate layer 2 is 5%, and the graphene content in the interface layer 7 further away from the intermediate layer 2 gradually increases to 15%, thus achieving a gradient increase in thermal conductivity. The thermal conductivity of the cured interface layer 7 increases linearly from 65 W / mK near the intermediate layer 2 to 100 W / mK near the manifold cover 4, with a final average thermal conductivity of 82 W / mK after overall curing. In the heat transfer path from chip 1 to heat sink 3 to interface layer 7 to manifold cover 4, interface layer 7 acts as an intermediate hub, and its gradient thermal design perfectly connects the thermal conductivity of heat sink 3 and manifold cover 4, avoiding abrupt thermal resistance loss.

[0045] Optionally, the three-dimensional gradient heat dissipation structure further includes a filling layer. The filling layer 8 includes a first filling layer 81 and a second filling layer 82. Specifically, the first filling layer 81 is located between the interposer layer 2 and the manifold cover plate 4, and the second filling layer 82 is located between the chip 1 and the interposer layer 2. The filling layer is used to fill the gaps between the interposer layer 2 and the manifold cover plate 4, and between the chip 1 and the interposer layer 2, to improve the bonding strength of the heat dissipation structure. Specifically, the material of the filling layer includes a filler adhesive, such as epoxy resin, as an electrical isolation layer to prevent short circuits between the heat sink and the metal substrate of the cover plate.

[0046] Example 2

[0047] This embodiment also provides a method for preparing a three-dimensional gradient heat dissipation structure, such as... Figure 2-5 The diagram shown is an intermediate structure schematic of the three-dimensional gradient heat dissipation structure preparation method provided in this embodiment.

[0048] The fabrication method of the three-dimensional gradient heat dissipation structure specifically includes the following steps:

[0049] S1: Provide an interposer layer, on which blind vias are etched;

[0050] S2: Fill the blind hole with composite material to form a heat dissipation column;

[0051] S3: Bond the flip chip to one side of the interposer layer;

[0052] S4: An interface layer is formed on the side of the interposer layer away from the chip;

[0053] S5: Fabricate a manifold cover plate and form a microchannel within the manifold cover plate;

[0054] S6: Bond the manifold cover to the side of the interface layer away from the chip.

[0055] Specifically, step S1: Provide an interposer layer, and etch blind vias onto the interposer layer: such as Figure 2 As shown, an interposer layer 2 is provided. A silicon substrate or an organic substrate is used as the interposer layer 2. In this embodiment, a silicon substrate is used, with a thickness of 50-300 μm. The process also includes pretreatment of the silicon substrate, including mechanical and chemical polishing, to ensure that the surface roughness Ra of the front and back surfaces of the silicon substrate is less than 0.5 nm, thereby guaranteeing uniform photoresist coating and improving the flatness of the bonding interface.

[0056] Blind vias 201 are etched onto the interposer layer 2. This includes: providing a photomask with a blind via array pattern formed thereon, wherein the blind via opening diameter is 50 μm, the spacing between blind via openings in the corresponding region of the logic chip is 100 μm, and the spacing between blind via openings in the corresponding region of the memory chip is 150 μm; transferring the blind via array pattern from the photomask to the interposer layer 2; coating the surface of the interposer layer 2 with photoresist (positive photoresist is used in this embodiment), employing an ultraviolet laser direct writing system with a wavelength of 355 nm and a spot diameter of 10 μm, without the need for a mask; directly exposing the interposer layer 2; reducing the error in the edge linewidth of the opening pattern by dynamically adjusting the laser energy density (5 J / cm²) and the number of scans; developing the interposer layer 2 after exposure with a developer to form photoresist openings on the interposer layer 2 that are consistent with the blind via array pattern on the photomask; and etching the interposer layer 2 to form the blind vias 201.

[0057] Optionally, the process also includes surface activation of the hole wall of the blind via 201. Specifically, this includes: lightly etching with a dilute nitric acid solution to remove the heavily doped damage layer remaining on the hole wall after etching; then introducing a mixture of oxygen and argon gas into the blind via 201 to perform plasma cleaning on the hole wall at a power of 300 W for 120 s, in order to remove organic residues and introduce hydroxyl (-OH) active groups.

[0058] Optionally, such as Figure 2 As shown, the method also includes depositing a barrier layer 31 within the sidewall of the blind hole 201. Specifically, a titanium-tungsten barrier layer 31 is deposited on the inner wall of the blind hole using a magnetron sputtering system. The target material is a TiW alloy target. The thickness of the barrier layer 31 is monitored by a profilometer to ensure that the thickness is 20 nm, thus ensuring the adhesion of the subsequent electroplating layer.

[0059] Step S2: As Figure 3 As shown, the blind hole 201 is filled with a composite material to form a heat dissipation column 3. Specifically, the composite material comprises a matrix of 50% tungsten skeleton and 40% copper-silver alloy, with 10% graphene coating the matrix to form a "core-shell" structure. The tungsten skeleton uses tungsten powder with a particle size of 5-10 μm and a purity of ≥99.9% to ensure skeleton strength; the copper-silver alloy consists of 30% copper and 10% silver, using copper and silver powder with a particle size of 1-3 μm and a purity of ≥99.5% to improve thermal conductivity; the graphene uses single-layer or few-layer graphene sheets with a diameter of 5-20 μm and a thickness of ≤1 nm to reduce interfacial thermal resistance. The composite material provided in this embodiment has a thermal conductivity of up to 220 W / mK, and the coefficient of thermal expansion (CTE) can be adjusted to 4.8 ppm / K (close to the 2.6 ppm / K of silicon substrates), which can effectively reduce thermomechanical stress.

[0060] Step S2 includes: preparing the electrolyte: the electrolyte composition is 65 wt% W, 22 wt% Cu, and 13 wt% Ag; the specific sources include: sodium tungstate (Na2WO4·2H2O), 50 g / L, providing tungsten ions (WO2... 2- Copper sulfate (CuSO4·5H2O), 25 g / L, provides Cu 2+ Silver nitrate (AgNO3), 10 g / L, provides Ag + ; Graphene oxide dispersion (concentration 0.5 wt%); also includes other additives and other materials. Pulse electroplating filling: A pulse electroplating process is used to deposit tungsten-copper-silver / graphene composite material in the blind hole 201. Specifically, the current density is 3-5 A / dm², and the voltage is gradually increased from 0.5 V to 2 V under a duty cycle of 30%, to achieve void-free filling in the blind hole 201. Annealing strengthening treatment: After electroplating, annealing treatment is performed in a hydrogen / nitrogen mixed atmosphere (H2:N2=1:9) and held at 650℃ for 2 hours to allow the intermetallic compound (Cu5W6) to disperse and precipitate, forming the heat dissipation column 3.

[0061] Step S3: As Figure 3 As shown, a flip chip 1 is bonded to one side of the interposer layer 2 to form a chip-interposer unit. Specific steps include: fabricating multiple microbumps 13 on the flip chip 1; using thermoforming bonding to flip-chip 1 onto the interposer layer 2; bonding the microbumps 13 of the chip 1 to some heat sinks 3; and directly attaching some heat sinks 3 to the non-circuit contact areas of the chip 1. Electrical connection between the chip 1 and the heat sinks 3 is achieved through the microbumps 13.

[0062] Optionally, the method further includes thinning the side of the interposer 2 away from the chip 1 and removing the barrier layer 31 at the bottom of the heat sink 3 on the side away from the chip 1 to expose the heat sink 3. Specifically, mechanical polishing or other methods are used to make the distance between the end of the heat sink 3 away from the chip 1 and the side of the interposer 2 away from the chip 1 less than or equal to 15 μm; then etching or other methods are used to remove the barrier layer 31 at the bottom of the heat sink 3 on the side away from the chip 1.

[0063] Step S4: As Figure 5 As shown, a manifold cover plate 4 is fabricated, and microchannels 5 are formed within the manifold cover plate 4. A copper-molybdenum alloy cover plate is provided, and a femtosecond laser is used on the side of the cover plate near the chip 1, specifically with a wavelength of 1030 nm and a pulse energy of 100 μJ (this data is for illustrative purposes only and should not be used to limit the scope of protection of this application). A tree-shaped microchannel 5 is etched: specifically, the main channel is 500 μm wide, the branch channel is 100 μm wide, and the inlet and outlet interface diameter is 2 mm (to match the external liquid cooling system, not shown in the figure).

[0064] Optionally, the method further includes forming a trench 6 on the side of the manifold cover plate 4 away from the side where the chip 1 is soldered. Specifically, the pattern of the trench 6 is designed according to the positional relationship of the microchannels 5 and the heat dissipation requirements of the manifold cover plate 4. Specifically, the trenches 6 are closely arranged in the high heat flux region corresponding to the logic chip 11, and sparsely arranged in the low heat flux region corresponding to the memory chip 12. Then, the trenches 6 are formed by etching along the thickness direction of the manifold cover plate 4 using a femtosecond laser etching system. The trenches 6 formed by etching have a trapezoidal structure, with a narrower upper base on the side closer to the chip 1 and a wider lower base on the side away from the chip 1.

[0065] Optionally, the process also includes fine machining of the inner walls of the microchannels 5 and trenches 6, including plasma polishing and hydrophilic layer treatment. Specifically, high-energy plasma is used to perform atomic-level etching on the inner walls of the microchannels 5 and trenches 6 to remove protruding burrs and micro-defects, ensuring a machining accuracy of ±2 μm and a channel inner wall roughness Ra < 0.1 μm. The microchannels 5 and trenches 6 are then hydrophilicated by immersing the manifold cover 4 in a 10% NaOH solution at 80°C for 5 minutes. This chemical reaction generates a nano-CuO whisker structure on the copper-molybdenum alloy surface, reducing the surface contact angle to 15° and enhancing capillary action.

[0066] Optionally, a protective coating 61 may be formed on the inner wall of the trench 6. Optionally, a process such as magnetron sputtering or chemical plating may be used. Specifically, taking magnetron sputtering as an example: the target material is Ti, the sputtering gas is an N2 / Ar mixture (ratio 1:5), the power is 300 W, and the deposition thickness is 500-1000 nm, ensuring uniform coverage of the inner wall of the trench (including the trapezoidal inclined surface and the bottom rounded corners). Since the inner wall of the trench 6 is in direct contact with the cooling medium (such as ethylene glycol aqueous solution, fluorinated liquid) or air, the copper-molybdenum alloy substrate is prone to electrochemical corrosion (such as copper oxidation, acidic corrosion of ethylene glycol). Therefore, physical isolation is achieved through the protective coating 61.

[0067] Optionally, it also includes Figure 4As shown, an interface layer 7 is formed on the side of the interposer 2 away from the chip 1. Specifically, a silver paste layer 71 is first formed on the side of the interposer 2 close to the chip 1. A uniform slurry is formed by mixing 70% micron-sized silver flakes and 30% epoxy resin. A piezoelectric dispensing machine (positioning accuracy ±5 μm) is used to completely cover the area of ​​the heat sink 3 with the silver paste. Where there are no heat sink 3 on the interposer 2, no silver paste is applied. The silver paste is cured in a nitrogen oven to form the silver paste layer 71. In this embodiment, the thickness of the silver paste layer 71 is 10 μm. Next, an indium-based thin film 72 is deposited on the side of the silver paste layer 71 away from the chip 1. Optionally, the cured silver paste layer 71 is plasma activated to remove surface organic residues and improve adhesion to the metal thin film. Indium tin alloy (In) is then sputtered sequentially onto the silver paste layer 71. 52 Sn 48 The indium tin alloy layer and the indium silver-graphene gradient layer are both deposited. Specifically, the indium tin alloy layer has a thickness of 15 μm, and the indium silver-graphene gradient layer has a thickness of 15 μm. Specific parameters include: sputtering pressure 0.3 Pa, substrate temperature 80 ℃, RF power 150 W, and deposition rate 0.8 μm / min. The thermal conductivity is adjusted by changing the graphene content in the indium silver-graphene gradient layer. Specifically, from chip 1 to the manifold cover plate 4, the Ag content gradually increases from 0% to 20%, and the graphene content gradually increases from 5 wt% to 15 wt%.

[0068] Step S5: As Figure 1 As shown, the manifold cover 4 is bonded to the side of the interposer layer 2 away from the chip 1.

[0069] Specifically, in a vacuum chamber (vacuum degree <10) -3 In a thermocompression bonding process (Pa), the chip-intermediate unit is aligned with the manifold cover plate 4, and stepped pressure is applied: first, a pre-pressure of 5 MPa for 10 s is applied to initially deform the interface layer 7 and expel residual gas at the interface; then, the pressure is increased to 15 MPa and held for 60 s, with the high pressure promoting metal atom diffusion and bonding the interface layer 7 to the cover plate microchannel 5. The temperature profile starts at 150 ℃, gradually increases to 250 ℃ at a rate of 10 ℃ / min, holds for 3 min, and then cools. This step, through precise control of alignment accuracy, pressure, and temperature parameters, achieves a metallurgical bond with a silver paste flow coverage of ≥98%.

[0070] Optionally, it also includes a filling layer 8, which includes a first filling layer 81 and a second filling layer 82.

[0071] Optionally, for the first filler layer 81 located between the interposer layer 2 and the manifold cover plate 4, a high-precision dispensing machine is used to apply filler adhesive to one side of the edge of the interposer layer 2, naturally filling the gap by capillary action. For the second filler layer 82, after the chip 1 is flip-bonded onto the interposer layer 2, adhesive is dispensed at the edge of the chip 1 (at the gap with the interposer layer 2), and the filler adhesive fills along the gap by capillary action, covering the area around all the microbumps 13.

[0072] In summary, the three-dimensional gradient heat dissipation structure and fabrication method provided in this application greatly improve heat dissipation capacity by combining three-dimensional heat dissipation channels with microchannel liquid cooling and trench heat exchange; the cover plate is directly integrated into the interposer layer without the need for an additional metal substrate, thus avoiding changes to the existing packaging process; the gradient interface layer achieves a gradual change in thermal conductivity from 86 to 120 W / mK, which is 40% more efficient than traditional indium wafers and 50% cheaper; in addition, the stepped thermocompression bonding achieves a void-free interface bonding, ensuring long-term operational stability while avoiding chip damage.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A three-dimensional gradient heat dissipation structure, characterized in that, include: chip; An interposer layer, on which the chip is flip-chip mounted; A heat sink is disposed within the interposer layer, with one end of the heat sink extending to the side of the interposer layer near the chip and coupled to the chip, and the other end of the heat sink extending to the side of the interposer layer away from the chip. A manifold cover is disposed on the side of the interlayer away from the chip. A microchannel is formed inside the manifold cover, and the microchannel is connected to the end of the heat sink away from the chip. An interface layer is arrayed between the interposer layer and the manifold cover. The interface layer comprises a silver paste layer and an indium-based thin film. The silver paste layer, located closer to the chip, consists of 60%-80% silver flakes, 20%-40% epoxy resin, and 5%-15% graphene. The indium-based thin film, located further away from the chip, comprises an indium-tin alloy layer closer to the chip and an indium-silver-graphene gradient layer closer to the manifold cover. The graphene content in the indium-silver-graphene gradient layer is adjusted to gradually increase from the chip side to the manifold cover side, thereby gradually increasing the thermal conductivity of the interface layer from the interposer layer towards the manifold cover.

2. The three-dimensional gradient heat dissipation structure according to claim 1, characterized in that, The heat dissipation column comprises a tungsten-copper-silver alloy material, which is composed of 40%-60% tungsten skeleton, 30%-60% copper-silver alloy and 5%-15% graphene.

3. The three-dimensional gradient heat dissipation structure according to claim 1, characterized in that, The manifold cover has a groove formed on the side away from the chip.

4. The three-dimensional gradient heat dissipation structure according to claim 3, characterized in that, The cross-sectional shape of the trench is trapezoidal. The direction of heat conduction from the chip to the manifold cover is defined as the vertical direction, and the plane passing through the center of the trench along the vertical direction is the cross-section.

5. The three-dimensional gradient heat dissipation structure according to claim 3, characterized in that, The inner wall of the trench is covered with a protective coating.

6. The three-dimensional gradient heat dissipation structure according to claim 1, characterized in that, It also includes a barrier layer, located around the heat dissipation pillars near the interlayer.

7. The three-dimensional gradient heat dissipation structure according to claim 1, characterized in that, Also includes: A filler layer, a first filler layer located between the interposer layer and the manifold cover, and a second filler layer located between the chip and the interposer layer.

8. A method for preparing a three-dimensional gradient heat dissipation structure according to any one of claims 1-7, characterized in that, include: An intermediate layer is provided, and blind vias are etched onto the intermediate layer; The blind holes are filled with composite material to form heat dissipation columns; Flip chips are bonded to one side of the interposer layer. Fabricate a manifold cover plate and form microchannels within the manifold cover plate; The manifold cover is bonded to the side of the interposer away from the chip; Before bonding the manifold cover to the side of the interposer away from the chip, an interface layer is formed on the side of the interposer away from the chip, and the interface layer is arrayed between the interposer and the manifold cover.

9. The method for preparing the three-dimensional gradient heat dissipation structure according to claim 8, characterized in that, Fabricating the manifold cover also includes forming a groove on the side of the manifold cover away from the chip.

10. The method for preparing the three-dimensional gradient heat dissipation structure according to claim 8, characterized in that, After etching a blind via on the intermediate layer, the process further includes depositing a barrier layer within the sidewalls of the blind via.

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