Interposer, semiconductor system and manufacturing method thereof

Abstract

A semiconductor system includes an active interposer and a plurality of semiconductor chips. The active interposer includes an interposer substrate, a semiconductor die, and a front side redistribution layer (RDL). A semiconductor die is formed in an interposer substrate and includes a die substrate, an active die circuit, and a conductive layer. An active die circuit is fabricated over the die substrate and includes one or more active components. The conductive layer is connected to the active die circuitry. The front side RDL is connected to the conductive layer. A semiconductor chip is bonded to the front side RDL. A method of manufacturing the semiconductor system and an interposer are also disclosed.

Description

Technical Field

[0001] Embodiments of the present application relate to an interposer, a semiconductor system, and a method for manufacturing the same. Background Art

[0002] Packaging technologies, such as three-dimensional integrated circuits (3D-ICs) and chip-on-wafer-on-substrate (CoWoS) technologies, involve stacking semiconductor chips on top of each other and interconnecting them through a passive interposer. This arrangement can improve performance while reducing the surface area occupied by the semiconductor chips on the package substrate. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor system is provided including an active interposer and a plurality of semiconductor chips. The active interposer includes: an interposer substrate; a first semiconductor die formed in the interposer substrate. And the first semiconductor die includes: a first die substrate; an active die circuit manufactured above the first die substrate and including one or more active components; and a first conductive layer connected to the active die circuit. The active interposer also includes: a front-side redistribution layer connected to the first conductive layer; a back-side redistribution layer formed above the bottom surface of the interposer substrate; one or more through-substrate vias interconnecting the first conductive layer and the back-side redistribution layer; and one or more through-interposer vias (TIVs) connected between the front-side redistribution layer and the back-side redistribution layer. Multiple semiconductor chips are bonded to the front-side redistribution layer.

[0004] According to another aspect of an embodiment of the present application, an interposer is provided, comprising an interposer substrate and a semiconductor die. The semiconductor die is formed in the interposer substrate and includes a die substrate, a passive die circuit, a conductive layer, and a front-side redistribution layer. The passive die circuit is fabricated above the die substrate and includes one or more passive components. The conductive layer is connected to the passive die circuit. At least one of the passive die circuit and the conductive layer includes one or more passive components. The front-side redistribution layer is connected to the conductive layer.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor system is provided, including manufacturing an active interposer by the following steps: receiving an interposer substrate; providing a tube core substrate in the interposer substrate; manufacturing an active tube core circuit including multiple active components above the tube core substrate; connecting a conductive layer to the active tube core circuit; forming a front side redistribution layer located above the interposer substrate and connected to the conductive layer; and bonding multiple semiconductor chips to the front side redistribution layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings:

[0007] Figure 1is a schematic block diagram illustrating an exemplary system according to various embodiments;

[0008] Figure 2A is a schematic top view illustrating another exemplary system according to various embodiments;

[0009] Figure 2B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0010] Figure 3A is a schematic top view illustrating another exemplary system according to various embodiments;

[0011] Figure 3B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0012] Figure 4 is a schematic cross-sectional view illustrating an exemplary semiconductor die connected between front-side and back-side redistribution layers according to various embodiments;

[0013] Figure 5A is a schematic top view illustrating another exemplary system according to various embodiments;

[0014] Figure 5B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0015] Figure 6A is a schematic top view illustrating another exemplary system according to various embodiments;

[0016] Figure 6B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0017] Figure 7A is a schematic top view illustrating another exemplary system according to various embodiments;

[0018] Figure 7B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0019] Figure 8A is a schematic top view illustrating another exemplary system according to various embodiments;

[0020] Figure 8B is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0021] Figure 9A is a schematic top view illustrating another exemplary system according to various embodiments;

[0022] Figure 9Bis a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments;

[0023] Figure 10 is a flowchart illustrating exemplary operations of a method of manufacturing a system according to various embodiments;

[0024] Figures 11A-11F is a cross-sectional view illustrating another exemplary method for manufacturing a system at an intermediate stage according to various embodiments; and

[0025] Figure 12 is a schematic cross-sectional diagram illustrating another exemplary system according to various embodiments. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, for ease of description, spacing terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spacing terms are intended to encompass different orientations of the device in use or during operation in addition to the orientations depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and spacing descriptors used herein should be interpreted accordingly.

[0028] The systems and methods herein describe three-dimensional integrated circuit (3D-IC) technology, chip-on-wafer-on-substrate (CoWoS) technology, and other modern packaging technologies that involve stacking semiconductor chips (also known as integrated circuits or semiconductor dies) on top of each other and interconnecting the semiconductor chips using a passive interposer. In one embodiment, the passive interposer connects one or more semiconductor chips (e.g., a system on a chip (SoC)) to one or more semiconductor chips, such as memory devices, such as high-bandwidth memory (HBM) devices. For example, the passive interposer may include an interposer substrate, a front-side redistribution layer (RDL) on a top surface of the interposer substrate, a back-side RDL on a bottom surface of the interposer substrate, and a plurality of through-interposer vias (TIVs) connected between the front-side and back-side RDLs.

[0029] This passive interposer can be inefficient because it limits the number of HBM devices that can be connected to the SoC. For example, while HBM devices close to the SoC may not cause significant degradation of the signal between them and the SoC, HBM devices farther away from the passive interposer may significantly degrade the signal quality between them and the SoC. The systems and methods described in certain examples herein alleviate this problem by interconnecting the SoC and HBM devices using an active interposer. In some embodiments, the active interposer includes a die circuit that performs a predetermined circuit function and is capable of maintaining or even enhancing signal integrity during signal transmission and reception between the SoC and the HBM device.

[0030] Figure 1 FIG. 1 is a schematic block diagram illustrating an exemplary system 100 according to various embodiments of the present disclosure. Figure 1 As shown, an example system 100 (e.g., a 3D-IC, CoWoS, or other system using modern packaging technology) includes an active interposer 110 and a plurality of semiconductor chips 120-140 interconnected by the active interposer 110. In some embodiments, the active interposer 110 includes an interposer substrate, one or more semiconductor dies, and a front-side RDL. Examples of materials for the interposer substrate include silicon, organic materials, glass, ceramics, polymer-based materials, other suitable interposer substrate materials, and combinations thereof.

[0031] Semiconductor chips can take many forms. In one example, a semiconductor chip includes a chip substrate, chip circuitry fabricated on the chip substrate and performing a predetermined circuit function, and conductive layers (e.g., back-end-of-line or BEOL) connected to the chip circuitry. The chip circuitry includes components, such as passive electronic components such as resistors, capacitors, and inductors, and active electronic components such as transistors, diodes, and integrated circuits.

[0032] A semiconductor die (also referred to herein as a local silicon interposer or LSI) includes a die substrate formed in an interposer substrate, die circuitry fabricated on the die substrate and performing predetermined circuit functions, and conductive layers (e.g., BEOL) connected to the die circuitry. Examples of materials for the die substrate include silicon, silicon-on-insulator (SOI), gallium arsenide, silicon carbide, sapphire, germanium, gallium nitride, indium phosphide, and combinations thereof.

[0033] In one example, the die circuitry includes active components (e.g., transistors, diodes, and integrated circuits) and / or passive components (e.g., resistors, inductors, and capacitors). The front-side RDL is connected between the conductive layer and the semiconductor chips 120-140. In some embodiments, the active interposer 110 also includes a back-side RDL formed on the bottom surface of the interposer substrate and one or more through-interposer vias (TIVs) interconnecting the front-side and back-side RDLs. In these embodiments, the semiconductor die (or LSI) also includes one or more through-substrate vias (TSVs) connected between the BEOL and the back-side RDL. Example materials for the conductive layer, RDL, TSV, and TIV include copper, nickel, gold, silver, cobalt, tungsten, aluminum, other conductive materials, and combinations thereof.

[0034] Semiconductor chips 120-140 are bonded to the top and / or bottom surfaces of active interposer 110 and may include a SoC and multiple HBM devices. The SoC may include a central processing unit (CPU) that executes instructions and performs calculations, on-chip memory (e.g., random access memory or RAM, such as static RAM or SRAM) that stores data and instructions, input / output (I / O) ports for communicating with other devices (e.g., universal serial bus or USB, high-definition multimedia interface or HDMI, and other suitable interfaces), one or more peripheral devices each having a predetermined circuit function (e.g., a graphics processing unit or GPU, a digital signal processor or DSP, etc.), power management circuitry that manages power distribution across the chip, and other digital and / or analog components.

[0035] An HBM device is a dynamic RAM (DRAM) device that provides higher data transfer rates and lower power consumption by vertically stacking DRAM dies and interconnecting them using TSVs, thereby reducing the footprint in directions where space is limited. In some embodiments, the semiconductor die or LSI of the active interposer 110 maintains or enhances communication between the SoC and the HBM device (i.e., prevents signal degradation). In some such embodiments, a relatively large number (e.g., more than four) of HBM devices can be connected to the SoC. In other embodiments, portions of the SoC can be incorporated into the LSI of the active interposer 110. This approach saves space within the SoC, allows for the inclusion of additional circuitry, reduces the power consumption of the SoC, and reduces the temperature of the SoC.

[0036] Figure 2A is a schematic top view illustrating another exemplary system 200 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 2B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 200) according to various embodiments of the present disclosure. Figure 2A and Figure 2B As shown, the example system 200 includes an active interposer (e.g., active interposer 110), a SoC 220, and a plurality of HBM devices 230. The active interposer 110 includes an interposer substrate 210a, one or more semiconductor dies or LSIs 210b, first and second RDLs 210c, 210d, one or more TIVs 210e, and one or more TSVs 210f.

[0037] LSI 210b includes a die substrate, die circuitry, and conductive layers (e.g., BEOL) formed within interposer substrate 210a. The die circuitry is fabricated above the die substrate and maintains or enhances signal integrity (e.g., data, instructions, control signals, etc.) by ensuring that signals are transmitted to subsequent stages without degradation. It also includes buses (e.g., digital buses such as buffer circuits) and connects SoC 220 to HBM device 230. A first (or front-side) RDL 210c is disposed on the top surface of interposer substrate 210a and connects between LSI 210b and semiconductor chips 220 and 230. A second (or back-side) RDL 210d is disposed on the bottom surface of interposer substrate 210a. A TIV 210e interconnects the front-side and back-side RDLs 210c and 210d. A TSV 210f connects between the BEOL and back-side RDL 210d.

[0038] The active interposer 110 also includes a plurality of interconnects 240 formed over the backside RDL 210 d and can be bonded to another semiconductor chip, a package substrate, or a printed circuit board (PCB). The semiconductor chips 220, 230 include a plurality of interconnects 250 formed on their bottom surfaces and bonded to the frontside RDL 210 c. In some embodiments, the interconnects 240, 250 are in the form of microbumps, solder balls, copper pillars, ball grid arrays (BGAs), combinations of metal and dielectric interconnects, other interconnects created by, for example, hybrid bonding, tape automated bonding (TAB), wire bonding, flip-chip bonding, other suitable interconnects, or combinations thereof.

[0039] As described above, the active interposer 110 can maintain or enhance the integrity of signal transmission and reception between the SoC 220 and the HBM devices 230. This allows for greater flexibility in the placement of the HBM devices 230 relative to the SoC 220 and each other. Thus, a relatively large number of HBM devices 230 can be bonded to the active interposer 110 and connected to the SoC 220. For example, Figure 3A is a schematic top view illustrating another exemplary system 300 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 3B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 300 ) according to various embodiments of the present disclosure.

[0040] like Figure 3A and Figure 3B As shown, the example system 300 differs from the system 200 in that the system 300 includes multiple semiconductor chip layers (eg, semiconductor chip layers 310-330) and multiple active interposers 340, 350. For clarity, Figure 3B Only the LSIs 210b of the active interposer 110 are shown. The semiconductor chip layer 310 includes the SoC 220 and a pair of HBM devices 230, each of which is disposed on a respective one of opposing sides of the SoC 220. The active interposer 340 is bonded to the top surface of the semiconductor chip layer 310 and includes one or more LSIs 210b, each of which connects an HBM device 230 to the SoC 220. Similarly, the active interposer 350 is bonded to the bottom surface of the semiconductor chip layer 310 and includes one or more LSIs 210b, each of which connects an HBM device 230 to the SoC 220. Furthermore, the semiconductor chip layer 320 is bonded to the active interposer 340 and includes one or more HBM devices 230 interconnected by the LSIs 210b of the active interposer 340. Similarly, the semiconductor chip layer 330 is bonded to the active interposer 350 and includes one or more HBM devices 230 interconnected by the LSIs 210 b of the active interposer 350 .

[0041] Figure 4 is a schematic cross-sectional view illustrating an exemplary LSI 400 (eg, LSI 210b) connected between front-side and back-side RDLs 450, 460 (eg, front-side and back-side RDLs 210c, 210d) according to various embodiments of the present disclosure. Figure 4As shown, an example LSI (or semiconductor die) 400 includes a die substrate 410, die circuitry 420, a conductive layer (e.g., BEOL) 430, and one or more TSVs 440. Examples of materials for the die substrate 410 include silicon, silicon-on-insulator (SOI), gallium arsenide, silicon carbide, sapphire, germanium, gallium nitride, indium phosphide, and combinations thereof.

[0042] The die circuit 420 is fabricated above the die substrate 410, performs a predetermined circuit function, and includes active components (e.g., transistors, diodes, and / or integrated circuits) and passive components (e.g., resistors, inductors, and / or capacitors). The BEOL 430 connects between the die circuit 420 and the front-side RDL 450 and includes horizontal and vertical metal lines. In some embodiments, passive components may be fabricated within the die circuit 420, the BEOL 430, or both. The TSVs 440 interconnect the BEOL 430 and the back-side RDL 460. In some embodiments, the RDLs 450, 460, the BEOL 430, and the TSVs 440 are made of copper, aluminum, tungsten, other conductive materials, or combinations thereof.

[0043] Figure 5A is a schematic top view illustrating another exemplary system 500 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 5B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 500) according to various embodiments of the present disclosure. Figure 5A and Figure 5B As shown, example system 500 differs from the previous embodiments in that the active interposer of system 500, such as active interposer 110, further includes at least one passive LSI 510. In this exemplary embodiment, passive LSI 510 includes a die substrate, die circuitry, a conductive layer, and one or more TSVs 520. The die substrate of passive LSI 510 is formed in interposer substrate 210a. The die circuitry is fabricated on the die substrate of passive LSI 510. In this exemplary embodiment, the die circuitry of passive LSI 510 includes one or more passive components (e.g., resistors, inductors, and capacitors) and, unlike active LSI 210b, does not include active components (e.g., transistors, diodes, and / or integrated circuits). The conductive layer (or BEOL) of passive LSI 110 connects between the die circuitry of passive LSI 510 and front-side RDL 210c and includes horizontal and vertical metal lines. The TSVs 520 of the passive LSI 510 interconnect the BEOL and the backside RDL 210d of the passive LSI 510. In some embodiments, the passive components of the LSI 510 may be fabricated within the die circuitry of the passive LSI 510, the BEOL in the passive LSI 510, or both.

[0044] Figure 6A is a schematic top view illustrating another exemplary system 600 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 6B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 600) according to various embodiments of the present disclosure. Figure 6A and Figure 6B As shown, example system 600 differs from the aforementioned embodiments in that system 600 also includes one or more device circuits 610, such as a memory controller, such as die circuit 420. Memory controller 610 manages the operation of HBM device 230. For example, memory controller 610 may include a portion formed in SoC 220 and another portion formed in active LSI 210b. In an alternative embodiment, the entire memory controller 610 is formed in active LSI 210b. This configuration of system 600 saves space within SoC 220. This allows for the inclusion of additional circuitry within SoC 220, reduces the SoC's power consumption, and lowers the SoC's temperature. In some embodiments, memory controller 610 is omitted from at least one of active LSIs 210b.

[0045] Figure 7A is a schematic top view illustrating another exemplary system 700 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 7B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 700) according to various embodiments of the present disclosure. Figure 7A and Figure 7B As shown, example system 700 differs from the previous embodiments in that system 700 further includes one or more device circuits 710, such as an integrated voltage regulator (IVR), such as die circuit 420. IVR 710 generates a substantially constant output voltage regardless of fluctuations in the input voltage it receives or changes in the load across it (e.g., the current consumed by semiconductor chips 220, 230). In this exemplary embodiment, IVR 710 is embedded in active LSI 210b. In another embodiment, a portion of IVR 710 is formed in SoC 220, and another portion of IVR 710 is formed in active LSI 210b. In some embodiments, IVR 710 is omitted from at least one of active LSIs 210b.

[0046] In some embodiments, the system 700 further includes a package substrate 720 for supporting the components 110, 220, 230 thereon and mounted on a printed circuit board (PCB) 730. In some such embodiments, the system 700 further includes a package voltage regulator (PVR) 740, which is mounted on the PCB 730 and provides power to the semiconductor chip mounted on the PCB 730. In other embodiments, the system 700 does not include a PVR.

[0047] Figure 8A is a schematic top view illustrating another exemplary system 800 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 8B 8 is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 800) according to various embodiments of the present disclosure. Figure 8A and Figure 8B As shown, the example system 800 differs from the previous embodiments in that the system 800 further includes one or more device circuits 810, for example, a cache memory device, such as the die circuit 420. The cache memory device 810 stores data frequently accessed by the SoC 220 from the main memory device (e.g., the HBM device 230) to speed up data retrieval, minimize latency, and improve the overall performance of the system 800.

[0048] In some embodiments, the cache memory device 810 includes a portion formed in the SoC 220 and another portion formed in the active LSI 210b. For example, the cache memory device 810 has different cache levels, such as a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache. The L1 cache is the smallest and fastest cache and can be located on the SoC 220, the active LSI 210b, or both. It has a capacity of several kilobytes (KB) and is the first level of data retrieval. The L2 cache is larger than the L1 cache, but still relatively small and fast, and can be located on the SoC 220, the active LSI 210b, or both. Its capacity is larger than the L1 cache, for example, several hundred kilobytes (KB) to several megabytes (MB). The L3 cache is larger and slower than the L1 and L2 caches and can be located on the SoC 220, the active LSI 210b, or both, and has a capacity of several megabytes (MB) to tens of megabytes (MB). It serves as a last level cache before data is retrieved from the main memory device (eg, HBM device 230 ).

[0049] Although the systems 100-300, 500-800 are exemplified by a semiconductor chip including one SoC 220 and a certain number of HBM devices 230, it should be understood that after reading this disclosure, the number of SoCs and HBM devices can be increased or decreased as needed, and other types of semiconductor chips can be considered in further embodiments. For example, Figure 9A is a schematic top view illustrating another exemplary system 900 (eg, system 100 ) according to various embodiments of the present disclosure. Figure 9B is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 900) according to various embodiments of the present disclosure. Figure 9A and Figure 9B As shown, the exemplary system 900 differs from the previous embodiments in that the system 900 includes multiple semiconductor chip layers 950-970 and multiple active interposers 980, 990. For clarity, Figure 9B Only the LSI 210 b of the active interposer 110 is shown.

[0050] In some embodiments, semiconductor chip layer 950 includes a pair of SoCs 220 and HBM devices 230. Active interposer 980 is bonded to the top surface of semiconductor chip layer 950 and connects the semiconductor chips of semiconductor chip layer 960 (e.g., one or more HBM devices 230 and one or more input / output devices or IODs 910) to SoCs 220. IODs facilitate communication between system 900 and devices external to system 900, such as input devices (e.g., keyboards, mice, scanners, microphones, and cameras) and output devices (e.g., monitors, printers, and speakers).

[0051] Similarly, an active interposer 990 is bonded to the bottom surface of the semiconductor chip layer 910 and connects the semiconductor chips of the semiconductor chip layer 930 (e.g., one or more HBM devices 230, one or more power management integrated circuits or PMICs 920, and one or more integrated passive devices or IPDs 930) to the SoC 220. The PMIC manages the power requirements of the system 900 (e.g., power distribution, power usage, voltage regulation, and protection components), while the IPD combines passive components (e.g., resistors, capacitors, and inductors) into a single package. In some embodiments, the semiconductor chip layers 910-930 also include one or more cache memory devices (e.g., L2 and / or L3 cache) 940a, 940b connected to the SoC 220 through the active interposers 980, 990.

[0052] Figure 10is a flow chart illustrating exemplary operations of a method 1000 for manufacturing a system (e.g., systems 100, 200, 300, 500-900) according to various embodiments of the present disclosure. Figures 11A-11F An example method 1000 is described. Figures 11A-11F is a cross-sectional view illustrating another exemplary method (e.g., method 1000) for manufacturing a system (e.g., systems 100, 200, 300, 500-900) at an intermediate stage according to various embodiments of the present disclosure. It should be understood that method 1000 is applicable to Figures 11A-11F Furthermore, it should be understood that in alternative embodiments of method 1000, additional operations may be provided before, during, and after method 1000, and some of the operations described below may be replaced or eliminated.

[0053] In operation 1010, as Figure 11A As shown, system manufacturing equipment receives a structure including a first substrate 1110 and an active interposer (e.g., active interposer 1120) supported by the first substrate 1110. In some embodiments, operation 1010 includes receiving an interposer substrate 1120a, forming an LSI in the interposer substrate 1120a, forming a conductive layer (e.g., BEOL) above the LSI, connecting a front-side RDL 1120b to the conductive layer, forming a back-side RDL 1120c on a bottom surface of the interposer substrate 1120a, interconnecting the front-side and back-side RDLs via one or more TIVs 1120d, and connecting the LSI to the back-side RDL 1120c using one or more TSVs 1120e.

[0054] In operation 1020, as Figure 11B As shown, the system manufacturing equipment bonds multiple semiconductor chips, such as one or more SoCs 1130a and one or more HBM devices 1130b. In this exemplary embodiment, operation 1020 includes forming an underfill 1130c between the top surface of the active interposer 110 and the bottom surfaces of the semiconductor chips 1130a and 1130b, and forming a molding layer 1130d between the semiconductor chips 1130a and 1130b.

[0055] Then, in operation 1030, as Figure 11C As shown, the system manufacturing equipment from Figure 11B The first substrate 1110 is removed from the structure, the resulting structure is flipped over, mounted on a second substrate 1140, and a plurality of interconnects 1150 are connected to the backside RDL 1120c. In operation 1040, as shown in FIG. Figure 11D As shown, the system manufactures the device and then Figure 11C Next, in operation 1050, as shown in FIG. Figure 11EAs shown, the system manufacturing equipment will Figure 11D The structure is bonded to the package substrate 1160. In this exemplary embodiment, operation 1050 includes: the system manufacturing equipment forms an underfill 1170 between the bottom surface of the active interposer 110 and the top surface of the package substrate 1160, and forms a molding layer 1180 on the opposite edges of the resulting structure. In an alternative embodiment, operation 1050 is Figure 11D The components are bonded to another semiconductor chip layer. Thereafter, in operation 1060, as Figure 11F As shown, Figure 11E The structure is mounted on PCB 1190.

[0056] although Figures 11A-11F The system in the embodiment of the present invention uses a single active interposer and a single semiconductor chip as an example, but it should be understood that after reading this disclosure, the number of active interposers and / or the number of semiconductor chip layers can be increased as needed. For example, Figure 12 is a schematic cross-sectional diagram illustrating another exemplary system (eg, system 100) according to various embodiments of the present disclosure. Figure 12 As shown, the exemplary system 1200 includes a plurality of active interposers 1210-1230 and a plurality of semiconductor chip layers 1240-1260. In this exemplary embodiment, the active interposers 1210-1230 and the semiconductor chip layers 1240-1260 are arranged alternately. In alternative embodiments, the active interposers 1210-1230 and the semiconductor chip layers 1240-1260 may be arranged in other orders.

[0057] In one embodiment, a semiconductor system includes an active interposer and multiple semiconductor chips. The active interposer includes an interposer substrate, a semiconductor die, a frontside RDL, a backside RDL, one or more TSVs, and one or more TIVs. The semiconductor die is formed in the interposer substrate and includes a die substrate, an active die circuit, and a conductive layer. The active die circuit is fabricated above the die substrate and includes one or more active components. The conductive layer is connected to the active die circuit. The frontside RDL is connected to the conductive layer. The backside RDL is formed on the bottom surface of the interposer substrate. The TSVs interconnect the conductive layer and the backside RDL. One or more TIVs are connected between the frontside and backside RDLs. The semiconductor chip is bonded to the frontside RDL.

[0058] In one embodiment, a semiconductor system includes an active interposer and a plurality of semiconductor chips. The active interposer includes: an interposer substrate; a first semiconductor die formed in the interposer substrate. And the first semiconductor die includes: a first die substrate; an active die circuit fabricated above the first die substrate and including one or more active components; and a first conductive layer connected to the active die circuit. The active interposer also includes: a front-side redistribution layer connected to the first conductive layer; a back-side redistribution layer formed above the bottom surface of the interposer substrate; one or more through-substrate vias interconnecting the first conductive layer and the back-side redistribution layer; and one or more through-interposer vias (TIVs) connected between the front-side redistribution layer and the back-side redistribution layer. A plurality of semiconductor chips are bonded to the front-side redistribution layer.

[0059] In some embodiments, the active die circuitry is configured to maintain or enhance the integrity of signal transmission and reception between semiconductor chips.

[0060] In some embodiments, the semiconductor system further includes device circuitry configured to perform a predefined circuit function, wherein the active die circuitry includes a portion of the device circuitry and another portion of the device circuitry is embedded in the semiconductor chip.

[0061] In some embodiments, the device circuit includes at least one of a buffer circuit, an integrated voltage regulator (IVR), a memory device, and a memory controller.

[0062] In some embodiments, the semiconductor system further includes one or more passive components, wherein the one or more passive components are within the active die circuitry, the conductive layer, or both.

[0063] In some embodiments, the semiconductor system further includes a second semiconductor die formed in the interposer substrate and including: a second die substrate; a passive die circuit formed above the second die substrate and including one or more passive components; a second conductive layer connected between the passive die circuit and the front-side redistribution layer, wherein the passive die circuit, the second conductive layer, or both include one or more passive components; and one or more through-substrate vias interconnecting the second conductive layer and the back-side redistribution layer.

[0064] In some embodiments, the semiconductor chip includes at least one of a system on chip (SoC), a memory device, an integrated voltage regulator (IVR), an input / output device (IOD), a power management integrated circuit (PMIC), and an integrated passive device (IPD).

[0065] In some embodiments, the semiconductor system further includes: a plurality of active interposers; and a plurality of semiconductor chip layers, wherein the active interposers and the semiconductor chip layers are stacked on each other.

[0066] In some embodiments, the semiconductor system further includes a package substrate, wherein the structure including the active interposer and the semiconductor chip is mounted on the package substrate.

[0067] In another embodiment, an interposer includes an interposer substrate and a semiconductor die. The semiconductor die is formed in the interposer substrate and includes a die substrate, passive die circuitry, a conductive layer, and a front-side redistribution layer. The passive die circuitry is fabricated above the die substrate and includes one or more passive components. The conductive layer is connected to the passive die circuitry. At least one of the passive die circuitry and the conductive layer includes one or more passive components. The front-side redistribution layer is connected to the conductive layer.

[0068] In some embodiments, the interposer further includes device circuitry formed in the interposer substrate, configured to perform a predefined circuit function, and connected to the front-side redistribution layer.

[0069] In some embodiments, the device circuit includes at least one of an integrated voltage regulator (IVR), a cache memory device, a memory controller, an input / output device (IOD), a power management integrated circuit (PMIC), and an integrated passive device (IPD).

[0070] In some embodiments, the interposer is configured to bond a semiconductor chip to the interposer.

[0071] In some embodiments, the interposer further includes: a backside redistribution layer formed over the bottom surface of the interposer substrate; one or more through-substrate vias interconnecting the conductive layer and the backside redistribution layer; and one or more through-interposer vias (TIVs) connected between the frontside redistribution layer and the backside redistribution layer.

[0072] In another embodiment, a method of manufacturing a semiconductor system includes manufacturing an active interposer by: receiving an interposer substrate; providing a die substrate in the interposer substrate; fabricating an active die circuit including a plurality of active components over the die substrate; connecting a conductive layer to the active die circuit; forming a front-side redistribution layer over the interposer substrate and connected to the conductive layer; and bonding a plurality of semiconductor chips to the front-side redistribution layer.

[0073] In some embodiments, the active die circuitry is configured to maintain or enhance the integrity of signal transmission and reception between semiconductor chips.

[0074] In some embodiments, the active die circuitry includes at least one of a buffer circuit, an integrated voltage regulator (IVR), a memory device, and a memory controller.

[0075] In some embodiments, portions of the active die circuitry are embedded in at least one of the semiconductor chips.

[0076] In some embodiments, the method further includes: forming a backside redistribution layer over a bottom surface of the active interposer; connecting the active die circuitry to the backside redistribution layer using one or more through-substrate vias; and connecting one or more through-interposer vias (TIVs) between the frontside redistribution layer and the backside redistribution layer.

[0077] In some embodiments, the semiconductor chip includes an input / output device (IOD), a memory device, a power management integrated circuit (PMIC), and an integrated passive device (IPD).

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor system comprising: Active interposer, including: interposer substrate; a first semiconductor die formed in the interposer substrate and comprising: a first die substrate; an active die circuit fabricated over said first die substrate and comprising one or more active components; and a first conductive layer connected to the active die circuit; a front-side redistribution layer connected to the first conductive layer; a backside redistribution layer formed over a bottom surface of the interposer substrate; one or more through-substrate vias interconnecting the first conductive layer and the backside redistribution layer; and One or more interposer through-vias connected between the front-side redistribution layer and the back-side redistribution layer; and A plurality of semiconductor chips are bonded to the front-side redistribution layer.

2. The semiconductor system according to claim 1, wherein The active die circuitry is configured to maintain or enhance the integrity of signal transmission and reception between the semiconductor chips.

3. The semiconductor system according to claim 1 , further comprising a device circuit configured to perform a predefined circuit function, wherein The active die circuitry includes portions of the device circuitry, and another portion of the device circuitry is embedded in the semiconductor chip.

4. The semiconductor system of claim 1 , further comprising one or more passive components, wherein The one or more passive components are in the active die circuitry, in the conductive layer, or both.

5. The semiconductor system of claim 1 , further comprising a second semiconductor die formed in the interposer substrate and comprising: a second die substrate; a passive die circuit formed over the second die substrate and comprising one or more passive components; a second conductive layer connected between the passive die circuit and the front-side redistribution layer, wherein the passive die circuit, the second conductive layer, or both include the one or more passive components; as well as One or more through-substrate vias interconnect the second conductive layer and the backside redistribution layer.

6. The semiconductor system according to claim 1 , further comprising: multiple active interposers; as well as A plurality of semiconductor chip layers, wherein the active interposer and the semiconductor chip layers are stacked on each other.

7. The semiconductor system according to claim 1, further comprising a packaging substrate, wherein A structure including the active interposer and the semiconductor chip is mounted on the package substrate.

8. An intermediary layer, comprising: interposer substrate; as well as a semiconductor die formed in the interposer substrate and comprising: die substrate; a passive die circuit fabricated over the die substrate and comprising one or more passive components; a conductive layer connected to the passive die circuitry, wherein at least one of the passive die circuitry and the conductive layer includes the one or more passive components; and A front-side redistribution layer is connected to the conductive layer.

9. The interposer according to claim 8, further comprising: a backside redistribution layer formed over a bottom surface of the interposer substrate; one or more through-substrate vias interconnecting the conductive layer and the backside redistribution layer; as well as One or more interposer through-vias are connected between the front-side redistribution layer and the back-side redistribution layer.

10. A method of manufacturing a semiconductor system, the method comprising: The active interposer is fabricated using the following steps: a receiving interposer substrate; providing a die substrate in the interposer substrate; fabricating an active die circuit comprising a plurality of active components over the die substrate; connecting a conductive layer to the active die circuit; forming a front-side redistribution layer over the interposer substrate and connected to the conductive layer; as well as A plurality of semiconductor chips are bonded to the front-side redistribution layer.

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