Semiconductor element with composite dielectric layer and manufacturing method thereof

Abstract

The invention discloses a semiconductor element with a composite dielectric layer and a manufacturing method of the semiconductor element, and particularly relates to a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes: a first interconnect structure disposed in a semiconductor substrate; a first dielectric layer and a second dielectric layer disposed on the semiconductor substrate; the second interconnection structure is arranged in the first dielectric layer and the second dielectric layer; and a third interconnection structure disposed in the semiconductor substrate. The first interconnection structure comprises a first wire and a first manganese-containing layer. The second interconnection structure comprises a second lead and a second manganese-containing layer. The third interconnection structure comprises a third wire and a third manganese-containing layer. The third manganese-containing layer of the third interconnect structure and the first manganese-containing layer of the first interconnect structure are made of the same material.

Description

[0001] Related applications

[0002] This application is a divisional application of Chinese invention patent application No. 2024106620181, filed on May 27, 2024, with the invention name “Semiconductor element with composite dielectric layer and manufacturing method thereof”. Application No. 2024106620181 claims priority and benefits of U.S. formal application No. 18 / 612,042 filed on March 21, 2024. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a composite dielectric layer and a method for manufacturing the same. Background Art

[0004] Semiconductor components are used in a variety of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor component size continues to shrink to meet the ever-increasing demand for computing power. However, the challenges associated with this reduction in size are becoming increasingly frequent and impactful. Consequently, challenges remain in reducing complexity while improving quality, yield, performance, and reliability.

[0005] The discussion in the prior art section provides background information only. Statements in the discussion in the prior art section are not an admission that the content disclosed in that section constitutes prior art to the present disclosure, and no part of the discussion in the prior art section shall be used as an admission that any part of the present application, including the part in the discussion in the prior art section, constitutes prior art to the present disclosure. Summary of the Invention

[0006] One aspect of the present disclosure provides a semiconductor device, comprising: a first interconnect structure disposed in a semiconductor substrate; a first dielectric layer disposed on the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a second interconnect structure disposed in the first and second dielectric layers and electrically connected to the first interconnect structure; and a third interconnect structure disposed in the semiconductor substrate. The first interconnect structure comprises a first conductive line; and a first manganese-containing layer disposed on the first conductive line. The second interconnect structure comprises a second conductive line and a second manganese-containing layer disposed between the second conductive line and the first dielectric layer, and between the second conductive line and the second dielectric layer. The third interconnect structure comprises a third conductive line and a third manganese-containing layer disposed on the third conductive line. The third manganese-containing layer of the third interconnect structure is made of the same material as the first manganese-containing layer of the first interconnect structure. The first and second interconnect structures are disposed in a sparsely patterned area, and the third interconnect structure is disposed in a densely patterned area.

[0007] Another aspect of the present disclosure provides a semiconductor element, comprising: a capacitor contact disposed on a semiconductor substrate; a first dielectric layer disposed on the capacitor contact; a patterned mask disposed on the first dielectric layer; and a bottom capacitor electrode disposed on the capacitor contact and electrically connected to the capacitor contact. The bottom capacitor electrode comprises: a base layer disposed between the capacitor contact and the first dielectric layer; a surrounding portion disposed on the base layer and along the sidewalls of the first dielectric layer and the sidewalls of the patterned mask; and a first interconnect portion disposed between the patterned mask and the base layer. The first interconnect portion is substantially parallel to the base layer. The patterned mask is surrounded by the surrounding portion. The sidewalls of the patterned mask are substantially aligned with the sidewalls of the first dielectric layer.

[0008] Another aspect of the present disclosure provides a semiconductor element, comprising: a first interconnect structure disposed in a semiconductor substrate; a second interconnect structure disposed above the first interconnect structure and electrically connected to the first interconnect structure, wherein the second interconnect structure comprises: a first portion disposed on the first interconnect structure; and a second portion disposed on the first portion; a first dielectric layer disposed above the semiconductor substrate and surrounding the first portion of the second interconnect structure; a top barrier layer disposed between the second portion of the second interconnect structure and the first dielectric layer; and a second dielectric layer disposed above the first dielectric layer, covering the top barrier layer and surrounding the second portion of the second interconnect structure.

[0009] Due to the design of the semiconductor device disclosed herein, the parasitic capacitance of the semiconductor device can be reduced by using a dielectric layer with a lower dielectric constant, thereby improving the performance of the semiconductor device.

[0010] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art of the present disclosure that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art of the present disclosure that such equivalent constructions cannot depart from the concept and scope of the present disclosure as defined by the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A more complete understanding of the present disclosure can be gained by referring to the detailed description and claims in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0012] Figure 1 is a flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0013] Figures 2 to 23 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figures 24 to 26 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0015] Figure 27 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0016] Figure 28 is a top view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0017] Figure 29 and Figure 30 is a cross-sectional view, illustrating Figure 28 The semiconductor components of some embodiments of the present disclosure are shown.

[0018] Explanation of symbols

[0019] 1A: Semiconductor components

[0020] 1B: Semiconductor components

[0021] 1C: Semiconductor components

[0022] 1D: semiconductor components

[0023] 1E: Semiconductor components

[0024] 1F: Semiconductor components

[0025] 10: Manufacturing method

[0026] 101: Substrate

[0027] 101T: Top surface

[0028] 102: Source / drain region

[0029] 103: First bottom conductive layer

[0030] 104: Dielectric layer

[0031] 105: Second bottom conductive layer

[0032] 106: Capacitive contact

[0033] 107: Bottom dielectric layer

[0034] 108: Bottom barrier

[0035] 109: Top dielectric layer

[0036] 110: Basal layer

[0037] 111: Dielectric layer

[0038] 111a: third barrier layer

[0039] 111b: first barrier layer

[0040] 111S: Sidewall

[0041] 113a: Third wire

[0042] 113b: First conductor

[0043] 119a: Third manganese-containing layer

[0044] 119aT: Top surface

[0045] 119b: First manganese-containing layer

[0046] 119bT: Top surface

[0047] 121a: Third interconnect structure

[0048] 121b: first interconnect structure

[0049] 123: Dielectric layer

[0050] 141: Patterned mask

[0051] 141S: Sidewall

[0052] 143': Second barrier layer

[0053] 145': Second manganese-containing layer

[0054] 145'S: Sidewall

[0055] 147': Second conductor

[0056] 147'S: Sidewall

[0057] 149: Second interconnect structure

[0058] 149P1: Top part

[0059] 149P2: bottom part

[0060] 151: Around the part

[0061] 151S: Sidewall

[0062] 153: First Interconnection Section

[0063] 155: Second interconnection section

[0064] 157: Crown structure

[0065] 159: Bottom capacitor electrode

[0066] 200: Non-mixed region conductive structure

[0067] 201: Non-mixed area liner

[0068] 203: Non-mixed area conductive layer

[0069] 203H: horizontal part

[0070] 203V: vertical part

[0071] 205: Non-mixed area hard mask layer

[0072] 300: Mixed area conductive structure

[0073] 301: Mixed area lining layer

[0074] 303: Mixed area conductive layer

[0075] 303H: horizontal part

[0076] 303V: vertical part

[0077] 305: Hybrid region hard mask layer

[0078] 401: Bottom energy removable layer

[0079] 401TS: Top surface

[0080] 403: Top energy removable layer

[0081] 403TS: Top surface

[0082] 411: Bottom porous dielectric layer

[0083] 413: Top porous dielectric layer

[0084] 415: Intermediate porous dielectric layer

[0085] 421: Bottom barrier

[0086] 423: Top barrier layer

[0087] 501: Bottom barrier material

[0088] 503: Top barrier material

[0089] 505: First liner material

[0090] 507: Secondary liner material

[0091] 509: first conductive material

[0092] 511: Second conductive material

[0093] 601: First mask layer

[0094] 603: Second mask layer

[0095] 605: third mask layer

[0096] 607: Fourth mask layer

[0097] 1041: Bottom porous dielectric layer

[0098] 1043: Top porous dielectric layer

[0099] 1061: cushioning layer

[0100] 1063: Conductive layer

[0101] 1063H: horizontal part

[0102] 1063V: vertical part

[0103] A: Pattern-dense area

[0104] B: Sparse pattern area

[0105] MA: Mixed Area

[0106] NMA: Non-Mixed Area

[0107] R1: Non-mixing area notch

[0108] R2: Hybrid Area Notch

[0109] S11: Steps

[0110] S13: Steps

[0111] S15: Steps

[0112] S17: Steps

[0113] VL1: Vertical Height

[0114] VL2: Vertical height

[0115] W1: width

[0116] W2: width

[0117] W3: Width

[0118] W4: Width

[0119] W5: width

[0120] W6: Width

[0121] W7: Width

[0122] W8: Width

[0123] W9: Width

[0124] W10: Width

[0125] W11: Width

[0126] W12: Width

[0127] W13: Width

[0128] W14: Width

[0129] W15: Width DETAILED DESCRIPTION

[0130] The present disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The specific examples of components and configurations described below are to simplify the present disclosure. Of course, these are merely illustrative and are not intended to be limiting. For example, in the description below, forming a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse element symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations discussed.

[0131] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," or similar terms, may be used herein to describe the relative relationship of one element or feature to another element or feature as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of an element in use or operation in addition to the orientation depicted in the figures. The element may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0132] It will be understood that when a component or layer is referred to as being “connected” or “coupled” to another component or layer, it can be directly connected or coupled to the other component or layer, or intervening components or layers may be present.

[0133] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one component from another. Thus, for example, a first component, a first member, or a first portion discussed below could be referred to as a second component, a second member, or a second portion without departing from the teachings of the present disclosure.

[0134] Unless the context indicates otherwise, terms such as "same," "equal," "planar," or "coplanar" as used herein when referring to an orientation, layout, position, shape, size, quantity, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to encompass nearly the same orientation, layout, position, shape, size, quantity, or other measurement within an acceptable range of variation that may occur (e.g., due to manufacturing processes). The term "substantially" may be used herein to reflect this meaning. For example, items described as "substantially the same," "substantially equal," or "substantially coplanar" may be exactly the same, equal, or coplanar, or may be nearly the same, equal, or coplanar within an acceptable range of variation that may occur (e.g., due to manufacturing processes).

[0135] In the present disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices are all included in the category of semiconductor devices.

[0136] It should be noted that, in the description of the present disclosure, upward (or up) corresponds to the direction of the arrow in the Z direction, and downward (or down) corresponds to the opposite direction of the arrow in the Z direction.

[0137] It should be noted that in the description of the present disclosure, the terms "to form", "formed" and "formation" may represent and include any method of creating, constructing, patterning, implanting or depositing an element, a dopant or a material. Examples of formation methods may include but are not limited to atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching and wet etching.

[0138] It should be noted that in the description of the present disclosure, the functions or steps mentioned herein may occur in a different order than that shown in the drawings. For example, two figures shown in succession may actually be performed substantially simultaneously or may sometimes be performed in the opposite order, depending on the functions or steps involved.

[0139] Figure 1 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 23 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device 1A according to an embodiment of the present disclosure.

[0140] See also Figures 1 to 4In step S11, a substrate 101 including a non-mixed area NMA and a mixed area MA can be provided, a first bottom conductive layer 103 can be formed in the mixed area MA, and a second bottom conductive layer 105 can be formed in the non-mixed area NMA, a bottom dielectric layer 107 can be formed on the substrate 101, and a bottom energy removable layer 401 can be formed on the bottom dielectric layer 107.

[0141] See also Figure 2 In some embodiments, the mixed area MA and the non-mixed area NMA may be separated from each other. In some embodiments, the mixed area MA and the non-mixed area NMA may be formed adjacent to each other.

[0142] It should be noted that the mixing area MA may include a portion of the substrate 101 and the space above this portion of the substrate 101. When an element is described as being disposed on the mixing area MA, it means that the element is disposed on the top surface of this portion of the substrate 101. When an element is described as being disposed within the mixing area MA, it means that the element is disposed within the substrate 101; however, the top surface of the element may be flush with the top surface of this portion of the substrate 101. When an element is described as being disposed above (or on) the mixing area MA, it means that the element is disposed above (or above) the top surface of this portion of the substrate 101. Accordingly, the non-mixing area NMA may include another portion of the substrate 101 and the space above this other portion of the substrate 101.

[0143] See also Figure 2 The substrate 101 may include a bulk semiconductor substrate composed entirely of at least one semiconductor material, a plurality of component elements (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The bulk semiconductor substrate may be formed of, for example, an elemental semiconductor such as silicon or germanium; a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors; or a combination thereof.

[0144] In some embodiments, the substrate 101 may also include a semiconductor-on-insulator substrate, which is composed of a handle substrate, an insulator layer and a topmost semiconductor material layer from bottom to top. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulator layer may be a crystalline or amorphous dielectric material, for example, an oxide and / or a nitride. For example, the insulator layer may be a dielectric oxide, for example, silicon oxide. For another example, the insulator layer may be a dielectric nitride, for example, silicon nitride or boron nitride. For another example, the insulator layer may include a stack of dielectric oxides and dielectric nitrides in any order, which is a stack of silicon oxide and either silicon nitride or boron nitride. The insulator layer may have a thickness between about 10 nm and 200 nm.

[0145] It should be noted that in the description of the present disclosure, when the term "about" is used to modify the amount of an ingredient, component, or reactant of the present disclosure, it refers to the variation in the value that may occur, for example, due to the typical measurement and liquid handling procedures used to prepare the concentrate or solution. Furthermore, variations may occur due to inadvertent errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to practice the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2% or 1% of the reported value.

[0146] A plurality of component assemblies may be formed on the substrate 101. Portions of the plurality of component assemblies may be formed within the substrate 101. The plurality of component assemblies may be transistors, such as complementary metal oxide semiconductor transistors, metal oxide semiconductor field effect transistors, fin field effect transistors, other similar transistors, or combinations thereof.

[0147] Multiple dielectric layers can be formed on the substrate 101 and cover multiple component assemblies. In some embodiments, the multiple dielectric layers can be formed of materials such as silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, other similar materials or combinations thereof. The low-k dielectric material can have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material can have a dielectric constant of less than 2.0. The multiple dielectric layers can be formed by a deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition or other similar deposition processes. A planarization process can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0148] Multiple conductive features can include interconnect layers, conductive vias, and conductive pads. The interconnect layers can be separated from each other and can be horizontally arranged in multiple dielectric layers arranged along the Z direction. In the present embodiment, the topmost interconnect layer can be designated as a conductive pad. The conductive vias can connect interconnect layers adjacent to each other along the Z direction, connect component assemblies to adjacent interconnect layers, and / or connect conductive pads to adjacent interconnect layers. In some embodiments, the conductive vias can improve heat dissipation and can provide structural support. In some embodiments, multiple conductive features can be formed by the following materials, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (for example, tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (for example, titanium nitride), transition metal aluminides, or combinations thereof. Multiple conductive features can be formed during the formation of multiple dielectric layers.

[0149] In some embodiments, multiple component assemblies and multiple conductive layers may collectively comprise a functional unit of semiconductor device 1A. In the present disclosure, a functional unit generally refers to functionally related circuits that are divided into distinct units for functional purposes. In some embodiments, a functional unit of semiconductor device 1A may comprise, for example, highly complex circuits such as a processor core, a memory controller, an accelerator unit, or other suitable functional circuits.

[0150] See also Figure 2The first bottom conductive layer 103 may be formed in the mixed area MA. The second bottom conductive layer 105 may be formed in the non-mixed area NMA. In some embodiments, the first bottom conductive layer 103 and the second bottom conductive layer 105 may be referred to as part of the conductive features of the substrate 101. In some embodiments, the first bottom conductive layer 103 and the second bottom conductive layer 105 may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, the width W1 of the first bottom conductive layer 103 and the width W2 of the second bottom conductive layer 105 may be substantially the same. In some embodiments, the width W1 of the first bottom conductive layer 103 and the width W2 of the second bottom conductive layer 105 may be different. The top surface of the substrate 101, the top surface of the first bottom conductive layer 103, and the top surface of the second bottom conductive layer 105 may be substantially coplanar.

[0151] See also Figure 3 A bottom dielectric layer 107 may be formed on the substrate 101 to cover the non-mixed area NMA and the mixed area MA. In some embodiments, the bottom dielectric layer 107 may be formed of a porous dielectric material having a low porosity. For example, the porosity of the bottom dielectric layer 107 may be less than 5%, less than 4%, less than 3%, less than 2%, less than 1%, or 0%. In some embodiments, the bottom dielectric layer 107 may be formed of, for example, silicon oxide. In some embodiments, the bottom dielectric layer 107 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0152] See also Figure 4 , the bottom energy removable layer 401 can be formed on the bottom dielectric layer 107. The bottom energy removable layer 401 can completely cover the non-mixed area NMA and the mixed area MA. In some embodiments, the bottom energy removable layer 401 may include the following materials, for example, a thermally decomposable material, a photon decomposable material, an electron beam decomposable material, or a combination thereof. For example, the bottom energy removable layer 401 may include a base material and a decomposable porogen material, which is sacrificially removed once exposed to an energy source. The base material may include a methylsilsesquioxane-based material. The decomposable porogen material may include a porogen organic compound that provides porosity to the base material of the bottom energy removable layer 401.

[0153] In some embodiments, the bottom energy removable layer 401 may comprise approximately 55% of a decomposable porogen material component and approximately 45% of a substrate material component. In some embodiments, the bottom energy removable layer 401 may comprise approximately 45% of a decomposable porogen material component and approximately 55% of a substrate material component. In some embodiments, the bottom energy removable layer 401 may comprise approximately 35% of a decomposable porogen material component and approximately 65% ​​of a substrate material component. In some embodiments, the bottom energy removable layer 401 may comprise approximately 25% of a decomposable porogen material component and approximately 75% of a substrate material component. In some embodiments, the bottom energy removable layer 401 may comprise approximately 15% of a decomposable porogen material component and approximately 85% of a substrate material component.

[0154] See also Figure 1 and Figures 5 to 12 In step S13 , a non-mixed region conductive structure 200 may be formed on the non-mixed region NMA of the substrate 101 .

[0155] See also Figure 5 A layer of bottom barrier material 501 may be formed on the bottom energy removable layer 401. This layer of bottom barrier material 501 may completely cover the non-mixed area NMA and the mixed area MA. In some embodiments, the bottom barrier material 501 may be a material having an etching selectivity to the material of the bottom energy removable layer 401. In some embodiments, the bottom barrier material 501 may be a material having an etching selectivity to aluminum, copper, or tungsten. In some embodiments, the bottom barrier material 501 may be, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof. In some embodiments, the bottom barrier material layer 501 may be formed by, for example, atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0156] It should be noted that silicon oxynitride in this disclosure refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0157] See also Figure 5 , a first mask layer 601 may be formed on this layer of bottom barrier material 501. In some embodiments, the first mask layer 601 may be a photoresist layer and may include a pattern of the bottom barrier layer 421, which will be described below. The pattern of the first mask layer 601 may be formed by a photolithography process. The unpatterned first mask layer 601 (not shown) Figure 5 in) can be made according to the mask (not shown in Figure 5The process light is exposed to process light (in the process light). The wavelength of the process light can be related to the critical dimension of the pattern. In some embodiments, the process light can be deep ultraviolet (DUV) radiation. In some embodiments, the process light can be extreme ultraviolet (EUV) radiation, and the photolithography process can be EUV lithography. After the first mask layer 601 is exposed to the process light, the pattern on the mask is transferred to the unpatterned first mask layer 601. In this way, the unpatterned first mask layer 601 can be etched according to the transferred pattern, thereby forming a pattern on the first mask layer 601.

[0158] See also Figure 6 A first barrier layer etching process can be performed using the first mask layer 601 as a mask to remove a portion of the bottom barrier material 501. In some embodiments, during the first barrier layer etching process, the ratio of the etching rate of the bottom barrier material 501 relative to the etching rate of the bottom energy-removable layer 401 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 3:1, or between approximately 10:1 and approximately 5:1. After the first barrier layer etching process, the remaining bottom barrier material 501 can be converted into a bottom barrier layer 421. The bottom barrier layer 421 can be formed above the non-mixed area NMA and on the bottom energy-removable layer 401. In some embodiments, the width W3 of the bottom barrier layer 421 can be greater than the width W2 of the second bottom conductive layer 105. In some embodiments, the width W3 of the bottom barrier layer 421 can be substantially the same as the width W2 of the second bottom conductive layer 105. In some embodiments, the width W3 of the bottom barrier layer 421 can be less than the width W2 of the second bottom conductive layer 105. The first mask layer 601 may be removed after forming the bottom barrier layer 421 .

[0159] See also Figure 7 A second mask layer 603 may be formed on the bottom energy removable layer 401 and may cover a portion of the bottom barrier layer 421. The second mask layer 603 may include a pattern of non-mixed region recesses R1, which will be described below. The pattern of the second mask layer 603 may be formed using a similar process to that of the first mask layer 601 and will not be further described herein.

[0160] See also Figure 8A first recess etching process may be performed to remove a portion of the bottom barrier layer 421, a portion of the bottom energy-removable layer 401, and a portion of the bottom dielectric layer 107. In some embodiments, the first recess etching process may be a multi-stage etching process. For example, the first recess etching process may be a three-stage anisotropic dry etching process. The etching chemistry of the first recess etching process may be different in each stage to provide different etching selectivities. In some embodiments, during the first stage of the first recess etching process, the ratio of the etching rate of the bottom barrier layer 421 to the etching rate of the bottom energy-removable layer 401 may be between approximately 100:1 and approximately 1.05, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. In some embodiments, during the second stage of the first recess etching process, the ratio of the etching rate of the bottom energy-removable layer 401 to the etching rate of the bottom dielectric layer 107 may be between approximately 100:1 and approximately 1.05, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. In some embodiments, during the third stage of the first recess etching process, a ratio of an etch rate of the bottom dielectric layer 107 relative to an etch rate of the second bottom conductive layer 105 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0161] See also Figure 8 After the first recess etching process, a non-mixed region recess R1 may be formed in the bottom barrier layer 421, the bottom energy removable layer 401, and the bottom dielectric layer 107. The second bottom conductive layer 105 may be partially exposed through the non-mixed region recess R1. In some embodiments, a width W4 of the non-mixed region recess R1 may be smaller than a width W2 of the second bottom conductive layer 105 and smaller than a width W3 of the bottom barrier layer 421. After forming the non-mixed region recess R1, the second mask layer 603 may be removed.

[0162] See also Figure 9 A layer of first liner material 505 may be conformally formed on the bottom energy removable layer 401, the bottom barrier layer 421, the non-mixed region recess R1, and the second bottom conductive layer 105. In some embodiments, the first liner material 505 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the first liner material 505 may be formed by, for example, chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0163] For example, the first liner material 505 can be formed by chemical vapor deposition. In some embodiments, the formation of the first liner material 505 can include a source gas introduction step, a first purge step, a reactant flow step, and a second purge step. The source gas introduction step, the first purge step, the reactant flow step, and the second purge step can be referred to as a cycle. Multiple cycles can be performed to achieve the desired thickness of the first liner material 505.

[0164] Figure 8 The intermediate semiconductor element shown can be loaded into a reaction chamber. In the source gas introduction step, a source gas containing a precursor and a reactant can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursor and the reactant can diffuse across the boundary layer and reach the surface of the intermediate semiconductor element (i.e., the surface of the bottom energy removable layer 401, the surface of the bottom barrier layer 421, the surface of the non-mixed region recess R1, and the surface of the second bottom conductive layer 105). The precursor and the reactant can be adsorbed on the above-mentioned surface and then migrate on the above-mentioned surface. The adsorbed precursor and the adsorbed reactant can react on the above-mentioned surface and form solid by-products. The solid by-products can form nuclei on the aforementioned surface. The nuclei can grow into islands and the islands can merge into a continuous thin film on the above-mentioned surface. In the first purge step, a purge gas (e.g., argon) can be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors, and unreacted reactants.

[0165] In the reactant flow step, reactants may be introduced separately into the reaction chamber to convert the continuous film into the first liner material layer 505. In the second purge step, a purge gas (e.g., argon) may be injected into the reaction chamber to purge out gaseous byproducts and unreacted reactants.

[0166] In some embodiments, the formation of the layer of first liner material 505 using chemical vapor deposition can be performed with the assistance of plasma. The source of the plasma can be, for example, argon, hydrogen, or a combination thereof.

[0167] In some embodiments, the precursor may be titanium tetrachloride. The reactant may be ammonia. Due to incomplete reaction between titanium tetrachloride and ammonia, the titanium tetrachloride and ammonia may react on the surface and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step can reduce the chloride content of the titanium nitride film. After the ammonia treatment, the titanium nitride film can be referred to as the first liner material 505.

[0168] In other embodiments, the layer of first liner material 505 can be formed by atomic layer deposition, such as light-assisted atomic layer deposition or liquid injection atomic layer deposition. In some embodiments, forming the layer of first liner material 505 can include a first precursor introduction step, a first purge step, a second precursor introduction step, and a second purge step. The first precursor introduction step, the first purge step, the second precursor introduction step, and the second purge step can be referred to as a cycle. Multiple cycles can be performed to achieve a desired thickness of the layer of first liner material 505.

[0169] Figure 8 The intermediate semiconductor element shown can be loaded into the reaction chamber. In the first precursor introduction step, the first precursor can be introduced into the reaction chamber. The first precursor can diffuse across the boundary layer and reach the surface of the intermediate semiconductor element (i.e., the surface of the bottom energy removable layer 401, the surface of the bottom barrier layer 421, the surface of the non-mixed region recess R1, and the surface of the second bottom conductive layer 105). The first precursor can be adsorbed on the above-mentioned surfaces to form a monolayer at the level of a single atomic layer. In the first purge step, a purge gas (e.g., argon) can be injected into the reaction chamber to purge out unreacted first precursor.

[0170] In the second precursor introduction step, a second precursor can be introduced into the reaction chamber. The second precursor can react with the monolayer and convert the monolayer into the first liner material 505. In the second purge step, a purge gas (e.g., argon) can be injected into the reaction chamber to purge out unreacted second precursor and gaseous byproducts. Compared to chemical vapor deposition, because the first and second precursors are introduced separately, particle generation caused by gas phase reactions can be suppressed.

[0171] In some embodiments, the first precursor may be titanium tetrachloride. The second precursor may be ammonia. The adsorbed titanium tetrachloride may form a titanium nitride monolayer. The ammonia introduced during the second precursor introduction step may react with the titanium nitride monolayer and convert it into the first liner material 505.

[0172] In some embodiments, the formation of the first liner material 505 using atomic layer deposition can be performed with the assistance of plasma. The plasma source can be, for example, argon, hydrogen, oxygen, or a combination thereof. In some embodiments, the oxygen source can be, for example, water, oxygen, or ozone. In some embodiments, a co-reactant can be introduced into the reaction chamber. The co-reactant can be selected from the group consisting of hydrogen, hydrogen plasma, oxygen, air, water, ammonia, hydrazine, alkylhydrazine, borane, silane, ozone, and combinations thereof.

[0173] In some embodiments, the formation of the first liner material 505 can be performed using the following process conditions: The substrate temperature can be between approximately 160° C. and approximately 300° C. The evaporator temperature can be approximately 175° C. The pressure of the reaction chamber can be approximately 5 mbar. The solvent for the first and second precursors can be toluene.

[0174] See also Figure 10 A layer of first conductive material 509 may be formed on the first liner material 505 and may completely fill the non-mixed region recess R1. In some embodiments, the first conductive material 509 may include aluminum, copper, tungsten, or a combination thereof. In some embodiments, the first conductive material 509 may be formed by, for example, physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, or other suitable deposition processes.

[0175] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed on the layer of first conductive material 509 to provide a substantially planar surface for subsequent process steps.

[0176] See also Figure 11 A non-mixed region hard mask layer 205 may be formed on the first conductive material 509 and above the bottom barrier layer 421. In some embodiments, a width W5 of the non-mixed region hard mask layer 205 may be less than a width W3 of the bottom barrier layer 421. In some embodiments, a width W5 of the non-mixed region hard mask layer 205 may be greater than a width W2 of the second bottom conductive layer 105. In some embodiments, the width W5 of the non-mixed region hard mask layer 205 and the width W2 of the second bottom conductive layer 105 may be substantially the same.

[0177] In some embodiments, the non-mixed region hard mask layer 205 can be formed of a material, such as a material having etching selectivity with respect to the first conductive material 509, the first liner material 505, or the material of the bottom barrier layer 421. In some embodiments, the non-mixed region hard mask layer 205 can be formed of a material, such as silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide, similar materials, or combinations thereof. In some embodiments, the non-mixed region hard mask layer 205 can be formed by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or the like. The process temperature for forming the non-mixed region hard mask layer 205 can be less than 400° C.

[0178] In some embodiments, the non-mixed region hard mask layer 205 can be formed of a material such as boron nitride, silicon boron nitride, boron phosphorus nitride, silicon carbon boron nitride, or the like. In some embodiments, the non-mixed region hard mask layer 205 can be formed by a film formation process and a treatment process. During the film formation process, a first precursor (which can be a boron-based precursor) can be introduced onto the first conductive material 509 to form a boron-based layer. Subsequently, during the treatment process, a second precursor (which can be a nitrogen-based precursor) can be introduced to react with the boron-based layer and convert the boron-based layer into the non-mixed region hard mask layer 205.

[0179] In some embodiments, the first precursor can be, for example, diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursor can be introduced at a flow rate between about 5 sccm (standard cubic centimeters per minute) and about 50 slm (standard liters per minute), or between about 10 sccm and about 1 slm. In some embodiments, the first precursor can be introduced with a diluent gas, such as nitrogen, hydrogen, argon, or a combination thereof. The diluent gas can be introduced at a flow rate between about 5 sccm and about 50 slm, or between about 1 slm and about 10 slm.

[0180] In some embodiments, the film forming process may be performed without plasma assistance. In this case, the substrate temperature of the film forming process may be between about 100° C. and about 1000° C. For example, the substrate temperature of the film forming process may be between about 300° C. and about 500° C. The process pressure of the film forming process may be between about 10 mTorr (milliTorr) and about 760 Torr (Torr). For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr.

[0181] In some embodiments, the film forming process may be performed in the presence of plasma. In this case, the substrate temperature of the film forming process may be between about 100° C. and about 1000° C. For example, the substrate temperature of the film forming process may be between about 300° C. and about 500° C. The process pressure of the film forming process may be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr. The plasma may be generated by a radio frequency (RF) power between 2 W and 5000 W. For example, the RF power may be between 30 W and 1000 W.

[0182] In some embodiments, the second precursor can be, for example, ammonia or hydrazine. In some embodiments, the second precursor can be introduced at a flow rate between about 5 sccm and about 50 slm or between about 10 sccm and about 1 slm.

[0183] In some embodiments, an oxygen-based precursor may be introduced into the treatment process along with the second precursor. The oxygen-based precursor may be, for example, oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0184] In some embodiments, a silicon-based precursor may be introduced into the process along with the second precursor. The silicon-based precursor may be, for example, silane, trisilylamine, trimethylsilane, or a silazane (eg, hexamethylcyclotrisilazane).

[0185] In some embodiments, a phosphorus-based precursor may be introduced into the treatment process along with the second precursor. The phosphorus-based precursor may be, for example, phosphine.

[0186] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor may be introduced together with the second precursor during the treatment process.

[0187] In some embodiments, the treatment process may be performed with the assistance of a plasma process, a UV curing process, a thermal annealing process, or a combination thereof.

[0188] When the treatment is performed with the assistance of a plasma process, the plasma of the plasma process can be generated by RF power. In some embodiments, the RF power can be between about 2 W and about 5000 W at a single low frequency between about 100 kHz and up to about 1 MHz. In some embodiments, the RF power can be between about 30 W and about 1000 W at a single high frequency greater than about 13.6 MHz. In this case, the substrate temperature during the treatment process can be between about 20° C. and about 1000° C. The process pressure during the treatment process can be between about 10 mTorr and about 760 Torr.

[0189] When the treatment is performed with the assistance of a UV curing process, the substrate temperature of the treatment process can be between approximately 20°C and approximately 1000°C. The process pressure of the treatment process can be between approximately 10 mTorr and approximately 760 Torr. UV curing can be provided by any UV light source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or a high-efficiency UV light-emitting diode array. The UV light source can have a wavelength between approximately 170 nm and approximately 400 nm. The UV light source can provide a photon energy between approximately 0.5 eV and approximately 10 eV, or between approximately 1 eV and approximately 6 eV. The assistance of the UV curing process can remove hydrogen from the non-mixed region hard mask layer 205. Because hydrogen can diffuse into other regions of the semiconductor device 1A and potentially reduce the reliability of the semiconductor device 1A, removing hydrogen with the assistance of the UV curing process can improve the reliability of the semiconductor device 1A. In addition, the UV curing process can increase the density of the non-mixed region hard mask layer 205.

[0190] When the treatment is performed with the assistance of a thermal annealing process, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0191] See also Figure 12 A first etching process can be performed using the non-mixed region hard mask layer 205 as a mask to remove a portion of the first conductive material 509 and a portion of the first liner material 505. In some embodiments, the first etching process can be a multi-stage etching process. For example, the first etching process can be a two-stage anisotropic dry etching process. The etching chemistry in each stage can be different to provide different etching selectivities. In some embodiments, during the first stage of the first etching process, the ratio of the etching rate of the first conductive material 509 to the etching rate of the non-mixed region hard mask layer 205 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 3:1. In some embodiments, during the first stage of the first etching process, the ratio of the etching rate of the first conductive material 509 to the etching rate of the first liner material 505 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 3:1.

[0192] In some embodiments, during the second stage of the first etching process, a ratio of the etch rate of the first liner material 505 to the etch rate of the non-mixed region hard mask layer 205 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1. In some embodiments, during the second stage of the first etching process, a ratio of the etch rate of the first liner material 505 to the etch rate of the bottom barrier layer 421 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1. In some embodiments, during the second stage of the first etching process, a ratio of the etch rate of the first liner material 505 to the etch rate of the bottom energy removable layer 401 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1.

[0193] See also Figure 12 After the first etching process, the remaining first conductive material 509 can be referred to as a non-mixed region conductive layer 203. The remaining first liner material 505 can be referred to as a non-mixed region liner layer 201. The non-mixed region liner layer 201, the non-mixed region conductive layer 203, and the non-mixed region hard mask layer 205 together constitute a non-mixed region conductive structure 200. The non-mixed region conductive structure 200 can be formed on the second bottom conductive layer 105 and the non-mixed region NMA.

[0194] See also Figure 12 The non-mixed region conductive layer 203 may include a vertical portion 203V and a horizontal portion 203H. The vertical portion 203V may be disposed on the second bottom conductive layer 105 and within the non-mixed region recess R1. The top portion of the vertical portion 203V may protrude from the top surface 401TS of the bottom energy removable layer 401 and may be surrounded by the bottom barrier layer 421. In other words, the top surface of the vertical portion 203V may be at a vertical height VL1, and this vertical height VL1 may be higher than the top surface 401TS of the bottom energy removable layer 401. The bottom portion of the vertical portion 203V may be surrounded by the bottom dielectric layer 107. In some embodiments, the width W6 of the vertical portion 203V may be less than the width W5 of the non-mixed region hard mask layer 205.

[0195] See also Figure 12, the horizontal portion 203H may be disposed on the vertical portion 203V and the bottom barrier layer 421. In some embodiments, the horizontal portion 203H may have the same width W5 as the non-mixed region hard mask layer 205. In some embodiments, the width W5 of the horizontal portion 203H may be greater than the width W6 of the vertical portion 203V. That is, the non-mixed region conductive layer 203 may have a T-shaped cross-sectional profile. In some embodiments, the width W5 of the horizontal portion 203H may be less than the width W3 of the bottom barrier layer 421.

[0196] See also Figure 12 The non-mixed region liner layer 201 may be conformably disposed between the non-mixed region conductive layer 203 and the bottom energy removable layer 401, between the non-mixed region conductive layer 203 and the bottom barrier layer 421, between the non-mixed region conductive layer 203 and the bottom dielectric layer 107, and between the non-mixed region conductive layer 203 and the second bottom conductive layer 105. The non-mixed region liner layer 201 may be conformably disposed between the horizontal portion 203H and the bottom barrier layer 421, between the vertical portion 203V and the bottom barrier layer 421, between the vertical portion 203V and the bottom energy removable layer 401, between the vertical portion 203V and the bottom dielectric layer 107, and between the vertical portion 203V and the second bottom conductive layer 105. The non-mixed region liner layer 201 can improve the adhesion between the non-mixed region conductive layer 203 and the bottom barrier layer 421, between the non-mixed region conductive layer 203 and the bottom energy removable layer 401, between the non-mixed region conductive layer 203 and the bottom dielectric layer 107, and between the non-mixed region conductive layer 203 and the second bottom conductive layer 105. The non-mixed region liner layer 201 can also prevent metal ions from diffusing from the non-mixed region conductive layer 203 to the bottom energy removable layer 401 or the substrate 101.

[0197] See also Figure 1 and Figures 13 to 21 In step S15 , a mixed region conductive structure 300 may be formed on the mixed region MA of the substrate 101 .

[0198] See also Figure 13, a top energy removable layer 403 can be formed on the bottom energy removable layer 401, and can cover the non-mixed region conductive structure 200 and the bottom barrier layer 421. The top energy removable layer 403 can completely cover the non-mixed region NMA and the mixed region MA. In some embodiments, the top energy removable layer 403 may include the following materials, for example, a thermally decomposable material, a photon decomposable material, an electron beam decomposable material, or a combination thereof. For example, the top energy removable layer 403 may include a base material and a decomposable porogen material, which is sacrificially removed once exposed to an energy source. The base material may include a methyl silsesquioxane-based material. The decomposable porogen material may include a porogen organic compound that provides porosity to the base material of the top energy removable layer 403.

[0199] In some embodiments, the percentage composition of the substrate material in the top energy removable layer 403 may be less than the percentage composition of the substrate material in the bottom energy removable layer 401. In some embodiments, the top energy removable layer 403 may include approximately 55% decomposable porogen material components and approximately 45% substrate material components. In some embodiments, the top energy removable layer 403 may include approximately 65% ​​decomposable porogen material components and approximately 35% substrate material components. In some embodiments, the top energy removable layer 403 may include approximately 75% decomposable porogen material components and approximately 25% substrate material components. In some embodiments, the top energy removable layer 403 may include approximately 85% decomposable porogen material components and approximately 15% substrate material components.

[0200] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially planar surface for subsequent processing steps.

[0201] See also Figure 14 A layer of top barrier material 503 may be formed on the top energy removable layer 403. This layer of top barrier material 503 may completely cover the non-mixed area NMA and the mixed area MA. In some embodiments, the top barrier material 503 may be a material having an etch selectivity to the material of the top energy removable layer 403. In some embodiments, the top barrier material 503 may be a material having an etch selectivity to aluminum, copper, or tungsten. In some embodiments, the top barrier material 503 may be, for example, silicon nitride, silicon oxynitride, silicon nitride oxide, or a combination thereof. In some embodiments, the top barrier material 503 may be formed by, for example, atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0202] See also Figure 14, a third mask layer 605 may be formed on this layer of top barrier material 503. In some embodiments, the third mask layer 605 may be a photoresist layer and may include a pattern of the top barrier layer 423, which will be described below. The pattern of the third mask layer 605 may be formed by a photolithography process. The unpatterned third mask layer 605 (not shown) Figure 14 in) can be made according to the mask (not shown in Figure 14 The process light is exposed to process light (in the process light). The wavelength of the process light can be associated with the critical dimension of the pattern. In some embodiments, the process light can be deep ultraviolet (DUV) radiation. In some embodiments, the process light can be extreme ultraviolet (EUV) radiation, and the photolithography process can be EUV lithography. After the unpatterned third mask layer 605 is exposed to the process light, the pattern on the mask is transferred to the unpatterned third mask layer 605. In this way, the unpatterned third mask layer 605 can be etched according to the transferred pattern, thereby forming a pattern on the third mask layer 605.

[0203] See also Figure 15 , a second barrier layer etching process can be performed using the third mask layer 605 as a mask to remove a portion of the top barrier material 503. In some embodiments, during the second barrier layer etching process, a ratio of an etching rate of the top barrier material 503 relative to an etching rate of the top energy-removable layer 403 can be between about 100:1 and about 1.05:1, between about 15:1 and about 3:1, or between about 10:1 and about 5:1. After the second barrier layer etching process, the remaining top barrier material 503 can be converted into a top barrier layer 423. The top barrier layer 423 can be formed on the mixed region MA and the top energy-removable layer 403.

[0204] In some embodiments, the width W7 of the top barrier layer 423 may be greater than the width W1 of the first bottom conductive layer 103. In some embodiments, the width W7 of the top barrier layer 423 may be substantially the same as the width W1 of the first bottom conductive layer 103. In some embodiments, the width W7 of the top barrier layer 423 may be less than the width W1 of the first bottom conductive layer 103. In some embodiments, the width W7 of the top barrier layer 423 may be substantially the same as the width W3 of the bottom barrier layer 421. In some embodiments, the width W7 of the top barrier layer 423 may be different from the width W3 of the bottom barrier layer 421. The third mask layer 605 may be removed after forming the top barrier layer 423.

[0205] See also Figure 16A fourth mask layer 607 may be formed on the top energy removable layer 403 and may cover a portion of the top barrier layer 423. The fourth mask layer 607 may include a pattern of a hybrid region recess R2, which will be described below. The pattern of the fourth mask layer 607 may be formed using a process similar to that of the third mask layer 605 and will not be further described herein.

[0206] See also Figure 17 A second recess etching process may be performed to remove a portion of the top barrier layer 423, a portion of the top energy removable layer 403, a portion of the bottom energy removable layer 401, and a portion of the bottom dielectric layer 107. In some embodiments, the second recess etching process may be a multi-stage etching process. For example, the second recess etching process may be a three-stage anisotropic dry etching process. The etching chemistry in each stage may be different to provide different etching selectivities.

[0207] In some embodiments, during the first stage of the second recess etch process, a ratio of the etch rate of the top barrier layer 423 relative to the etch rate of the top energy-removable layer 403 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, during the second stage of the second recess etch process, a ratio of the etch rate of the top energy-removable layer 403 (and the bottom energy-removable layer 401) relative to the etch rate of the bottom dielectric layer 107 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, during the third stage of the second recess etching process, a ratio of an etch rate of the bottom dielectric layer 107 relative to an etch rate of the first bottom conductive layer 103 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0208] See also Figure 17 After the second recess etching process, a hybrid region recess R2 may be formed in the top barrier layer 423, the top energy removable layer 403, the bottom energy removable layer 401, and the bottom dielectric layer 107. The first bottom conductive layer 103 may be partially exposed through the hybrid region recess R2. In some embodiments, a width W8 of the hybrid region recess R2 may be less than a width W1 of the first bottom conductive layer 103 and less than a width W7 of the top barrier layer 423. After forming the hybrid region recess R2, the fourth mask layer 607 may be removed.

[0209] See also Figure 18A layer of second liner material 507 may be conformally formed on the top energy removable layer 403, the top barrier layer 423, the sidewalls of the hybrid region recess R2, and the first bottom conductive layer 103. In some embodiments, the second liner material 507 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. In some embodiments, the second liner material 507 may be formed by, for example, chemical vapor deposition, atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0210] In some embodiments, the second liner material 507 may be the same material as the first liner material 505. The formation of the second liner material 507 may be similar to the formation of the first liner material 505. Figure 9 As shown, the description is not repeated here.

[0211] See also Figure 19 A layer of second conductive material 511 may be formed on the second liner material 507 and may completely fill the hybrid region recess R2. In some embodiments, the second conductive material 511 may include aluminum, copper, tungsten, or a combination thereof. In some embodiments, the second conductive material 511 may be formed by, for example, physical vapor deposition, sputtering, electroplating, electroless plating, chemical vapor deposition, or other suitable deposition processes.

[0212] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed on the layer of second conductive material 511 to provide a substantially planar surface for subsequent process steps.

[0213] See also Figure 20 A hybrid region hard mask layer 305 may be formed on the layer of second conductive material 511 and above the top barrier layer 423. In some embodiments, a width W9 of the hybrid region hard mask layer 305 may be less than a width W7 of the top barrier layer 423. In some embodiments, a width W5 of the hybrid region hard mask layer 305 may be greater than a width W1 of the first bottom conductive layer 103. In some embodiments, the width W9 of the hybrid region hard mask layer 305 and the width W1 of the first bottom conductive layer 103 may be substantially the same. In some embodiments, the width W9 of the hybrid region hard mask layer 305 and the width W5 of the non-hybrid region hard mask layer 205 may be substantially the same. In some embodiments, the width W9 of the hybrid region hard mask layer 305 and the width W5 of the non-hybrid region hard mask layer 205 may be different.

[0214] In some embodiments, the hybrid region hard mask layer 305 can be formed of a material such as a material having etching selectivity to the second conductive material 511, the second liner material 507, and the top barrier layer 423. In some embodiments, the hybrid region hard mask layer 305 can be formed of a material such as silicon, silicon germanium, tetraethyl orthosilicate, silicon nitride, silicon oxynitride, silicon nitride oxide, silicon carbide, or similar materials, or a combination thereof. In some embodiments, the hybrid region hard mask layer 305 can be formed of a material such as boron nitride, silicon boron nitride, phosphorus boron nitride, boron carbon silicon nitride, or similar materials. The pattern of the hybrid region hard mask layer 305 can be formed by a process similar to that of the non-hybrid region hard mask layer 205, such as Figure 11 As shown, the description is not repeated here.

[0215] See also Figure 21 A second etching process can be performed using the mixed region hard mask layer 305 as a mask to remove a portion of the second conductive material 511 and a portion of the second liner material 507. In some embodiments, the second etching process can be a multi-stage etching process. For example, the second etching process can be a two-stage anisotropic dry etching process. The etching chemistry in each stage can be different to provide different etching selectivities. In some embodiments, during the first stage of the second etching process, the ratio of the etching rate of the second conductive material 511 to the etching rate of the mixed region hard mask layer 305 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 3:1. In some embodiments, during the first stage of the second etching process, the ratio of the etching rate of the second conductive material 511 to the etching rate of the second liner material 507 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 5:1, or between approximately 10:1 and approximately 3:1.

[0216] In some embodiments, during the second stage of the second etch process, the ratio of the etch rate of the second liner material 507 relative to the etch rate of the hybrid region hard mask layer 305 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1. In some embodiments, during the second stage of the second etch process, the ratio of the etch rate of the second liner material 507 relative to the etch rate of the top barrier layer 423 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1. In some embodiments, during the second stage of the second etch process, the ratio of the etch rate of the second liner material 507 relative to the etch rate of the top energy removable layer 403 may be between about 100:1 and about 1.05:1, between about 15:1 and about 5:1, or between about 10:1 and about 3:1.

[0217] See also Figure 21 After the second etching process, the remaining second conductive material 511 can be referred to as a hybrid region conductive layer 303. The remaining second liner material 507 can be referred to as a hybrid region liner layer 301. The hybrid region liner layer 301, the hybrid region conductive layer 303, and the hybrid region hard mask layer 305 together constitute a hybrid region conductive structure 300. The hybrid region conductive structure 300 can be formed on the first bottom conductive layer 103 and the hybrid region MA.

[0218] See also Figure 21 The hybrid region conductive layer 303 may include a vertical portion 303V and a horizontal portion 303H. The vertical portion 303V may be disposed on the first bottom conductive layer 103 and within the hybrid region recess R2. The top portion of the vertical portion 303V may protrude from the top surface 403TS of the top energy removable layer 403 and may be surrounded by the top barrier layer 423. In other words, the top surface of the vertical portion 303V may be at a vertical height VL2, which is higher than the top surface 403TS of the top energy removable layer 403. The bottom portion of the vertical portion 303V may be surrounded by the bottom dielectric layer 107. In some embodiments, the width W10 of the vertical portion 303V may be less than the width W9 of the hybrid region hard mask layer 305. In some embodiments, the width W10 of the vertical portion 303V may be substantially the same as the width W6 of the vertical portion 203V. In some embodiments, the width W10 of the vertical portion 303V may be different from the width W6 of the vertical portion 203V.

[0219] See also Figure 21Horizontal portion 303H may be disposed on vertical portion 303V and top barrier layer 423. In some embodiments, horizontal portion 303H may have the same width W9 as hybrid region hard mask layer 305. In some embodiments, width W9 of horizontal portion 303H may be greater than width W10 of vertical portion 303V. That is, hybrid region conductive layer 303 may have a T-shaped cross-sectional profile. In some embodiments, width W9 of horizontal portion 303H may be less than width W7 of top barrier layer 423. In some embodiments, width W9 of horizontal portion 303H may be substantially the same as width W5 of horizontal portion 203H. In some embodiments, width W9 of horizontal portion 303H may be different from width W5 of horizontal portion 203H.

[0220] See also Figure 21 The mixed region liner layer 301 can be conformably disposed between the mixed region conductive layer 303 and the bottom energy removable layer 401, between the mixed region conductive layer 303 and the top barrier layer 423, between the mixed region conductive layer 303 and the bottom dielectric layer 107, and between the mixed region conductive layer 303 and the first bottom conductive layer 103.

[0221] The mixed region liner layer 301 may be conformably disposed between the horizontal portion 303H and the top barrier layer 423, between the vertical portion 303V and the top barrier layer 423, between the vertical portion 303V and the bottom energy removable layer 401, between the vertical portion 303V and the bottom dielectric layer 107, and between the vertical portion 303V and the first bottom conductive layer 103. The mixed region liner layer 301 may improve adhesion between the mixed region conductive layer 303 and the top barrier layer 423, between the mixed region conductive layer 303 and the top energy removable layer 403, between the mixed region conductive layer 303 and the bottom dielectric layer 107, and between the mixed region conductive layer 303 and the first bottom conductive layer 103. The mixed region liner layer 301 may also prevent metal ions from diffusing from the mixed region conductive layer 303 to the bottom energy removable layer 401, the top energy removable layer 403, or the substrate 101.

[0222] See also Figure 1 、 Figure 22 and Figure 23 In step S17, energy treatment may be performed to transform the bottom energy-removable layer 401 into a bottom porous dielectric layer 411, transform the top energy-removable layer 403 into a top porous dielectric layer 413, form an intermediate porous dielectric layer 415 above the mixed area MA of the substrate 101 and between the bottom porous dielectric layer 411 and the top porous dielectric layer 413, and form a top dielectric layer 109 on the top porous dielectric layer 413.

[0223] See also Figure 22 , you can Figure 21 The intermediate semiconductor element shown is subjected to an energy source for energy treatment. This energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy treatment may be between about 800° C. and about 900° C. When light is used as the energy source, ultraviolet light may be applied. The energy treatment may remove the decomposable porogen material from the bottom energy-removable layer 401 and the top energy-removable layer 403 to create empty spaces (pores), while the substrate material remains in place. These empty spaces may be filled with air, so that the dielectric constant of the resulting layer containing these empty spaces may be significantly lower.

[0224] After the energy treatment, the bottom energy-removable layer 401 can be converted into a bottom porous dielectric layer 411. The bottom porous dielectric layer 411 can be disposed on the bottom dielectric layer 107 and above the non-mixed area NMA and the mixed area MA of the substrate 101. The top energy-removable layer 403 can be converted into a top porous dielectric layer 413. The top porous dielectric layer 413 can be disposed on the bottom porous dielectric layer 411 and above the non-mixed area NMA and the mixed area MA of the substrate 101. In some embodiments, the porosity of the top porous dielectric layer 413 can be greater than the porosity of the bottom porous dielectric layer 411.

[0225] In some embodiments, above the mixing region MA, because there is no barrier layer between the bottom energy-removable layer 401 and the top energy-removable layer 403, the bottom energy-removable layer 401 and the top energy-removable layer 403 can mix at the interface between the two energy-removable layers 401 and 403. As a result, after energy treatment, an intermediate porous dielectric layer 415 can be formed between the bottom porous dielectric layer 411 and the top porous dielectric layer 413 and only above the mixing region MA. In some embodiments, the porosity of the intermediate porous dielectric layer 415 can be less than the porosity of the top porous dielectric layer 413 and can be greater than the porosity of the bottom porous dielectric layer 411. In some embodiments, the interface between the top porous dielectric layer 413 and the intermediate porous dielectric layer 415 can be fuzzy. In some embodiments, the interface between the intermediate porous dielectric layer 415 and the bottom porous dielectric layer 411 can be fuzzy.

[0226] In some embodiments, the porosity of the middle porous dielectric layer 415 may gradually decrease at decreasing distances above the substrate 101. In some embodiments, the porosity of the bottom dielectric layer 107 may be less than the porosity of the bottom porous dielectric layer 411, the porosity of the middle porous dielectric layer 415, or the porosity of the top porous dielectric layer 413.

[0227] See also Figure 23, a top dielectric layer 109 can be formed on the top porous dielectric layer 413 and cover the hybrid region conductive structure 300 and the top barrier layer 423. In some embodiments, the top dielectric layer 109 can be formed of materials such as silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-on low-k dielectric materials, chemical vapor deposited low-k dielectric materials, or combinations thereof. The term "low-k" as used in this disclosure refers to a dielectric material having a dielectric constant less than that of silicon dioxide. In some embodiments, the top dielectric layer 109 can include a self-planarizing material, such as spin-on glass or spin-on low-k dielectric materials, such as SiLK™. The use of a self-planarizing dielectric material can avoid the need for a subsequent planarization step. In some embodiments, the top dielectric layer 109 can be formed by a deposition process, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating.

[0228] The inclusion of the bottom porous dielectric layer 411, the top porous dielectric layer 413, and the middle porous dielectric layer 415, all having a low dielectric constant, reduces parasitic capacitance in the semiconductor device 1A. This improves the performance of the semiconductor device 1A. Furthermore, the bottom barrier layer 421 or the top barrier layer 423 prevents outgassing of the porous layers (i.e., the bottom porous dielectric layer 411, the top porous dielectric layer 413, and the middle porous dielectric layer 415), thereby preventing damage to the conductive structures (i.e., the mixed region conductive structure 300 and the non-mixed region conductive structure 200) and improving the reliability of the semiconductor device 1A. Furthermore, the bottom barrier layer 421 and the top barrier layer 423 can serve as etch stop layers during the formation of the conductive structure, thereby preventing damage to the bottom energy-removable layer 401 and the top energy-removable layer 403 during the formation of the conductive structure.

[0229] Figures 24 to 26 1 is a cross-sectional view illustrating semiconductor devices 1B, 1C, and 1D according to some embodiments of the present disclosure.

[0230] See also Figures 24 to 26 , each of the semiconductor elements 1B, 1C and 1D may have Figure 23 The structure shown is similar to the structure shown in Figures 24 to 26 The components in Figure 23 The same or similar elements in the present invention are marked with like reference numerals, and repeated descriptions are omitted.

[0231] See also Figure 24In the semiconductor element 1B, the bottom barrier layer 421 may be disposed between the bottom porous dielectric layer 411 and the top porous dielectric layer 413 , and may completely separate the bottom porous dielectric layer 411 and the top porous dielectric layer 413 located above the non-mixed area NMA of the substrate 101 .

[0232] See also Figure 25 In the semiconductor device 1C, the top barrier layer 423 can completely separate the top dielectric layer 109 located above the non-mixed area NMA and the mixed area MA of the substrate 101 from the top porous dielectric layer 413. In this regard, the top barrier layer 423 can be referred to as a capping layer 423 or a sealing layer 423.

[0233] See also Figure 26 In the semiconductor device 1D, the bottom barrier layer 421 may be disposed between the bottom porous dielectric layer 411 and the top porous dielectric layer 413, and may completely separate the bottom porous dielectric layer 411 located above the non-mixed area NMA of the substrate 101 from the top porous dielectric layer 413. The top barrier layer 423 may completely separate the top dielectric layer 109 located above the non-mixed area NMA and the mixed area MA of the substrate 101 from the top porous dielectric layer 413.

[0234] Figure 27 FIG is a cross-sectional view illustrating a semiconductor element 1E according to some embodiments of the present disclosure. Figure 27 The semiconductor element 1E in Figure 23 The semiconductor structures in FIG. 1 and FIG. 2 are similar in many respects, so similar features are not described again here. The main differences are described below.

[0235] See also Figure 27 In the semiconductor element 1E, a first interconnection structure 121b may be formed in the pattern sparse region B, a second interconnection structure 149 may be formed on the first interconnection structure 121b and above the pattern sparse region B, and a third interconnection structure 121a may be formed in the pattern dense region A.

[0236] The first interconnect structure 121b and the third interconnect structure 121a (also referred to as a lower interconnect structure) may be disposed in the substrate 101. In some embodiments, details of the third interconnect structure 121a are similar or identical to those of the first interconnect structure 121b except for being located in different regions.

[0237] Specifically, the third interconnect structure 121a may include a third barrier layer 111a, a third conductive line 113a disposed on the third barrier layer 111a, and a third manganese-containing layer 119a disposed on the third conductive line 113a. In some embodiments, the third barrier layer 111a covers the sidewalls of the third conductive line 113a and the sidewalls of the third manganese-containing layer 119a. In some embodiments, the third conductive line 113a and the third manganese-containing layer 119a are separated from the substrate 101 by the third barrier layer 111a.

[0238] Similar to the third interconnect structure 121a in the densely patterned region A, the first interconnect structure 121b in the sparsely patterned region B may include a first barrier layer 111b, a first conductive line 113b disposed on the first barrier layer 111b, and a first manganese-containing layer 119b disposed on the first conductive line 113b. In some embodiments, the first conductive line 113b in the sparsely patterned region B is parallel to the third conductive line 113a in the densely patterned region A. Furthermore, in some embodiments, the first barrier layer 111b covers the sidewalls of the first conductive line 113b and the sidewalls of the first manganese-containing layer 119b.

[0239] In some embodiments, the first conductive line 113b and the first Mn-containing layer 119b are separated from the substrate 101 by the first barrier layer 111b. In addition, according to some embodiments, the top surface 119aT of the third Mn-containing layer 119a and the top surface 119bT of the first Mn-containing layer 119b are substantially flush with the top surface 101T of the substrate 101.

[0240] Still see Figure 27 The semiconductor device structure 1E may further include a bottom porous dielectric layer 411 , a middle porous dielectric layer 415 , a top porous dielectric layer 413 , a dielectric layer 123 , a top barrier layer 423 and a second interconnect structure 149 .

[0241] The bottom porous dielectric layer 411 may be disposed on the sparsely patterned region B and the densely patterned region A of the substrate 101, the middle porous dielectric layer 415 may be disposed on the bottom porous dielectric layer 411, the top porous dielectric layer 413 may be disposed on the middle porous dielectric layer 415, and the dielectric layer 123 may be disposed on the top porous dielectric layer 413. The bottom porous dielectric layer 411 may completely cover the densely patterned region A of the substrate 101, the middle porous dielectric layer 415 may completely cover the bottom porous dielectric layer 411 located above the densely patterned region A of the substrate 101, the top porous dielectric layer 413 may completely cover the middle porous dielectric layer 415 located above the densely patterned region A of the substrate 101, and the dielectric layer 123 may completely cover the top porous dielectric layer 413 located above the densely patterned region A of the substrate 101. The bottom porous dielectric layer 411, the middle porous dielectric layer 415 and the top porous dielectric layer 413 are Figure 23The bottom porous dielectric layer 411 , the middle porous dielectric layer 415 , and the top porous dielectric layer 413 are shown to be identical, and thus descriptions of their formation, materials, and features will not be repeated herein.

[0242] The second interconnection structure 149 (also referred to as an upper interconnection structure) can be formed on the pattern sparse region B of the substrate 101 and on the first interconnection structure 121b and electrically connected to the first interconnection structure 121b. In some embodiments, the second interconnection structure 149 can directly contact the first interconnection structure 121b.

[0243] Specifically, the second interconnect structure 149 may include a second barrier layer 143', a second manganese-containing layer 145' disposed on the second barrier layer 143', and a second conductive line 147' disposed on the second manganese-containing layer 145'. In some embodiments, the second conductive line 147' may be surrounded by the second manganese-containing layer 145', and the second manganese-containing layer 145' may be surrounded by the second barrier layer 143'. Specifically, a sidewall 147'S of the second conductive line 147' may be covered by the second manganese-containing layer 145', and a sidewall 145'S of the second manganese-containing layer 145' may be covered by the second barrier layer 143'.

[0244] In some embodiments, the second manganese-containing layer 145' may be interposed between the second barrier layer 143' and the second conductive line 147', and the second conductive line 147' may be separated from the second barrier layer 143' by the second manganese-containing layer 145'. In some embodiments, a portion of the second barrier layer 143' may be interposed between the second manganese-containing layer 145' of the second interconnect structure 149 and the manganese-containing layer 119b of the first interconnect structure 121b. In some embodiments, the second manganese-containing layer 145' may be separated from the dielectric layer 123 by the second barrier layer 143'.

[0245] Furthermore, according to some embodiments, the top surface of the second conductive line 147' is substantially flush with the top surface of the second manganese-containing layer 145' and the top surface of the second barrier layer 143'. In some embodiments, a portion of the first manganese-containing layer 119b and a portion of the first barrier layer 111b of the first interconnect structure 121b are covered by the bottom porous dielectric layer 411. In some embodiments, the width W11 of the top portion 149P1 of the second interconnect structure 149 can be greater than the width W12 of the bottom portion 149P2 of the second interconnect structure 149, and the second interconnect structure 149 can have a T-shaped cross-sectional profile. In some embodiments, the top portion 149P1 of the second interconnect structure 149 can be surrounded by the dielectric layer 123 located above the pattern sparse region B of the substrate 101, and the bottom portion 149P2 of the second interconnect structure 149 can be surrounded by the bottom porous dielectric layer 411, the middle porous dielectric layer 415, and the top porous dielectric layer 413 located above the pattern sparse region B of the substrate 101. It should be noted that, according to some embodiments, the third interconnect structure 121 a in the pattern-dense area A is completely covered by the bottom porous dielectric layer 411 .

[0246] In some embodiments, the first manganese-containing layer 119b, the third manganese-containing layer 119a, and the second manganese-containing layer 145' are made of manganese (Mn). In some embodiments, the first conductive line 113b, the third conductive line 113a, and the second conductive line 147' are made of copper (Cu). In some embodiments, the first barrier layer 111b, the third barrier layer 111a, and the second barrier layer 143' are made of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), combinations thereof, or other suitable materials. In some embodiments, the manganese atomic percentage of the first interconnect 121b can be substantially the same as the manganese atomic percentage of the third interconnect 121a, and the manganese atomic percentage of the first interconnect 121b can be different from the manganese atomic percentage of the second interconnect 149. In some embodiments, the manganese atomic percentage of the first interconnect 121b is greater than the manganese atomic percentage of the second interconnect 149.

[0247] In some embodiments, the top barrier layer 423 may be disposed between the second barrier layer 143′ and the top porous dielectric layer 413, and the top barrier layer 423 may be surrounded by the dielectric layer 123 located above the pattern sparse region B of the substrate 101. In some embodiments, a width W13 of the top barrier layer 423 may be smaller than a width W11 of the top portion 149P1 of the second interconnect structure 149.

[0248] Figures 28 to 30 is a schematic diagram illustrating a semiconductor element 1F according to some embodiments of the present disclosure. Figure 28 It is the top view. Figure 29 It is along Figure 28The cross-sectional view shown by the section line AA or BB. Figure 30 It is along Figure 28 A cross-sectional view shown by section line CC or DD.

[0249] See also Figures 28 to 30 The semiconductor device 1F includes a substrate 101 , source / drain regions 102 , a dielectric layer 104 , a capacitor contact 106 , a bottom barrier layer 108 , a dielectric layer 111 , a patterned mask 141 and a bottom capacitor electrode 159 .

[0250] The substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 101 may include an elemental semiconductor material, a compound semiconductor material, and / or an alloy semiconductor material. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium phosphide, and / or indium gallium arsenide phosphide.

[0251] In some embodiments, substrate 101 may include an epitaxial layer. For example, substrate 101 may include an epitaxial layer covering a bulk semiconductor. In some embodiments, substrate 101 may be a semiconductor-on-insulator (SIO) substrate, which may include a substrate, a buried oxide layer located above the substrate, and a semiconductor layer located above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SIO substrate may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

[0252] See also Figure 29 and Figure 30 , source / drain regions 102 may be formed in the substrate 101. In some embodiments, the source / drain regions 102 may be formed by an ion implantation process, and P-type dopants such as boron (B), gallium (Ga), or indium (In), or N-type dopants such as phosphorus (P) or arsenic (As) may be implanted into the substrate 101 to form the source / drain regions 102, depending on the conductivity type of the semiconductor device 1F.

[0253] See also Figure 29 and Figure 30A dielectric layer 104 may be formed over the source / drain regions 102. In some embodiments, the dielectric layer 104 may include a bottom porous dielectric layer 1041 disposed over the source / drain regions 102 and a top porous dielectric layer 1043 disposed over the bottom porous dielectric layer 1041. A capacitor contact 106 may be formed over the source / drain regions 102 and may be surrounded by the dielectric layer 104. The capacitor contact 106 may include a liner layer 1061 and a conductive layer 1063, wherein the conductive layer 1063 includes a vertical portion 1063V and a horizontal portion 1063H. In some embodiments, a width W15 of the vertical portion 1063V is less than a width W14 of the horizontal portion 1063H. A bottom barrier layer 108 may be formed over the source / drain regions 102 and disposed between the dielectric layer 104 and the capacitor contact 106. It should be noted that the dielectric layer 104 (including the bottom porous dielectric layer 1041 and the top porous dielectric layer 1043), the capacitor contact 106 (including the liner layer 1061 and the conductive layer 1063) and the bottom barrier layer 108 are each the same or similar to Figure 23 The bottom porous dielectric layer 411, the top porous dielectric layer 413, the non-mixed region liner layer 201 and the non-mixed region conductive layer 203 of the non-mixed region conductive structure 200 and the bottom barrier layer 421 are described, so the description of these features will not be repeated here.

[0254] See also Figure 29 and Figure 30 , a dielectric layer 111 can be formed over the capacitor contact 106. In some embodiments, the dielectric layer 111 can be disposed over the base layer 110 of the bottom capacitor electrode 159, as will be described below. In some embodiments, the dielectric layer 111 can include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. In some embodiments, the dielectric layer 111 can be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable process.

[0255] See also Figure 29 and Figure 30 , a patterned mask 141 can be formed over the dielectric layer 111. In some embodiments, the patterned mask 141 can completely cover the dielectric layer 111. In some embodiments, the patterned mask 141 can be used as an etching mask in the etching process of the dielectric layer 111. A peripheral area (not shown) of the dielectric layer 111 can be exposed by the patterned mask 141. The sidewalls 111S of the dielectric layer 111 are substantially aligned with the sidewalls 141S of the patterned mask 141. In the context of the present disclosure, the term "substantially" means preferably at least 90%, preferably 95%, further preferably 98%, and most preferably 99%.

[0256] See also Figure 29 and Figure 30 , a bottom capacitor electrode 159 can be formed on the capacitor contact 106 and electrically connected to the capacitor contact 106. The bottom capacitor electrode 159 can include a base layer 110 disposed between the capacitor contact 106 and the dielectric layer 111. The bottom capacitor electrode 159 can also include a surrounding portion 151 disposed on the base layer 110 and disposed along the sidewalls 111S of the dielectric layer 111 and the sidewalls 141S of the patterned mask 141. The bottom capacitor electrode 159 also includes a first interconnect portion 153 disposed in the dielectric layer 111 and between the patterned mask 141 and the base layer 110, wherein the first interconnect portion 153 is substantially parallel to the base layer 110. In some embodiments, the bottom capacitor electrode 159 also includes a second interconnect portion 155 disposed in the dielectric layer 111 and between the first interconnect portion 153 and the base layer 110. The second interconnect portion 155 can be substantially parallel to the first interconnect portion 153.

[0257] In some embodiments, the base layer 110 may be made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), combinations thereof, or other suitable conductive materials. Furthermore, the base layer 110 may be formed by a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a metal-organic chemical vapor deposition (MOCVD) process, a sputtering process, an electroplating process, or other suitable processes.

[0258] In some embodiments, the surrounding portion 151, the first interconnect portion 153, and the second interconnect portion 155 are made of a conductive material, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), a combination thereof, or other suitable conductive materials. The surrounding portion 151, the first interconnect portion 153, and the second interconnect portion 155 are formed by performing a deposition process and a subsequent planarization process. The deposition process may include a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, an organic metal chemical vapor deposition process, a sputtering process, an electroplating process, or other suitable processes. The planarization process may include a chemical mechanical polishing (CMP) process. In some embodiments, the surrounding portion 151 is formed along the sidewalls 111S of the dielectric layer 111 and along the sidewalls 141S of the patterned mask 141. After the planarization process, the top surface of the surrounding portion 151 is substantially flush (coplanar) with the top surface of the patterned mask 141.

[0259] In some embodiments, base layer 110, surrounding portion 151, first interconnect 153, and second interconnect 155 are physically and electrically connected. In some embodiments, base layer 110 and surrounding portion 151 together form a crown structure 157. In some embodiments, first interconnect 153 and second interconnect 155 both directly contact adjacent sidewall 151S (i.e., the inner sidewall of surrounding portion 151). In some embodiments, base layer 110, first interconnect 153, and second interconnect 155 are separated from each other by dielectric layer 111.

[0260] Still see Figures 28 to 30 In some embodiments, the first interconnecting portion 153 substantially overlaps the second interconnecting portion 155, and the first interconnecting portion 153 and the second interconnecting portion 155 form a grid pattern in a top view, as shown in FIG. Figure 28 In some embodiments, the first interconnection portion 153, the second interconnection portion 155, and the base layer 110 are substantially parallel to each other. In some embodiments, the semiconductor device 1F is a dynamic random access memory (DRAM) device.

[0261] One aspect of the present disclosure provides a semiconductor device, comprising: a first interconnect structure disposed in a semiconductor substrate; a first dielectric layer disposed on the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; a second interconnect structure disposed in the first and second dielectric layers and electrically connected to the first interconnect structure; and a third interconnect structure disposed in the semiconductor substrate. The first interconnect structure comprises a first conductive line; and a first manganese-containing layer disposed on the first conductive line. The second interconnect structure comprises a second conductive line and a second manganese-containing layer disposed between the second conductive line and the first dielectric layer, and between the second conductive line and the second dielectric layer. The third interconnect structure comprises a third conductive line and a third manganese-containing layer disposed on the third conductive line. The third manganese-containing layer of the third interconnect structure is made of the same material as the first manganese-containing layer of the first interconnect structure. The first and second interconnect structures are disposed in a sparsely patterned area, and the third interconnect structure is disposed in a densely patterned area.

[0262] Another aspect of the present disclosure provides a semiconductor element, comprising: a capacitor contact disposed on a semiconductor substrate; a first dielectric layer disposed on the capacitor contact; a patterned mask disposed on the first dielectric layer; and a bottom capacitor electrode disposed on the capacitor contact and electrically connected to the capacitor contact. The bottom capacitor electrode comprises: a base layer disposed between the capacitor contact and the first dielectric layer; a surrounding portion disposed on the base layer and along the sidewalls of the first dielectric layer and the sidewalls of the patterned mask; and a first interconnect portion disposed between the patterned mask and the base layer. The first interconnect portion is substantially parallel to the base layer. The patterned mask is surrounded by the surrounding portion. The sidewalls of the patterned mask are substantially aligned with the sidewalls of the first dielectric layer.

[0263] Another aspect of the present disclosure provides a semiconductor element, comprising: a first interconnect structure disposed in a semiconductor substrate; a second interconnect structure disposed above the first interconnect structure and electrically connected to the first interconnect structure, wherein the second interconnect structure comprises: a first portion disposed on the first interconnect structure; and a second portion disposed on the first portion; a first dielectric layer disposed above the semiconductor substrate and surrounding the first portion of the second interconnect structure; a top barrier layer disposed between the second portion of the second interconnect structure and the first dielectric layer; and a second dielectric layer disposed above the first dielectric layer, covering the top barrier layer and surrounding the second portion of the second interconnect structure.

[0264] Due to the design of the semiconductor device disclosed herein, the parasitic capacitance of the semiconductor device 1A can be reduced by employing a bottom porous dielectric layer 411, a top porous dielectric layer 413, and an intermediate porous dielectric layer 415 having a low dielectric constant. This improves the performance of the semiconductor device 1A. Furthermore, the bottom barrier layer 421 or the top barrier layer 423 can prevent outgassing of the porous layers (i.e., the bottom porous dielectric layer 411, the top porous dielectric layer 413, and the intermediate porous dielectric layer 415), thereby preventing damage to the conductive structures (i.e., the mixed region conductive structure 300 and the non-mixed region conductive structure 200) and improving the reliability of the semiconductor device 1A. Furthermore, the bottom barrier layer 421 and the top barrier layer 423 can also serve as etch stop layers during the formation of the conductive structure, thereby preventing damage to the bottom energy-removable layer 401 and the top energy-removable layer 403 during the formation of the conductive structure.

[0265] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the concept and scope of the present disclosure as defined in the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0266] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are intended to be included within the claims of this application.

Claims

1. A semiconductor device comprising: a capacitor contact disposed on a semiconductor substrate; a first dielectric layer disposed on the capacitor contact; a patterned mask disposed on the first dielectric layer; as well as a bottom capacitor electrode disposed above the capacitor contact and electrically connected to the capacitor contact, wherein the bottom capacitor electrode comprises: a base layer disposed between the capacitor contact and the first dielectric layer; a surrounding portion disposed on the base layer and along a sidewall of the first dielectric layer and a sidewall of the patterned mask; and a first interconnection portion disposed between the patterned mask and the base layer, wherein the first interconnection portion is substantially parallel to the base layer, The patterned mask is surrounded by the surrounding portion, and the sidewall of the patterned mask is substantially aligned with the sidewall of the first dielectric layer. 2 . The semiconductor device as claimed in claim 1 , wherein a source / drain region is formed in the semiconductor substrate, and the capacitor contact is disposed on the source / drain region.

3. The semiconductor device of claim 2, further comprising a second dielectric layer disposed on the source / drain region, wherein the second dielectric layer comprises a bottom porous dielectric layer disposed on the source / drain region and a top porous dielectric layer disposed on the bottom porous dielectric layer. 4 . The semiconductor device as claimed in claim 3 , wherein a porosity of the top porous dielectric layer is greater than a porosity of the bottom porous dielectric layer. The semiconductor device as claimed in claim 4 , wherein the capacitor contact is surrounded by the second dielectric layer. 6 . The semiconductor device as claimed in claim 5 , wherein the capacitor contact comprises a conductive layer and a pad layer, wherein the conductive layer comprises a vertical portion disposed on the semiconductor substrate and a horizontal portion disposed on the vertical portion. The semiconductor device as claimed in claim 6 , wherein a width of the vertical portion is smaller than a width of the horizontal portion. 8 . The semiconductor device of claim 6 , further comprising a bottom barrier layer, wherein the bottom barrier layer is formed on the source / drain region and disposed between the second dielectric layer and the capacitor contact. 9 . The semiconductor device as claimed in claim 8 , wherein the bottom barrier layer is made of tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof. 10 . The semiconductor device of claim 1 , wherein the bottom capacitor electrode further comprises a second interconnection portion, wherein the second interconnection portion is disposed on the first dielectric layer and located between the first interconnection portion and the base layer. The semiconductor device as claimed in claim 10 , wherein the second interconnection portion is substantially parallel to the first interconnection portion. 12 . The semiconductor device as claimed in claim 1 , wherein the base layer is made of aluminum, copper, tungsten, titanium, tantalum, or a combination thereof.

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