Circuit board calibration method, device, circuit board and storage medium

Abstract

This invention proposes a board calibration method, apparatus, board, and storage medium, relating to the field of satellite communication. The method involves the board's FPGA acquiring pre-measured transmit power calibration values ​​and receive power calibration values. Upon receiving a carrier leakage correction start signal from the CPU, it acquires the transmit frequency point of the transmit channel and the receive frequency point of the receive channel, configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction. While the CPU controls the transmit channel to transmit a carrier leakage test signal, it detects the single-carrier frequency power of the transmit frequency point and the carrier leakage frequency power of the receive frequency point. Based on the single-carrier frequency power, carrier leakage frequency power, transmit power calibration value, and receive power calibration value, carrier leakage correction is performed on the board, thereby achieving automated carrier leakage correction of the board without manual intervention. Furthermore, the accuracy of correction is improved by introducing transmit power calibration values ​​and receive power calibration values.

Description

Technical Field

[0001] This invention relates to the field of satellite communications, and more specifically, to a board calibration method, apparatus, board, and storage medium. Background Technology

[0002] Satellite communication systems transmit data via a wireless link between an "earth station" (ground equipment) and a "satellite." Satellite communication systems require high-precision and high-reliability signal transmission to ensure data integrity and communication quality.

[0003] Carrier leakage refers to the failure to completely suppress the carrier component in the transmitted signal, resulting in leakage into the receiving channel and causing nonlinear effects that generate image signals. This leakage can lead to image signals and other spurious signals in the receiving channel, thereby affecting communication quality and system performance.

[0004] To solve these problems, engineers typically need to manually calibrate the boards in the satellite terminal, which requires a lot of manpower and time. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a board calibration method, apparatus, board, and storage medium.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0007] In a first aspect, the present invention provides a board calibration method applied to an FPGA board, wherein the board's transmit and receive channels are connected via radio frequency cables, and the board further includes a CPU; the method includes:

[0008] Obtain pre-measured transmit power calibration values ​​and receive power calibration values; wherein, the transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer;

[0009] Upon receiving the carrier leakage correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction.

[0010] When the CPU controls the transmission channel to transmit a carrier leakage test signal, the single carrier frequency power of the transmission frequency point and the carrier leakage frequency power of the receiving frequency point are detected.

[0011] The board is subjected to carrier leakage correction based on the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value.

[0012] Optionally, the step of correcting carrier leakage of the board based on the single carrier frequency power, the carrier leakage frequency power, the transmit power calibration value, and the receive power calibration value includes:

[0013] The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power.

[0014] The carrier leakage frequency power is corrected for path loss using the received power calibration value to obtain the corrected carrier leakage frequency power.

[0015] Calculate the first power difference between the corrected single-carrier frequency power and the corrected carrier leakage frequency power;

[0016] If the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition, wherein the first register is a register related to carrier leakage.

[0017] Optionally, the method further includes:

[0018] After the carrier leakage correction is completed, an interrupt signal is sent to the CPU so that the CPU can reconfigure the transmission frequency point of the transmission channel and the receiving frequency point of the receiving channel according to the frequency point configuration strategy corresponding to the transmit image frequency correction, and send a transmit image frequency correction start signal to the FPGA.

[0019] Optionally, the method further includes:

[0020] Upon receiving the transmit image frequency correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to the transmit image frequency correction.

[0021] When the CPU controls the transmission channel to transmit the first image frequency test signal, the single carrier frequency power of the transmission frequency point and the transmission image frequency power of the receiving frequency point are detected.

[0022] The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power.

[0023] The path loss of the transmit mirror frequency power is corrected using the received power calibration value to obtain the corrected transmit mirror frequency power.

[0024] Calculate the second power difference between the corrected single-carrier frequency power and the corrected transmit mirror frequency power;

[0025] If the second power difference does not meet the second preset condition, adjust the three second registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmit mirror frequency power of the receiving frequency point until the second power difference meets the second preset condition, wherein the second register is a register related to the transmit mirror frequency.

[0026] Optionally, the method further includes:

[0027] After the transmit image frequency correction is completed, an interrupt signal is sent to the CPU so that the CPU can reconfigure the transmit frequency point of the transmit channel and the receive frequency point of the receive channel according to the frequency point configuration strategy corresponding to the receive image frequency correction, and send a receive image frequency correction start signal to the FPGA.

[0028] Optionally, the method further includes:

[0029] Upon receiving the receive image frequency correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to the receive image frequency correction.

[0030] When the CPU controls the transmission channel to transmit the second image frequency test signal, the single carrier frequency power of the transmission frequency point and the received image frequency power of the receiving frequency point are detected.

[0031] The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power.

[0032] The path loss is corrected for the received image frequency power using the received power calibration value to obtain the corrected received image frequency power.

[0033] Calculate the third power difference between the corrected single-carrier frequency power and the corrected received image frequency power;

[0034] If the third power difference does not meet the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point until the third power difference meets the third preset condition, wherein the third register is a register related to the receiving image frequency.

[0035] Optionally, the board further includes a memory, and the method further includes:

[0036] After the carrier leakage correction, transmit image frequency correction, or receive image frequency correction is completed, the corresponding carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters are generated and sent to the CPU, so that the CPU writes the carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters into the memory, and calls the carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters stored in the memory when the board is running.

[0037] Secondly, the present invention provides a board calibration device applied to an FPGA board, wherein the board's transmit and receive channels are connected via radio frequency cables, and the board further includes a CPU. The device comprises:

[0038] The acquisition module is used to acquire pre-measured transmit power calibration values ​​and receive power calibration values; wherein, the transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; upon receiving the carrier leakage correction start signal sent by the CPU, the module acquires the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction;

[0039] The calibration module is used to control the transmission channel to transmit a carrier leakage test signal and detect the single carrier frequency power of the transmission frequency point and the carrier leakage frequency power of the receiving frequency point; and to perform carrier leakage correction on the board based on the single carrier frequency power, the carrier leakage frequency power, the transmission power calibration value and the receiving power calibration value.

[0040] Thirdly, the present invention provides a board including a CPU and an FPGA, wherein the CPU sends a calibration start signal to the FPGA, and the FPGA executes machine-executable instructions according to the calibration start signal to implement the board calibration method described in the first aspect.

[0041] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by an FPGA, implements the board calibration method as described in the first aspect above.

[0042] The board calibration method, apparatus, board, and storage medium provided in this invention embodiment involve the board's FPGA acquiring pre-measured transmit power calibration values ​​and receive power calibration values. The transmit power calibration value is obtained based on the output level of the transmit channel measured by a spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable. The receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer. Upon receiving a carrier leakage correction start signal from the CPU, the system acquires the transmit frequency point of the transmit channel and the receive frequency point of the receive channel, configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction. With the CPU controlling the transmit channel to transmit a carrier leakage test signal, the system detects the single carrier frequency power of the transmit frequency point and the carrier leakage frequency power of the receive frequency point. Based on the single carrier frequency power, carrier leakage frequency power, transmit power calibration value, and receive power calibration value, the system performs carrier leakage correction on the board. Since the embodiments of the present invention achieve automated carrier leakage correction of the board through FPGA control and CPU instruction scheduling, no manual intervention is required. Furthermore, by introducing transmit power calibration values ​​and receive power calibration values, the path loss in the RF link is accurately compensated, ensuring that the measured values ​​truly reflect the signal state, thereby improving the accuracy of the correction.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This figure shows a schematic block diagram of a circuit board provided in an embodiment of the present invention;

[0046] Figure 2 This diagram illustrates a logic functional framework diagram of an FPGA-PL provided by an embodiment of the present invention;

[0047] Figure 3 This diagram illustrates a flowchart of a board calibration method provided by an embodiment of the present invention. Figure 1 ;

[0048] Figure 4 This diagram illustrates the principle of circuit board leakage and image frequency correction provided in an embodiment of the present invention.

[0049] Figure 5This diagram illustrates a flowchart of a board calibration method provided by an embodiment of the present invention. Figure 2 ;

[0050] Figure 6 This diagram illustrates a flowchart of a board calibration method provided by an embodiment of the present invention. Figure 3 ;

[0051] Figure 7 The diagram shows a functional block diagram of a board calibration device provided in an embodiment of the present invention.

[0052] Icons: 100 - Board calibration device; 101 - Acquisition module; 102 - Calibration module. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0055] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0056] Please refer to Figure 1 This is a block diagram of a circuit board. The board includes a memory, a CPU, and an FPGA. The memory, CPU, and FPGA are electrically connected to each other directly or indirectly to enable data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0057] The memory is used to store programs or data. The memory may be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0058] The CPU is used to read / write data or programs stored in memory and perform corresponding functions.

[0059] like Figure 2 As shown, the programmable logic section FPGA-PL in the FPGA includes two independent beacon demodulation channels and corresponding frequency / power statistics modules. The "self-test control" module is used to implement the board calibration method provided in this embodiment of the invention.

[0060] It should be understood that, Figure 1 The structure shown is only a schematic diagram of the board; the board may also include components such as... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0061] Please refer to Figure 3 The board calibration method provided in this embodiment of the invention includes steps S101 to S104.

[0062] S101, obtain the pre-measured transmit power calibration value and receive power calibration value.

[0063] The transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable. The receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer.

[0064] In this embodiment of the invention, a signal source and a spectrum analyzer are connected via an RF cable. The output power of the signal source is configured to be 0 dBm, and the signal source is adjusted to transmit at different frequencies (e.g., in 50 MHz increments). The displayed power values ​​at each frequency are recorded on the spectrum analyzer, and the attenuation value of the RF cable at each frequency is calculated. The attenuation value of the RF cable is recorded as a line loss parameter of the RF cable.

[0065] Connect one end of the RF cable to the transmit channel of the board under test, and the other end to the spectrum analyzer. Configure the board's transmit power to 0dBm, with transmit frequencies ranging from 950MHz to 2400MHz in 50MHz increments. Measure the actual power value at each frequency point using the spectrum analyzer and calculate the transmit power calibration value. The transmit power calibration value is calculated as follows: Transmit power calibration value = Spectrum analyzer display value - (Transmit configuration value - Line loss parameter).

[0066] Record the transmit power calibration values ​​for all frequencies for power compensation of the transmit channels during subsequent board calibration.

[0067] Connect the transmit and receive channels of the board under test directly via an RF cable, and configure the transmit and receive channels to have the same frequency, symbol rate, and roll-off factor. Set the transmit power to -10dBm, record the transmit level value displayed on the spectrum analyzer (recorded as the transmit level display value) and the background level value of the receive channel (recorded as the receive level display value), and calculate the receive power calibration value. The receive power calibration value is calculated as: Receive power calibration value = Transmit level display value - Receive level display value.

[0068] Record the received power calibration values ​​for all frequency points for use in power compensation of the receiving channel.

[0069] For the board to be calibrated, first check if the board's software version supports the self-test program. If not, a software update is required to load a firmware version that supports self-test control registers, transmit / receive frequency control, and calibration parameter storage.

[0070] If the board's software version supports a self-test program, press Ctrl+C in the board's serial terminal to enter U-Boot mode, and enter the command to load and start the self-test program. After the program loads, the user will be prompted to enter the previously recorded transmit power calibration value and receive power calibration value for power compensation during the calibration process.

[0071] The CPU writes these two parameters into specific registers of the FPGA, such as the transmit power calibration register TX_PWR_CALIB_REG and the receive power calibration register RX_PWR_CALIB_REG.

[0072] When the calibration process begins, the CPU of the board to be calibrated initializes the self-test parameters, including configuring the transmit frequency point, the receive frequency point as the current test frequency point (such as 950MHz, 1000MHz, etc.), setting the transmit power to -10dBm, configuring the self-test control register, and selecting the self-test items to be executed.

[0073] The self-test items include carrier leakage correction, transmit image frequency correction, and receive image frequency correction. For each frequency point under test, the board must be subjected to carrier leakage correction, transmit image frequency correction, and receive image frequency correction in sequence.

[0074] S102, upon receiving the carrier leakage correction start signal sent by the CPU, obtains the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction.

[0075] In this embodiment of the invention, for the transmitting channel, the CPU sets the transmitting frequency to "center frequency + 1MHz" and the transmitting power to 0dBm. For the receiving channel, the CPU configures the receiving frequency to "transmitting frequency - 2MHz" and enables the simulated AGC function.

[0076] Carrier leakage occurs at the receiving frequency, such as Figure 4 As shown, the receiving frequency is 2MHz on the baseband.

[0077] S103 detects the single-carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point when the CPU controls the transmitting channel to transmit a carrier leakage test signal.

[0078] In this embodiment of the invention, the carrier leakage test signal is a single carrier with a frequency 1 MHz higher than the center frequency. The FPGA detects the single carrier frequency power at the transmit frequency point and the carrier leakage frequency power at the receive frequency point in the baseband.

[0079] S104 performs carrier leakage correction on the board based on the single carrier frequency power, carrier leakage frequency power, transmit power calibration value, and receive power calibration value.

[0080] In a possible implementation, step S104 can be implemented as follows:

[0081] S104-1, the path loss of the single carrier frequency power is corrected using the transmit power calibration value to obtain the corrected single carrier frequency power; the path loss of the carrier leakage frequency power is corrected using the receive power calibration value to obtain the corrected carrier leakage frequency power.

[0082] The transmit power calibration value is used to correct for power losses introduced by hardware such as RF cables, filters, and power amplifiers in the transmit channel. The FPGA adds the transmit power calibration value to the measured single-carrier frequency power of the transmit point to obtain the corrected single-carrier frequency power.

[0083] The received power calibration value is used to correct signal gain or attenuation deviations introduced by hardware such as LNA, filters, and ADC in the receiving channel. The FPGA adds the received power calibration value to the measured carrier leakage frequency power at the receiving frequency point to obtain the corrected carrier leakage frequency power.

[0084] S104-2, calculate the first power difference between the corrected single-carrier frequency power and the corrected carrier leakage frequency power.

[0085] S104-3, if the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition.

[0086] The first preset condition is that the first power difference is less than the first threshold, and the first register is a register related to carrier leakage, that is, a register that affects carrier leakage.

[0087] In this embodiment of the invention, the FPGA adjusts the register values ​​of the two first registers according to the first power difference, and after each adjustment is completed, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point, and recalculates the first power difference.

[0088] When the calculated first power difference is less than the first threshold, the carrier leakage correction is completed. At this time, the current register values ​​of the two first registers are recorded as carrier leakage correction parameters and sent to the CPU so that the CPU can write the carrier leakage correction parameters into the board's memory. The carrier leakage correction parameters stored in the memory can be called when the board is running.

[0089] For example, the two first registers include a bias voltage register for the transmit I channel (address 0xa5) and a bias voltage register for the transmit Q channel (address 0xa7). Register 0xa5 is adjusted first, and then register 0xa7 is adjusted.

[0090] The adjustment process can be as follows: First, set the transmit I-path bias voltage to the minimum value, then wait 100ms and record the power difference. If the I-path bias voltage reaches the maximum value at this time, then proceed to adjust the transmit Q-path bias voltage.

[0091] If the I-channel bias voltage does not reach its maximum, increase the I-channel bias voltage and wait another 100ms while recording the power difference. Repeat the above operation until the I-channel bias voltage reaches its maximum.

[0092] The process of adjusting the transmit Q-path bias voltage is as follows: set the transmit Q-path bias voltage to the minimum value and wait for 100ms, then record and compare the power difference. If the transmit Q-path bias voltage reaches the maximum value at this time, the adjustment of the register values ​​of the two registers related to carrier leakage is completed.

[0093] If the transmit Q-path bias voltage does not reach its maximum, increase the Q-path bias voltage and wait another 100ms while recording the power difference. Repeat this process until the Q-path bias voltage reaches its maximum.

[0094] Please refer to Figure 5 After step S104, the board calibration method provided in this embodiment of the invention further includes step S105.

[0095] S105, after carrier leakage correction is completed, sends an interrupt signal to the CPU so that the CPU can reconfigure the transmit frequency point of the transmit channel and the receive frequency point of the receive channel according to the frequency point configuration strategy corresponding to transmit image frequency correction, and sends a transmit image frequency correction start signal to the FPGA.

[0096] In this embodiment of the invention, for the transmitting channel, the CPU sets the transmitting frequency to "center frequency ± 1MHz" and the transmitting power to 0dBm. For the receiving channel, the CPU configures the receiving frequency to "transmitting frequency - 2MHz" and enables the simulated AGC function.

[0097] At the receiving frequency point, a transmitting mirror frequency is generated, such as Figure 4 As shown, the receiving frequency is 1MHz on the baseband.

[0098] Furthermore, please refer to again Figure 5 After step S105, the board calibration method provided in this embodiment of the invention further includes steps S106 to S110.

[0099] S106, upon receiving the transmit image frequency correction start signal sent by the CPU, obtains the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to the transmit image frequency correction.

[0100] S107, under the control of the CPU to transmit the first image frequency test signal through the transmission channel, the single carrier frequency power of the transmission frequency point and the transmission image frequency power of the receiving frequency point are detected.

[0101] In this embodiment of the invention, the first image frequency test signal is a single carrier frequency offset by 1MHz from the center frequency. The FPGA detects the single carrier frequency power at the baseband transmission frequency point and the transmit image frequency power at the receiver frequency point.

[0102] S108: The path loss of the single-carrier frequency power is corrected using the transmit power calibration value to obtain the corrected single-carrier frequency power; the path loss of the transmit image frequency power is corrected using the receive power calibration value to obtain the corrected transmit image frequency power.

[0103] Specifically, the FPGA adds the measured single-carrier frequency power of the transmitting frequency point to the transmit power calibration value to obtain the corrected single-carrier frequency power. Similarly, the FPGA adds the measured transmit image frequency power of the receiving frequency point to the receive power calibration value to obtain the corrected transmit image frequency power.

[0104] S109, calculate the second power difference between the corrected single-carrier frequency power and the corrected transmit mirror frequency power.

[0105] S110, if the second power difference does not meet the second preset condition, adjust the three second registers and return to the steps of detecting the single carrier frequency power of the transmitting frequency point and the transmit mirror frequency power of the receiving frequency point until the second power difference meets the second preset condition.

[0106] The second preset condition is that the second power difference is less than the second threshold, and the second register is a register related to the transmission mirror frequency, that is, a register that affects the transmission mirror frequency.

[0107] In this embodiment of the invention, the FPGA adjusts the register values ​​of the three second registers according to the second power difference, and after each adjustment, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmit mirror frequency power of the receiving frequency point, and recalculates the second power difference.

[0108] When the calculated second power difference is less than the second threshold, the transmit image frequency correction is completed. At this time, the current register values ​​of the three second registers are recorded as transmit image frequency correction parameters and sent to the CPU so that the CPU can write the transmit image frequency correction parameters into the board's memory. When the board is running, the transmit image frequency correction parameters stored in the memory can be called.

[0109] For example, the three second registers include the amplitude factor register for the transmit I channel (address 0xa3), the amplitude factor register for the transmit Q channel (address 0xa4), and the transmit phase correction value register (address 0xa9). First, adjust register 0xa3, then adjust register 0xa9, and finally adjust register 0xa4.

[0110] Please refer to Figure 6 After step S110, the board calibration method provided in this embodiment of the invention further includes step S111.

[0111] S111: After the transmit image frequency correction is completed, an interrupt signal is sent to the CPU so that the CPU can reconfigure the transmit frequency point of the transmit channel and the receive frequency point of the receive channel according to the frequency point configuration strategy corresponding to the receive image frequency correction, and send a receive image frequency correction start signal to the FPGA.

[0112] In this embodiment of the invention, for the transmitting channel, the CPU sets the transmitting frequency to be the same as the center frequency and the transmitting power to 0dBm. For the receiving channel, the CPU configures the receiving frequency to "center frequency - 2MHz" and enables the simulated AGC function.

[0113] At the receiving frequency point, a receiving image frequency is generated, such as Figure 4 As shown, the receiving frequency is -3MHz on the baseband.

[0114] Furthermore, please refer to again Figure 6 After step S111, the board calibration method provided in this embodiment of the invention further includes steps S112 to S116.

[0115] S112, upon receiving the receive image frequency correction start signal sent by the CPU, obtain the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to the receive image frequency correction.

[0116] S113, under the control of the CPU, transmits the second mirror frequency test signal through the transmission channel, and detects the single carrier frequency power of the transmission frequency point and the received mirror frequency power of the receiving frequency point.

[0117] In this embodiment of the invention, the second image frequency test signal is a single carrier with the same frequency as the center frequency. The FPGA detects the single carrier frequency power at the transmit frequency point and the received image frequency power at the receive frequency point in the baseband.

[0118] S114, use the transmit power calibration value to correct the path loss of the single carrier frequency power to obtain the corrected single carrier frequency power; use the receive power calibration value to correct the path loss of the receive image frequency power to obtain the corrected receive image frequency power.

[0119] Specifically, the FPGA adds the measured single-carrier frequency power of the transmit frequency point to the transmit power calibration value to obtain the corrected single-carrier frequency power. Similarly, the FPGA adds the measured receive image frequency power of the receive frequency point to the receive power calibration value to obtain the corrected transmit image frequency power.

[0120] S115, calculate the third power difference between the corrected single-carrier frequency power and the corrected received image frequency power.

[0121] S116, if the third power difference does not meet the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the receiving mirror frequency power of the receiving frequency point until the third power difference meets the third preset condition.

[0122] The third preset condition is that the third power difference is less than the third threshold, and the third register is a register related to the receiving image frequency, that is, a register that affects the receiving image frequency.

[0123] In this embodiment of the invention, the FPGA adjusts the register values ​​of the three third registers according to the third power difference, and after each adjustment, returns to the step of detecting the single carrier frequency power of the transmitting frequency point and the received image frequency power of the receiving frequency point, and recalculates the third power difference.

[0124] When the calculated third power difference is less than the third threshold, the receiving image frequency correction is completed. At this time, the current register values ​​of the three third registers are recorded as receiving image frequency correction parameters and sent to the CPU so that the CPU can write the receiving image frequency correction parameters into the board's memory. The receiving image frequency correction parameters stored in the memory can be called when the board is running.

[0125] For example, the three third registers include the amplitude factor register for the receive I channel (address 0xac), the amplitude factor register for the receive Q channel (address 0xad), and the receive phase correction value register (address 0xae). First, adjust the 0xac register, then adjust the 0xad register, and finally adjust the 0xae register.

[0126] After the FPGA completes carrier leakage correction, transmit image frequency correction, and receive image frequency correction at each frequency point, it exits the self-test program, restarts the board, and loads the normally running software version.

[0127] The FPGA automatically reads the carrier leakage correction parameters, transmit image frequency correction parameters, and receive image frequency correction parameters from the memory and writes them into the corresponding registers.

[0128] Connect the board's transmit channel to the spectrum analyzer and configure the transmit frequency from 950MHz to 2400MHz in 50MHz increments.

[0129] The spectrum analyzer measures the transmit power at each frequency point and compares it with the calibrated transmit power value to verify the calibration accuracy. Simultaneously, it observes whether the transmit waveform is normal and whether there is carrier leakage or image frequency interference.

[0130] By using serial port or host computer tools, multi-frequency transmission and reception tasks can be set up to automatically complete the retesting process for multiple frequencies. If some frequencies fail to meet the standards, manual corrections can be made or feedback can be provided to the hardware team for device troubleshooting.

[0131] After calibration and retesting, a physical shielding cover is installed on the board to reduce electromagnetic wave leakage and external interference, thereby improving system stability.

[0132] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0133] (1) Through FPGA control and CPU instruction scheduling, the key performance indicators of the board, such as carrier leakage correction, transmit image frequency correction and receive image frequency correction, can be automatically corrected without manual intervention.

[0134] (2) By introducing transmit power calibration value and receive power calibration value, the path loss in the radio frequency link is accurately compensated to ensure that the measured value truly reflects the signal state, thereby improving the accuracy of the correction.

[0135] (3) The correction process is divided into three independent modules: carrier leakage correction, transmit image frequency correction, and receive image frequency correction. It supports on-demand start and interrupt response mechanisms, making it easy to integrate into the communication system as a standard functional module.

[0136] (4) By comparing the detected power difference with the preset conditions, the register values ​​related to carrier leakage and image frequency suppression are dynamically adjusted to form a closed-loop feedback correction mechanism to ensure the best correction effect.

[0137] (5) After the calibration is completed, the FPGA sends the generated calibration parameters to the CPU and writes them into the non-volatile memory to ensure that the board automatically loads these parameters when restarting or running, and maintains long-term stable performance.

[0138] To perform the corresponding steps in the above embodiments and various possible methods, an implementation of the board calibration device 100 is given below. Further, please refer to... Figure 7 , Figure 7 This is a functional block diagram of a board calibration device 100 provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the board calibration device 100 provided in this embodiment are the same as those in the above embodiments. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the above embodiments. The board calibration device 100 includes:

[0139] The acquisition module 101 is used to acquire pre-measured transmit power calibration values ​​and receive power calibration values. The transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable. The receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer. When the carrier leakage correction start signal sent by the CPU is received, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction are acquired.

[0140] The calibration module 102 is used to detect the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point when the CPU controls the transmitting channel to transmit a carrier leakage test signal; and to perform carrier leakage correction on the board based on the single carrier frequency power, carrier leakage frequency power, transmitting power calibration value and receiving power calibration value.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0142] In addition, the functional modules in the various embodiments of the present invention can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0143] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a circuit board, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0144] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A circuit board calibration method, characterized in that, An FPGA is used in a board, wherein the board's transmit and receive channels are connected via radio frequency cables, and the board also includes a CPU. The method includes: Obtain pre-measured transmit power calibration values ​​and receive power calibration values; wherein, the transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; Upon receiving the carrier leakage correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction. When the CPU controls the transmission channel to transmit a carrier leakage test signal, the single carrier frequency power of the transmission frequency point and the carrier leakage frequency power of the receiving frequency point are detected. The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power. The carrier leakage frequency power is corrected for path loss using the received power calibration value to obtain the corrected carrier leakage frequency power. Calculate the first power difference between the corrected single-carrier frequency power and the corrected carrier leakage frequency power; If the first power difference does not meet the first preset condition, adjust the two first registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition, wherein the first register is a register related to carrier leakage.

2. The board calibration method as described in claim 1, characterized in that, The method further includes: After the carrier leakage correction is completed, an interrupt signal is sent to the CPU so that the CPU can reconfigure the transmission frequency point of the transmission channel and the receiving frequency point of the receiving channel according to the frequency point configuration strategy corresponding to the transmit image frequency correction, and send a transmit image frequency correction start signal to the FPGA.

3. The board calibration method as described in claim 2, characterized in that, The method further includes: Upon receiving the transmit image frequency correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to the transmit image frequency correction. When the CPU controls the transmission channel to transmit the first image frequency test signal, the single carrier frequency power of the transmission frequency point and the transmission image frequency power of the receiving frequency point are detected. The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power. The path loss of the transmit mirror frequency power is corrected using the received power calibration value to obtain the corrected transmit mirror frequency power. Calculate the second power difference between the corrected single-carrier frequency power and the corrected transmit mirror frequency power; If the second power difference does not meet the second preset condition, adjust the three second registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the transmit mirror frequency power of the receiving frequency point until the second power difference meets the second preset condition, wherein the second register is a register related to the transmit mirror frequency.

4. The board calibration method as described in claim 3, characterized in that, The method further includes: After the transmit image frequency correction is completed, an interrupt signal is sent to the CPU so that the CPU can reconfigure the transmit frequency point of the transmit channel and the receive frequency point of the receive channel according to the frequency point configuration strategy corresponding to the receive image frequency correction, and send a receive image frequency correction start signal to the FPGA.

5. The board calibration method as described in claim 4, characterized in that, The method further includes: Upon receiving the receive image frequency correction start signal sent by the CPU, the transmit frequency point of the transmit channel and the receive frequency point of the receive channel are obtained by the CPU according to the frequency point configuration strategy corresponding to the receive image frequency correction. When the CPU controls the transmission channel to transmit the second image frequency test signal, the single carrier frequency power of the transmission frequency point and the received image frequency power of the receiving frequency point are detected. The path loss is corrected for the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power. The path loss is corrected for the received image frequency power using the received power calibration value to obtain the corrected received image frequency power. Calculate the third power difference between the corrected single-carrier frequency power and the corrected received image frequency power; If the third power difference does not meet the third preset condition, adjust the three third registers and return to the step of detecting the single carrier frequency power of the transmitting frequency point and the receiving image frequency power of the receiving frequency point until the third power difference meets the third preset condition, wherein the third register is a register related to the receiving image frequency.

6. The board calibration method as described in claim 5, characterized in that, The board also includes a memory, and the method further includes: After the carrier leakage correction, transmit image frequency correction, or receive image frequency correction is completed, the corresponding carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters are generated and sent to the CPU, so that the CPU writes the carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters into the memory, and calls the carrier leakage correction parameters, transmit image frequency correction parameters, or receive image frequency correction parameters stored in the memory when the board is running.

7. A circuit board calibration device, characterized in that, An FPGA applied to a board, wherein the board's transmit and receive channels are connected via radio frequency cables, and the board also includes a CPU; the device comprises: The acquisition module is used to acquire pre-measured transmit power calibration values ​​and receive power calibration values; wherein, the transmit power calibration value is obtained based on the output level of the transmit channel measured by the spectrum analyzer, the configuration value of the transmit channel, and the line loss parameters of the RF cable, and the receive power calibration value is obtained based on the output level of the transmit channel and the receive level of the receive channel measured by the spectrum analyzer; upon receiving the carrier leakage correction start signal sent by the CPU, the module acquires the transmit frequency point of the transmit channel and the receive frequency point of the receive channel configured by the CPU according to the frequency point configuration strategy corresponding to carrier leakage correction; The calibration module is configured to, when the CPU controls the transmission channel to transmit a carrier leakage test signal, detect the single-carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point; perform path loss correction on the single-carrier frequency power using the transmit power calibration value to obtain the corrected single-carrier frequency power; perform path loss correction on the carrier leakage frequency power using the receive power calibration value to obtain the corrected carrier leakage frequency power; calculate a first power difference between the corrected single-carrier frequency power and the corrected carrier leakage frequency power; if the first power difference does not meet a first preset condition, adjust two first registers and return to the step of detecting the single-carrier frequency power of the transmitting frequency point and the carrier leakage frequency power of the receiving frequency point until the first power difference meets the first preset condition, wherein the first registers are registers related to carrier leakage.

8. A circuit board, characterized in that, The system includes a CPU and an FPGA. The CPU sends a calibration start signal to the FPGA, and the FPGA executes machine-executable instructions according to the calibration start signal to implement the board calibration method according to any one of claims 1-6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the FPGA, it implements the board calibration method as described in any one of claims 1-6.

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