Fault detection modeling method and system of communication module and storage medium

Abstract

The invention relates to the technical field of fault detection, in particular to a fault detection modeling method and system of a communication module and a storage medium. The method comprises the following steps: acquiring communication module structure data; analyzing a topological structure of the communication module structure data, and performing baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data based on the topological structure to obtain a baseband clock signal and an RF front-end IQ signal; the baseband chip clock stability of the baseband clock signal is analyzed, and a clock stability feature set is generated; and analyzing the radio frequency front-end IQ balance of the RF front-end IQ signal to obtain a radio frequency front-end IQ balance feature set. Through multi-source signal acquisition, structural topology analysis and dynamic simulation optimization, the accuracy, comprehensiveness and real-time response capability of fault detection of the communication module are effectively improved, and the problems that a traditional method is single in detection, inaccurate in positioning and lack of dynamic optimization are solved.

Description

Technical Field

[0001] The present invention relates to the field of fault detection technology, and in particular to a fault detection modeling method, system and storage medium for a communication module. Background Art

[0002] As a core component of modern communication systems, the performance of communication modules directly impacts the stability and efficiency of the entire communication network. With the rapid development of wireless communication technology, communication modules have become increasingly complex and their functionality has been continuously enhanced. They have evolved from early single signal transmission modules to highly integrated devices that integrate multiple frequency bands, multiple protocols, and multiple functions, meeting the demands of emerging fields such as 5G and the Internet of Things. At the same time, when operating in complex environments, communication modules are susceptible to various interference and faults, such as signal attenuation, electromagnetic interference, and temperature fluctuations, leading to system performance degradation and even communication interruption. Therefore, fault detection technology for communication modules has gradually become a research hotspot. In recent years, the integration of machine learning and artificial intelligence technologies has enabled communication module fault detection models to become automated and intelligent, capable of efficiently identifying complex fault modes and improving detection accuracy and real-time performance. However, traditional methods currently lack in-depth analysis of baseband chip clock stability and RF front-end IQ balance, making it difficult to accurately distinguish normal fluctuations from actual faults, resulting in high false alarm and missed detection rates. Furthermore, most existing solutions focus solely on fault point identification, lacking the ability to predict the fault's spread and dynamically reconfigure the topology. This makes targeted isolation and optimization impossible, increasing system risk. Summary of the Invention

[0003] Based on this, it is necessary to provide a fault detection modeling method, system and storage medium for a communication module to solve at least one of the above technical problems.

[0004] To achieve the above object, a fault detection modeling method for a communication module is provided, the method comprising the following steps: Step S1: Acquire communication module structure data; analyze the topology of the communication module structure data, and perform baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data based on the topology to obtain a baseband clock signal and an RF front-end IQ signal; Step S2: Analyze the baseband chip clock stability of the baseband clock signal to generate a clock stability feature set; analyze the RF front-end IQ balance of the RF front-end IQ signal to obtain an RF front-end IQ balance feature set; mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set to obtain a communication module anomaly marking result; Step S3: Constructing a communication module fault detection model based on the communication module anomaly labeling results, and using the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; dynamically reconstructing and isolating the communication module topology structure based on the distortion fault impact range prediction data to obtain a topology optimized structure; Step S4: Perform connectivity and performance simulation on the topology optimization structure, and perform difference area structure modeling on the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

[0005] The present invention collects the baseband clock signal and RF front-end IQ signal of the communication module and analyzes its clock stability and IQ balance respectively, which can comprehensively characterize the internal operating state of the communication module and improve the accuracy and sensitivity of anomaly detection. By constructing a clock stability feature set and an IQ balance feature set and jointly performing anomaly marking, potential modulation distortion problems in the communication module can be effectively identified, which is particularly suitable for monitoring module performance degradation in complex channels and non-ideal working environments. A fault detection model is constructed based on the anomaly marking results, which can perform feedforward prediction and quantitative analysis on the potential fault propagation path and impact area in the communication module structure, and realize global risk management for local anomalies. Dynamic reconstruction and isolation operations are performed on the topology structure based on the fault impact range prediction data, which can effectively limit the spatial spread of communication faults and improve system fault tolerance and operational reliability. By comparing the connectivity and performance simulation results of the topology optimization structure and the original structure, the difference areas are accurately extracted, guiding the communication module fault detection modeling work to focus on key areas, and realizing the refined allocation of modeling resources. This method not only improves the automation level and modeling accuracy of communication module fault detection, but also effectively enhances the overall adaptive and intelligent maintenance capabilities of the communication network through topology optimization and differential modeling mechanisms. Therefore, through multi-source signal acquisition, structural topology analysis, and dynamic simulation optimization, the present invention effectively improves the accuracy, comprehensiveness, and real-time response capabilities of communication module fault detection, addressing the problems of traditional methods such as single detection, inaccurate positioning, and lack of dynamic optimization.

[0006] Preferably, analyzing the baseband chip clock stability of the baseband clock signal in step S2 includes: Extract the clock period of the baseband clock signal and calculate the rate of change of the time interval between consecutive clock periods to generate period jitter data; Calculate the short-term frequency drift of the baseband clock signal based on the periodic jitter data, extract the short-term frequency stability characteristics, and generate short-term frequency drift characteristic data; Perform Allan variance analysis on the baseband clock signal based on the short-term frequency drift characteristic data, extract long-term stability statistical indicators, and generate long-term stability characteristic data; The periodic jitter data, short-term frequency drift feature data and long-term stability feature data are combined and fused to generate a multi-scale clock stability description vector. The multi-scale clock stability description vector is subjected to feature normalization and parameter reorganization to finally generate a clock stability feature set.

[0007] By extracting periodic jitter data, short-term frequency drift characteristics, and long-term stability indicators, covering frequency fluctuations from sub-millisecond to second levels, this method achieves cross-scale clock stability modeling and enhances the ability to accurately characterize potential jitter and offset in clock systems. Using Allan variance to perform statistical analysis on baseband clock signals effectively filters out white noise interference and identifies low-frequency random walks, thereby extracting core parameters reflecting the long-term clock drift trend, addressing the shortcomings of traditional short-term analysis methods. Periodic jitter, short-term frequency drift, and long-term stability characteristics are combined to form a multi-scale clock stability description vector, which helps to uniformly describe clock fluctuation patterns from a global perspective and provides more consistent and comprehensive data support for subsequent anomaly detection. Normalization and reorganization of the fused feature vector improves the comparability of features across different dimensions and amplitudes and their adaptability to downstream models, thereby enhancing the stability and generalization of the fault identification model. By constructing a stability feature set with multi-scale statistical characteristics in the time domain, subsequent modulation distortion anomaly labeling is not based solely on single-point features but rather incorporates temporal structural correlations, improving the robustness and fault tolerance of overall anomaly diagnosis.

[0008] Preferably, analyzing the RF front-end IQ balance of the RF front-end IQ signal in step S2 includes: Reconstruct the complex coordinates of the baseband IQ signal sampling data to generate complex coordinate data of the constellation diagram; Performing angle extraction on the complex coordinate data of the constellation diagram and dividing the area into 30° intervals to generate constellation diagram quadrant division label data; classifying and mapping the constellation diagram quadrant division label data based on the complex coordinate data of the constellation diagram to generate quadrant division mapping data; Extracting an IQ sampling point set from each quadrant in the quadrant partition mapping data to generate quadrant IQ sampling point data; Calculate the phase value of the quadrant IQ sampling point data, and perform variance operation on the phase value to generate quadrant phase offset variance data; The quadrant phase offset variance data is judged to be out of limit by using a preset quadrant threshold. When the quadrant phase offset variance data is greater than or equal to the preset quadrant threshold, the corresponding quadrant IQ sampling point data is marked as quadrant out-of-limit judgment data. Perform logical screening on the quadrant over-limit judgment data to determine whether there is any quadrant abnormality and generate quadrant imbalance detection result data; A joint analysis of quadrant imbalance is performed based on the quadrant phase offset variance data and the quadrant imbalance detection result data to obtain the quadrant amplitude-phase mismatch feature data; the object amplitude-phase mismatch feature data is structured and organized to generate the RF front-end IQ balance feature set.

[0009] The present invention divides the constellation diagram into multiple quadrants through complex coordinate reconstruction and 30° region division. The IQ sampling points within each quadrant are independently extracted and analyzed, enabling regionalized identification of IQ imbalance and accurately capturing non-ideal modulation characteristics in different directions. By calculating the variance of the phase values ​​of the sampling points within each quadrant and setting an out-of-limit determination threshold, phase offset anomalies caused by modulation link or front-end mismatch can be effectively identified, compensating for the shortcomings of traditional overall error assessment methods in local anomaly detection. Combining quadrant imbalance detection results with phase variance data for joint analysis helps to simultaneously identify IQ imbalance problems caused by amplitude mismatch and phase rotation, improving the systematicity and completeness of RF front-end anomaly characterization. By structuring the quadrant amplitude-phase mismatch features, a unified format of RF front-end IQ balance feature sets is generated, providing a stable, high-dimensional, and easily integrated input data foundation for subsequent model training and anomaly labeling. The proposed method not only quantifies signal distortion caused by nonlinear imbalance in the front-end circuit, but also locates the specific imbalance direction and quadrant distribution pattern, thereby providing a traceable basis for modulation distortion anomaly identification and module performance recovery.

[0010] Preferably, marking the modulation distortion abnormality of the communication module according to the clock stability feature set and the RF front-end IQ balance feature set in step S2 includes: If any of the following conditions occurs, the clock stability is considered abnormal and the clock stability abnormality data is obtained: the clock frequency offset exceeds ±100ppm, the clock period jitter standard deviation is greater than 2ns, or the phase noise is higher than –80dBc / Hz; When the following conditions occur simultaneously, it is determined to be an IQ balance abnormality and IQ balance abnormality data is obtained: the IQ amplitude imbalance rate is greater than 3dB, the IQ phase offset angle exceeds ±10°, and the average EVM value in the modulation constellation diagram exceeds 8%; If any of the following conditions are met simultaneously, a modulation distortion anomaly is identified and communication module modulation distortion anomaly data is obtained: the clock frequency offset exceeds ±150 ppm and the IQ amplitude imbalance rate is greater than 4 dB; the phase noise is greater than –75 dBc / Hz and the IQ phase offset angle exceeds ±15°; the period jitter exceeds 3 ns and the EVM average exceeds 10%; Integrate clock stability anomaly data, IQ balance anomaly data, and modulation distortion anomaly data. If any anomaly type occurs two or more times in three consecutive communication cycles, or a serious anomaly occurs once in a single cycle, it is marked as a communication module modulation distortion anomaly and the communication module anomaly marking result data is output.

[0011] By setting specific judgment thresholds, such as clock frequency offset ±100ppm, jitter standard deviation 2ns, and IQ amplitude imbalance rate 3dB, this system objectively quantifies communication module performance anomalies, improving the accuracy and standardization of anomaly identification. By employing a combined judgment logic based on clock stability and RF IQ balance characteristics, the system not only independently identifies anomalies but also, through feature combination, identifies complex distortion issues within the modulation process, thereby enhancing the breadth and depth of fault identification. By defining multiple combinations of anomaly conditions (such as frequency offset and amplitude imbalance, phase noise and phase offset), the system performs multi-dimensional cross-validation of the communication module's modulation link, enhancing the diagnostic capabilities for complex issues such as nonlinear distortion and system synchronization deviation. By counting the number of anomaly occurrences within consecutive cycles and identifying severe anomalies in a single cycle, the system balances the persistence and suddenness of anomalies, effectively avoiding missed detections or misjudgments and enhancing the system's ability to detect dynamic instability. By integrating abnormal data to form a unified abnormality labeling result, it can provide high-confidence basic data support for subsequent fault detection modeling, module isolation and topology optimization processes, and enhance the system's self-diagnosis and evolution capabilities.

[0012] Preferably, step S3 includes the following steps: Step S31: performing spatiotemporal distribution analysis on the communication module abnormality marking results to generate abnormal module distribution feature data; dividing the abnormal module distribution feature data into data sets to generate a model training set and a model test set; Step S32: Performing model training on the model training set using a convolutional neural network algorithm to generate a communication module fault detection pre-model; performing model optimization iteration on the communication module fault detection pre-model using the model test set to generate a communication module fault detection model; Step S33: using the communication module fault detection model to predict the fault impact range of the communication module structure data, and generate distortion fault impact range prediction data; Step S34: performing spatial propagation range fitting on the communication module fault prediction result data to generate distortion fault impact range prediction data; performing influence node extraction on the communication module topology structure based on the distortion fault impact range prediction data to generate communication topology abnormal node set data; Step S35: Execute dynamic isolation rule processing on the communication topology abnormal node set data to generate topology structure reconstruction control data; perform module isolation and reconnection on the communication module structure data combined with the topology structure reconstruction control data to generate a communication module topology optimization structure.

[0013] The present invention improves the expressive power of fault data by extracting the spatial aggregation features of abnormal modules through spatiotemporal distribution analysis, and provides more representative and generalized input data for model training. The deep learning of abnormal features using convolutional neural networks can automatically capture complex spatial correlations and potential patterns, and improve the accuracy and robustness of fault detection. Through model training and optimization iteration, a high-performance fault detection model is obtained, which effectively adapts to the diverse abnormal forms and dynamic changes of communication modules and enhances the adaptive ability of the system. Combined with the fault detection results to predict the fault impact range and fit the spatial propagation range, it is possible to accurately identify the fault propagation path and affected nodes, and realize the prediction and control of fault spread. By dynamically isolating abnormal nodes and reconstructing the topological structure, the fault impact range is effectively limited, the fault tolerance and stability of the system are improved, and the continuous and reliable operation of the communication network is guaranteed. The generation of topological optimization structure provides a more reasonable system structure foundation for subsequent fault diagnosis and maintenance, and promotes the intelligent management of communication modules and the improvement of maintenance efficiency.

[0014] Preferably, in step S35, isolating and reconnecting the communication module structure data in combination with the topology structure reconstruction control data includes: Constructing a logical connection diagram based on the communication module structure data to generate communication module logical connection diagram data; Map and synchronize the communication module logical connection diagram data with the topology reconstruction control data to generate abnormal node isolation plan data; The execution module node is disconnected for abnormal node isolation plan data, and residual structure data after node isolation is generated; Perform connectivity-preserving reconstruction analysis on the residual structure data after node isolation to generate candidate reconnection path data; Perform weighted path optimization on candidate reconnection path data to generate optimal reconnection structure data; The optimal reconnection structure data and the residual structure data after node isolation are structurally synthesized to generate the communication module topology optimization structure.

[0015] By synchronizing the mapping of logical connection diagrams with reconstruction control data, the present invention can accurately locate and isolate faulty or abnormal nodes, preventing fault propagation and ensuring the stability of the communication system. After node isolation, a connectivity-preserving reconstruction analysis is performed to ensure that the communication module network maintains a valid connectivity structure after removing abnormal nodes, avoiding communication interruption or isolation. A weighted path optimization method is used to select the optimal reconnection path based on performance indicators (such as latency, bandwidth, and load), improving network transmission efficiency and resource utilization. Through structural synthesis, the optimal reconnection structure is integrated with the residual structure to achieve dynamic adaptive optimization of the topology, enhancing the system's response and recovery capabilities to faults. The module isolation and reconnection mechanism effectively limits the scope of fault impact while ensuring the continuity and reliability of overall network operation through intelligent reconstruction, improving the robustness of the communication system. The resulting optimized topology provides a more reasonable and stable network structure for subsequent fault detection, performance monitoring, and maintenance decisions, promoting intelligent system management.

[0016] Preferably, step S4 includes the following steps: Step S41: performing graph traversal path integrity detection on the communication module topology optimization structure to generate connectivity simulation data; performing node throughput simulation on the communication module topology optimization structure to generate performance simulation data; performing multi-index aggregation analysis on the connectivity simulation data and the performance simulation data to generate simulation results; Step S42: performing node-level structural alignment on the topology optimization structure and the topological structure to generate structural alignment mapping data; performing node index difference calculation on the structural alignment mapping data based on the simulation results to generate topological difference area positioning data; Step S43: performing local topology substructure modeling on the topology difference area positioning data to perform fault detection modeling operations of the communication module.

[0017] This invention comprehensively evaluates the connectivity and performance of the optimized topology structure through graph traversal path integrity testing and node throughput simulation, ensuring that the optimized structure meets the basic functional and performance requirements of the communication network and avoiding communication interruptions or performance degradation caused by reconstruction. By integrating connectivity and performance simulation data and performing multi-dimensional indicator aggregation analysis, the system's overall state perception is enhanced, providing a scientific basis for subsequent structural adjustments and fault detection, and improving the system's intelligent decision-making capabilities. Node-level structural alignment and difference calculation accurately identify key structural changes before and after topology optimization, helping to focus fault detection modeling on key areas, avoiding resource waste and improving detection efficiency and accuracy. Based on the difference areas, local topology substructure modeling is performed, allowing in-depth fault analysis of key anomaly areas. This enables hierarchical and targeted fault detection, effectively improving the sensitivity and accuracy of fault detection. This method enables fault detection modeling to dynamically respond to topology changes, timely adjusting the model structure and monitoring focus, and enhancing the communication module's adaptability to complex environments and sudden failures. Through systematic simulation and difference analysis, a scientific basis is provided for subsequent fault warning and maintenance strategy formulation, promoting the development of intelligent and automated management of communication systems and improving operation and maintenance efficiency and reliability.

[0018] Preferably, performing node throughput simulation on the communication module topology optimization structure in step S41 includes: Simulate the node throughput of the optimized communication module topology: Establish a multi-node network model of the optimized communication module topology, which includes no fewer than eight functional nodes and no fewer than two relay nodes. The inter-node connection distance is limited to 5m to 30m, the link bandwidth is set to 10Mbps to 100Mbps, and the simulated transmission protocol adopts IEEE 802.11 or equivalent standards. Based on the set communication service type, a throughput loading simulation is performed on each node. The simulation period is not less than 60 seconds, the packet injection rate per unit time is in the range of 10pkt / s to 500pkt / s, and the size of a single packet is 128 to 2048 bytes. The communication service type includes periodic transmission, burst broadcast or multicast command transmission. The effective throughput of each node during the simulation is counted and analyzed. If a node's throughput is less than 60% of its theoretical maximum, or if there is a node with an average packet loss rate exceeding 5%, the node is marked as a throughput bottleneck. The average throughput of the entire network and the throughput variance σ are also calculated. If σ ≥ 1.5 Mbps, it is considered to be a significant load imbalance. Integrate the effective throughput data, packet loss rate, average delay and bandwidth utilization of each node to generate performance simulation data of the communication module topology.

[0019] This method simulates real-world communication network structures by configuring multifunctional nodes and relay nodes, combined with appropriate inter-node distance and link bandwidth parameters, to improve the representativeness and practicality of simulation results. It supports diverse communication services such as periodic transmission, burst broadcast, and multicast command transmission, comprehensively reflecting the performance of communication modules under different service loads and traffic patterns, and enhancing the comprehensiveness of simulation analysis. Throughput bottlenecks are marked by threshold determination (throughput below 60% of the maximum value or packet loss rate exceeding 5%), helping to quickly locate performance bottleneck nodes and providing clear targets for subsequent optimization and troubleshooting. By calculating the average throughput and throughput variance across the entire network, it identifies imbalanced load distribution, facilitating timely adjustments to network resource allocation and improving overall network efficiency and stability. By combining multi-dimensional performance indicators such as throughput, packet loss rate, latency, and bandwidth utilization, comprehensive performance simulation data is generated, providing a multi-faceted basis for communication module optimization design and fault detection. Through sophisticated modeling and multi-metric analysis, this simulation method ensures more scientific and accurate performance evaluation, effectively supporting the rationality verification of topology optimization structures and subsequent performance improvements.

[0020] In this specification, a communication module fault detection modeling system is provided, which is used to execute the above-mentioned communication module fault detection modeling method. The communication module fault detection modeling system includes: A signal acquisition module is used to obtain communication module structure data; analyze the topology of the communication module structure data, and based on the topology, perform baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data to obtain the baseband clock signal and RF front-end IQ signal; The distortion anomaly analysis module is used to analyze the baseband chip clock stability of the baseband clock signal and generate a clock stability feature set; analyze the RF front-end IQ balance of the RF front-end IQ signal and obtain an RF front-end IQ balance feature set; and mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set to obtain a communication module anomaly marking result. The fault detection module is used to build a communication module fault detection model based on the communication module anomaly labeling results, and use the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; based on the distortion fault impact range prediction data, the topology structure is dynamically reconstructed and isolated to obtain a topology optimized structure; The regional modeling module is used to simulate the connectivity and performance of the topology optimization structure, and to perform differential regional structure modeling of the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

[0021] The present invention also provides a storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the above-mentioned method for fault detection modeling of a communication module.

[0022] The beneficial effects of the present invention include enabling precise acquisition of communication module structural data and multi-dimensional signal acquisition, ensuring high-quality input of baseband clock signals and RF front-end IQ signals, and providing a reliable data foundation for subsequent analysis. Through comprehensive analysis of baseband chip clock stability and RF front-end IQ balance, a comprehensive modulation distortion anomaly identification mechanism is established, effectively improving the accuracy and sensitivity of anomaly detection and enhancing the health monitoring capabilities of the communication module. Anomaly labeling results are used to construct a fault detection model, dynamically predicting and quantifying the impact range of distortion faults, supporting data-driven intelligent fault location and risk assessment, and improving the timeliness and effectiveness of fault warnings. Combined with fault impact range prediction data, the communication module topology is dynamically reconstructed and module isolation is performed, effectively limiting fault propagation and improving the system's fault tolerance and operational stability. Through connectivity and performance simulation, as well as precise modeling of topology difference areas, fault detection modeling operations are ensured to focus on key anomaly areas, achieving optimal allocation of modeling resources and improving detection efficiency. The overall system architecture implements closed-loop management from signal acquisition to fault detection and topology optimization, promoting intelligent and automated maintenance of communication modules and enhancing the stability and reliability of network operations. Therefore, the present invention effectively improves the accuracy, comprehensiveness and real-time response capability of communication module fault detection through multi-source signal acquisition, structural topology analysis and dynamic simulation optimization, and solves the problems of single detection, inaccurate positioning and lack of dynamic optimization of traditional methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the steps of a fault detection modeling method for a communication module; Figure 2 for Figure 1 Detailed implementation steps of step S3 in FIG. Figure 3 for Figure 1 Detailed implementation steps of step S4 in FIG. The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0025] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0026] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0027] To achieve this, please refer to Figures 1 to 3 , a fault detection modeling method for a communication module, the method comprising the following steps: Step S1: Acquire communication module structure data; analyze the topology of the communication module structure data, and perform baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data based on the topology to obtain a baseband clock signal and an RF front-end IQ signal; Step S2: Analyze the baseband chip clock stability of the baseband clock signal to generate a clock stability feature set; analyze the RF front-end IQ balance of the RF front-end IQ signal to obtain an RF front-end IQ balance feature set; mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set to obtain a communication module anomaly marking result; Step S3: Constructing a communication module fault detection model based on the communication module anomaly labeling results, and using the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; dynamically reconstructing and isolating the communication module topology structure based on the distortion fault impact range prediction data to obtain a topology optimized structure; Step S4: Perform connectivity and performance simulation on the topology optimization structure, and perform difference area structure modeling on the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

[0028] The present invention collects the baseband clock signal and RF front-end IQ signal of the communication module and analyzes its clock stability and IQ balance respectively, which can comprehensively characterize the internal operating state of the communication module and improve the accuracy and sensitivity of anomaly detection. By constructing a clock stability feature set and an IQ balance feature set and jointly performing anomaly marking, potential modulation distortion problems in the communication module can be effectively identified, which is particularly suitable for monitoring module performance degradation in complex channels and non-ideal working environments. A fault detection model is constructed based on the anomaly marking results, which can perform feedforward prediction and quantitative analysis on the potential fault propagation path and impact area in the communication module structure, and realize global risk management for local anomalies. Dynamic reconstruction and isolation operations are performed on the topology structure based on the fault impact range prediction data, which can effectively limit the spatial spread of communication faults and improve system fault tolerance and operational reliability. By comparing the connectivity and performance simulation results of the topology optimization structure and the original structure, the difference areas are accurately extracted, guiding the communication module fault detection modeling work to focus on key areas, and realizing the refined allocation of modeling resources. This method not only improves the automation level and modeling accuracy of communication module fault detection, but also effectively enhances the overall adaptive and intelligent maintenance capabilities of the communication network through topology optimization and differential modeling mechanisms. Therefore, through multi-source signal acquisition, structural topology analysis, and dynamic simulation optimization, the present invention effectively improves the accuracy, comprehensiveness, and real-time response capabilities of communication module fault detection, addressing the problems of traditional methods such as single detection, inaccurate positioning, and lack of dynamic optimization.

[0029] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a flow chart of a method for fault detection and modeling of a communication module according to the present invention. In this example, the method for fault detection and modeling of a communication module includes the following steps: Step S1: Acquire communication module structure data; analyze the topology of the communication module structure data, and perform baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data based on the topology to obtain a baseband clock signal and an RF front-end IQ signal; Step S2: Analyze the baseband chip clock stability of the baseband clock signal to generate a clock stability feature set; analyze the RF front-end IQ balance of the RF front-end IQ signal to obtain an RF front-end IQ balance feature set; mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set to obtain a communication module anomaly marking result; Step S3: Constructing a communication module fault detection model based on the communication module anomaly labeling results, and using the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; dynamically reconstructing and isolating the communication module topology structure based on the distortion fault impact range prediction data to obtain a topology optimized structure; Step S4: Perform connectivity and performance simulation on the topology optimization structure, and perform difference area structure modeling on the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

[0030] In one embodiment of the present invention, a high-precision 3D scanner or industrial CT equipment is used to scan the communication module under test, obtaining detailed 3D structural data including the module's internal structural units and their connections. Software based on point cloud processing technology is then used to clean and filter the scan results, removing noise points and filling in missing data areas to ensure the integrity and accuracy of the structural data. A design file parsing tool is then used to extract the communication module's circuit design data, obtaining a detailed circuit connection topology. Combining the physical structure data with the circuit topology data, a topological diagram of the communication module is constructed. Based on this topological structure, a high-speed oscilloscope and logic analyzer are used to acquire signals from the clock lines of each baseband chip within the communication module. The acquisition clock frequency is typically set between 10 MHz and 1 GHz, with a sampling rate of no less than 5 GSa / s to ensure complete capture of signal details. Simultaneously, a vector signal analyzer is used to acquire IQ signals from the RF front-end. The sampling bandwidth should cover the module's operating frequency band (e.g., 2.4 GHz or 5 GHz), and the sampling rate should be no less than 20 MSa / s to ensure complete amplitude and phase information of the IQ signals. The baseband clock signal and RF front-end IQ signal are synchronously acquired and saved as high-resolution digital signal data for subsequent analysis. In the time domain, the zero-crossing counting method is used to calculate the clock signal's period and period jitter, with period accuracy required to reach the picosecond level and a jitter threshold set to within 100 ps. Next, a frequency-domain Fourier transform is performed to obtain the clock signal's spectral distribution, focusing on monitoring the frequency offset and sidelobe noise of the main frequency component. The frequency offset tolerance is limited to ±10 ppm. Based on the time-domain period stability and frequency-domain frequency stability, the clock signal's stability index is calculated, including the jitter standard deviation, frequency deviation mean, and spectral spurious ratio, forming a clock stability feature set. The RF front-end IQ balance analysis of the IQ signal is performed using amplitude and phase error calculation methods. After amplitude normalization of the IQ signal, the complex difference method is used to calculate the amplitude and phase imbalance of the IQ signal, with the amplitude error limited to within ±0.5 dB and the phase error to within ±3 degrees. Through time domain correlation analysis and frequency domain cross-spectral analysis, a set of IQ signal balance feature indicators is obtained. Thresholds are applied to the clock stability feature set and the IQ balance feature set. The thresholds are set based on industry standards or test experience. For example, if the jitter exceeds 100ps or the IQ error exceeds the limit, it is marked as a modulation distortion anomaly, and the communication module anomaly marking result is generated. The format is structured data containing the anomaly type, severity, and corresponding timestamp. Statistical methods are used to perform distribution analysis on the anomaly marking data, calculating the frequency of anomaly occurrence and its spatial distribution characteristics in the structural topology. Based on the topological structure diagram, the anomaly data is mapped to the corresponding structural units and their connection relationships. The fault impact propagation path analysis technology is used, combined with topological connectivity, to determine the potential spread range of the fault impact and generate distortion fault impact range prediction data.This prediction process involves constructing propagation weights from the faulty node to other nodes in a directed graph. These weights are determined based on signal transmission characteristics, connection strength, and known fault propagation patterns, and are generally set between 0.1 and 1.0. Subsequently, graph theory algorithms are used to dynamically reconstruct and isolate the communication module topology based on the predicted fault impact area. The reconstruction step involves removing the faulty node and its immediate neighbors from the topology graph and reestablishing the shortest paths and connectivity paths to the remaining nodes, ensuring remaining network connectivity with a redundancy of at least 15%. Isolation is achieved by disconnecting key edges in the faulty area. Edges are selected based on edge weights and traffic impact assessments, with a weight threshold generally set above 0.5. Finally, optimized topology data is generated, ensuring that the communication module is locally isolated within the fault impact area while maintaining the overall topology's functional integrity. Graph theory analysis tools are used to test the connectivity of the optimized topology and calculate the network connectivity index, requiring a minimum of 0.95. Network simulation software was used to simulate the data transmission performance of the optimized topology structure, with parameters set to include a transmission rate of 1 Gbps, a transmission latency of no more than 5 ms, and a packet loss rate of less than 0.01%. Based on the simulation results, the difference areas between the optimized structure and the original topology were identified. A difference structure extraction algorithm was used to extract structural difference data, such as node additions and deletions, and changes in edge connectivity. Subsequently, a difference area structural modeling module was established to perform fine-grained performance and stability modeling of the difference areas. Modeling parameters included node reliability indicators (range 0.9-1.0), link bandwidth, and latency variation range. The model was implemented using a deterministic graphical model. The results of this modeling process were used to guide subsequent fault detection modeling of the communication module, ensuring that the fault detection model accurately reflects the impact of topology changes on communication performance.

[0031] Preferably, analyzing the baseband chip clock stability of the baseband clock signal in step S2 includes: Extract the clock period of the baseband clock signal and calculate the rate of change of the time interval between consecutive clock periods to generate period jitter data; Calculate the short-term frequency drift of the baseband clock signal based on the periodic jitter data, extract the short-term frequency stability characteristics, and generate short-term frequency drift characteristic data; Perform Allan variance analysis on the baseband clock signal based on the short-term frequency drift characteristic data, extract long-term stability statistical indicators, and generate long-term stability characteristic data; The periodic jitter data, short-term frequency drift feature data and long-term stability feature data are combined and fused to generate a multi-scale clock stability description vector. The multi-scale clock stability description vector is subjected to feature normalization and parameter reorganization to finally generate a clock stability feature set.

[0032] In this embodiment of the present invention, a high-sampling-rate digital oscilloscope is used to continuously sample the baseband clock signal over a long period of time. The sampling rate must reach over 5 billion points per second, the duration must be at least 10 seconds, and the total number of sampling points must be no less than 50 million. Using predefined zero-crossing detection logic, each complete clock cycle is extracted and the changes in the time intervals between consecutive cycles are recorded to generate a data sequence describing the jitter phenomenon. This sequence is used to calculate core statistical indicators such as the average jitter variation, maximum amplitude, and degree of fluctuation. The extracted clock cycle data is then divided into sliding windows of fixed length, with each window covering approximately 100 consecutive cycles. Within each time window, an autocorrelation-based analysis method is used to extract the actual frequency variation of that segment of the signal. The frequency drift amplitude of this segment compared to the preceding and following windows is then calculated to determine the frequency drift trend within a short timeframe. This operation can identify whether the frequency rises or falls rapidly within a short period of time, and the maximum, average, and standard deviation of the frequency change rate are recorded. Subsequently, a long-term statistical analysis of the clock signal's frequency stability is performed using full signal coverage. This process averages the sampled signal over different timeframes, ranging from ten milliseconds to one second, spanning multiple timescales. At each timescale, the frequency variation trends between adjacent signal segments are calculated, extracting the average frequency fluctuation magnitude and its variation trend over long timeframes to determine the stability characteristics of the clock signal over long periods. The analysis focuses on key statistical information, including the timeframe with minimal frequency variation, the duration of the fluctuation amplitude, and the timing of frequency jumps. The clock period variation characteristics, short-term drift characteristics, and long-term stability statistical indicators obtained from the three steps above are integrated to form a comprehensive clock stability description vector. To ensure data consistency and comparability in subsequent analysis, all feature data are normalized using linear scaling within the minimum to maximum range or standard deviation normalization. The processed multidimensional features are reorganized into a standard structure, with each feature position maintaining a one-to-one correspondence with its physical meaning. For example, the first term represents the average period interval fluctuation amplitude, the second term represents the maximum short-term frequency drift value, and the third term represents the optimal timeframe for long-term stability. Ultimately, the output clock stability feature set forms a standard data structure for baseband chip clock signal stability assessment, providing a high-precision input basis for subsequent modulation anomaly identification and fault analysis. The entire processing process utilizes fixed parameter acquisition, high-precision time series processing, and a multi-scale statistical fusion strategy to ensure a comprehensive, multi-faceted, and systematic assessment of signal stability.

[0033] Preferably, analyzing the RF front-end IQ balance of the RF front-end IQ signal in step S2 includes: Reconstruct the complex coordinates of the baseband IQ signal sampling data to generate complex coordinate data of the constellation diagram; Performing angle extraction on the complex coordinate data of the constellation diagram and dividing the area into 30° intervals to generate constellation diagram quadrant division label data; classifying and mapping the constellation diagram quadrant division label data based on the complex coordinate data of the constellation diagram to generate quadrant division mapping data; Extracting an IQ sampling point set from each quadrant in the quadrant partition mapping data to generate quadrant IQ sampling point data; Calculate the phase value of the quadrant IQ sampling point data, and perform variance operation on the phase value to generate quadrant phase offset variance data; The quadrant phase offset variance data is judged to be out of limit by using a preset quadrant threshold. When the quadrant phase offset variance data is greater than or equal to the preset quadrant threshold, the corresponding quadrant IQ sampling point data is marked as quadrant out-of-limit judgment data. Perform logical screening on the quadrant over-limit judgment data to determine whether there is any quadrant abnormality and generate quadrant imbalance detection result data; A joint analysis of quadrant imbalance is performed based on the quadrant phase offset variance data and the quadrant imbalance detection result data to obtain the quadrant amplitude-phase mismatch feature data; the object amplitude-phase mismatch feature data is structured and organized to generate the RF front-end IQ balance feature set.

[0034] In this embodiment of the present invention, a radio frequency tester (such as a spectrum analyzer with IQ demodulation or a vector signal analyzer) is used to collect IQ-demodulated baseband complex signal data. The data format is a sequence of ordered pairs of in-phase (I) and quadrature (Q) components. Complex coordinate reconstruction is performed on this sequence, representing each sampling point as a complex point in a rectangular coordinate system, with the I component on the horizontal axis and the Q component on the vertical axis. This constitutes a standard constellation complex coordinate dataset. Next, the polar angle value of each complex point is calculated, and the entire constellation is divided into twelve equiangular regions of thirty degrees, serving as the constellation quadrant label regions. Each sampling point is labeled with the corresponding quadrant number based on the range of its polar angle, thereby forming constellation quadrant label data. The original complex coordinate data is paired with the quadrant labels and organized into a unified quadrant partition mapping data structure. This data is used to cluster the spatial distribution of signal points in the constellation. Based on this quadrant partition mapping data, the IQ sampling point sets in each quadrant are extracted one by one to form quadrant IQ sampling point data. Phase extraction is performed on the set of sampling points in each quadrant. The specific method is to calculate the angle of each complex point relative to the I-axis and record all phase values ​​by quadrant. Subsequently, variance statistics are analyzed on the phase value data within each quadrant to generate quadrant phase offset variance data, which reflects the degree of IQ phase dispersion within each quadrant. To identify the presence of IQ imbalance, a fixed quadrant phase offset variance threshold is set. For example, for a typical 16QAM or QPSK constellation, the phase offset variance can be capped at one degree squared (in squared angles). This threshold is determined based on empirical device testing data. The quadrant phase offset variance data is compared with the threshold. If the offset variance of a particular quadrant is greater than or equal to the threshold, that quadrant is marked as an abnormal region, generating quadrant out-of-limit judgment data. Furthermore, a logical combination analysis is performed on all quadrant out-of-limit judgment data to determine whether multiple quadrants are out-of-limit simultaneously or whether abnormal structures such as symmetry violation are present. These results are integrated into the quadrant imbalance detection result data to determine whether there is global imbalance, local offset, or amplitude-phase inconsistency. Based on the above results, a complete quadrant amplitude-phase mismatch feature data set is constructed by combining the average amplitude value, phase offset value, and balance difference between quadrants. This feature data not only includes the phase offset indicator, but also introduces supplementary data indicators such as quadrant average amplitude difference and quadrant symmetry offset to comprehensively describe the IQ mismatch characteristics. Ultimately, all quadrant amplitude-phase mismatch feature data is structured and organized to form an RF front-end IQ balance feature set with complete fields and clear data. This feature set includes the phase discreteness, amplitude consistency, and offset from the ideal constellation point of each quadrant, serving as one of the key input data for communication module modulation anomaly identification.The entire process uses analysis techniques such as high-resolution sampling, polar coordinate transformation, quadrant mapping and statistical clustering. The data processing process is fixed and has a clear structure. It does not rely on model training and directly outputs a set of interpretable features of physical measurements.

[0035] Of particular importance is the fact that the quadrant imbalance joint analysis based on the quadrant phase offset variance data and the quadrant imbalance detection result data also includes: Normalizing the quadrant phase offset variance data to generate standardized phase offset variance data; Aligning the normalized phase offset variance data with the quadrant imbalance detection result data by corresponding quadrant indexes to generate quadrant joint analysis index data; Calculate the amplitude asymmetry ratio of the quadrant joint analysis index data, extract the amplitude mismatch factor of each quadrant, and generate quadrant amplitude mismatch feature data; Extract the maximum difference of phase offset angle from the quadrant joint analysis index data to generate quadrant phase offset feature data; The quadrant amplitude mismatch feature data and the quadrant phase offset feature data are jointly fused to generate quadrant amplitude-phase mismatch feature data.

[0036] In this embodiment of the present invention, normalization is performed on quadrant phase offset variance data. Phase offset variance values ​​for all quadrants are selected and linearly normalized based on the range of their maximum and minimum values, converting the offset variance values ​​for each quadrant to a uniform value between 0 and 1. Normalization employs a fixed interval stretching method to prevent overall imbalance caused by outliers in a particular quadrant. After processing, standardized phase offset variance data is generated and used for subsequent feature calculations. Next, index alignment is performed on the standardized phase offset variance data and the quadrant imbalance detection results. Based on the quadrant number information collected by the system, each set of standardized phase offset variance values ​​and the imbalance detection results for the corresponding quadrant are arranged in a unified quadrant index order, for example, from quadrants 1 to 4. A quadrant joint analysis index data structure is constructed to ensure that the phase and imbalance values ​​for each quadrant are logically organized and consistent. Subsequently, based on the quadrant joint analysis index data, the signal amplitudes for each quadrant are extracted, compared, and the amplitude asymmetry ratio is calculated. This ratio represents the degree of deviation in amplitude between the two quadrants. The amplitude ratios between each quadrant are statistically calculated, and the result is used to measure amplitude imbalance. The amplitude mismatch factor for each quadrant is further calculated and output as quadrant amplitude mismatch feature data, which represents the asymmetry in the amplitude distribution. Furthermore, based on the same joint analysis index data, the phase offset angle values ​​for each quadrant are extracted, and the maximum inter-quadrant phase offset angle difference (i.e., the maximum phase difference between any two quadrants in the four quadrants) is calculated. This maximum difference reflects the most severe phase offset in the system's phase distribution and is output as quadrant phase offset feature data. Finally, the quadrant amplitude mismatch feature data obtained above is combined with the quadrant phase offset feature data for joint feature fusion. The fusion process uses a feature-level splicing approach, combining the amplitude mismatch factors and phase offset angle features of each quadrant into a set of high-dimensional descriptive vectors, forming the complete quadrant amplitude-phase mismatch feature data. This data is used to describe the coordinated mismatch pattern in amplitude and phase between the system's quadrant signals and provides input feature support for subsequent diagnostic modeling or fault classification. Data processing is performed using platforms such as Python and MATLAB, using vector indexing, matrix normalization, interpolation, and feature concatenation. All intermediate data is output as a structured matrix to facilitate statistical analysis and visualization.

[0037] Preferably, marking the modulation distortion abnormality of the communication module according to the clock stability feature set and the RF front-end IQ balance feature set in step S2 includes: If any of the following conditions occurs, the clock stability is considered abnormal and the clock stability abnormality data is obtained: the clock frequency offset exceeds ±100ppm, the clock period jitter standard deviation is greater than 2ns, or the phase noise is higher than –80dBc / Hz; When the following conditions occur simultaneously, it is determined to be an IQ balance abnormality and IQ balance abnormality data is obtained: the IQ amplitude imbalance rate is greater than 3dB, the IQ phase offset angle exceeds ±10°, and the average EVM value in the modulation constellation diagram exceeds 8%; If any of the following conditions are met simultaneously, a modulation distortion anomaly is identified and communication module modulation distortion anomaly data is obtained: the clock frequency offset exceeds ±150 ppm and the IQ amplitude imbalance rate is greater than 4 dB; the phase noise is greater than –75 dBc / Hz and the IQ phase offset angle exceeds ±15°; the period jitter exceeds 3 ns and the EVM average exceeds 10%; Integrate clock stability anomaly data, IQ balance anomaly data, and modulation distortion anomaly data. If any anomaly type occurs two or more times in three consecutive communication cycles, or a serious anomaly occurs once in a single cycle, it is marked as a communication module modulation distortion anomaly and the communication module anomaly marking result data is output.

[0038] In this embodiment of the present invention, the collected clock stability feature set should include multiple key indicators, including frequency offset, period jitter standard deviation, and phase noise density. The frequency offset value is directly compared with a set threshold of ±100ppm. If the measured frequency offset exceeds this range, the current test moment is recorded as a frequency anomaly marker. The period jitter standard deviation is calculated based on the standard deviation data obtained after sliding window averaging in the previous step. If this value is greater than 2 nanoseconds, a period jitter anomaly flag is added to the anomaly flag table. Similarly, for the phase noise metric, the phase noise density is measured at a specific offset frequency (such as 1kHz or 10kHz). If it exceeds -80dB relative to the carrier per Hz, a phase noise anomaly flag is added. If any of these indicators is triggered, a clock stability anomaly is identified, and a structured clock anomaly dataset is generated, including the anomaly type, trigger indicator name, value, and limit-exceeding amplitude. Next, the IQ amplitude ratio of the RF front-end IQ signal is extracted, and the imbalance rate is calculated. The maximum amplitudes of the I and Q channels are counted separately, the ratio is calculated, converted to decibels, and compared to a 3dB upper limit. If exceeded, an amplitude imbalance anomaly is flagged. For the phase offset angle, the average polar angle offset of all IQ sample points is calculated. If it exceeds ±10 degrees, a phase asymmetry anomaly is flagged. Furthermore, the average error vector magnitude (EVM) percentage is calculated based on the measured RMS distance of each sample point from its ideal position in the constellation diagram. If it exceeds 8%, it is recorded as an overall constellation distortion. Only when all three conditions are met simultaneously is IQ balance anomaly data generated, including complete data fields such as IQ channel amplitude, average offset angle, and constellation diagram offset indicators. These two types of anomaly indicators are then combined to determine whether a combined modulation distortion anomaly condition is triggered. If any combination of these conditions is present, such as the simultaneous presence of a frequency offset exceeding ±150ppm and an amplitude imbalance exceeding 4dB, or a phase noise exceeding –75dB / Hz and a phase offset exceeding ±15 degrees, a modulation distortion anomaly event is flagged. Each combined event needs to form a structured record item, indicating the corresponding indicator name, measurement value, set threshold and over-limit amplitude. Finally, establish an abnormality frequency record table and compare the collected communication module data within at least three consecutive communication cycles. If any abnormality (clock stability abnormality, IQ balance abnormality or modulation distortion abnormality) occurs twice or more in three cycles, or if there is a serious abnormality in a certain cycle where any single indicator exceeds the set threshold by more than twice (such as frequency offset exceeds ±300ppm, EVM is greater than 20%), it will be marked as "communication module modulation distortion abnormality" and the final abnormality marking result data will be output. This data should include the abnormality category, corresponding cycle number, number of abnormality types, the most serious indicator value and its corresponding parameter source, and be used as input basis for subsequent modeling tasks and system alarm processes.The entire labeling process is based on a static threshold system and combinatorial logic judgment. It does not rely on any model or reasoning algorithm and has clear data flow paths and judgment rules.

[0039] As an example of the present invention, refer to Figure 2 As shown, in this example, step S3 includes: Step S31: performing spatiotemporal distribution analysis on the communication module abnormality marking results to generate abnormal module distribution feature data; dividing the abnormal module distribution feature data into data sets to generate a model training set and a model test set; Step S32: Performing model training on the model training set using a convolutional neural network algorithm to generate a communication module fault detection pre-model; performing model optimization iteration on the communication module fault detection pre-model using the model test set to generate a communication module fault detection model; Step S33: using the communication module fault detection model to predict the fault impact range of the communication module structure data, and generate distortion fault impact range prediction data; Step S34: performing spatial propagation range fitting on the communication module fault prediction result data to generate distortion fault impact range prediction data; performing influence node extraction on the communication module topology structure based on the distortion fault impact range prediction data to generate communication topology abnormal node set data; Step S35: Execute dynamic isolation rule processing on the communication topology abnormal node set data to generate topology structure reconstruction control data; perform module isolation and reconnection on the communication module structure data combined with the topology structure reconstruction control data to generate a communication module topology optimization structure.

[0040] In this embodiment of the present invention, abnormality flagging data collected during the operation of a communication module is acquired. This data should include a timestamp, abnormal module number, abnormality category, physical area number (e.g., cabinet number or board number), and the communication module's location within the overall communication topology. Based on the timestamp field, abnormal events are divided into time windows at fixed time intervals (e.g., 5-minute or 30-minute intervals) to form a time period abnormality statistics table. For each time period, the number of abnormal modules, the frequency of abnormal events, and the distribution of abnormal categories are counted and arranged in order by time window to form a time series abnormality curve. Regarding spatial distribution, the abnormal module numbers are mapped to a two-dimensional or three-dimensional spatial coordinate system based on the spatial location of the communication module in the physical deployment diagram. For example, for modules distributed within a communication cabinet, the cabinet numbers are used to divide the areas, and a module spatial location matrix is ​​constructed based on the module's specific location (e.g., level or row number). Spatial clustering analysis is performed on the abnormal events, using density-based clustering methods (e.g., DBSCAN) to identify the physical clusters of abnormal modules, generating abnormal module cluster data. This clustered data is combined with the time series anomaly curve data to construct anomaly module distribution feature data, which serves as feature extraction input for subsequent model training. Subsequently, the anomaly module distribution feature data is randomly partitioned based on the mixed distribution characteristics of the temporal and spatial dimensions. 70% of the data serves as the model training set, and 30% as the model testing set, ensuring consistency in the distribution of anomaly type, module region, and time period between the training and testing sets. This partitioned dataset serves as the input data structure for subsequent steps. The data format is fixed, and each data entry should contain fields such as the anomaly module number, anomaly time period number, anomaly category code, physical location coordinates, and the topological path node number. A standard convolutional neural network architecture (such as ResNet or a simplified version of VGGNet) is used. The input layer is set to a concatenated matrix consisting of a time series anomaly vector with a time series length of 20 and a module spatial location coordinate vector. The input size is 20×6 (20 time slices, 6 spatial or topological features). The first layer of the network is a two-dimensional convolutional layer with a kernel size of 3×3, 64 convolution kernels, and a ReLU activation function. Next, a maximum pooling layer is connected for spatiotemporal feature compression. Two consecutive convolutional layers are then set to extract local spatial anomaly patterns, followed by a fully connected layer to output the impact of anomalies on the classification results. The cross-entropy function is selected as the loss function, and the Adam algorithm is used as the optimizer. The learning rate is initially set to 0.001, and the number of training rounds is set to 100. After each iteration, the accuracy, recall, and F1 score are evaluated on the test set and recorded in the model evaluation log. After training is complete, the optimal weighted version with stable training and test accuracy is selected as the pre-model for communication module fault detection.The pre-model is used for error analysis on the test set. Based on the areas of misjudgment, the number of convolutional channels or feature combinations in the network architecture is adjusted inversely. For example, a regional attention mechanism is introduced for easily confused regions to improve detection resolution. The final communication module fault detection model is constructed through at least three rounds of optimization iterations. The input of the final model is the distribution feature data of abnormal modules, and the output is the fault impact level label and the identification of the affected region for each module. The model is fed with the structural data of the actual communication modules in operation. This structural data must first be converted into a standard input format, including each module's topological node number, physical coordinates, historical anomaly labels, and historical neighboring node status, and then constructed into a graph-like adjacency matrix. This structured input is fed into the fault detection model, and the fault impact level output value for each module is calculated. Based on the output values, the module numbers of all modules with a fault impact level above a set threshold (e.g., 0.7) are extracted. Combined with their topological neighbors, the information is propagated two levels (i.e., one-hop and two-hop neighbors) to the surrounding neighborhood using a path extension algorithm. These nodes are then marked as nodes within the potential fault impact range. All affected nodes are organized into a prediction dataset, named the distortion fault impact range prediction data. This data structure must include fields such as module number, impact level, fault transmission path length, associated upstream node number, and downstream path length, serving as the input for the next step of spatial fitting. Multivariate surface fitting is first performed on the spatial coordinates of the affected nodes. Using radial basis function interpolation, a distribution function for the fault impact field is constructed in three-dimensional physical space. Based on this distribution function, equipotential surfaces are calculated. The propagation threshold is defined as the spatial boundary at an impact level of 0.5, forming a fault propagation range boundary surface. This boundary surface is then spatially partitioned into voxels, and the regions containing the largest number of abnormal nodes are counted as critical impact regions. These voxel regions are mapped back into the topology map, and the numbers of all communication modules intersecting these voxel regions are extracted to generate the abnormal node set data for the communication topology. Dynamic isolation rules are set, including: direct disconnection when a single node fault level exceeds 0.8; regional isolation when a continuous abnormal chain of more than two nodes within a three-hop neighborhood is exceeded; and isolated nodes must not exceed 30% of the total number of nodes in the topology. Based on the above rules, an isolation control strategy mapping table is constructed within the communication topology graph, marking the communication paths to be disconnected. Subsequently, based on the current topology graph and the isolation control mapping table, a graph reconstruction function is called. This function involves disconnecting the designated path, inserting a backup connection (using the shortest physically distance path selected from predefined candidate module connection paths), and recalculating the shortest path hop count and network connectivity. Ultimately, topology reconstruction control data is generated and applied to the original communication module structure data to generate a new topology connection structure, forming an optimized communication module topology structure.This structure is output in the form of an adjacency matrix and a physical connection path table. The data structure must include the reconstructed module number, connection node number, connection path number, reconstruction operation type (disconnect / reconnect) and affected node list for subsequent system deployment modules to perform configuration updates.

[0041] Preferably, in step S35, isolating and reconnecting the communication module structure data in combination with the topology structure reconstruction control data includes: Constructing a logical connection diagram based on the communication module structure data to generate communication module logical connection diagram data; Map and synchronize the communication module logical connection diagram data with the topology reconstruction control data to generate abnormal node isolation plan data; The execution module node is disconnected for abnormal node isolation plan data, and residual structure data after node isolation is generated; Perform connectivity-preserving reconstruction analysis on the residual structure data after node isolation to generate candidate reconnection path data; Perform weighted path optimization on candidate reconnection path data to generate optimal reconnection structure data; The optimal reconnection structure data and the residual structure data after node isolation are structurally synthesized to generate the communication module topology optimization structure.

[0042] In an embodiment of the present invention, a logical connection graph is established based on communication module structure data. Each communication module is considered a node, and the actual physical connections between modules are considered edges, forming an undirected graph structure. Node numbers are assigned based on the module's unique number within the structure, and edge weights are initially set to 1, indicating a clear communication path. All nodes and connection relationships are organized into an adjacency list to generate communication module logical connection graph data. This data is stored and managed using a graph database such as Neo4j or a graph processing framework such as NetworkX. Subsequently, topology reconstruction control data is loaded. This data should include the numbers of nodes marked as abnormal, the start and end node numbers of edges to be disconnected, designated isolation paths, and definitions of candidate alternative paths. This data is compared item by item with the communication module logical connection graph data, and a mapping is performed based on the node numbers to generate abnormal node isolation plan data. This data records fields such as the edge number to be disconnected, the module number to which it belongs, and the type of disconnection operation (single point isolation or link isolation). Module node disconnection operations are executed based on the abnormal node isolation plan data. The specific approach is to logically delete all marked disconnected edges, removing the corresponding connection relationships from the adjacency table and marking them as "disconnected" in the connection graph. The disconnection operation does not change the original node numbers; it only changes the connection status. After the disconnection is complete, a connectivity analysis is performed on the current connection graph to identify the independent subgraphs resulting from the disconnection operation and save them as residual structure data after node isolation. Next, based on this residual structure data, the original connectivity graph structure is analyzed to determine if there are any interruptions. Communication links with isolated nodes or where the number of connection path hops has increased by more than two times are marked as "areas requiring reconnection." Within these areas, all reconnection paths are searched within a range of three hops from the node, meaning that each node searches for alternative paths among its three adjacent nodes. Path search is based on a depth-first traversal of the graph, recording the start and end nodes, path length, and node number sequence of each candidate path to generate candidate reconnection path data. Weighted path optimization is then performed on the candidate reconnection path data. The weight of each path is calculated based on the following parameters: number of hops (shortest first), current path load (lower is better), and the health level of the nodes in the path (higher is better). A weighted evaluation function is used to calculate the overall path quality score. For each set of start and end nodes, only the path with the highest score is retained as the optimal path. All optimal path data are merged to form the optimal reconnection structure data. Finally, the optimal reconnection structure data is combined with the residual structure data after node isolation.The processing includes: inserting the newly generated optimal path connection relationship into the original graph and updating the adjacency list structure; re-evaluating the number of hops of the shortest communication path between all nodes and correcting the topology path table; updating the status of the nodes involved in the newly added path to "reconnection participation", and the final graph structure generated is used as the communication module topology optimization structure. Its output format includes the node connection matrix, node status identification table, path redundancy index and the updated communication module deployment table, which can be called by subsequent simulation verification modules or control systems.

[0043] As an example of the present invention, refer to Figure 3 As shown, in this example, step S4 includes: Step S41: performing graph traversal path integrity detection on the communication module topology optimization structure to generate connectivity simulation data; performing node throughput simulation on the communication module topology optimization structure to generate performance simulation data; performing multi-index aggregation analysis on the connectivity simulation data and the performance simulation data to generate simulation results; Step S42: performing node-level structural alignment on the topology optimization structure and the topological structure to generate structural alignment mapping data; performing node index difference calculation on the structural alignment mapping data based on the simulation results to generate topological difference area positioning data; Step S43: performing local topology substructure modeling on the topology difference area positioning data to perform fault detection modeling operations of the communication module.

[0044] In this embodiment of the present invention, the communication module topology optimization structure generated in the previous steps is converted into graph structure data and input into a graph simulation tool, such as the NS-3 network simulator or a custom Python-based graph traversal and throughput analysis scripting environment. A graph traversal path integrity check is performed, using breadth-first and depth-first search algorithms to search for paths among all nodes in the graph. The existence of the shortest path between all nodes is counted, and unconnected node pairs are recorded to generate a path integrity report. This report is saved in matrix form, noting whether there is a valid connection between each pair of nodes, generating connectivity simulation data. Subsequently, an equal number of virtual data packet transmission tasks are applied to each node in the topology to simulate parallel data transmission between communication modules. By setting the virtual data packet size (e.g., 512 bytes), the transmission rate (e.g., 100 packets per second), and the simulation time window (e.g., 30 seconds), the data reception rate, average response time, and packet loss rate of each node are sampled to generate throughput data for each node. This process simulates ideal forwarding performance without considering link outages. The simulation process sets a maximum inter-node transmission bandwidth cap (e.g., 10 Mbps) and records the transmission success rate and retransmission count of each node to generate performance simulation data. Finally, a multi-metric aggregation analysis is performed on the connectivity and performance simulation data. This aggregation analysis uses normalization to process the metric data and calculates core metrics such as connectivity integrity (node-pair accessibility), average node throughput, and throughput deviation. Tabulated simulation results are generated according to a unified structure, providing comparable simulation result data. The optimized communication module topology obtained by simulation is aligned with the original communication module topology at the node level. This structural alignment, based on the node unique number matching rule, maps the two topologies one-to-one by node number. This generates structural alignment mapping data, which lists all matching node pairs, their positions in both structures, connecting edge information, and corresponding attribute values ​​in a comparison table format. The simulation result data is then retrieved and, based on the node number alignment, performance metrics such as throughput, number of connected paths, and average path hop count are read for each mapped node pair. The difference in these metrics for each node in the two structures is calculated. Nodes whose variance exceeds a preset threshold (e.g., a throughput drop greater than 20% or a path hop count increase of more than two levels) are marked and recorded as structurally mutated nodes. Their adjacent nodes and connected edges are then traced back to identify regions of significant structural change, generating topologically mutated region location data. Based on this topologically mutated region location data, a local subgraph containing the mutated node and its one-hop adjacent nodes is extracted from the optimized structure to generate a local topological substructure sample. Each local subgraph undergoes structural vectorization, calculating graph feature parameters such as connectivity distribution, node degree distribution, average path length, and clustering coefficient. These subgraphs are then labeled based on the structural features of historically known fault types to construct a fault feature sample library.Subsequently, graph-structure modeling techniques are used to encode the features of these local substructures. For example, graph embedding methods are used to convert them into high-dimensional vector representations. Clustering methods (such as density clustering or hierarchical clustering) are then used to identify substructure regions with similar structural characteristics. The clustering results can be used to summarize typical topological morphological types of fault regions. Based on these morphological types, structural backtracking is performed to extract the causes of formation and their evolution within the original structure. Ultimately, the graph structure, parameter characteristics, and topological evolution trends obtained during this local modeling process are compiled into a standard modeling output, forming a sample library of fault detection models that can be used for subsequent communication module structural health assessment and simulation verification, serving as the final result of the communication module fault detection modeling process.

[0045] Of particular importance is the graph traversal path integrity test for the communication module topology optimization structure, which also includes: Extract nodes from the topology optimization structure of the communication module to generate topology node set data; Construct a directed graph path table based on the topological node set data and generate topological path connection data; Perform breadth-first traversal on the topological path connection data, mark the traversed reachable areas, and generate path coverage mark data; Perform full node coverage statistics on the path coverage mark data, calculate the path integrity index, and generate path integrity evaluation data; Based on the path integrity assessment data, abnormal or broken connection segments are marked and connectivity simulation data is output.

[0046] In an embodiment of the present invention, node extraction is performed on the topologically optimized structure of the communication module. By parsing the structural connectivity information of the communication module, all actual functional nodes and relay nodes in the structure are extracted. Each node is identified by a unique number, and its adjacency relationships are extracted to form standardized topological node set data. The node type, connection direction, and physical location are also recorded as node attributes to ensure accurate subsequent graph structure construction. Next, a directed graph path table is constructed based on the topological node set data. The adjacency relationships of each node are traversed, and directed edges are constructed based on the connection direction. The information of each edge is recorded in a triple format: starting point, end point, and path weight (e.g., link bandwidth or latency), generating topological path connection data. This directed graph path table is used to represent the logical connectivity relationships within the entire communication module, facilitating subsequent graph algorithm processing. Subsequently, a breadth-first traversal is performed on the topological path connection data. Starting from any master control node or data receiving node, a breadth-first search algorithm is used to traverse the entire graph layer by layer. Each time a node is visited, it is marked as reachable, and its adjacent nodes are added to a queue for continued traversal until all connected regions in the graph are marked. The traversal results record the reachability of each node as a Boolean flag, forming path coverage data. The path coverage data is then used to calculate the node coverage rate. The ratio of the number of nodes successfully marked as reachable to the total number of nodes in the topology is calculated to form a coverage metric. If the coverage rate falls below a set threshold (e.g., 98%), it indicates that some nodes are not covered by the path traversal. Further backtracking analysis is performed on these unvisited nodes. The number and proportion of paths that are unreachable due to broken links or one-way communication anomalies are calculated to form path integrity metrics, which are then output as path integrity assessment data. Finally, based on the path integrity assessment data, path segments with abnormal or broken connections are marked. A connection validity check is performed on all paths connecting untraversed nodes to their upstream connections. If a path has a wrong link direction, an isolated node, or zero transmission capacity, the path segment is marked as abnormal. Information on all broken or abnormal path segments is integrated to generate structured connectivity simulation data, which is used to identify potential structural flaws and topology design issues in the communication module network. This process can be implemented in Python using graph processing tools (such as the NetworkX library). This process, combined with a node attribute database, connection weight table, and simulation parameter setting module, allows for full-graph traversal, connectivity assessment, and anomaly identification. All intermediate data is retained in a traceable data frame format for subsequent performance optimization and simulation iteration.

[0047] Preferably, performing node throughput simulation on the communication module topology optimization structure in step S41 includes: Simulate the node throughput of the optimized communication module topology: Establish a multi-node network model of the optimized communication module topology, which includes no fewer than eight functional nodes and no fewer than two relay nodes. The inter-node connection distance is limited to 5m to 30m, the link bandwidth is set to 10Mbps to 100Mbps, and the simulated transmission protocol adopts IEEE 802.11 or equivalent standards. Based on the set communication service type, a throughput loading simulation is performed on each node. The simulation period is not less than 60 seconds, the packet injection rate per unit time is in the range of 10pkt / s to 500pkt / s, and the size of a single packet is 128 to 2048 bytes. The communication service type includes periodic transmission, burst broadcast or multicast command transmission. The effective throughput of each node during the simulation process is counted and analyzed. If a node's throughput is less than 60% of its theoretical maximum, or if there is a node with an average packet loss rate exceeding 5%, the node is marked as a throughput bottleneck. The average throughput of the entire network and the throughput variance σ are also calculated. If σ ≥ 1.5 Mbps, it is considered that there is a significant load imbalance. Integrate the effective throughput data, packet loss rate, average delay and bandwidth utilization of each node to generate performance simulation data of the communication module topology.

[0048] In this embodiment of the present invention, a multi-node network simulation model is constructed based on the optimized topology of the communication module. The model includes at least eight functional nodes and two relay nodes. The relative positions of the nodes in three-dimensional space are determined according to the actual device layout, and the connection distance between nodes is limited to 5 to 30 meters. Link bandwidth parameters are set according to device specifications, ranging from 10 Mbps to 100 Mbps, ensuring coverage for both low-speed and high-speed communication needs. The simulation environment uses a wireless transmission protocol that complies with the IEEE 802.11 protocol suite, supporting multiple transmission modes and rate control to ensure that the simulation results meet actual communication conditions. Secondly, a variety of communication service types are set to simulate real-world scenarios. These include periodic data transmission, burst broadcast, and multicast command transmission. Each service type is simulated at a preset packet injection rate, with a simulation period of no less than 60 seconds to cover different load fluctuation periods. The packet injection rate is controlled between 10 and 500 packets per second, and the size of a single packet ranges from 128 bytes to 2048 bytes, covering both small control signaling and large data block transmission. During the simulation, the effective throughput of each node is calculated in real time: the amount of valid data successfully transmitted divided by the simulation duration, measured in Mbps. Packet loss is also monitored, the packet loss percentage for each node is calculated, and the average packet delay and link bandwidth utilization are recorded. Each node's throughput is compared with its theoretical maximum throughput capacity. If a node's throughput falls below 60% of the maximum, or its average packet loss rate exceeds 5%, the node is marked as a throughput bottleneck for subsequent performance bottleneck location analysis. Furthermore, network-wide node throughput data is aggregated to calculate the overall average throughput and throughput variance. If the throughput variance is greater than or equal to 1.5 Mbps, the network is deemed to have significant load imbalance. Network performance metrics, including node throughput, packet loss rate, average latency, and bandwidth utilization, are integrated to form a performance simulation dataset for the optimized communication module topology. All collected simulation data is stored in a database or structured file in a format that supports subsequent statistical analysis and visualization, facilitating fault diagnosis and network optimization evaluation. The simulation tool uses a software platform with accurate physical layer and MAC layer modeling capabilities, such as NS-3, OMNeT++, or self-developed simulation framework to ensure the authenticity and reliability of the simulation data.

[0049] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0050] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A fault detection modeling method for a communication module, characterized in that: The following steps are involved: Step S1: Obtain communication module structure data; Analyze the topology of the communication module structure data, and based on the topology, collect baseband clock signals and RF front-end signals to obtain baseband clock signals and RF front-end IQ signals. Step S2: Analyze the baseband chip clock stability of the baseband clock signal and generate a clock stability feature set; Analyze the RF front-end IQ balance of the RF front-end IQ signal to obtain an RF front-end IQ balance feature set; Mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set, and obtain the communication module anomaly marking result; Step S3: Constructing a communication module fault detection model based on the communication module anomaly labeling results, and using the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; dynamically reconstructing and isolating the communication module topology structure based on the distortion fault impact range prediction data to obtain a topology optimized structure; Step S4: Perform connectivity and performance simulation on the topology optimization structure, and perform difference area structure modeling on the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

2. The fault detection modeling method of the communication module according to claim 1, characterized in that: Analyzing the baseband chip clock stability of the baseband clock signal in step S2 includes: Extract the clock period of the baseband clock signal and calculate the rate of change of the time interval between consecutive clock periods to generate period jitter data; Calculate the short-term frequency drift of the baseband clock signal based on the periodic jitter data, extract the short-term frequency stability characteristics, and generate short-term frequency drift characteristic data; Perform Allan variance analysis on the baseband clock signal based on the short-term frequency drift characteristic data, extract long-term stability statistical indicators, and generate long-term stability characteristic data; The periodic jitter data, short-term frequency drift feature data and long-term stability feature data are combined and fused to generate a multi-scale clock stability description vector. The multi-scale clock stability description vector is subjected to feature normalization and parameter reorganization to finally generate a clock stability feature set.

3. The fault detection modeling method of the communication module according to claim 1, characterized in that: Analyzing the RF front-end IQ balance of the RF front-end IQ signal in step S2 includes: Reconstruct the complex coordinates of the baseband IQ signal sampling data to generate complex coordinate data of the constellation diagram; Performing angle extraction on the complex coordinate data of the constellation diagram and dividing the area into 30° intervals to generate constellation diagram quadrant division label data; classifying and mapping the constellation diagram quadrant division label data based on the complex coordinate data of the constellation diagram to generate quadrant division mapping data; Extracting an IQ sampling point set from each quadrant in the quadrant partition mapping data to generate quadrant IQ sampling point data; Calculate the phase value of the quadrant IQ sampling point data, and perform variance operation on the phase value to generate quadrant phase offset variance data; The quadrant phase offset variance data is judged to be out of limit by using a preset quadrant threshold. When the quadrant phase offset variance data is greater than or equal to the preset quadrant threshold, the corresponding quadrant IQ sampling point data is marked as quadrant out-of-limit judgment data. Perform logical screening on the quadrant over-limit judgment data to determine whether there is any quadrant abnormality and generate quadrant imbalance detection result data; A joint analysis of quadrant imbalance is performed based on the quadrant phase offset variance data and the quadrant imbalance detection result data to obtain the quadrant amplitude-phase mismatch feature data; the object amplitude-phase mismatch feature data is structured and organized to generate the RF front-end IQ balance feature set.

4. The fault detection modeling method of the communication module according to claim 1, characterized in that: In step S2, marking the modulation distortion anomaly of the communication module according to the clock stability feature set and the RF front-end IQ balance feature set includes: If any of the following conditions occurs, the clock stability is considered abnormal and the clock stability abnormality data is obtained: the clock frequency offset exceeds ±100ppm, the clock period jitter standard deviation is greater than 2ns, or the phase noise is higher than –80dBc / Hz; When the following conditions occur simultaneously, it is determined to be an IQ balance abnormality and IQ balance abnormality data is obtained: the IQ amplitude imbalance rate is greater than 3dB, the IQ phase offset angle exceeds ±10°, and the average EVM value in the modulation constellation diagram exceeds 8%; If any of the following conditions are met simultaneously, a modulation distortion anomaly is identified and communication module modulation distortion anomaly data is obtained: the clock frequency offset exceeds ±150 ppm and the IQ amplitude imbalance rate is greater than 4 dB; the phase noise is greater than –75 dBc / Hz and the IQ phase offset angle exceeds ±15°; the period jitter exceeds 3 ns and the EVM average exceeds 10%; Integrate clock stability anomaly data, IQ balance anomaly data, and modulation distortion anomaly data. If any anomaly type occurs two or more times in three consecutive communication cycles, or a serious anomaly occurs once in a single cycle, it is marked as a communication module modulation distortion anomaly and the communication module anomaly marking result data is output.

5. The fault detection modeling method of the communication module according to claim 1, characterized in that: Step S3 includes the following steps: Step S31: performing spatiotemporal distribution analysis on the communication module abnormality marking results to generate abnormal module distribution feature data; dividing the abnormal module distribution feature data into data sets to generate a model training set and a model test set; Step S32: Performing model training on the model training set using a convolutional neural network algorithm to generate a communication module fault detection pre-model; performing model optimization iteration on the communication module fault detection pre-model using the model test set to generate a communication module fault detection model; Step S33: using the communication module fault detection model to predict the fault impact range of the communication module structure data, and generate distortion fault impact range prediction data; Step S34: performing spatial propagation range fitting on the communication module fault prediction result data to generate distortion fault impact range prediction data; performing influence node extraction on the communication module topology structure based on the distortion fault impact range prediction data to generate communication topology abnormal node set data; Step S35: Execute dynamic isolation rule processing on the communication topology abnormal node set data to generate topology structure reconstruction control data; perform module isolation and reconnection on the communication module structure data combined with the topology structure reconstruction control data to generate a communication module topology optimization structure.

6. The fault detection modeling method for a communication module according to claim 5, characterized in that: In step S35, the communication module structure data is combined with the topology structure reconstruction control data to perform module isolation and reconnection, including: Constructing a logical connection diagram based on the communication module structure data to generate communication module logical connection diagram data; Map and synchronize the communication module logical connection diagram data with the topology reconstruction control data to generate abnormal node isolation plan data; The execution module node is disconnected for abnormal node isolation plan data, and residual structure data after node isolation is generated; Perform connectivity-preserving reconstruction analysis on the residual structure data after node isolation to generate candidate reconnection path data; Perform weighted path optimization on candidate reconnection path data to generate optimal reconnection structure data; The optimal reconnection structure data and the residual structure data after node isolation are structurally synthesized to generate the communication module topology optimization structure.

7. The fault detection modeling method for a communication module according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: performing graph traversal path integrity detection on the communication module topology optimization structure to generate connectivity simulation data; performing node throughput simulation on the communication module topology optimization structure to generate performance simulation data; performing multi-index aggregation analysis on the connectivity simulation data and the performance simulation data to generate simulation results; Step S42: performing node-level structural alignment on the topology optimization structure and the topological structure to generate structural alignment mapping data; performing node index difference calculation on the structural alignment mapping data based on the simulation results to generate topological difference area positioning data; Step S43: performing local topology substructure modeling on the topology difference area positioning data to perform fault detection modeling operations of the communication module.

8. The fault detection modeling method for a communication module according to claim 7, characterized in that: The node throughput simulation of the communication module topology optimization structure in step S41 includes: Simulate the node throughput of the optimized communication module topology: Establish a multi-node network model of the optimized communication module topology, which includes no fewer than eight functional nodes and no fewer than two relay nodes. The inter-node connection distance is limited to 5m to 30m, the link bandwidth is set to 10Mbps to 100Mbps, and the simulated transmission protocol adopts IEEE 802.11 or equivalent standards. Based on the set communication service type, a throughput loading simulation is performed on each node. The simulation period is not less than 60 seconds, the packet injection rate per unit time is in the range of 10pkt / s to 500pkt / s, and the size of a single packet is 128 to 2048 bytes. The communication service type includes periodic transmission, burst broadcast or multicast command transmission. The effective throughput of each node during the simulation is counted and analyzed. If a node's throughput is less than 60% of its theoretical maximum, or if there is a node with an average packet loss rate exceeding 5%, the node is marked as a throughput bottleneck. The average throughput of the entire network and the throughput variance σ are also calculated. If σ ≥ 1.5 Mbps, it is considered to be a significant load imbalance. Integrate the effective throughput data, packet loss rate, average delay and bandwidth utilization of each node to generate performance simulation data of the communication module topology.

9. A fault detection modeling system for a communication module, characterized in that: A method for performing a fault detection modeling method for a communication module according to claim 1, wherein the fault detection modeling system for the communication module comprises: A signal acquisition module is used to obtain communication module structure data; analyze the topology of the communication module structure data, and based on the topology, perform baseband clock signal acquisition and RF front-end signal acquisition on the communication module structure data to obtain the baseband clock signal and RF front-end IQ signal; The distortion anomaly analysis module is used to analyze the baseband chip clock stability of the baseband clock signal and generate a clock stability feature set; analyze the RF front-end IQ balance of the RF front-end IQ signal and obtain an RF front-end IQ balance feature set; and mark the modulation distortion anomaly of the communication module based on the clock stability feature set and the RF front-end IQ balance feature set to obtain a communication module anomaly marking result. The fault detection module is used to build a communication module fault detection model based on the communication module anomaly labeling results, and use the communication module fault detection model to predict the fault impact range of the communication module structure data to generate distortion fault impact range prediction data; based on the distortion fault impact range prediction data, the topology structure is dynamically reconstructed and isolated to obtain a topology optimized structure; The regional modeling module is used to simulate the connectivity and performance of the topology optimization structure, and to perform differential regional structure modeling of the topology optimization structure and the topology structure based on the simulation results to perform fault detection modeling operations for the communication module.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the fault detection modeling method of the communication module as described in any one of claims 1 to 8.

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