Power semiconductor device and method for producing power semiconductor device

Abstract

A power semiconductor device and a method of producing a power semiconductor device. A power semiconductor device includes a trench structure including one or more control trenches, each of the one or more control trenches including a control trench electrode isolated from a first load terminal and configured to control a forward load current, and a plurality of source trenches, each source trench includes a source trench electrode electrically connected to a first load terminal. A plurality of mesas are configured to conduct a forward load current, where each mesa surrounds one of the source trenches and is surrounded by one or more of the one or more control trenches. A plurality of first contact plugs extend along a vertical direction from a first load terminal toward a first side, where each first contact plug is associated with one of source trenches and one of mesas surrounding the source trenches and is configured to contact both the mesas and source trench electrodes of the source trenches.

Description

Technical Field

[0001] This description relates to embodiments of a power semiconductor device and embodiments of a method of producing a power semiconductor device. Background Art

[0002] Many functions of modern devices in automotive, consumer, and industrial applications—such as converting electrical energy and driving electric motors or electric machines—rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and diodes, to name a few, have been used in a variety of applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device includes a semiconductor body configured to conduct a positive load current along a load current path between two load terminals of the device. The load current is conducted via an active region of the power semiconductor device. The active region is surrounded by an edge termination region, which is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device, such as a transistor, the load current path can be controlled by means of an insulated electrode, often referred to as a gate electrode. For example, upon receiving a corresponding control signal, such as from a driver unit and via a control terminal of the device, the control electrode can set the power semiconductor device in one of a forward conducting state and a blocking state.

[0005] Furthermore, some devices provide reverse load current capability, i.e., the active region of the semiconductor body is further configured to conduct a reverse load current along a reverse load current path between two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such devices. In an RC IGBT, a single chip combines an IGBT structure and a diode structure.

[0006] In a typical IGBT design, the gate electrode is housed in a trench structure extending into the semiconductor body. The trench structure spatially confines a portion of the semiconductor body, typically called a mesa, within which a conductive channel can form, allowing forward load current to flow. The conductive channel, typically based on a semiconductor source region and a semiconductor body region of opposite conductivity to the source region, is controlled by an adjacent control electrode.

[0007] For example, to achieve favorable charge carrier confinement, specific dimensions of the mesa may be appropriate, e.g., in terms of lateral extension (width) and / or vertical extension (height). However, if the width of the mesa becomes smaller, reliably establishing an electrical connection between the mesa and the load terminals may become more challenging. Summary of the Invention

[0008] The subject matter of the independent claims is set out. Features of exemplary embodiments are defined in the dependent claims.

[0009] According to an embodiment, a power semiconductor device includes: an active area surrounded by an edge termination area; a semiconductor body extending in both the active area and the edge termination area and including a semiconductor drift region of a first conductivity type in the active area; a first load terminal at a first side of the semiconductor body; a second load terminal at a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active area; in the active area, a trench structure extending in a vertical direction from the first side toward the second side, wherein the trench structure includes one or more control trenches and a plurality of source trenches, each of the one or more control trenches including a first load terminal and a second load terminal. A control trench electrode isolated from a load terminal and configured to control a forward load current, each source trench including a source trench electrode electrically connected to the first load terminal; in the active area, a plurality of mesas configured to conduct the forward load current and extending from a first side toward a second side along a vertical direction, wherein each mesa surrounds a corresponding one of the source trenches and is surrounded by one or more of the one or more control trenches; and in the active area, a plurality of first contact plugs extending from the first load terminal toward the first side along a vertical direction, wherein each first contact plug is associated with one of the source trenches and one of the mesas surrounding the source trench, and is configured to contact both the mesa and the source trench electrode of the source trench.

[0010] According to another embodiment, a method of producing a power semiconductor device includes forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending in both the active region and the edge termination region and including a semiconductor drift region of a first conductivity type in the active region; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; and a trench structure in the active region extending in a vertical direction from the first side toward the second side, wherein the trench structure includes one or more control trenches and a plurality of source trenches, wherein the one or more control trenches have a plurality of source trenches. Each includes a control trench electrode isolated from a first load terminal and configured to control a forward load current, each source trench includes a source trench electrode electrically connected to the first load terminal; in the active area, a plurality of mesas configured to conduct a forward load current and extending in a vertical direction from a first side toward a second side, wherein each mesa surrounds a corresponding one of the source trenches and is surrounded by one or more of the one or more control trenches; and in the active area, a plurality of first contact plugs extending in a vertical direction from the first load terminal toward the first side, wherein each first contact plug is associated with one of the source trenches and one of the mesas surrounding the source trench, and is configured to contact both the mesa and the source trench electrode of the source trench.

[0011] According to the embodiments described herein, electrical connections to both the control trench electrode and the source trench electrode can be established based on the same etching process steps, as will be explained in more detail below. Furthermore, each first contact plug can simultaneously contact both one of the mesas and its associated source trench electrode. Furthermore, since the mesas can exhibit corresponding chimney-like shapes, the first contact plug connecting the mesa to the first load terminal can be implemented as a self-aligned contact plug. Furthermore, mesas having relatively small widths can be implemented.

[0012] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The parts in the drawings are not necessarily to scale, instead emphasis is placed on illustrating the principles of the present invention. Moreover, in the various figures, like reference numerals designate corresponding parts. In the drawings:

[0014] Figure 1 schematically and exemplarily illustrates a horizontal projection of a power semiconductor device according to one or more embodiments;

[0015] Figure 2schematically and exemplarily illustrates a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0016] FIG. 3(A) schematically and exemplarily illustrates a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0017] 3(B) schematically and exemplarily illustrates a portion of a perspective view of a mesa of a power semiconductor device according to one or more embodiments;

[0018] 3(C) schematically and exemplarily illustrates a portion of an exploded view of a mesa and a first contact plug of a power semiconductor device according to one or more embodiments;

[0019] Figure 4 (A)-(C) each schematically and exemplarily illustrate a portion of an exploded view of a mesa and a first contact plug of a power semiconductor device according to one or more embodiments;

[0020] Figure 5 schematically and exemplarily illustrates a horizontal projection of a portion of an active area of ​​a power semiconductor device according to one or more embodiments; and

[0021] Figure 6-Figure 19 The method of producing a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated based on several vertical cross sections and horizontal projections. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0023] In this regard, directional terms, such as "top," "bottom," "below," "front," "back," "back," "front end," "end," "above," etc., may be used with reference to the orientation of the various figures being described. Because portions of the embodiments may be positioned in a variety of different orientations, directional terms are used for illustrative purposes and are in no way limiting. It is to be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0024] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the various figures. Each example is provided by way of explanation and is not intended to be limiting of the present invention. For example, features illustrated or described as part of one embodiment may be used on other embodiments or used in combination with other embodiments to produce yet further embodiments. It is intended that the present invention include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. For clarity, identical elements or manufacturing steps have been designated by the same reference in different figures unless otherwise stated.

[0025] As used in this specification, the term "horizontal" is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor structure or semiconductor substrate. For example, this may be the surface of a semiconductor wafer, die, or chip. For example, the first lateral direction X and the second lateral direction Y mentioned below may both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0026] As used in this specification, the term "vertical" is intended to describe an orientation that is substantially perpendicular to a horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z."

[0027] In this specification, n-doping is referred to as the “first conductivity type,” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be employed such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0028] In the context of this specification, the terms "ohmic contact", "electrical contact", "ohmically connected" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, sections, zones, parts or portions of a semiconductor device or between different terminals of one or more devices or between a terminal or metallization or electrode of a semiconductor device and a part or portion of a semiconductor device, wherein "low-ohmic" may mean that the properties of the respective contact are essentially unaffected by ohmic resistance. Further, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, the transition between two elements in contact with each other may not include further intermediate elements, etc.

[0029] Furthermore, in the context of this specification, unless otherwise stated, the term "electrically insulated" is used in its generally understood context and is therefore intended to describe two or more components that are located separately from each other and that there is no ohmic connection connecting those components. However, components that are electrically insulated from each other can still be coupled to each other, such as mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a junction). To give an example, for example, two electrodes of a capacitor can be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other by means of an insulator, such as a dielectric.

[0030] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Thus, in embodiments, such power semiconductor devices can be configured to carry a load current, which is fed to a load and / or is provided by a power source, respectively. For example, a power semiconductor device can include one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, for example a monolithically integrated IGBT or MOSFET cell and / or a derivative thereof. Such a diode / transistor cell can be integrated in a single chip. A plurality of such cells can constitute a cell field arranged in an active area of ​​the power semiconductor device.

[0031] The term "blocking state" of a power semiconductor device may refer to a condition when the power semiconductor device is in a state configured to block the flow of a load current when an external voltage is applied. More particularly, the power semiconductor device may be configured to block a forward load current through the power semiconductor device when a forward voltage bias is applied. In contrast, the power semiconductor device may be configured to conduct a forward load current in a "conducting state" of the power semiconductor device when a forward voltage bias is applied. The transition between the blocking state and the conducting state may be controlled by a control electrode or, more particularly, by the potential of the control electrode. Of course, the electrical characteristics may only apply within a predetermined operating range of the current density and the external voltage within the power semiconductor device. Therefore, the term "forward biased blocking state" may refer to a condition in which the power semiconductor device is in a blocking state when a forward voltage bias is applied.

[0032] As used in this specification, the term "power semiconductor device" is intended to describe a power semiconductor device on a single chip having a high voltage blocking capability and / or a high current carrying capability. In other words, such a power semiconductor device is intended for high current and / or high voltage, depending on the respective application, the high current being typically in the ampere range, for example, up to tens or hundreds of amperes, and the high voltage being typically above 15 V, more typically 100 V and above, for example up to at least 400 V or even more, for example up to at least 3 kV or even up to 10 kV or more.

[0033] For example, the term "power semiconductor device" as used in this specification does not refer to logic semiconductor devices that are used, for example, to store data, compute data, and / or other types of semiconductor-based data processing.

[0034] For example, the power semiconductor device described below may be a single semiconductor chip, for example, exhibiting a stripe cell configuration (or honeycomb / pin cell configuration), and may be configured to be employed as a power component in low voltage, medium voltage, and / or high voltage applications.

[0035] about Figure 1 and Figure 2 , aspects related to a possible general configuration of the power semiconductor device 1 will be explained:

[0036] A power semiconductor device 1, also referred to herein as "device 1," includes, for example, a semiconductor body 10 in a single chip, configured to conduct a load current between a first load terminal 11 on a first side 110 of the semiconductor body 10 and a second load terminal 12 on a second side 120 of the semiconductor body 10 in an active region 1-2. Device 1 may be, for example, an IGBT (or a derivative thereof, such as an RC IGBT) or, for example, a MOSFET (or a derivative thereof). Thus, first load terminal 11 may be an emitter terminal (or source terminal), and second load terminal 12 may be a drain terminal.

[0037] like Figure 1 As shown in the exemplary embodiment of the device 1, the active area 1-2 is surrounded by the edge termination area 1-3. In the active area 1-2, a trench structure (see FIG3, reference numerals 14, 16) can form a cell field, which will be explained further below. As is known to those skilled in the art, the edge termination area 1-3 is typically not used for load current conduction. The edge termination area 1-3 is terminated by the chip edge 1-4.

[0038] like Figure 2As exemplarily illustrated in FIG, the first side 110 and the second side 120 can be arranged opposite each other. For example, the first side 110 is the front side of the device 1 and the second side 120 is the back side of the device 1. Thus, the device 1 can have a vertical configuration, according to which the load current in the device 1 follows a path parallel to the vertical direction Z. The semiconductor body 10 can be sandwiched between the first load terminal 11 and the second load terminal 12 and has a vertical extension d, for example, in the range of 40 μm to 750 μm, depending on, for example, a specified maximum blocking voltage.

[0039] Device 1 further includes a drift region 100 of the first conductivity type within semiconductor body 10. The term "drift region" is used herein in the sense typically associated with it by those skilled in the art of power semiconductor devices. For example, the vertical extension of drift region 100 influences the voltage blocking capability (e.g., maximum blocking voltage) of device 1.

[0040] The device 1 further includes trench structures 14, 16 extending from the first side 110 toward the second side 120 into the semiconductor body 10, for example, along a vertical direction Z. The trench structures will be described in more detail below. The trench structures 14, 16 include a control trench electrode 141 (see FIG3(A) ) electrically insulated from the first load terminal 11 and configured to receive a control signal. To this end, according to an embodiment, the control trench electrode 141 can be electrically connected to the control terminal 13 of the device 1.

[0041] like Figure 2 As schematically illustrated in FIG3 and illustrated in more detail in FIG3(B) and FIG3(C), on the first side 110, the semiconductor body 10 further includes a semiconductor body region 102 of a second conductivity type electrically connected to the first load terminal 11 and a semiconductor source region 101 of a first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 at least by the semiconductor body region 102. The control trench electrode 141 of the trench structure can be configured to induce an inversion channel in the semiconductor body region 102 when receiving a corresponding turn-on control signal. This process can set the device 1 to a conductive state. The control trench electrode 141 can further be configured to cut off the inversion channel in the semiconductor body region 102 when receiving a corresponding turn-off control signal, which can set the device 1 to a forward biased blocking state.

[0042] Reference again Figure 2 The doped region 108 of the semiconductor body 10 below the drift region 100 adjoining the second load terminal 12 at the second side 120 may be configured according to the specified characteristics of the device 1 .

[0043] For example, if the device 1 is to be configured as an IGBT, the doped region 108 may be an emitter region of the second conductivity type. The doped region 108 is arranged to be in contact with the second load terminal 12. As known to those skilled in the art, if the device 1 is to be configured as an RC IGBT, the doped region 108 may be an emitter region of the second conductivity type that is a sub-portion of the first conductivity type.

[0044] If the device 1 is to assume a MOSFET configuration, the doped region 108 may be a highly doped region of the first conductivity type adjacent to the second load terminal 12 .

[0045] Furthermore, a field stop zone (not shown) of the first conductivity type may be provided between the drift zone 100 and the second load terminal 12 , wherein the field stop zone exhibits a greater dopant concentration than the drift zone 100 .

[0046] Figure 3(A)-Figure 3(C) An embodiment of a power semiconductor device 1 is illustrated schematically and exemplarily.

[0047] In this embodiment, referring to FIG3(A), the trench structure includes a plurality of control trenches 14, wherein each control trench 14 includes a control trench electrode 141 isolated from the first load terminal 11 and configured to control a forward load current. Furthermore, in this embodiment, the trench structure includes a plurality of source trenches 16, wherein each source trench 16 includes a source trench electrode 161 electrically connected to the first load terminal 11.

[0048] Still refer to Figure 3(A)-Figure 3(C) In the embodiment illustrated in FIG, the device 1 further includes a plurality of mesas 17 in the active region 1 - 2 , which are configured to conduct a forward load current and extend along a vertical direction Z from the first side 110 toward the second side 120 .

[0049] Each mesa 17 surrounds a corresponding one of the source trenches 16. For example, each mesa completely surrounds a corresponding one of the source trenches 16. In an embodiment, each source trench 16 is surrounded by a corresponding one of the mesas 17, for example, completely surrounded.

[0050] Furthermore, according to an embodiment, each mesa 17 is surrounded, for example completely surrounded, by one or more of the one or more control grooves 14 (see also Figure 5 ).

[0051] The control trenches 14 and the source trenches 16 may respectively laterally delimit the mesas 17. For example, wherein the trench structure presents a pattern in the active area 1-2, according to which each source trench 16 is surrounded by one or more of the control trenches 14 (see also Figure 5 ).

[0052] The device 1 further includes a plurality of first contact plugs 111 in the active region 1-2, which extend from the first load terminal 11 toward the first side 110 along the vertical direction Z. Each first contact plug 111 is associated with one of the source trenches 16 and one of the mesas 17 surrounding the source trench 16. For example, the first contact plugs 111 penetrate the insulating layer 190 arranged between the semiconductor body 10 and the first load terminal 11. Each first contact plug 111 is configured to contact both the mesa 17 and the source trench electrode 161.

[0053] In an embodiment, each mesa 17 includes (e.g., see FIG. 3(A) and FIG. 3(B) ) the semiconductor source region 101 of the first conductivity type and is electrically connected to the first load terminal 11 via an associated first contact plug 111. In an embodiment, each mesa 17 further includes the semiconductor body region 102 of the second conductivity type in contact with the semiconductor source region 101. For example, the semiconductor body region 102 isolates the semiconductor source region 101 from the semiconductor drift region 100.

[0054] In an embodiment, in each mesa 17, the semiconductor source region 101 includes an even number of spatially distributed semiconductor source sub-regions, for example, four semiconductor source sub-regions 101-1, 101-2, 101-3, and 101-4, as illustrated in FIG3(A) and FIG3(B). The even number of spatially distributed semiconductor source sub-regions may be different from four; for example, two, six, or eight spatially distributed semiconductor source sub-regions may be provided. For example, in each mesa 17, the semiconductor source region 101 may consist of the even number of spatially distributed semiconductor source sub-regions.

[0055] As illustrated in Figures 3(A) and 3(B), the semiconductor source sub-regions can be uniformly spatially distributed with respect to the corresponding mesas 17, wherein the four semiconductor source sub-regions 101-1, 101-2, 101-3 and 101-4 are arranged within the mesas 17 at respective angular distances of 90°. In this embodiment, the mesas 17 can present a shape that is at least approximately circular.

[0056] For example, as exemplarily illustrated in Figures 3(A) and 3(B), in each mesa 17, the semiconductor body region 102 of the second conductivity type is also electrically connected to the first load terminal 11 via the associated first contact plug 111. In each mesa 17, the semiconductor body region 102 can be at least partially arranged below the semiconductor source region 101. In each mesa 17, the semiconductor body region 102 can further include a portion 1021 extending between the spatially distributed semiconductor source sub-regions 101-1 to 101-4 to electrically contact the associated first contact plug 111. The portion 1021 of the semiconductor body region 102 can vertically overlap with the semiconductor source sub-regions 101-1 to 101-4, respectively. For example, the portion 1021 of the semiconductor body region 102 and the semiconductor source sub-regions 101-1 to 101-4 are alternately arranged relative to each other. The portion 1021 of the semiconductor body region 102 may exhibit a dopant concentration that is greater than the dopant concentration of the remainder of the semiconductor body region 102 , for example, at least twice as great, or even in the range of 100 times the dopant concentration of the remainder of the semiconductor body region 102 .

[0057] In an embodiment, the device 1 further includes the control terminal 13 electrically connected to the control trench electrode 141 of the control trench 14 at the first side 110. For example, as illustrated in FIG3(A), contact between the control terminal 13 and the control trench electrode 141 is established only in the edge termination region 1-3, for example based on the second contact plug 131.

[0058] For example, device 1 further includes a connector trench 15 extending into edge termination region 1-3 and active region 1-2. Connector trench 15 includes a connector trench electrode 151. Connector trench electrode 151 is arranged in edge termination region 1-3 to contact second contact plug 131 electrically connected to control terminal 13. Connector trench electrode 151 extends toward an adjacent one of mesas 17 in active region 1-2. Connector trench electrode 151 may be isolated by a connector trench insulator structure 152.

[0059] As explained above, when subjected to a correspondingly configured control signal (e.g., based on a first control voltage applied between the first load terminal 11 and the control terminal 13), the control electrode 141 adjacent to the mesa 17 can induce an inversion channel in the body region 102, thereby setting the device 1 to a forward conducting state. When subjected to another correspondingly configured control signal (e.g., based on a second control voltage applied between the first load terminal 11 and the control terminal 13), the control electrode 141 adjacent to the mesa 17 can cut off the inversion channel in the body region 102, thereby setting the device 1 to a forward biased blocking state.

[0060] In the embodiment, the width wm of each mesa 17 (see Figure 3B and Figure 5 and Figure 11 ) is in the range of 50 nm to 500 nm, or in the range of 10 nm to 50 nm, or in the range of 50 nm to 100 nm, or in the range of 100 nm to 200 nm. For example, the width of mesa 17 is defined as the lateral distance between (a) the periphery of source trench 16 surrounded by mesa 17 and (b) the periphery of control trench 14 surrounding mesa 17.

[0061] In an embodiment, each control trench 14 and each source trench 16 has a vertical extension vt in the range of 0.5 μm to 3 μm, or in the range of 0.5 μm to 1 μm, or in the range of 1 μm to 2 μm, or in the range of 2 μm to 3 μm. The vertical extension vt of the control trench 14 can be the same as or different from the vertical extension vt of the source trench. In an embodiment, the vertical extension vt of the control trench 14 and the source trench 16 defines the vertical extension of the mesa 17; for example, the vertical extension of the mesa 17 is at least approximately the same as the vertical extension vt of the control trench 14 and the source trench 16.

[0062] In the embodiment, as shown in FIG3(A), FIG3(C) and Figure 4 (A)- Figure 4 As exemplarily shown in (C), the lateral cross-sectional area of ​​each source trench 16 is smaller than the lateral cross-sectional area of ​​the associated first contact plug 111. For example, the lateral cross-sectional area of ​​each first contact plug 111 is reduced by at least 10% or at least 20% of the maximum lateral cross-sectional area of ​​the corresponding first contact plug 111 along the vertical direction Z. In an embodiment, each first contact plug 111 has a shape corresponding to a portion of a cone.

[0063] For example, the following applies to each source trench 16: the associated first contact plug 111 laterally overlaps the entire source trench 16 and at least partially (or completely) laterally overlaps the mesa 17 surrounding the source trench 16. For example, at the mesa contact interface, the associated first contact plug 111 partially laterally overlaps the mesa 17. Because the associated first contact plug 111 may extend against the vertical direction Z in a lateral cross-section, the associated first contact plug 111 may completely laterally overlap the mesa 17 at the first load terminal contact interface.

[0064] In an embodiment, each first contact plug 111 has a monolithic structure. However, one or more intermediate layers (not shown), such as a barrier layer, may be provided between the corresponding first contact plug 111 and the associated source trench electrode 161, and / or between the corresponding first contact plug 111 and the associated semiconductor source region 101, and / or between the corresponding first contact plug 111 and the associated semiconductor body region 102, and / or between the corresponding first contact plug 111 and the first load terminal 11.

[0065] refer to Figure 4 (A)- Figure 4 (C), each mesa 17 may have a circular transverse cross-sectional area (see Figure 4 (A) and Figure 3(A)-Figure 3(C) ), or a rectangular transverse cross-sectional area with rounded corners (see Figure 4 (B)) or rectangular transverse cross-sectional area (see Figure 4 (C)). Regardless of the shape of the lateral cross-sectional area, the features explained above, such as those related to the mesa width wm, the vertical extension, the source region 101, the body region 102, the trench structure, etc., can also be provided. In addition, the shape of the source trench 16 can be changed accordingly, such as Figure 4 (A)- Figure 4 As shown in (C).

[0066] like Figure 5 As exemplarily shown in FIG. 1 , according to an embodiment, in the active region 1 - 2 , the control trench electrode 141 of the control trench 14 may form a monolithic electrode structure. Figure 3A As explained, the monolithic electrode structure can be electrically connected to the control terminal 13 based on the connector groove 15, for example, as Figure 3A For example, the active region 1 - 2 does not have any conductive structure on the first side 110 that is electrically connected to one or more of the control trench electrodes 141 .

[0067] For example, the active area 1-2 has a total lateral cross-sectional area A. Based on the trench mesa pattern explained above, the cell density, ie the number of separated mesas 17 within the total lateral cross-sectional area A, can reach, for example, one million cells / mm 2 , or more than one million cells / mm 2 If realized in a circular transverse cross-sectional shape, each mesa may present a diameter md in the range of 0.4 μm to 1 μm or in the range of 1 μm to 2 μm.

[0068] 3(A) again, furthermore, each control trench 14 may include a control trench insulator structure having a lower portion 142-1 and an upper portion 142-2, wherein the lower portion 142-1 insulates the corresponding control trench electrode 141 from the semiconductor body 10. For example, the lower portion 142-1 of the control trench insulator structure exhibits a thickness along the vertical direction Z at the bottom of the corresponding control trench 14 that is greater than 150% of the thickness of the control trench insulator 142-1 laterally adjacent to the mesa 17 along the first lateral direction X.

[0069] Likewise, each source trench 16 may include a source trench insulator 162 that insulates the corresponding source trench electrode 161 from the semiconductor body 10. For example, at the bottom of the corresponding source trench 16, the thickness of the source trench insulator 162 along the vertical direction Z is greater than 150% of the thickness of the source trench insulator 162 laterally adjacent to the mesa 17 along the first lateral direction X.

[0070] Regardless of the optional feature of the trench insulator thickness, each control trench electrode 141 has a U-shape in vertical cross-section, as exemplarily illustrated in Figure 3(A). For example, the U-shaped well region is filled with the upper portion 142-2 of the control trench insulator structure.

[0071] A method for producing a power semiconductor device is also provided herein. For example, the method for producing a power semiconductor device includes forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending in both the active region and the edge termination region and including a semiconductor drift region of a first conductivity type in the active region; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite to the first side, wherein the power semiconductor device is configured to conduct a positive load current between the first load terminal and the second load terminal in the active region; and a trench structure in the active region extending in a vertical direction from the first side toward the second side, wherein the trench structure includes one or more control trenches and a plurality of source trenches, each of the one or more control trenches including a first load terminal and a second load terminal. The active region includes a plurality of first contact plugs extending in a vertical direction from the first load terminal toward the first side, wherein each first contact plug is associated with one of the source trenches and one of the mesas surrounding the source trench, and is configured to contact both the mesa and the source trench electrode of the source trench.

[0072] The above-described embodiments of the method correspond to the above-described embodiments of the power semiconductor device 1. Therefore, these embodiments of the method will not be described literally in this document, but reference is made to the above.

[0073] For example, based on the joint etching process step, the trench electrode and the source trench electrode are controlled to be in electrical contact. Further, forming the first contact plug may occur such that the first contact plug is self-aligned.

[0074] Figure 6-Figure 19 An exemplary embodiment of a power semiconductor production method 2 is illustrated.

[0075] In processing stage 200, see Figure 6 To produce the trench structures 14, 16, a circular structure 301 is formed in the active area 12, and a line structure 302 is formed in the edge termination areas 1-3 in a processing stage 202, which can be carried out simultaneously with the processing stage 200. The circular structure 301 and the line structure 302 are based on a resist layer formed on top of the oxide layer 300 on top of the carbon layer 303 on top of the semiconductor body 10, for example. Figure 6 The two figures on the right show horizontal sections, and Figure 6 The two figures on the left show a vertical section at the dashed line (1).

[0076] In the subsequent processing stage 204, see Figure 7 , which is only illustrated for the active area 1-2, but can also be implemented in the edge termination area 1-3, for example based on an etching process step and a stripping process step, the structures 301 and 302 and the oxide layer 300 are removed so that a corresponding structure 3031 is formed in the (previous) carbon layer 303.

[0077] In the subsequent processing stage 206, see Figure 8 , which is illustrated only for the active areas 1 - 2 , but can also be implemented in the edge termination areas 1 - 3 , for example, by forming spacers 304 adjacent to corresponding structures 3031 based on a deposition process step and an etching process step.

[0078] After the post-processing stage 208, see Figure 9 , again illustrated only for active areas 1 - 2 , but can also be implemented in edge termination areas 1 - 3 , the spacers 304 are freestanding when the structure 3031 is removed in stage 208 , for example based on an etching process step or a stripping process step.

[0079] Then, in the subsequent processing stage 210, see Figure 10, again only illustrated for the active areas 1-2, but can also be realized in the edge termination areas 1-3, based on, for example, using spacers 304 acting as a hard mask, for example based on an etching process step, a trench is formed in the semiconductor body 10. In this way, a chimney-shaped portion of the semiconductor body 10 can be formed (see also the perspective view). Figure 10 ), which can be configured as a table 17 in a subsequent processing stage.

[0080] In the subsequent processing stage 212, see Figure 11 , again illustrated only for active areas 1-2, but can also be implemented in edge termination areas 1-3, removing spacers 304. Furthermore, the width wm of mesas 17 can be reduced, for example, by one or more isotropic etching process steps.

[0081] In the subsequent processing stage 214, see Figure 12 , again illustrated only for active areas 1-2, but can also be implemented in edge termination areas 1-3, for example, based on deposition and one or more etch-back process steps, such as high-density plasma chemical vapor deposition process steps, such as dry and / or wet etching process steps, to form the lower portion of control trench insulator 142-1 and source trench insulator 162. For example, process stage 214 is performed such that, at the bottom of the respective trench 14 / 16, the insulator structure exhibits a thickness in the vertical direction Z that is greater than 150% of the thickness of the insulator structure laterally adjacent to the mesa 17 along the first lateral direction X. For example, depending on the magnitude of the control voltage, the thickness of the insulator structure laterally adjacent to the mesa 17 along the first lateral direction X can be in the range of 10 nm to 50 nm, or in the range of 50 nm to 150 nm, while the thickness of the insulator structure at the bottom of the respective trench 14 / 16 along the vertical direction Z can be in the range of 15 nm to 75 nm, or in the range of 75 nm to 300 nm.

[0082] In the subsequent processing stage 216, see Figure 13 , again illustrated only for the active areas 1-2, but also possible in the edge termination areas 1-3, the material for forming the control trench electrode 141 and the source trench electrode 161 is deposited. Depending on the amount of said material and the diameter of the chimney-shaped mesa 17, a corresponding gap 163 can remain in the source trench 16, see variant (A), or not (see variant (B)). Furthermore, for example, in the area indicated by the reference numeral 145, some of said material can be removed, for example, to adjust the total capacity of the control trench electrode 141.

[0083] In the subsequent processing stage 218, see Figure 14, the upper portion 142-2 of the control trench insulator structure is formed, and the void 163 (if present) is filled with the same material 165. For example, as illustrated, no void is formed in the connector trench 15. For example, a deposition process step may be performed in stage 218, followed by a chemical mechanical polishing (CMP) process step.

[0084] In the subsequent processing stage 220, see Figure 15 , which is again illustrated only for the active area 1-2, a material removal step is performed to separate the source trench electrode 161 and the control trench electrode 141 from one another and to expose the upper portion of the mesa 17. For example, an etching step is performed to recess the electrode material of the source trench electrode 161 and the control trench electrode 141, and then, for example, an etching step is performed to remove parts of the isolation material of the trench insulator structure having the lower portion 142-1 and the upper portion 142-2. Furthermore, not illustrated, in the edge termination area 1-3, a control terminal flow channel 135 for electrical connection of the control trench electrodes can be formed (see Figure 17 ), for example by protecting the area with a photolithographic mask.

[0085] In the subsequent processing stage 222, see Figure 16 , which is again illustrated only for the active regions 1-2, the semiconductor source region 101 and the semiconductor body region 102 being formed in the mesa 17. In this context, reference is also made to the above description related to the device, in particular with respect to FIG. Figure 4 and Figure 5 ; This description applies similarly here. For example, based on the implantation process step and the previous lithography process step, the semiconductor source region 101 and the semiconductor body region 102 are formed, for example, to form the four semiconductor source sub-regions 101-1, 101-2, 101-3 and 101-4, as shown in FIG. Figure 16 As shown in the upper right part of .

[0086] In the subsequent processing stage 224, see Figure 17 , an insulating layer 190 is formed in both the active region 1 - 2 and the edge termination region 1 - 3 .

[0087] In the subsequent processing stage 226, see Figure 18 , which is shown only for the active areas 1 - 2 but can also be implemented in the edge termination area 13 , forms contact trenches 191 for the first contact plugs 111 and optionally the second contact plugs 131 (not shown). Figure 18 Part (A) in FIG. 1 illustrates a source trench electrode 161 having a corresponding gap filled with an insulator 165, and Figure 181 shows a source trench electrode 161 without a void. Part (C) shows an enlarged view of the region indicated by reference numeral 198 in part (B). Contact trenches 191 are formed, for example, based on an oxide etching process selective to silicon, which allows for the formation of self-aligned first contact plugs 111. Contact trenches 191 expose portions of each source trench electrode 161 (and, if present, portions of insulator 165), source trench insulator 162, and portions of mesas 17.

[0088] As shown, see also Figure 16 Along the mesa 17 , the source regions 101 (eg, portions of each of the four semiconductor source sub-regions 101 - 1 , 101 - 2 , 101 - 3 , and 101 - 4 ) alternate with portions 1021 connecting the body regions 102 . Figure 18 As shown in part (C) of FIG, the size of the contact trenches 191 can vary laterally on top of the mesas 17 (reference numerals 190-1, 190-2, and 190-3), and the insulating layer 190 is pulled back a distance s along / against the first lateral direction X. However, the size of the contact trenches 191 between the mesas 17 is limited by the size of these chimney-like structures (see FIG. Figure 4 (A) Figure 4 (B) Figure 4 (C)). Since the contact groove 191 extends beyond the top of the mesa in the Z direction, a stable vertical contact area 195 is formed. As shown, see also Figure 16 , establishing contact with source regions 101 (e.g., portions of each of four semiconductor source sub-regions 101-1, 101-2, 101-3, and 101-4) that alternate with portions 1021 of connected body region 102. Thus, since lateral sides 190-1, 190-2, and 190-3 do not cause significant degradation in contact properties, variations caused by process tolerances (e.g., photolithographic processing steps, such as etching processing steps) can be tolerated using such a structure. A second contact trench for contact plug 131 (not shown) can be formed in a similar manner, but without the same restrictions as for contact trench 191.

[0089] In the subsequent processing stage 228, see Figure 19 , forming the first contact plug 111 and the second contact plug 131 as well as the first load terminal 11 and the control terminal 13 . Figure 19 Mainly corresponds to Figure 3 (A), so reference is made to the above. In contrast to Figure 3 (A), Figure 19 The source trench electrode 161 in FIG. 1 includes the gap filled with the insulator 165 .

[0090] In the above, embodiments concerning a power semiconductor device and a corresponding production method were explained.

[0091] For example, these power semiconductor devices are based on silicon (Si). Therefore, the single-crystalline semiconductor region or layer (e.g., the semiconductor body and its regions / regions, such as regions, etc.) can be a single-crystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0092] However, it should be understood that the semiconductor body and its regions / zones can be made of any semiconductor material suitable for manufacturing semiconductor devices. To name a few, examples of such materials include, but are not limited to: elemental semiconductor materials such as silicon (Si) or germanium (Ge); Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe). The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials." A heterojunction semiconductor material is formed when two different semiconductor materials are combined. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs, and GaN materials are currently used.

[0093] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding devices in addition to those depicted in the figures. Further, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, and the like and are not intended to be limiting. Throughout this description, similar terms may refer to similar elements.

Claims

1. A power semiconductor device (1), comprising - an active region (1-2) surrounded by an edge termination region (1-3); a semiconductor body (10) extending both in the active region (1-2) and in the edge termination region (1-3) and comprising a semiconductor drift region (100) of a first conductivity type in the active region (1-2); - a first load terminal (11) on a first side (110) of the semiconductor body (10); a second load terminal (12) at a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12) in the active region (1-2); - in the active area (1-2), a trench structure (14, 16) extending along a vertical direction (Z) from a first side (110) toward a second side (120), wherein the trench structure (14, 16) comprises o one or more control trenches (14), each of the one or more control trenches (14) comprising a control trench electrode (141) isolated from the first load terminal (11) and configured to control a forward load current, and o a plurality of source trenches (16), each source trench (16) comprising a source trench electrode (161) electrically connected to the first load terminal (11); - In the active region (1-2), a plurality of mesas (17) configured to conduct a forward load current and extending along a vertical direction (Z) from a first side (110) toward a second side (120), wherein each mesa (17) o surrounds a corresponding one of the source trenches (16), and o surrounded by one or more of the one or more control grooves (14); and - In the active area (1-2), a plurality of first contact plugs (111) extending from the first load terminal (11) toward the first side (110) along the vertical direction (Z), wherein each first contact plug (111) o is associated with one of the source trenches (16) and one of the mesas (17) surrounding said source trench (16), and o A source trench electrode (161) configured to contact both the mesa (17) and the source trench (16).

2. The power semiconductor device (1) according to claim 1, wherein each mesa (17) comprises: - a semiconductor source region (101) of a first conductivity type and electrically connected to a first load terminal (11) via an associated first contact plug (111), and - a semiconductor body region (102) of a second conductivity type in contact with the semiconductor source region (101).

3. The power semiconductor device (1) according to claim 1 or 2, wherein the width (wm) of each mesa (17) is in the range of 50 nm to 500 nm.

4. The power semiconductor device (1) according to one of the preceding claims, wherein each of the one or more control trenches (14) and each of the source trenches (16) has a vertical extension (vt) in the range of 0.5 μm to 3 μm.

5. The power semiconductor device (1) according to one of the preceding claims, wherein a lateral cross-sectional area of ​​each of the source trenches (16) is smaller than a lateral cross-sectional area of ​​the associated first contact plug (111).

6. The power semiconductor device (1) according to one of the preceding claims, wherein the following applies to each of the source trenches (16): The associated first contact plug (111) laterally overlaps the entire source trench (16) and at least partially laterally overlaps the mesa (17) surrounding the source trench (16).

7. The power semiconductor device (1) according to one of the preceding claims, wherein each of the first contact plugs (111) exhibits a monolithic structure.

8. The power semiconductor device (1) according to one of the preceding claims, wherein the lateral cross-sectional area of ​​each of the first contact plugs (111) is reduced along the vertical direction (Z) by at least 10% of the maximum lateral cross-sectional area of ​​the respective first contact plug (111).

9. The power semiconductor device (1) according to one of the preceding claims, wherein each of the mesas (17) presents a circular lateral cross-sectional area or a rectangular lateral cross-sectional area with rounded corners or a rectangular lateral cross-sectional area.

10. The power semiconductor device (1) according to one of the preceding claims, wherein In each of the mesas (17), the semiconductor source region (101) presents an even number of spatially distributed semiconductor source sub-regions (101-1, . . . , 101-4).

11. The power semiconductor device (1) according to one of the preceding claims, wherein In each of the mesas (17), a semiconductor body region (102) is arranged at least partially below the semiconductor source region (101).

12. The power semiconductor device (1) according to claim 10 and claim 11, wherein: In each of the mesas (17), a portion (1021) of the semiconductor body region (102) extends between the spatially distributed semiconductor source subregions (101-1, ..., 101-4) to electrically contact the associated first contact plug (111).

13. The power semiconductor device (1) according to one of the preceding claims, wherein In the active region (1-2), the control trench electrodes (141) of the one or more control trenches (14) form a monolithic electrode structure.

14. The power semiconductor device (1) according to one of the preceding claims, further comprising, on the first side (110), a control terminal (13) electrically connected to the control trench electrode(s) (141) of the one or more control trenches (14), wherein - The contact between the control terminal (13) and the control trench electrode(s) (141) is established only in the edge termination region (1-3).

15. The power semiconductor device (1) according to claim 14, further comprising a connector trench (15) extending into the edge termination region (1-3) and the active region (1-2), the connector trench (15) comprising a connector trench electrode (151), wherein the connector trench electrode (151): - being arranged in the edge termination region (1-3) to be in contact with a second contact plug (131) electrically connected to the control terminal (13), and - extending toward an adjacent one of the mesas (17) in the active region (1-2).

16. The power semiconductor device (1) according to one of the preceding claims, wherein the trench structure (14, 16) presents a pattern in the active area (1-2), according to which each source trench (16) is surrounded by one or more of the control trenches (14).

17. The power semiconductor device (1) according to one of the preceding claims, wherein the active region (1-2) is free of any electrically conductive structures on the first side (110) that are electrically connected to one or more of the control trench electrodes (141).

18. The power semiconductor device (1) according to one of the preceding claims, wherein - each of the control trenches (14) comprises a control trench insulator structure (142-1, 142-2) insulating the respective control trench electrode (141) from the semiconductor body (10), wherein the control trench insulator structure (142-1, 142-2) exhibits at the bottom of the respective control trench (14) a thickness along a vertical direction (Z) that is greater than 150% of the thickness of the control trench insulator (142-1) laterally adjacent to the mesa (17) along a lateral direction (X), and / or wherein - Each of the source trenches (16) comprises a source trench insulator (162) insulating the corresponding source trench electrode (161) from the semiconductor body (10), wherein the thickness of the source trench insulator (162) at the bottom of the corresponding source trench (16) along the vertical direction (Z) is greater than 150% of the thickness of the source trench insulator (162) laterally adjacent to the mesa (17) along the lateral direction (X).

19. The power semiconductor device (1) according to one of the preceding claims, wherein each of the control trench electrodes (141) exhibits a U-shape in a vertical cross section.

20. A method (2) of producing a power semiconductor device (1), comprising forming the following components: - an active region (1-2) surrounded by an edge termination region (1-3); a semiconductor body (10) extending both in the active region (1-2) and in the edge termination region (1-3) and comprising a semiconductor drift region (100) of a first conductivity type in the active region (1-2); - a first load terminal (11) on a first side (110) of the semiconductor body (10); a second load terminal (12) at a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12) in the active region (1-2); - in the active area (1-2), a trench structure (14, 16) extending along a vertical direction (Z) from a first side (110) toward a second side (120), wherein the trench structure (14, 16) comprises o one or more control trenches (14), each of the one or more control trenches (14) comprising a control trench electrode (141) isolated from the first load terminal (11) and configured to control a forward load current, and o a plurality of source trenches (16), each source trench (16) comprising a source trench electrode (161) electrically connected to the first load terminal (11); - In the active region (1-2), a plurality of mesas (17) configured to conduct a forward load current and extending along a vertical direction (Z) from a first side (110) toward a second side (120), wherein each mesa (17) o surrounds one of the source trenches (16), and o surrounded by one or more of the one or more control grooves (14); and - In the active area (1-2), a plurality of first contact plugs (111) extending from the first load terminal (11) toward the first side (110) along the vertical direction (Z), wherein each first contact plug (111) o is associated with one of the source trenches (16) and one of the mesas (17) surrounding said source trench (16), and o A source trench electrode (161) configured to contact both the mesa (17) and the source trench (16).

21. The method (2) according to claim 20, wherein the control trench electrode(s) (141) and the source trench electrode (161) are electrically contacted based on a joint etching process step.

22. The method (2) according to claim 20 or 21, wherein forming the first contact plug (111) occurs such that the first contact plug (111) is self-aligned.

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