Intelligent calibration multi-channel clock chip system and control method

Abstract

The application belongs to the technical field of clock chip, and discloses a multi-channel clock chip system and a control method for intelligent calibration, the system comprising a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprising a digital control circuit and a frequency divider connected with each other; the initial phase-locked loop is used for receiving an input clock signal, frequency doubling the input clock signal, obtaining a reference clock signal and sending the reference clock signal to the digital control circuit of at least one clock output branch through the selector; the digital control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. The application can reduce the absolute synchronization error of each clock output branch, and improve the application scene diversity and flexibility of the clock chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock chip, and particularly to a multi-channel clock chip system with intelligent calibration and a control method. BACKGROUND

[0002] With more and more functional modules integrated in modern electronic systems, each module can need clock signals of different frequencies and phases, and therefore the functional requirements for clock generators are also increasing. A clock generator with more channels can provide appropriate clock signals for new modules or functions through programming and other ways without replacing hardware, facilitating system upgrade and expansion. For example, a multi-channel clock generator first uses a frequency-fixed crystal oscillator as a reference clock for internal clock, and then generates multiple independently adjustable clocks through multiple frequency dividers for the reference clock.

[0003] However, in the current clock generator, the initial reference clock signal generated by the phase-locked loop is transmitted to each frequency divider through a distributed wiring network. The transmission path lengths and parasitic parameters of different channels are different, which not only causes time differences in the arrival of clock signals at each frequency divider, resulting in clock deviation, but also amplifies or accumulates the internal circuit noise (such as thermal noise, 1 / f noise, etc.) of the main phase-locked loop during the long transmission process, resulting in synchronization errors in the output clocks of each channel. SUMMARY

[0004] The present application provides a multi-channel clock chip system with intelligent calibration and a control method, which can reduce the absolute synchronization error of each clock output branch and improve the application scene diversity and flexibility of the clock chip.

[0005] In a first aspect, the embodiments of the present application provide a multi-channel clock chip system with intelligent calibration, which comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the initial phase-locked loop and the selector are connected;

[0006] Each clock output branch comprises a digital control circuit and a frequency divider connected to each other;

[0007] Each digital control circuit is connected to the selector, and each frequency divider is connected to the coprocessor;

[0008] The initial phase-locked loop is configured to receive an input clock signal, multiply the input clock signal, obtain a reference clock signal and send the reference clock signal to the digital control circuit of at least one clock output branch through the selector;

[0009] The digital control circuit is configured to eliminate the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generate a target clock signal according to the reference clock signal after eliminating the delay difference, and send the target clock signal to the corresponding frequency divider;

[0010] The coprocessor is configured to receive clock mode information, determine clock control parameters according to the clock mode information, and control the respective frequency dividers to output target clock signals after adjusting the target clock signals according to the clock control parameters.

[0011] Further, the coprocessor is specifically configured to receive the clock mode information through a digital pin level combination, take the clock frequency parameters corresponding to the clock mode information as the clock control parameters, or receive the clock control parameters through an I2C interface or an SPI interface.

[0012] Further, the clock mode information includes a 5G base station mode and a vehicle-mounted system mode.

[0013] Further, the lines between the initial phase-locked loop and the respective digital control circuits adopt differential spiral wiring, and the upper half is covered with an electromagnetic shielding layer; the pitch of the differential spiral wiring is 1.5 microns, and the line width is 3 microns.

[0014] The material of the electromagnetic shielding layer is a tantalum-based composite material.

[0015] Further, the initial phase-locked loop and the respective digital control circuits are embedded with FBAR filters on the packaging substrates.

[0016] The respective FBAR filters are connected to the coprocessor.

[0017] The coprocessor is configured to send a suppression frequency band to the respective FBAR filters.

[0018] The FBAR filters are configured to perform interference suppression according to the received suppression frequency band.

[0019] Further, the digital control circuit includes a time-to-digital conversion module, a processing module, and a digital control oscillation module connected in sequence.

[0020] The time-to-digital conversion module is connected to the selector and is configured to receive a reference clock signal, detect a phase difference between a local clock signal and the reference clock signal, and send the phase difference and the reference clock signal to the processing module.

[0021] The processing module is configured to adjust the phase of the digital control oscillation module according to the phase difference and a digital compensation algorithm, and send the reference clock signal to the digital control oscillation module after the adjustment.

[0022] The digital control oscillation module is connected to the frequency divider and is configured to receive the reference clock signal, perform frequency adjustment or phase adjustment on the reference clock signal, generate a target clock signal, and send the target clock signal to the frequency divider.

[0023] Further, the processing module is also connected to the processing module in the adjacent clock output branch.

[0024] The processing module is also configured to send the received phase difference to an adjacent processing module as an adjacent phase difference;

[0025] The processing module is also configured to receive at least one adjacent phase difference, update the received phase difference according to the adjacent phase difference, and adjust the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and a digital compensation algorithm.

[0026] Further, the processing module is also configured to obtain a temperature-voltage compensation table and a control voltage of the digitally controlled oscillation module.

[0027] If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold.

[0028] Further, the processing module is also configured to adjust the frequency of the digitally controlled oscillation module according to the first compensation frequency value after adjusting the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm.

[0029] Further, the system also includes a temperature sensing module.

[0030] The temperature sensing module is configured to collect junction temperature data of each clock output branch and send the junction temperature data to the corresponding processing module.

[0031] The processing module is also configured to obtain a semiconductor carrier mobility temperature coefficient and a thermal expansion coefficient of a packaging material of the clock output branch; calculate a temperature delay change amount according to the junction temperature data, the semiconductor carrier mobility temperature coefficient, the thermal expansion coefficient, and a preset calibration temperature; obtain a temperature compensation frequency value in the temperature-voltage compensation table according to the temperature delay change amount; and adjust the frequency of the digitally controlled oscillation module according to the temperature compensation frequency value and the first compensation frequency value.

[0032] Further, the system also includes a voltage sensing module; the voltage sensing module is configured to measure the supply voltage of each clock output branch and send the supply voltage to the corresponding processing module.

[0033] The processing module is configured to calculate a voltage delay change amount according to the supply voltage, a preset nominal voltage, and a preset delay reference value; obtain a second compensation frequency value in the temperature-voltage compensation table according to the voltage delay change amount; and adjust the frequency of the digitally controlled oscillation module according to the first compensation frequency value, the second compensation frequency value, and the temperature compensation frequency value.

[0034] Furthermore, the numerically controlled oscillation module is specifically used to divide the frequency control word by a power of 2 and then multiply it by the frequency of the reference clock signal to obtain the frequency of the target clock signal; where the power is the bit width of the phase accumulator of the numerically controlled oscillation module.

[0035] Furthermore, the processing module is also used to calculate the average delay change based on multiple temperature delay changes and multiple voltage delay changes within a preset period; obtain the running time of the numerically controlled oscillation module; obtain the aging factor of the clock output branch based on the average delay change and the running time; and issue an aging warning when the aging factor is greater than the preset aging threshold.

[0036] Furthermore, the processing module is also used to obtain the historical frequency error of each clock output branch; construct an error probability density function based on each historical delay error; extract the fixed offset of the preset frequency point based on the error probability density function and use it as a systematic deviation component; and update the network parameters of the first linear model and the second linear model based on the systematic deviation component and the recursive least squares method.

[0037] Furthermore, the system also includes a compensation adaptive module;

[0038] The compensation adaptive module is connected to the initial phase-locked loop and each time-to-digital converter module respectively;

[0039] The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency scanning signal and send it to each time-to-digital converter module; acquire the transmission delay data of different frequency points recorded by each time-to-digital converter module; generate the compensation coefficient matrix corresponding to each clock output branch based on the transmission delay data; update the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix, and send it to the processing module of the clock output branch.

[0040] Secondly, embodiments of this application provide a smart calibration multi-channel clock chip control method, applied to a multi-channel clock chip control system. The multi-channel clock chip control system includes a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches; each clock output branch includes interconnected numerical control circuits and frequency dividers; the control method includes:

[0041] The initial phase-locked loop receives the input clock signal, multiplies the frequency of the input clock signal to obtain a reference clock signal, and sends it to the numerical control circuit of at least one clock output branch through a selector;

[0042] The numerical control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates the target clock signal based on the reference clock signal after eliminating the delay difference, and sends it to the corresponding frequency divider;

[0043] The coprocessor receives clock mode information, determines clock control parameters according to the clock mode information, and controls each frequency divider to output a target clock signal after adjusting the target clock signal according to the clock control parameters.

[0044] Further, the method further comprises:

[0045] The coprocessor receives the clock mode information through a digital pin level combination.

[0046] Alternatively, the coprocessor receives the clock control parameters through an I2C interface or an SPI interface.

[0047] Further, the digital control circuit comprises a time-to-digital conversion module, a processing module and a digitally controlled oscillation module connected in sequence.

[0048] The digital control circuit adopts a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal according to the reference clock signal after eliminating the delay difference, and sends the target clock signal to the corresponding frequency divider, comprising:

[0049] The time-to-digital conversion module receives the reference clock signal, detects the phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module.

[0050] The processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, and sends the reference clock signal to the digitally controlled oscillation module after adjustment.

[0051] The digitally controlled oscillation module receives the reference clock signal, adjusts the frequency or phase of the reference clock signal, generates a target clock signal and sends it to the frequency divider.

[0052] Further, the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, comprising:

[0053] The processing module sends the received phase difference as an adjacent phase difference to the processing module of the adjacent clock output branch.

[0054] The processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference, and adjusts the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and the digital compensation algorithm.

[0055] Further, the method further comprises:

[0056] The processing module is further configured to obtain a temperature voltage compensation table and a control voltage of the digitally controlled oscillation module.

[0057] If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to a temperature voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold.

[0058] The frequency of the digital controlled oscillation module is adjusted according to the first compensation frequency value.

[0059] Further, the method further comprises:

[0060] The compensation adaptive module controls the initial phase-locked loop to generate a frequency scanning signal and send it to each time-to-digital conversion module; obtains transmission delay data of different frequency points recorded by each time-to-digital conversion module; generates a compensation coefficient matrix corresponding to each clock output branch according to the transmission delay data; updates the temperature voltage compensation table of the corresponding clock output branch according to the compensation coefficient matrix, and sends it to the processing module of the clock output branch.

[0061] In summary, compared with the prior art, the technical scheme provided by the embodiments of the present application has at least the following beneficial effects:

[0062] The intelligent calibration multi-channel clock chip system provided by the embodiments of the present application first adds a digital control circuit to each clock output branch in a distributed transmission architecture, which is used to eliminate the distributed transmission delay difference in the reference clock signal before the reference clock signal reaches the frequency divider, and then generates a target clock signal according to the reference clock signal after the delay difference is eliminated, thereby reducing the absolute synchronization error of each clock output branch; secondly, a co-processor is added to control the frequency dividers of each clock output branch, so that the frequency multiplication operation of the frequency dividers on the target clock signal can be flexibly adjusted according to the use scenario, so that the multi-channel clock chip of the present application can adapt to the clock requirements of different scenarios and even newly added scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 The structure diagram of the intelligent calibration multi-channel clock chip system provided by one embodiment of the present application.

[0064] Figure 2 The internal structure diagram of the digital control circuit provided by one embodiment of the present application.

[0065] Figure 3 The flowchart of the intelligent calibration multi-channel clock chip control method provided by one embodiment of the present application.

[0066] Figure 4A flow chart of a target clock signal generation procedure provided by an embodiment of the present application.

[0067] Figure 5 A flow chart of a temperature voltage compensation table updating procedure provided by an embodiment of the present application DETAILED DESCRIPTION

[0068] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application.

[0069] Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0070] Please refer to Figure 1 The embodiments of the present application provide a multi-channel clock chip system with intelligent calibration, which comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches.

[0071] The clock output branch comprises a digital control circuit and a frequency divider connected with each other.

[0072] Each digital control circuit is connected with the selector, and each frequency divider is connected with the coprocessor.

[0073] The initial phase-locked loop is configured to receive an input clock signal, multiply the input clock signal, obtain a reference clock signal and send the reference clock signal to the digital control circuit of at least one clock output branch through the selector.

[0074] The digital control circuit is configured to eliminate the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generate a target clock signal according to the reference clock signal after the delay difference is eliminated, and send the target clock signal to the corresponding frequency divider.

[0075] The coprocessor is configured to receive clock mode information, determine clock control parameters according to the clock mode information, and control the frequency dividers to output after the target clock signal is adjusted according to the clock control parameters.

[0076] Specifically, the clock chip architecture of the present application is as shown in Figure 1As shown, the whole adopts a distributed hybrid PLL architecture, the clock signal input by the initial phase-locked loop to the input stage circuit is multiplied to generate a high-precision reference clock, which is transmitted to the digital control circuit of each clock output branch through a low-noise distributed wiring network, the digital control circuit configured in each clock output branch supports 0.1ps level phase fine tuning, and a digital compensation algorithm is used to eliminate the distributed transmission delay difference in the reference clock, so as to realize the absolute synchronization error of less than 5ps of each clock output branch; meanwhile, a micro coprocessor is integrated and connected with each frequency divider; the coprocessor is used to receive clock mode information, control the frequency or phase parameters of each frequency divider according to the clock control parameters corresponding to the clock mode information, so as to make the frequency divider output the clock signal meeting the demand of the clock mode information.

[0077] In the specific implementation process, the clock mode information can include a 5G base station mode and a vehicle-mounted system mode, the coprocessor is specifically used to receive the clock mode information through a digital pin level combination, for example, 01 combination corresponds to the 5G base station mode, 00 combination corresponds to the vehicle-mounted system mode, etc., and the coprocessor pre-stores the required clock frequency parameters corresponding to each clock mode information, and takes the clock frequency parameters corresponding to the clock mode information as the clock control parameters; or receives the clock control parameters through an I2C interface or an SPI interface. The migration learning algorithm can also be added to the coprocessor, so that the clock chip can adapt to the clock demand of a new scene.

[0078] The above embodiment provides an intelligent calibration multi-channel clock chip system, which first adds a digital control circuit for each clock output branch in the distributed transmission architecture, which is used to eliminate the distributed transmission delay difference in the reference clock signal before the reference clock signal reaches the frequency divider, and then generates a target clock signal according to the reference clock signal after the delay difference is eliminated, so as to reduce the absolute synchronization error of each clock output branch; secondly, the coprocessor is added to control the frequency dividers of each clock output branch, so that the frequency multiplication operation of the frequency dividers on the target clock signal can be flexibly adjusted according to the use scene, so that the multi-channel clock chip of the application can adapt to the clock demand of different scenes and even new scenes.

[0079] In some embodiments, the line between the initial phase-locked loop and each digital control circuit adopts a differential spiral wiring, and the upper half is covered with an electromagnetic shielding layer; the pitch of the differential spiral wiring is 1.5 microns, and the line width is 3 microns.

[0080] The above differential spiral wiring scheme can reduce the inter-line crosstalk of the clock chip by about 30%.

[0081] Further, the power supply line of the whole chip can adopt a honeycomb power supply network to reduce the power noise coupling.

[0082] The material of the electromagnetic shielding layer is a tantalum-based composite material, and the shielding effectiveness can be greater than 45 dB@10 GHz.

[0083] In some embodiments, the initial phase-locked loop and each digital number circuit are embedded with an FBAR filter on a packaging substrate.

[0084] Each FBAR filter is connected to a coprocessor.

[0085] The coprocessor is configured to send a suppression frequency band to each FBAR filter.

[0086] The FBAR filter is configured to perform interference suppression according to the received suppression frequency band.

[0087] The FBAR filter is a film bulk acoustic resonator, and its core function is to achieve precise management of different frequency bands in wireless communication devices through frequency selection, noise suppression, and signal processing.

[0088] The FBAR filter uses the inverse piezoelectric effect of a piezoelectric film to convert electrical energy into acoustic resonance, and through resonance at a specific frequency, it can effectively isolate interference signals and ensure that the device only receives target frequency band signals.

[0089] Moreover, the FBAR filter manufactured using MEMS technology has a volume that is only 1 / 3 to 1 / 2 of that of traditional ceramic filters, and can withstand higher power, meeting the needs of multi-channel clock chips for small area and multiple application scenarios.

[0090] Specifically, the coprocessor can be programmed to control the FBAR filter to suppress frequency bands such as 2.4 GHz and 5.8 GHz that are prone to interfere with clock signals, and different FBAR filters can suppress different frequency bands.

[0091] Please attend Figure 2 In some embodiments, the digital number circuit includes a time-to-digital conversion module, a processing module, and a digitally controlled oscillation module connected in sequence. The time-to-digital conversion module is connected to the selector and is configured to receive a reference clock signal, detect a phase difference between the local clock signal and the reference clock signal, and send the phase difference and the reference clock signal to the processing module.

[0092] Specifically, the detection of the phase difference by the time-to-digital conversion module is periodic, and the detection period can be within 1ms~1s. The phase difference detected in each period is sent to the processing module, and the reference clock signal is sent to the processing module in real time.

[0093] The processing module is configured to adjust the phase of the digitally controlled oscillation module according to the phase difference and a digital compensation algorithm, and to send the reference clock signal to the digitally controlled oscillation module after adjustment.

[0094] Specifically, the processing module adjusts the phase of the numerically controlled oscillation module according to the latest received phase difference.

[0095] It should be noted that the numerically controlled oscillation module is a numerically controlled oscillator, and the core function of the numerically controlled oscillator for the input signal is to generate a controllable high-precision digital signal according to the digital control instruction (frequency control word or phase offset word). The phase of the numerically controlled oscillation module adjusted here is the phase offset word of the numerically controlled oscillation module.

[0096] In the specific implementation process, the digital compensation algorithm can be a PID control algorithm:

[0097]

[0098] wherein, represents the control parameter output by the discrete PID controller at the nth moment, which is usually used to control the controlled object. In the clock chip system applied in the present application, the control parameter is the phase offset word of the numerically controlled oscillation module, so that the numerically controlled oscillation module can realize phase adjustment on the reference clock signal.

[0099] is a proportional coefficient, which determines the degree of immediate response of the PID controller to the error. The larger the proportional coefficient is, the more intense the reaction of the PID controller to the current error will be, and the larger the output control parameter will be, which can quickly reduce the error.

[0100] is an integral coefficient, which is mainly used to eliminate the steady-state error of the system, and it accumulates and sums the error in the past period of time, The larger the integral coefficient is, the stronger the integral effect will be, and the constant deviation existing in the system can be gradually eliminated.

[0101] is a differential coefficient, which is related to the rate of change of the error, and is used to predict the trend of the error change, so as to adjust the system in advance to improve the dynamic performance of the system. The larger the differential coefficient is, the more sensitive the reaction to the error change will be, and the overshoot of the system can be effectively suppressed.

[0102] represents the phase difference at the nth moment, which reflects the current deviation of the corresponding clock output branch and is the basis for the adjustment of the PID controller; represents the cumulative sum of the phase difference from the start time to the nth moment , which reflects the influence of the phase difference at all past moments on the current control effect, and eliminates the steady-state error through the integral effect; The difference between the phase difference at the n th moment and the phase difference at the n-1 th moment is used to calculate the rate of change of the phase difference between two adjacent detection periods, reflects the trend of the phase difference, and the differential element predicts the trend of the phase difference according to the difference, so as to adjust the control output in advance, so that the target clock signal can reach a stable state faster.

[0103] The digitally controlled oscillation module is connected with the frequency divider, and is used to receive the reference clock signal, adjust the frequency or the initial phase of the reference clock signal, generate the target clock signal, and send the target clock signal to the frequency divider.

[0104] Specifically, the digitally controlled oscillation module adjusts the frequency of the reference clock signal according to the frequency control word, adjusts the initial phase of the reference clock signal according to the phase offset word, and sends the adjusted signal to the frequency divider as the target clock signal.

[0105] In the above embodiment, the time-to-digital conversion module, the processing module and the digitally controlled oscillation module cooperate to make the target clock signal more accurate and stable compared with the reference clock signal, and to reduce the absolute synchronization error between the clock output branches.

[0106] In some embodiments, the processing module is also connected with a processing module in an adjacent clock output branch.

[0107] The processing module is also used to send the received phase difference to an adjacent processing module as an adjacent phase difference, receive at least one adjacent phase difference, update the received phase difference according to the adjacent phase difference, and adjust the frequency or the phase of the digitally controlled oscillation module according to the updated phase difference and the digital compensation algorithm.

[0108] The processing module can specifically average the adjacent phase difference and the phase difference received by itself as the updated phase difference.

[0109] In the clock chip, only the phase difference measured by the local channel is adjusted, which is equivalent to a first-order negative feedback, and the loop bandwidth must be made very narrow to suppress noise; after the phase difference of the adjacent channel is weighted, a "second-order" or even "multi-order" component is introduced, and the error energy is "flattened" to the adjacent nodes more quickly, the locking time can be shortened by 30%-50%, and the period jitter (RJ) of the output is also reduced. In addition, on-chip wiring, temperature gradient and power supply noise often cause directional skew of the phase difference, and only the local error, the adjustment direction may always fight with the real gradient; after introducing the adjacent channel information, the phase difference becomes smoother, and the adjustment direction naturally follows the gradient, and the residual skew can be reduced again.

[0110] In summary, when the reference clock signal is compensated by the phase difference controlled digital controlled oscillation module, the phase difference of the adjacent channel is updated, which is equivalent to changing the single-point adjustment of a single channel to a small distributed cooperative adjustment, so as to further reduce the error between different clock output branches and improve the robustness.

[0111] In some embodiments, the processing module is further configured to obtain a temperature-voltage compensation table and a control voltage of the digital controlled oscillation module; if the control voltage is less than a first preset voltage threshold, obtain a first compensation frequency value based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, obtain the first compensation frequency value based on a second linear model; if the control voltage is greater than the second preset voltage threshold, obtain the first compensation frequency value according to the temperature-voltage compensation table; the second preset voltage threshold is greater than the first preset voltage threshold; and after adjusting the phase of the digital controlled oscillation module according to the phase difference and the digital compensation algorithm, adjust the frequency of the digital controlled oscillation module according to the first compensation frequency value.

[0112] In the temperature-voltage compensation table, the frequency deviation caused by the transmission of the clock chip circuit under different environmental temperatures and different voltages is recorded according to historical experience values.

[0113] The control voltage of the digital controlled oscillation module is the voltage of the control signal sent by the processing module to the digital controlled oscillation module to adjust the frequency control word or phase offset word. The above-mentioned adjustment of the frequency of the digital controlled oscillation module according to the first compensation frequency value specifically adds the first compensation frequency value to the original frequency control word of the digital controlled oscillation module, so that the digital controlled oscillation module adjusts the frequency of the reference clock signal according to the updated frequency control word.

[0114] Specifically, if the control voltage is less than the first preset voltage threshold, the first linear model is used:

[0115]

[0116] wherein, is the first compensation frequency value, is the control voltage of the digital controlled oscillation module, which is a variable input into the linear model and is used to control the working state of the digital controlled oscillation module, and its size determines the frequency value that needs to be compensated finally.

[0117] If the control voltage is greater than or equal to the first preset voltage threshold and less than the second preset voltage threshold, the second linear model is used:

[0118]

[0119] wherein, , 、 、 、 are coefficients in different linear models, which are determined by certain methods according to the characteristics of the digital controlled oscillation module and specific compensation requirements, etc., and are used to calculate the compensation frequency values in different voltage intervals, which determine the specific functional relationship between the compensation frequency and the control voltage.

[0120] If the control voltage is greater than the second preset voltage threshold, then , the first compensation frequency value corresponding to the control voltage is obtained according to the preset temperature-voltage compensation table LUT.

[0121] The present application adopts a differentiated compensation method in different control voltage intervals of the digital controlled oscillation module, that is, a linear model compensation is adopted in the low voltage interval to ensure the frequency compensation accuracy, and a table lookup method is adopted in the high voltage interval to save the calculation resources.

[0122] Further, the processing module is further configured to obtain historical frequency errors of each clock output branch; construct an error probability density function according to each historical delay error, extract a fixed offset of a preset frequency point as a systematic deviation component according to the error probability density function; and update network parameters of the first linear model and the second linear model according to the systematic deviation component and the recursive least square method.

[0123] Specifically, during the long-term operation of the clock chip, the transmission delay of the clock chip may change due to device aging or other external factors. Therefore, the present application adds a self-learning mechanism in the processing module to extract the frequency offset features in the historical data, and sequentially updates the network parameters of the first linear model and the second linear model according to the recursive least square method (i.e. 、 、 、 、 ), so as to ensure the synchronization accuracy of the processing module or the entire multi-channel clock chip system during the long-term operation.

[0124] In some embodiments, the system further comprises a temperature sensing module.

[0125] The temperature sensing module is configured to collect junction temperature data of each clock output branch and send the junction temperature data to the corresponding processing module.

[0126] ​The processing module is also configured to acquire a semiconductor carrier mobility temperature coefficient and a thermal expansion coefficient of a packaging material of the clock output branch; calculate a temperature delay variation according to the junction temperature data, the semiconductor carrier mobility temperature coefficient, the thermal expansion coefficient and a preset calibration temperature; obtain a temperature compensation frequency value in a temperature voltage compensation table according to the temperature delay variation, and adjust the frequency of the numerically controlled oscillation module according to the temperature compensation frequency value and the first compensation frequency value.

[0127] Specifically, the temperature sensing module collects junction temperature data of each clock output branch on the basis that the collection accuracy meets ±0.5℃ and sends the junction temperature data to the corresponding processing module, and the processing module uses the junction temperature data to construct a temperature compensation model:

[0128]

[0129] Among them, is a temperature delay variation of the i th clock output branch caused by temperature change, which is used to measure the influence degree of temperature on channel transmission delay, and a temperature compensation frequency value is obtained by table lookup according to the temperature delay variation.

[0130] is a thermal expansion coefficient of the packaging material, which reflects the characteristics of expansion or contraction of the packaging material with temperature change, and the greater the coefficient, the more obvious the size change of the packaging material caused by temperature change, and the greater the influence on transmission delay.

[0131] is a semiconductor carrier mobility temperature coefficient, which embodies the relationship between the carrier mobility in the semiconductor and the temperature, and the carrier mobility affects the transmission speed of electrons in the semiconductor, thereby affecting the transmission delay of the channel.

[0132] is the junction temperature data actually measured by the temperature sensing module for the i th clock output branch, and the unit is ℃.

[0133] is a preset calibration temperature, which is a reference temperature value, and is usually a temperature set when the multi-channel clock chip is calibrated, and is used as a reference for calculating the influence of temperature change on transmission delay.

[0134] After obtaining the temperature compensation frequency value, the processing module adds the temperature compensation frequency value and the first compensation frequency value, and then adds the sum to the original frequency control word of the numerically controlled oscillation module, so as to update the frequency of the numerically controlled oscillation module.

[0135] The above embodiment collects the junction temperature data of the clock output branch through the temperature sensing module, compensates the delay variation of the reference clock signal transmission caused by the environmental temperature based on the junction temperature data, and further ensures the synchronization of each clock output branch.

[0136] In some embodiments, the system further comprises a voltage sensing module.

[0137] The voltage sensing module is configured to measure the supply voltage of each clock output branch and send to the corresponding processing module.

[0138] The processing module is configured to calculate the voltage delay variation according to the supply voltage, the preset nominal voltage and the preset delay reference value, obtain the second compensation frequency value in the temperature voltage compensation table according to the voltage delay variation, and adjust the frequency of the numerically controlled oscillation module according to the first compensation frequency value, the second compensation frequency value and the temperature compensation frequency value.

[0139] Specifically, the voltage sensing module monitors the supply voltage fluctuation at a sampling rate of 10MS / s, obtains the supply voltage of each clock output branch and sends to the corresponding processing module, and the processing module constructs a voltage compensation model according to the received supply voltage:

[0140]

[0141] Wherein, VDD is the measured supply voltage; is the preset nominal voltage, which is the normal working voltage value specified during chip design, serving as a reference for measuring whether the actual supply voltage deviates from the normal state.

[0142] is the preset nominal voltage is the preset delay reference value of the channel transmission, which is a reference value determined during chip design or calibration, representing the ideal transmission delay of the channel under normal voltage.

[0143] is a coefficient related to the characteristics of the chip circuit, usually ranging from 0.8 to 1.2, used to describe the degree of nonlinearity between the supply voltage and the transmission delay.

[0144] After obtaining the second compensation frequency value, the processing module adds the temperature compensation frequency value, the second compensation frequency value and the first compensation frequency value, and then adds the result to the original frequency control word of the numerically controlled oscillation module, to update the frequency of the numerically controlled oscillation module.

[0145] It should be noted that the supply voltage and the control voltage are different, and the objects of compensation are also different; the control voltage of the numerically controlled oscillation module is generated when the processing module adjusts and controls it, while the supply voltage is generated by the power supply of the clock chip; the control voltage only exists when the processing module controls the numerically controlled oscillation module, while the supply voltage exists during the power supply of the chip; the first compensation frequency value is used to compensate for the transmission delay of the reference clock signal transmission under different control voltages, and the second compensation frequency value is used to compensate for the transmission delay caused by the change of the supply voltage.

[0146] The above embodiment collects the power supply voltage of the clock output branch through the voltage sensing module, and then compensates the delay variation of the reference clock signal transmission caused by the change of the power supply voltage, thereby further ensuring the synchronization of each clock output branch.

[0147] In some embodiments, the digitally controlled oscillation module is specifically configured to multiply the frequency of the reference clock signal by a power of 2 of the frequency control word after division, to obtain the frequency of the target clock signal; wherein the power is the bit width of the phase accumulator of the digitally controlled oscillation module.

[0148] Specifically, the formula for adjusting the reference clock signal according to the frequency control word by the digitally controlled oscillation module is:

[0149]

[0150] wherein FCW is the frequency control word updated by the processing module in the digitally controlled oscillation module; N is the bit width of the phase accumulator of the digitally controlled oscillation module, which is a known data determined during chip design and development.

[0151] is the frequency of the output target clock signal, is the frequency of the received reference clock signal.

[0152] In some embodiments, the processing module is further configured to calculate an average delay variation according to a plurality of temperature delay variations and a plurality of voltage delay variations in a preset period; obtain the running time of the digitally controlled oscillation module; obtain the aging factor of the clock output branch based on the average delay variation and the running time; and perform aging warning when the aging factor is greater than a preset aging threshold.

[0153] Specifically, the processing module will average each temperature delay variation and voltage delay variation calculated in the current period every preset period, for example, 1 week or 1 month, to obtain an average delay variation, and calculate the aging factor in combination with the running time of the digitally controlled oscillation module, and the specific calculation formula is as follows:

[0154]

[0155] wherein, is the aging factor, which is the calculation result of the above formula, and is used to measure the aging degree of the multi-channel clock chip system of the application. It comprehensively considers other related parameters (running time, average delay variation, etc.) to obtain a quantitative value to evaluate the aging condition of the clock chip system. When the value exceeds the set preset aging threshold, a warning is triggered to prompt the relevant personnel that the device or system may have an aging problem, which needs to be checked, maintained or replaced, etc.

[0156] is the average delay variation; is the initial time delay, which refers to the time delay parameter corresponding to the start of operation or the initial state of the numerically controlled oscillation module connected to the processing module; is the running time, which refers to the time experienced by the numerically controlled oscillation module of the current clock output branch from the start of operation to the current time.

[0157] The above embodiment causes each processing module to perform aging evaluation on the clock output branch where it is located, so as to remind the staff to repair or replace as soon as possible when the device is aged to the extent that the clock signal synchronization cannot be achieved through frequency or phase compensation.

[0158] In some embodiments, the system further comprises a compensation adaptive module.

[0159] The compensation adaptive module is connected to the initial phase-locked loop and each time-to-digital conversion module, respectively.

[0160] The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency scanning signal and send it to each time-to-digital conversion module; obtain the transmission delay data of different frequency points recorded by each time-to-digital conversion module; generate a compensation coefficient matrix corresponding to each clock output branch according to the transmission delay data; update the temperature and voltage compensation table of the corresponding clock output branch according to the compensation coefficient matrix, and send it to the processing module of the clock output branch.

[0161] The frequency range of the frequency scanning signal is 10MHz-2GHz, and the step is 10MHz.

[0162] Specifically, the compensation adaptive module controls the initial phase-locked loop to generate a frequency scanning signal, and injects the input end of the time-to-digital conversion module of each clock output branch through a multiplexer MUX; for example, the first time sends a frequency scanning signal of 10MHz to each channel, the second time sends a frequency scanning signal of 20MHz to each channel, and so on.

[0163] The time-to-digital conversion module of each clock output branch records the transmission delay data of the channel at different frequency points and sends it to the compensation adaptive module, so that the compensation adaptive module constructs a delay-frequency model according to the transmission delay data:

[0164]

[0165] wherein, is the transmission delay data generated by the ith clock output branch when transmitting the frequency scanning signal with a frequency of f, which is obtained by sampling through the time-to-digital conversion module with a sampling rate of 1GS / s.

[0166] The quadratic coefficient caused by the parasitic capacitance of the wiring, The linear coefficient related to the matching degree of the characteristic impedance of the transmission line, The fixed wiring delay, and the above three coefficients are required to be determined according to the multiple And The fitting obtains; The random noise;

[0167] After the delay-frequency model is constructed, the compensation coefficient matrix of the current clock chip system is obtained according to the model:

[0168]

[0169] Wherein, The compensation coefficient matrix of the i-th clock output branch, k = 1...N frequency points, The maximum delay value of each clock output branch; The minimum phase adjustment step of the digital control oscillation module, generally 0.1ps.

[0170] After the compensation coefficient matrix is obtained, the compensation coefficient matrix is multiplied by the temperature and voltage compensation table summarized from historical experience to obtain a temperature and voltage compensation table suitable for the current clock chip system, and is written into the SRAM of each clock output branch.

[0171] It is worth noting that the traditional temperature and voltage compensation table is obtained according to historical experience, and the clock chip system is iterated with the development of technology, and the internal devices are also updated from generation to generation. Therefore, the historical temperature and voltage compensation table is not necessarily completely applicable to the current version of the clock chip system. Therefore, after the hardware architecture of the clock chip system is designed, the transmission delay data obtained by the frequency scanning signal is used to construct the compensation coefficient matrix, so as to update the traditional temperature and voltage compensation table, so that the table is adapted to the hardware condition of the current clock chip system, thereby realizing accurate error compensation.

[0172] In addition, the above embodiment adopts a pseudo-random frequency scanning sequence when measuring the transmission delay data of each channel of the clock chip system, which can enhance the robustness of the compensation coefficient matrix obtained by constructing the model.

[0173] Please refer to Figure 3 Another embodiment of the present application provides a kind of intelligent calibration multi-channel clock chip control method, applied to multi-channel clock chip control system, multi-channel clock chip control system includes coprocessor, initial phase-locked loop, selector and multiple clock output branches;Clock output branch includes mutually connected digital control circuit and frequency divider;The control method comprises:

[0174] Step S1, the initial phase-locked loop receives an input clock signal, frequency-multiplies the input clock signal, obtains a reference clock signal, and sends the reference clock signal to a digital control circuit of at least one clock output branch through a selector.

[0175] Step S2, the digital control circuit eliminates the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generates a target clock signal according to the reference clock signal after the delay difference is eliminated, and sends the target clock signal to a corresponding frequency divider.

[0176] Step S3, the coprocessor receives clock mode information, determines clock control parameters according to the clock mode information, and controls the frequency dividers to output after the target clock signal is adjusted according to the clock control parameters.

[0177] In some embodiments, the method further comprises:

[0178] The coprocessor receives the clock mode information through a digital pin level combination.

[0179] Alternatively, the coprocessor receives the clock control parameters through an I2C interface or an SPI interface.

[0180] In some embodiments, the digital control circuit comprises a time-to-digital conversion module, a processing module, and a digitally controlled oscillation module connected in sequence.

[0181] Please refer to Figure 4 The digital control circuit eliminates the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generates a target clock signal according to the reference clock signal after the delay difference is eliminated, and sends the target clock signal to a corresponding frequency divider, comprising:

[0182] Step S21, the time-to-digital conversion module receives the reference clock signal, detects the phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module.

[0183] Step S22, the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and a digital compensation algorithm, and sends the reference clock signal to the digitally controlled oscillation module after the adjustment.

[0184] Step S23, the digitally controlled oscillation module receives the reference clock signal, adjusts the frequency or phase of the reference clock signal, generates a target clock signal, and sends the target clock signal to the frequency divider.

[0185] In an embodiment, the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and a digital compensation algorithm, comprising:

[0186] The processing module sends the received phase difference as an adjacent phase difference to the processing module of an adjacent clock output branch.

[0187] The processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference, and adjusts the frequency or phase of the digital control oscillation module according to the updated phase difference and a digital compensation algorithm.

[0188] In some embodiments, the method further comprises:

[0189] In step S41, the processing module is further configured to obtain a temperature-voltage compensation table and a control voltage of the digital control oscillation module.

[0190] In step S42, if the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; and the second preset voltage threshold is greater than the first preset voltage threshold.

[0191] In step S43, the frequency of the digital control oscillation module is adjusted according to the first compensation frequency value.

[0192] Please refer to Figure 5 In some embodiments, the method further comprises:

[0193] In step S01, the compensation adaptive module controls an initial phase-locked loop to generate a frequency scanning signal and send it to each time-to-digital conversion module; and obtains transmission delay data of different frequency points recorded by each time-to-digital conversion module.

[0194] In step S02, a compensation coefficient matrix corresponding to each clock output branch is generated according to the transmission delay data; a temperature-voltage compensation table of the corresponding clock output branch is updated according to the compensation coefficient matrix, and is sent to the processing module of the clock output branch.

[0195] The specific limitations of the method for controlling the multi-channel clock chip provided in the embodiments can be referred to the embodiments of the multi-channel clock chip system for intelligent calibration described above, and will not be described here.

[0196] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0197] The above-described embodiments are merely illustrative of several embodiments of the present application, which are described in more detail and in a specific and detailed manner, but should not be construed as limiting the scope of the patent. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are all within the scope of the present application. Therefore, the scope of protection of the patent of the present application should be subject to the appended claims.

Claims

1. A multi-channel clock chip system with intelligent calibration, characterized in that, It includes a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches; the initial phase-locked loop and the selector are connected; The clock output branch includes interconnected numerical control circuits and frequency dividers; each numerical control circuit is connected to the selector; each frequency divider is connected to the coprocessor. The initial phase-locked loop is used to receive the input clock signal, multiply the input clock signal to obtain a reference clock signal, and send it to the numerical control circuit of at least one of the clock output branches through a selector. The numerical control circuit is used to eliminate distributed transmission delay differences in the reference clock signal using a digital compensation algorithm, generate a target clock signal based on the reference clock signal after delay difference elimination, and send it to the corresponding frequency divider; wherein, the numerical control circuit includes a time-to-digital conversion module, a processing module, and a numerically controlled oscillation module connected in sequence; the time-to-digital conversion module is connected to the selector, used to receive the reference clock signal, detect the phase difference between the local clock signal and the reference clock signal, and send the phase difference and the reference clock signal to the processing module; the processing module is used to adjust the phase of the numerically controlled oscillation module according to the phase difference and the digital compensation algorithm, and After adjustment, the reference clock signal is sent to the numerically controlled oscillation module; the processing module is also connected to the processing module in the adjacent clock output branch; the processing module is also used to send the received phase difference as an adjacent phase difference to the adjacent processing module; and to receive at least one adjacent phase difference, update the received phase difference according to the adjacent phase difference; adjust the frequency or phase of the numerically controlled oscillation module according to the updated phase difference and the digital compensation algorithm; the numerically controlled oscillation module is connected to the frequency divider, used to receive the reference clock signal, adjust the frequency or phase of the reference clock signal, generate the target clock signal and send it to the frequency divider; The coprocessor is used to receive clock mode information, determine clock control parameters based on the clock mode information, and control each frequency divider to adjust the target clock signal and output it based on the clock control parameters.

2. The intelligent calibration multi-channel clock chip system according to claim 1, characterized in that, The coprocessor is specifically used to receive the clock mode information through a combination of digital pin levels, and use the clock frequency parameter corresponding to the clock mode information as the clock control parameter; or to receive the clock control parameter through an I2C interface or an SPI interface.

3. The intelligent calibration multi-channel clock chip system according to claim 2, characterized in that, The clock mode information includes 5G base station mode and vehicle system mode.

4. The intelligent calibration multi-channel clock chip system according to claim 1, characterized in that, The wiring between the initial phase-locked loop and each of the numerical control circuits adopts differential spiral wiring, and the upper part is covered with an electromagnetic shielding layer. The differential spiral wiring has a spacing of 1.5 micrometers and a line width of 3 micrometers; The electromagnetic shielding layer is made of tantalum-based composite material.

5. The intelligent calibration multi-channel clock chip system according to claim 4, characterized in that, The initial phase-locked loop and the packaging substrate of each of the numerical control circuits are all embedded with FBAR filters. Each of the FBAR filters is connected to the coprocessor; The coprocessor is used to send the suppression band to each of the FBAR filters; The FBAR filter is used to suppress interference based on the received suppression frequency band.

6. The intelligent calibration multi-channel clock chip system according to claim 1, characterized in that, The processing module is also used to acquire the temperature and voltage compensation table and the control voltage of the numerical control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein, the second preset voltage threshold is greater than the first preset voltage threshold. Furthermore, after adjusting the phase of the numerically controlled oscillation module according to the phase difference and digital compensation algorithm, the frequency of the numerically controlled oscillation module is adjusted according to the first compensation frequency value.

7. The intelligent calibration multi-channel clock chip system according to claim 6, characterized in that, It also includes a temperature sensing module; the temperature sensing module is used to collect junction temperature data of each clock output branch and send it to the corresponding processing module; The processing module is also used to obtain the temperature coefficient of semiconductor carrier mobility and the coefficient of thermal expansion of the packaging material of the clock output branch; calculate the temperature delay change based on the junction temperature data, the temperature coefficient of semiconductor carrier mobility, the coefficient of thermal expansion and the preset calibration temperature; obtain the temperature compensation frequency value in the temperature voltage compensation table based on the temperature delay change; and adjust the frequency of the numerically controlled oscillation module based on the temperature compensation frequency value and the first compensation frequency value.

8. The intelligent calibration multi-channel clock chip system according to claim 7, characterized in that, It also includes a voltage sensing module; the voltage sensing module is used to measure the power supply voltage of each clock output branch and send it to the corresponding processing module; The processing module is used to calculate the voltage delay change based on the power supply voltage, the preset nominal voltage and the preset delay reference value, obtain the second compensation frequency value in the temperature and voltage compensation table based on the voltage delay change, and adjust the frequency of the numerical control oscillation module based on the first compensation frequency value, the second compensation frequency value and the temperature compensation frequency value.

9. The intelligent calibration multi-channel clock chip system according to claim 8, characterized in that, The numerically controlled oscillation module is specifically used to divide the frequency control word by a power of 2 and then multiply it by the frequency of the reference clock signal to obtain the frequency of the target clock signal; wherein, the power is the bit width of the phase accumulator of the numerically controlled oscillation module.

10. The intelligent calibration multi-channel clock chip system according to claim 8, characterized in that, The processing module is also used to calculate the average delay change based on multiple temperature delay changes and multiple voltage delay changes within a preset period; and to obtain the running time of the numerically controlled oscillation module; The aging factor of the clock output branch is obtained based on the average delay change and the running time; an aging warning is issued when the aging factor is greater than a preset aging threshold.

11. The intelligent calibration multi-channel clock chip system according to claim 6, characterized in that, The processing module is also used to obtain the historical frequency error of each clock output branch; construct an error probability density function based on each historical frequency error; extract a fixed offset of a preset frequency point based on the error probability density function and use it as a systematic deviation component; and update the network parameters of the first linear model and the second linear model based on the systematic deviation component and the recursive least squares method.

12. The intelligent calibration multi-channel clock chip system according to claim 6, characterized in that, It also includes a compensation and adaptive module; the compensation and adaptive module is connected to the initial phase-locked loop and each of the time-to-digital converter modules respectively; The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency scanning signal and send it to each of the time-to-digital converter modules; acquire transmission delay data at different frequency points recorded by each of the time-to-digital converter modules; generate a compensation coefficient matrix corresponding to each of the clock output branches based on the transmission delay data; update the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix, and send it to the processing module of the clock output branch.

13. A method for controlling a multi-channel clock chip with intelligent calibration, characterized in that, This is applied to a multi-channel clock chip control system, which includes a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches. The clock output branch includes interconnected numerical control circuits and frequency dividers; the control method includes: The initial phase-locked loop receives the input clock signal, multiplies the frequency of the input clock signal to obtain a reference clock signal, and sends it to the numerical control circuit of at least one clock output branch through a selector. The numerical control circuit uses a digital compensation algorithm to eliminate distributed transmission delay differences in the reference clock signal, generates a target clock signal based on the reference clock signal after eliminating delay differences, and sends it to the corresponding frequency divider; wherein, the numerical control circuit includes a time-to-digital conversion module, a processing module, and a numerically controlled oscillation module connected in sequence; The numerical control circuit employs a digital compensation algorithm to eliminate distributed transmission delay differences in the reference clock signal, generates a target clock signal based on the reference clock signal after delay difference elimination, and sends it to the corresponding frequency divider, including: The time-to-digital conversion module receives the reference clock signal, detects the phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module. The processing module adjusts the phase of the numerically controlled oscillation module according to the phase difference and digital compensation algorithm, and sends the reference clock signal to the numerically controlled oscillation module after adjustment; Specifically, the processing module sends the received phase difference as an adjacent phase difference to the processing module of the adjacent clock output branch; the processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference; and adjusts the frequency or phase of the numerically controlled oscillation module according to the updated phase difference and the digital compensation algorithm. The numerically controlled oscillation module receives the reference clock signal, adjusts the frequency or phase of the reference clock signal, generates the target clock signal, and sends it to the frequency divider. The coprocessor receives clock mode information, determines clock control parameters based on the clock mode information, and controls each frequency divider to adjust the target clock signal and output it based on the clock control parameters.

14. The intelligent calibration multi-channel clock chip control method according to claim 13, characterized in that, Also includes: The coprocessor receives the clock mode information via a combination of digital pin levels. Alternatively, the coprocessor receives the clock control parameters via an I2C interface or an SPI interface.

15. The intelligent calibration multi-channel clock chip control method according to claim 13, characterized in that, Also includes: The processing module is also used to acquire the temperature and voltage compensation table and the control voltage of the numerical control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein, the second preset voltage threshold is greater than the first preset voltage threshold. The frequency of the numerically controlled oscillation module is adjusted according to the first compensation frequency value.

16. The intelligent calibration multi-channel clock chip control method according to claim 15, characterized in that, Also includes: The compensation adaptive module controls the initial phase-locked loop to generate a frequency scanning signal and sends it to each of the time-to-digital converter modules; it acquires the transmission delay data of different frequency points recorded by each of the time-to-digital converter modules; it generates a compensation coefficient matrix corresponding to each of the clock output branches based on the transmission delay data; it updates the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and sends it to the processing module of the clock output branch.

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