Data reading request processing method and computer device

Abstract

The application discloses a data reading request processing method and computer equipment, and relates to the technical field of data storage, and comprises the following steps: determining to-be-read data according to a data reading request; comparing address information of the to-be-read data with a preset variable to determine whether the to-be-read data is stored in a first preset buffer; and if the comparison is successful, directly sending the to-be-read data in the first preset buffer to a host computer. The problem of wasting central processor resources caused by repeatedly reading Nand flash data when processing a host reading request can be solved. The method can directly return valid data cached in the first preset buffer to the host computer without performing additional operations on a logical-to-physical address mapping table, and the random reading performance of a solid state disk under a steady state is improved.

Description

Technical Field

[0001] This application relates to the field of data storage technology, specifically to a data read request processing method and a computer device. Background Technology

[0002] Random read performance is a metric for measuring the performance of solid-state drives (SSDs) when handling scattered, non-contiguous data reads. The level of random read performance directly impacts the data processing speed and efficiency of applications. Scenarios requiring frequent access to small files necessitate SSDs with high random read performance.

[0003] NAND flash memory is a non-volatile memory. When a solid-state drive (SSD) enters a steady state and triggers Garbage Collection (GC), the GC operation reads data from the NAND flash into the GC buffer but does not modify the Logical to Physical (L2P) table. At this point, if a data read request is received from the host, the data to be read might already be in the buffer. However, currently, processing this request requires repeatedly reading the NAND flash, identifying the data in the NAND flash, returning it to the corresponding buffer, and then returning it to the host. This results in repeated readings of NAND flash data, wasting CPU resources. Summary of the Invention

[0004] In view of this, this application provides a data read request processing method and a computer device to solve the problem of repeatedly reading Nand flash memory data when processing host read requests, which causes a waste of central processing unit resources.

[0005] Firstly, this application provides a data read request processing method, the method comprising:

[0006] Upon receiving a data read request from the host, determine the data to be read based on the data read request;

[0007] The address information of the data to be read is determined, and the address information is compared with a preset variable to obtain the comparison result. The preset variable is generated during the process of writing data into the first preset buffer and is used to determine the data stored in the first preset buffer.

[0008] If the comparison results determine that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0009] Secondly, this application provides a data read request processing apparatus, the apparatus comprising:

[0010] The data determination module is used to determine the data to be read based on the data read request sent by the host upon receiving the data read request.

[0011] The information comparison module is used to determine the address information of the data to be read and compare the address information with a preset variable to obtain the comparison result. The preset variable is generated during the process of writing data into the first preset buffer and is used to determine the data stored in the first preset buffer.

[0012] The data sending module is used to send the data to be read in the first preset buffer to the host if the comparison result determines that the data to be read is in the first preset buffer.

[0013] Thirdly, this application provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the data read request processing method described in the first aspect or any corresponding embodiment.

[0014] Fourthly, this application provides a computer-readable storage medium storing computer instructions that cause a computer to execute the data read request processing method described in the first aspect or any corresponding embodiment.

[0015] Fifthly, this application provides a computer program product, including computer instructions for causing a computer to execute the data read request processing method described in the first aspect or any corresponding embodiment.

[0016] This application provides a solution to the problem of wasted CPU resources caused by repeatedly reading Nand flash memory data when processing host read requests. This method determines the data to be read based on the data read request; compares the address information of the data to be read with a preset variable to determine if the data is stored in a first preset buffer; and if the comparison is successful, directly sends the data to be read from the first preset buffer to the host. Furthermore, this method can directly return valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thus improving the stable random read performance of the solid-state drive. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this application, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating the conventional processing of data read requests according to embodiments of this application;

[0019] Figure 2 This is a flowchart illustrating a data read request processing method according to an embodiment of this application;

[0020] Figure 3 This is a flowchart illustrating the process of handling a data read request based on preset variables according to an embodiment of this application;

[0021] Figure 4 This is a flowchart illustrating another data read request processing method according to an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of page-to-buffer mapping according to an embodiment of this application;

[0023] Figure 6 This is a schematic diagram illustrating how preset parameters are modified according to embodiments of this application;

[0024] Figure 7 This is a schematic diagram illustrating the processing of garbage collection requests according to preset variables based on an embodiment of this application;

[0025] Figure 8 This is a structural block diagram of a data read request processing apparatus according to an embodiment of this application;

[0026] Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] Random read performance is one of the core metrics for measuring the performance of solid-state drives (SSDs) in handling distributed, non-contiguous data reads. High random read performance is crucial for scenarios requiring frequent access to small files, such as system startup, game loading, and database operations. Random read performance is typically expressed using IOPS (Input / Output Operations Per Second) and Latency (time taken for a single random read operation). The quality of random read performance directly impacts the data processing speed and efficiency of applications. QLC (Quad-Level Cell) hard drives are a type of SSD. A single cell in a QLC hard drive represents four states, making it sensitive to voltage thresholds. Each layer contains several world lines (wls) of data. The process of writing data to a QLC hard drive involves: first, writing the complete data from the lowest layer into the Nand flash memory chip; this complete write operation is called the initial programming. Subsequently, when programming the word line data of the layer immediately above the bottom layer begins, a phenomenon called "write interference" occurs. This is because when a programming high voltage is applied to a layer 1 cell, the physically adjacent layer 0 cell may be affected by the electric field, causing a slight change or drift in its stored charge (representing voltage / data state). To ensure that the data of layer 0 is not corrupted by this interference, after completing the initial programming of layer 1, the original data of layer 0 from the previous step needs to be completely rewritten. This second write operation for layer 0 is called secondary programming. This process continues thereafter; after each initial programming of the current layer's data, the data of the layer above needs to be rewritten. Both the initial and secondary programming involve a complete, overwrite rewrite of the entire target layer.

[0029] QLC (Quickly Logic Controller) hard drives are ultra-high-capacity products, further increasing the amount of cached data. During garbage collection, approximately 196MB of data is cached in the garbage collection buffer. In a steady state, QLC hard drives have a large amount of data. After being read from the NAND flash memory, it is placed in the garbage collection buffer, greatly increasing the probability that the host's data read request will hit the garbage collection buffer. Currently, when a solid-state drive enters a steady state and triggers garbage collection, the garbage collection operation reads data into the garbage collection buffer but does not modify the L2P (Logical to Physical Mapping) table. This means the same data is stored in both the NAND flash memory and the garbage collection buffer. Even if the data the host reads is already stored in the garbage collection buffer, it still needs to be read from the NAND flash memory. Currently, the traditional data read request process is as follows: Figure 1As shown, upon receiving a host read command, a flash read command is sent to the Nand flash memory to read the Nand data. The flash read response information is then sent to a buffer, which in turn sends a host read response information back to the host, completing the data recovery process. This current data read request handling mechanism repeatedly reads data from the Nand flash memory, resulting in a waste of CPU resources.

[0030] Based on the above, this application provides a data read request processing method, adding a P2B (page-to-buffer mapping) technology. This technology uses two variables to indicate whether the PBA (physical block addressing) address corresponding to the LBA (logical block address) has been written to the garbage collection buffer during the data read request processing flow. Furthermore, to prevent the buffer from being released during the processing of host data read / write requests, this embodiment designs a GCbuffer refCount (garbage collection buffer reference counting) mechanism, using refCount to determine whether the buffer can be released. The method for processing data read requests is as follows: Figure 1 As shown, upon receiving a host read command, the corresponding data is determined from the buffer data, and the host read response information is sent to the host. This achieves the goal of directly returning the valid data cached in the garbage collection buffer to the host without additional operations on the L2P table, greatly improving the random read performance of the QLC hard drive under steady-state conditions.

[0031] According to an embodiment of this application, a data read request processing embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, for example, a computer, a server, etc., and although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0032] This embodiment provides a data read request processing method. Figure 2 This is a flowchart of a data read request processing method according to an embodiment of this application, such as... Figure 2 As shown, the process includes the following steps:

[0033] Step S201: Upon receiving a data read request from the host, determine the data to be read based on the data read request.

[0034] Specifically, in this embodiment, the data management module (DM) performs the operation. The data management module, upon receiving a data read request from the host within the solid-state drive, returns the data to be read corresponding to the data read request to the host.

[0035] Combination Figure 3 In this embodiment, when the data management module receives a data read request from the host, it parses the request and extracts the logical block address (LBA). The LBA is the data unit used for communication between the host and the solid-state drive (SSD), typically 4KB in size. If the host needs to read or write 400KB of data, that is, 400KB / 4KB = 100 LBAs of data. Based on the parsed LBA, the data management module can determine the data to be read by the host.

[0036] Step S202: Determine the address information of the data to be read, and compare the address information with a preset variable to obtain the comparison result. The preset variable is generated during the process of writing data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer.

[0037] Specifically, the data management module queries the logical-to-physical address mapping table to determine the PBA address of the data to be read. The PBA is the physical address mapping of the storage unit inside the Nand flash memory, which directly corresponds to the actual physical location of the flash memory medium and forms a mapping relationship with the logical block address. The L2P table records the logical-to-physical address mapping relationship and is a key core technology component table of solid-state drives.

[0038] Each user data LBA is saved to the NAND flash memory, and the corresponding NAND flash memory address is the PBA. The PBA format is as follows:

[0039] The `pba` structure is defined as follows: `struct {uint32_t logical_lun:5;uint32_t dataframe:2;uint32_t plane:2;uint32_t page:11;uint32_t block:10;uint32_t slun:2;}`. Here, `logical_lun:5` represents logical unit 5; `dataframe:2` represents data frame 2; `plane:2` represents logical partition 2; `page:11` represents page 11; `block:10` represents data block 10; and `slun:2` represents sub-logical unit 2. Based on this, the location of the current data in the Nand flash memory can be determined through the `pba`, using a multi-level indexing system of `lun`, `block`, `plane`, `page`, and `dataframe`. Therefore, based on the determined `pba` address, the address information of the data to be read can be obtained, including information such as `lun` (logical unit), `block` (data block), `page` (data page), `dataframe` (data frame), and `SPB_ID` (Super Block Identity document).

[0040] Preset variables, for example, are variables generated based on page-to-buffer mapping technology. These variables are generated during the process of writing data to the first preset buffer. In the data read request processing flow, this variable indicates whether the PBA corresponding to the LBA has been written to the first preset buffer. The first preset buffer is, for example, the garbage collection buffer. The address information is compared with the preset variables. If the address information matches the preset variables, it is determined that the data to be read has been written to the first preset buffer. The above process is as follows: Figure 3 As shown, the logical-to-physical address mapping table is read to obtain the corresponding physical block address, and it is determined whether the data is stored in the garbage collection buffer.

[0041] Step S203: If the comparison result determines that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0042] Specifically, if the comparison results determine that the data to be read is in the first preset buffer, the data management module returns the data to be read from the first preset buffer to the host. For example, if the address information matches the preset variable, it is determined that the data to be read is in the first preset buffer, and the data to be read is returned to the host. Figure 3 As shown, data is moved from the first preset buffer to the host.

[0043] The data read request processing method provided in this embodiment determines the data to be read based on the data read request; compares the address information of the data to be read with a preset variable to determine whether the data to be read is stored in a first preset buffer; if the comparison is successful, the data to be read in the first preset buffer is directly sent to the host. This method can directly return the valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thus improving the random read performance of the solid-state drive under steady-state conditions. It solves the problem of wasting CPU resources by repeatedly reading Nand flash memory data when processing host read requests.

[0044] This embodiment provides another method for handling data read requests. Figure 4 This is a flowchart of another data read request processing method according to an embodiment of this application, such as... Figure 4 As shown, the process includes the following steps:

[0045] Step S401: Upon receiving a data read request from the host, determine the data to be read based on the data read request.

[0046] For details on how to implement this step, please refer to [link / reference]. Figure 1 Step S201 of the illustrated embodiment will not be described again here.

[0047] Step S402: Determine the address information of the data to be read, and compare the address information with a preset variable to obtain the comparison result. The preset variable is generated during the process of writing data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer.

[0048] Specifically, the preset variables include a first sub-variable and a second sub-variable. The above step S402, "comparing the address information with the preset variables to obtain the comparison result", includes steps S4021 to S4023.

[0049] Step S4021: Determine the target data block identifier and the first physical block address corresponding to the data to be read based on the address information.

[0050] Step S4022: If the target data block identifier matches the first sub-variable successfully, and the first physical block address matches the second sub-variable successfully, the first comparison result is obtained.

[0051] Step S4023: If the target data block identifier fails to match the first sub-variable, or the first physical block address fails to match the second sub-variable, a second comparison result is obtained.

[0052] Specifically, according to the page-to-buffer mapping technique, during garbage collection, only one superblock (SPB) is moving data within each LUN. A superblock represents a set of physical data blocks with the same block number across several LUNs. Based on this, this embodiment generates a first sub-variable and a second sub-variable using the page-to-buffer mapping technique. These two variables are generated during the process of writing data into a first preset buffer. In the data read request processing flow, these two variables indicate whether the PBA corresponding to the LBA has been written into the first preset buffer, such as the garbage collection buffer. The first and second sub-variables are global variables stored in dynamic random access memory.

[0053] The first sub-variable, for example: `uint16_t g_gc_running_spb[lun]`, represents the superblock number currently undergoing garbage collection and relocation in the logical unit. This first sub-variable is updated when a superblock switch occurs. Furthermore, the conversion relationship between the superblock number and the data block number (block_idx) is: SPB_ID = block_idx / plane_num, as shown below. Figure 5 As shown, SPB0 actually contains four blocks: block0–block3. Figure 5 Logical partitions 0, 1, 2, and 3 can perform read operations in parallel. When garbage collection is performed inside the SSD, these data will be read into the garbage collection buffer at the same time. The superblock number is calculated when the SSD is powered on and initialized, and can be directly called afterward.

[0054] The second sub-variable, for example: `uint16_t g_P2B[lun][plane][page_num][data_frame]`, represents a specific data frame in the Nand flash memory (e.g., ...). Figure 5 The data frame (e.g., data frame 0, data frame 1, etc.) is read into the address in the buffer. The second sub-variable is updated when data is read from the Nand flash memory into the garbage collection buffer. If the second sub-variable is invalid, it means that the data has not been read.

[0055] Combination Figure 5This explains the principle of determining whether the data to be read is in the first preset buffer based on the first and second sub-variables. If the solid-state drive is currently undergoing garbage collection, and the first sub-variable g_gc_running_spb[0]=0, and the second sub-variable g_P2B[0][0][0][0] = buff0, it means that the superblock identifier SPB_ID of the superblock undergoing garbage collection on lun0 is 0, and lun0-plane0-page0-df0 has been read into the buff0 position of the first preset buffer.

[0056] At this point, if the host intends to read data with lba = 100, i.e., the data to be read has lba = 100, the solid-state drive will check the logical-to-physical address mapping table to find the corresponding pba. If the address of the data to be read is determined to be lun0-SPB1-plane0-page0-df0 based on the pba, then SPB1 does not match the first sub-variable g_gc_running_spb[0], and it is determined that the data to be read is not in the first preset buffer. If the address of the data to be read is determined to be lun0-SPB0-plane0-page0-df0 based on the pba, then SPB0 matches the first sub-variable g_gc_running_spb[0], and lun0-SPB0-plane0-page0-df0 matches the second sub-variable g_P2B[0][0][0][0], it is determined that the data to be read has been read into the first preset buffer.

[0057] The target data block identifier and the address of the first physical block corresponding to the data to be read are determined based on the address information. The target data block identifier is, for example, the superblock number. The first physical block address is, for example, information such as the LUN, plane, page, and DF corresponding to the data to be read.

[0058] If the target data block identifier matches the first sub-variable successfully, for example: the target data block identifier is SPB0, and the first sub-variable is g_gc_running_spb[0], the target data block identifier matches the first sub-variable successfully. If the first physical block address matches the second sub-variable successfully, for example: the first physical block address is lun0-plane0-page0-df0, and the second sub-variable is g_P2B[0][0][0][0], the first physical block address matches the second sub-variable successfully. At this time, the first comparison result is: the address information is the same as the preset variable, and the data to be read is in the first preset buffer.

[0059] If the target data block identifier fails to match the first sub-variable, for example: the target data block identifier is SPB1, and the first sub-variable is g_gc_running_spb[0], the target data block identifier fails to match the first sub-variable. If the first physical block address fails to match the second sub-variable, for example: the first physical block address is lun1-plane1-page0-df0, and the second sub-variable is g_P2B[0][0][0][0], the first physical block address fails to match the second sub-variable. In this case, the second comparison result is: the address information is different from the preset variable, and the data to be read is not in the first preset buffer.

[0060] In this embodiment, the operation of "comparing the address information with the preset variable and obtaining the comparison result" can be dynamically loaded and unloaded in a modular manner during actual operation without affecting the execution of the garbage collection business.

[0061] In this embodiment, a first sub-variable and a second sub-variable are designed. By using the first sub-variable and the second sub-variable, it is possible to determine whether the data to be read has been written into the first preset buffer without modifying the logical-to-physical address mapping table, and then directly return the data to be read in the first preset buffer to the host, thereby improving the random read performance of the solid-state drive.

[0062] Step S403: If the comparison result determines that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host.

[0063] Specifically, step S403 includes steps S4031 to S4034.

[0064] Step S4031: If the data to be read is determined to be in the first preset buffer based on the comparison result, the preset parameter is increased by a preset step size to obtain the first parameter, wherein the preset parameter is used to determine whether to release the first preset buffer.

[0065] Step S4032: Send the data to be read in the first preset buffer to the host.

[0066] Step S4033: If it is determined that the data to be read still exists in the first preset buffer, the first parameter is subtracted from the preset step size to obtain the second parameter.

[0067] Step S4034: If the second parameter is equal to the preset threshold, release the first preset buffer.

[0068] Specifically, the first preset buffer is, for example, a garbage collection buffer. Since the first preset buffer is used not only by garbage collection operations but also during the processing of data read requests sent by the host, to prevent errors in processing data read requests caused by the first preset buffer being released during the processing of data read requests sent by the host, this embodiment adds a garbage collection buffer reference counting mechanism. Using 4KB units as the unit, a refCount attribute is added to the first preset buffer, with refCount as the preset parameter. The method for modifying refCount is as follows... Figure 6 As shown, when a garbage collection operation first requests a buffer, or when a data read request hits the first preset buffer, `refCount++` is executed, which increments the preset parameter by 1. Other values ​​can also be added to `refCount` as needed. When data from the first preset buffer is written to the Nand flash memory, or when a data read request is completed, `refCount--` is executed, which decrements the preset parameter by 1. Other values ​​can also be subtracted from `refCount` as needed, ensuring that the incremented and decremented values ​​are the same. When `refCount` equals 0, the garbage collection buffer is released.

[0069] Preset parameters include, for example, `refCount`, and preset step size, for example, 1. If the comparison result determines that the data to be read is in the first preset buffer, meaning the data read request hits the first preset buffer, the preset parameter is increased by the preset step size to obtain the first parameter, for example, `refCount + 1`. The above process is as follows: Figure 3 As shown, it determines whether the data is stored in the garbage collection buffer. If the data is found to be in the GC buffer, refCount++ is executed. The data to be read from the first preset buffer is then sent to the host.

[0070] After the data to be read in the first preset buffer is sent to the host, the data to be read may still be stored in the first preset buffer or in other buffers. In order to determine whether the first preset buffer needs to be released, it is necessary to determine whether the data to be read is still stored in the first preset buffer. If the data to be read is still in the first preset buffer, it is then determined whether the preset parameters can be released according to the preset parameters. If the data to be read is not in the first preset buffer, the first preset buffer is released directly.

[0071] If it is determined that the data to be read still exists in the first preset buffer, the first parameter is subtracted from the preset step size to obtain the second parameter. For example, the second parameter is refCount + 1 - 1 = refCount. The preset threshold is, for example, 0 or other values ​​that meet actual needs. If the second parameter equals the preset threshold, for example, refCount = 0, it is determined that the garbage collection operation and the process of handling data read requests sent by the host no longer require the first preset buffer. Therefore, the first preset buffer is released.

[0072] The above process is as follows Figure 3 As shown, determine whether the data is stored in the first preset buffer; if the data is not stored in the first preset buffer, release the first preset buffer; if the data is stored in the first preset buffer, decrement refCount by 1 and determine whether refCount is 0 after decrementing by 1. If it is 0, release the first preset buffer; otherwise, end the process.

[0073] In this embodiment, by setting preset parameters and the method of modifying preset parameters, the situation where the first preset buffer is released during the data read request sent by the processing host is prevented, thereby avoiding errors in processing data read requests or garbage collection processes.

[0074] Step S404: If the comparison result determines that the data to be read is not in the first preset buffer, request the second preset buffer.

[0075] Step S405: Determine the data to be read in the preset memory according to the address information, and write the data to be read in the preset memory into the second preset buffer.

[0076] Step S406: Send the data to be read in the second preset buffer to the host.

[0077] Specifically, if the comparison results determine that the data to be read is not in the first preset buffer, the data management module needs to retrieve the data to be read from the Nand flash memory and return it to the host. For example, if the address information is inconsistent with the preset variable, it is determined that the data to be read is not in the first preset buffer.

[0078] The data management module requests buffers as the second preset buffer in 4Kb units. After successfully requesting the second preset buffer, the data management module generates a read request based on the address information of the data to be read and sends the read request to the Flash Channel Controller (FCC). The Flash Channel Controller is a set of independent modules used to directly operate the Nand flash memory. Other modules need to go through the Flash Channel Controller to read, write, and erase data.

[0079] The preset memory is, for example, Nand flash memory. After receiving the read request, the flash channel controller determines the data to be read in the preset memory based on the address information in the read request. The flash channel controller then sends a read request response message (readcpl) to the data management module, containing the data to be read from the preset memory. Upon receiving the read request response message, the data management module writes the data to be read into a second preset buffer, and finally sends the data in the second preset buffer to the host.

[0080] like Figure 3 As shown, it determines whether the data is stored in the garbage collection buffer. If it is determined that the data is not in the buffer, it first requests a second preset buffer, then moves the data from the Nand flash memory to the second preset buffer, and then moves the data from the second preset buffer to the host.

[0081] As an optional embodiment, the preset variables include a first sub-variable and a second sub-variable, and the data read request processing method further includes steps A1 to A5.

[0082] Step A1: Upon receiving a garbage collection request, determine the target data block identifier based on the garbage collection request, and set the first sub-variable based on the target data block identifier.

[0083] Step A2: Request the first preset buffer and determine the first target data block according to the target data block identifier.

[0084] Step A3: Write the data in the first target data block into the first preset buffer.

[0085] Step A4: Obtain a preset number of data frames based on the data in the first preset buffer.

[0086] Step A5: Set the second sub-variable according to the data frame and write the data frame into the second target data block.

[0087] Specifically, the first sub-variable is, for example: uint16_t g_gc_running_spb[lun]. The second sub-variable is, for example: uint16_t g_P2B[lun][plane][page_num][data_frame].

[0088] This embodiment is executed jointly by the write manager (WM), the reclaim block manager (RBM), and the flash channel controller. The write manager receives garbage collection data from the RBM, arranges it in a certain order, and then notifies the flash channel controller to write it into the Nand flash memory. The reclaim block manager moves specified superblock data to new data blocks.

[0089] Combination Figure 7 This embodiment will be described below. The write controller initiates a garbage collection request, which carries the target data block. The first target data block is, for example, the superblock to be reclaimed. Upon receiving the garbage collection request, the reclaim block manager determines the target data block identifier based on the request, for example, SPB_ID. All logical units within the same stripe are updated, and the first sub-variable is set according to the target data block identifier, for example, g_gc_running_spb[lun] = SPB_ID.

[0090] The garbage collection manager allocates a garbage collection buffer as the first preset buffer. For example, starting from page 0 of the first target data block, it processes all LUNs in a round-robin fashion, that is, it first reads page 0 of all LUNs, then reads page 1 of all LUNs, and so on, which can improve the concurrency of read operations. Within each LUN, a buffer of size 4 planes is allocated to obtain the first preset buffer.

[0091] After successfully allocating the first preset buffer, the reclaim block manager determines the first target data block based on the target data block identifier, initiates a read request (read req) for the first target data block to the flash channel controller, and uses the flash channel controller to write the data in the first target data block into the first preset buffer. The above process is as follows: Figure 7 As shown, the RBM executes: loop from page0 to pageMax; loop from lun0 to lunMax; assign a value to g_gc_running_spb[lun]; allocate a GC buffer; read the page data on the current lun into the buffer; determine whether to read lunMax and pageMax, i.e., whether to traverse all luns and pages. If satisfied, send a garbage collection request response to the garbage collection manager. The RBM sends a read request to the FCC, and the FCC returns a read response to the RBM, confirming that the data in the first target data block has been written to the first preset buffer.

[0092] Upon receiving a read request response from the flash channel controller, the reclaim block manager determines that the data of the first target data block has been written to the first preset buffer. Based on the data in the first preset buffer, the reclaim block manager obtains a preset number of data frames, for example, polling all planes within the same LUN and processing each data frame individually. A second sub-variable is set according to the data frame; for example, if the data address is determined to be LUN0-SPB0-plane0-page0-df0, the second sub-variable is set to g_P2B[0][0][0][0] = buff0. The data frame is then sent to the write controller, which writes the data frame to the second target data block. The above process is as follows: Figure 7 As shown, the loop runs from df0 to df3; it updates g_P2B[lun][plane][page_num][data_frame]; and it checks df3 to determine if the last data frame has been read. The second target data block is, for example, a data block other than the first target data block, such as a new target superblock. The preset number indicates multiple blocks; no specific limit is specified here.

[0093] In this embodiment, a first sub-variable and a second sub-variable are designed and incorporated into the garbage collection process without affecting it. By using the first and second sub-variables, it is possible to determine whether the data to be read has been written to the first preset buffer without modifying the logical-to-physical address mapping table, and then directly return the data to be read from the first preset buffer to the host, thereby improving the random read performance of the solid-state drive.

[0094] As an optional embodiment, after step A5 "writing the data frame into the second target data block" described above, steps B1 and B2 are also included.

[0095] Step B1: Subtract the preset step size from the third parameter to obtain the fourth parameter. The third parameter is generated by adding the preset step size to the preset parameter after setting the second sub-variable according to the data frame.

[0096] Step B2: If the fourth parameter is equal to the preset threshold, release the first preset buffer.

[0097] Specifically, the preset parameter is, for example, refCount, and the preset step size is, for example, 1. After setting the second sub-variable based on the data frame, the reclaimed block manager increments the preset parameter by the preset step size to obtain a third parameter, indicating that a service is currently using the first preset buffer. For example, the third parameter is refCount + 1. The above process is as follows: Figure 7As shown, update the second sub-variable g_P2B[lun][plane][page_num][data_frame], and increment refCount by 1 to add the preset parameter.

[0098] The preset threshold is, for example, 0 or other values ​​that meet actual needs. After receiving the write completion command from the flash channel controller, the write controller determines that the data frame has been written to the second target data block. The write controller subtracts the preset step size from the third parameter to obtain the fourth parameter, for example, the fourth parameter is refCount + 1 - 1 = refCount. After receiving the write completion command from the flash channel controller, the write controller decrements the refCount of the GC buffer for each dataframe. When refCount is 0, the GC buffer is released.

[0099] The write controller checks if the fourth parameter equals a preset threshold. If the fourth parameter equals the preset threshold, it determines that neither the garbage collection operation nor the process of handling data read requests sent by the host requires the first preset buffer; therefore, the first preset buffer is released. The above process is as follows: Figure 7 As shown, it determines whether the preset parameter minus 1 equals 0. If it does, the garbage collection buffer is released.

[0100] In this embodiment, by setting preset parameters and the method of modifying preset parameters, the situation where the first preset buffer is released during the data read request sent by the processing host is prevented, thereby avoiding errors in processing data read requests or garbage collection processes.

[0101] As an optional embodiment, step A5 "setting the second sub-variable according to the data frame" includes steps C1 to C4.

[0102] Step C1: Obtain the logical block address corresponding to the data frame;

[0103] Step C2: Obtain the second physical block address corresponding to the data frame from the metadata based on the logical block address;

[0104] Step C3: Obtain the third physical block address corresponding to the data frame from the logical-to-physical mapping table based on the logical block address;

[0105] Step C4: Take the data frame with the same second physical block address and third physical block address as the target data frame, and set the second sub-variable according to the target data frame.

[0106] Specifically, because the host is constantly writing data, previously written data may become invalid. For example, if the same LBA is written twice, the data written the first time is invalid, but the data is still on the Nand flash memory; it's just that the data corresponding to the current LBA is moved to a new PBA in the logical-to-physical address mapping table. Therefore, after obtaining a preset number of data frames, the reclaimed block manager needs to determine whether the LBA corresponding to the data frame is valid. The reclaimed block manager obtains the logical block address (LBA) corresponding to each data frame.

[0107] The metadata (Meta) stores all LBAs and their corresponding PBAs; the PBA in the metadata is denoted as `old_pba`. Based on the logical block address, the `old_pba` corresponding to the data frame is retrieved from the metadata, and this `old_pba` is used as the second physical block address. The current logical-to-physical address mapping table is read, and the PBA recorded in the table is denoted as `new_pba`. Based on the logical block address, the `new_pba` corresponding to the data frame is retrieved from the logical-to-physical address mapping table, and this `new_pba` is used as the third physical block address.

[0108] If `old_pba` equals `new_pba`, it means the data corresponding to the data frame is valid; otherwise, it is invalid. Therefore, the reclaimed block manager uses data frames with the same second and third physical block addresses as target data frames, and the data corresponding to the target data frames is valid. The second sub-variable is then set based on the target data frame.

[0109] In this embodiment, the second physical block address and the third physical block address corresponding to the data frame are obtained. The second sub-variable is set only for data frames whose second physical block address and third physical block address are the same, thereby filtering out invalid data frames and ensuring that each second sub-variable is valid.

[0110] As an optional embodiment, step A5 "writing the data frame into the second target data block" includes steps D1 to D3.

[0111] Step D1: Assemble the data frame into the first data to be written according to the first preset format.

[0112] Step D2: Assemble the first data to be written into the second data to be written according to the second preset format.

[0113] Step D3: Write the second data to be written into the second target data block.

[0114] Specifically, the first preset format is, for example, the CCB format. The reclaimed block manager assembles the data frame into the first data to be written according to the first preset format. For example, the reclaimed block manager assembles the data frame into the CCB format to obtain the first data to be written, and sends the first data to be written to the write controller.

[0115] The second preset format is, for example, the PO format. After receiving the first data to be written, the write controller assembles the first data to be written into the second data to be written according to the second preset format. For example, the write controller assembles CCBs into PO format. Taking a 4-plane configuration as an example, 4 CCBs constitute one PO, and each plane has one PO.

[0116] The write controller sends a write command to send the second data to be written to the flash channel controller, which then saves the second data to be written to the second target data block, such as a new target superblock.

[0117] After the flash channel controller saves the second data to be written to the second target data block, it sends a write response message to the write controller. The above process is as follows: Figure 7 As shown, the RBM assembles the CCB (first data to be written) and sends it to the WM; the WM assembles the first data to be written into the PO (second data to be written), saves it to the flash memory, sends a write request to the FCC, and after the FCC completes the write, it returns a write response message to the WM.

[0118] As an optional embodiment, the above step S4021 "determines the target data block identifier and the first physical block address corresponding to the data to be read based on the address information" includes steps E1 to E4.

[0119] Step E1: Determine the third target data block containing the data to be read based on the address information;

[0120] Step E2: Use the identifier of the third target data block as the target data block identifier;

[0121] Step E3: Obtain the logical unit, logical partition, data page, and data frame corresponding to the data to be read from the address information;

[0122] Step E4: Determine the address of the first physical block based on the logical unit, logical partition, data page, and data frame.

[0123] Specifically, according to the page-to-buffer mapping technique, during garbage collection, only one superblock is moving data within each LUN. The superblock represents a set of physical data blocks with the same block number in several LUNs.

[0124] The address information is determined based on the PBA address of the data to be read. The PBA address of the data to be read can also be determined from the address information. The data block corresponding to the data to be read is determined based on the PBA address, and the superblock containing the data block is used as the third target data block. The identifier of the third target data block is used as the target data block identifier, for example, the SPB_ID of the third target data block.

[0125] The address information includes logical units, logical partitions, data pages, and data frames. Based on these information, the address of the first physical block is determined. For example, if the logical unit is lun0, the logical partition is plane0, the data page is page0, and the data frame is df0, the address of the first physical block is determined to be lun0-plane0-page0-df0.

[0126] In this embodiment of the application, the target data block identifier and the first physical block address corresponding to the data to be read are determined according to the address information. The target data block identifier and the first physical block address can be used to accurately determine whether the data to be read has been written to the first preset buffer.

[0127] The data read request processing method provided in this embodiment determines the data to be read based on the data read request; compares the address information of the data to be read with a preset variable to determine whether the data to be read is stored in a first preset buffer; if the comparison is successful, the data to be read in the first preset buffer is directly sent to the host. This method can directly return the valid data cached in the first preset buffer to the host without performing additional operations on the logical-to-physical address mapping table, thus improving the random read performance of the solid-state drive under steady-state conditions. It solves the problem of wasting CPU resources by repeatedly reading Nand flash memory data when processing host read requests.

[0128] As an alternative embodiment, when the buffer capacity in the solid-state drive (SSD) is limited, it is necessary to reduce the memory requirements for multiple QLC programming operations in the memory-constrained SSD. Step D3, "Write the second data to be written to the second target data block," includes steps F1 to F5.

[0129] Step F1: Reserve a portion of SLC (Single-Level Cell) physical blocks inside the solid-state drive. Whenever the flash channel controller writes the second piece of data to be written, it is always written to the SLC physical blocks first.

[0130] Step F2: Reserve a small memory area inside the solid-state drive as a WL Buffer (Wordline Buffer).

[0131] Step F3: After writing the second data to be written to the SLC physical block, the second data to be written is read from the SLC physical block into the WL Buffer and transferred to the QLC physical block of the corresponding DIE. DIE represents a unit that can be operated independently and concurrently.

[0132] Step F4: Release the WL Buffer and initiate QLC programming for the corresponding DIE.

[0133] In step F5, the same process is performed on the other DIEs in sequence using the WL Buffer, and the QLC programming of all DIEs is waited for to be completed.

[0134] Specifically, firstly, a portion of SLC physical blocks are reserved within the SSD. When the SLC physical blocks are exhausted, a new set of blank SLC physical blocks is allocated. When the flash channel controller writes the second piece of data to be written, it is always written to the SLC physical blocks first. In addition, a small memory area, the WL Buffer, is reserved within the SSD, which contains a single DIE concurrent programming unit, such as one WL, which is four pages.

[0135] After the second piece of data to be written is written to the SLC physical block, it is read from the SLC physical block into the WL Buffer and transferred to the QLC physical block of the corresponding DIE. The WL Buffer is then released, and programming of the QLC physical block of the corresponding DIE is initiated. Using the same WL Buffer, the same process is performed on other DIEs in sequence. After the QLC programming is completed, the above process is repeated. Once all the data in the SLC physical block has been moved to the QLC physical block, the SLC physical block can be released to store subsequent data written by the flash channel controller.

[0136] In this scheme, a single WL Buffer is used for time-division multiplexing across multiple DIEs: it stores data read from the SLC and then transfers it to the QLC physical block. The corresponding DIE can then release the buffer, and QLC programming is performed internally within the DIE. The released WL Buffer can then be used as a data transfer intermediary for the next DIE to initiate QLC programming. It's important to note that QLC programming time is significantly longer than SLC reads, and the time required to transfer data from NAND to the WL Buffer or vice versa. Therefore, even with limited WL Buffer time-division multiplexing, concurrent programming of QLC physical blocks across different DIEs can be guaranteed, thus ensuring performance.

[0137] In this embodiment, the data migration rules and buffer release are optimized, which enables data writing to be completed with less memory, greatly reducing the memory requirements for multiple QLC programming in memory-constrained solid-state drives, thereby reducing costs.

[0138] This embodiment also provides a data read request processing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0139] This embodiment provides a data read request processing device, such as... Figure 8 As shown, it includes:

[0140] The data determination module 801 is used to determine the data to be read based on the data read request when a data read request is received from the host.

[0141] The information comparison module 802 is used to determine the address information of the data to be read and compare the address information with a preset variable to obtain the comparison result. The preset variable is generated during the process of writing data into the first preset buffer and is used to determine the data stored in the first preset buffer.

[0142] The data sending module 803 is used to send the data to be read in the first preset buffer to the host if it is determined from the comparison result that the data to be read is in the first preset buffer.

[0143] In some alternative embodiments, the device further includes:

[0144] The first application module is used to apply for a second preset buffer if it is determined from the comparison result that the data to be read is not in the first preset buffer.

[0145] The first writing module is used to determine the data to be read in the preset memory according to the address information, and write the data to be read in the preset memory into the second preset buffer.

[0146] The sending module is used to send the data to be read from the second preset buffer to the host.

[0147] In some optional implementations, the preset variables include a first sub-variable and a second sub-variable, and the information comparison module 802 includes:

[0148] The determining unit is used to determine the target data block identifier and the first physical block address corresponding to the data to be read based on the address information.

[0149] The first judgment unit is used to obtain the first comparison result if the target data block identifier matches the first sub-variable and the first physical block address matches the second sub-variable.

[0150] The second judgment unit is used to obtain a second comparison result if the target data block identifier fails to match the first sub-variable, or if the first physical block address fails to match the second sub-variable.

[0151] In some alternative implementations, the data transmission module 803 includes:

[0152] The first obtaining unit is used to increase the preset parameter by a preset step size to obtain the first parameter if it is determined from the comparison result that the data to be read is in the first preset buffer. The preset parameter is used to determine whether to release the first preset buffer.

[0153] The sending unit is used to send the data to be read from the first preset buffer to the host.

[0154] The second obtaining unit is used to subtract a preset step size from the first parameter to obtain the second parameter when it is determined that the data to be read still exists in the first preset buffer.

[0155] The release unit is used to release the first preset buffer when the second parameter is equal to the preset threshold.

[0156] In some optional implementations, the preset variable includes a first sub-variable and a second sub-variable, and the device further includes:

[0157] The configuration module is used to determine the target data block identifier based on the garbage collection request when a garbage collection request is received, and to set the first sub-variable based on the target data block identifier;

[0158] The second application module is used to apply for the first preset buffer and determine the first target data block according to the target data block identifier;

[0159] The second writing module is used to write the data in the first target data block into the first preset buffer;

[0160] The first obtaining module is used to obtain a preset number of data frames based on the data in the first preset buffer;

[0161] The third write module is used to set the second sub-variable according to the data frame and write the data frame to the second target data block.

[0162] In some alternative embodiments, the device further includes:

[0163] The second obtaining module is used to subtract the preset step size from the third parameter to obtain the fourth parameter. The third parameter is generated by adding the preset step size to the preset parameter after setting the second sub-variable according to the data frame.

[0164] The release module is used to release the first preset buffer when the fourth parameter is equal to the preset threshold.

[0165] In some alternative implementations, the third write module includes:

[0166] The first acquisition unit is used to acquire the logical block address corresponding to the data frame;

[0167] The second acquisition unit is used to obtain the second physical block address corresponding to the data frame from the metadata based on the logical block address;

[0168] The third acquisition unit is used to obtain the third physical block address corresponding to the data frame from the logical-to-physical mapping table according to the logical block address;

[0169] The setting unit is used to take the data frame with the same second physical block address and third physical block address as the target data frame, and set the second sub-variable according to the target data frame.

[0170] In some alternative implementations, the third write module includes:

[0171] The first assembly unit is used to assemble the data frame into the first data to be written according to the first preset format;

[0172] The second assembly unit is used to assemble the first data to be written into the second data to be written according to the second preset format;

[0173] The writing unit is used to write the second data to be written into the second target data block.

[0174] In some alternative implementations, the determining unit includes:

[0175] The first determination submodule is used to determine the third target data block containing the data to be read based on the address information.

[0176] The configuration submodule is used to use the identifier of the third target data block as the target data block identifier;

[0177] The acquisition submodule is used to obtain the logical unit, logical partition, data page, and data frame corresponding to the data to be read from the address information;

[0178] The second determination submodule is used to determine the address of the first physical block based on the logical unit, logical partition, data page, and data frame.

[0179] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0180] In this embodiment, the data read request processing device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0181] This application also provides a computer device having the above-described features. Figure 8 The data read request processing device shown.

[0182] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0183] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include an integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0184] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0185] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0186] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0187] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0188] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0189] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0190] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by this application.

Claims

1. A data read request processing method, characterized in that, The method includes: Upon receiving a data read request from the host, the data to be read is determined based on the data read request; The address information of the data to be read is determined, and the address information is compared with a preset variable to obtain a comparison result. The preset variable is generated during the process of writing data into the first preset buffer, and the preset variable is used to determine the data stored in the first preset buffer. If the comparison result determines that the data to be read is in the first preset buffer, the data to be read in the first preset buffer is sent to the host. The step of sending the data to be read in the first preset buffer to the host if the comparison result determines that the data to be read is in the first preset buffer includes: if the comparison result determines that the data to be read is in the first preset buffer, increasing a preset parameter by a preset step size to obtain a first parameter, wherein the preset parameter is used to determine whether to release the first preset buffer; sending the data to be read in the first preset buffer to the host; if it is determined that the data to be read still exists in the first preset buffer, subtracting the preset step size from the first parameter to obtain a second parameter; and releasing the first preset buffer if the second parameter is equal to a preset threshold.

2. The method according to claim 1, characterized in that, After comparing the address information with a preset variable to obtain a comparison result, the method further includes: If the comparison result determines that the data to be read is not in the first preset buffer, then request a second preset buffer. Based on the address information, determine the data to be read in the preset memory, and write the data to be read in the preset memory into the second preset buffer; The data to be read in the second preset buffer is sent to the host.

3. The method according to claim 1 or 2, characterized in that, The preset variables include a first sub-variable and a second sub-variable. The step of comparing the address information with the preset variables to obtain a comparison result includes: The target data block identifier and the first physical block address corresponding to the data to be read are determined based on the address information. If the target data block identifier matches the first sub-variable, and the first physical block address matches the second sub-variable, a first comparison result is obtained; If the target data block identifier fails to match the first sub-variable, or if the first physical block address fails to match the second sub-variable, a second comparison result is obtained.

4. The method according to claim 1, characterized in that, The preset variables include a first sub-variable and a second sub-variable, and the method further includes: Upon receiving a garbage collection request, the target data block identifier is determined based on the garbage collection request, and the first sub-variable is set based on the target data block identifier; Request the first preset buffer and determine the first target data block according to the target data block identifier; Write the data in the first target data block into the first preset buffer; Based on the data in the first preset buffer, a preset number of data frames are obtained; The second sub-variable is set according to the data frame, and the data frame is written into the second target data block.

5. The method according to claim 4, characterized in that, After writing the data frame into the second target data block, the method further includes: Subtract the preset step size from the third parameter to obtain the fourth parameter, wherein the third parameter is generated by adding the preset step size to the preset parameter after setting the second sub-variable according to the data frame; If the fourth parameter is equal to a preset threshold, the first preset buffer is released.

6. The method according to claim 4, characterized in that, Setting the second sub-variable according to the data frame includes: Obtain the logical block address corresponding to the data frame; The second physical block address corresponding to the data frame is obtained from the metadata based on the logical block address. The third physical block address corresponding to the data frame is obtained from the logical-to-physical mapping table based on the logical block address. The data frame whose second physical block address is the same as the third physical block address is taken as the target data frame, and the second sub-variable is set according to the target data frame.

7. The method according to claim 4 or 5, characterized in that, The step of writing the data frame into the second target data block includes: The data frame is assembled into first data to be written according to a first preset format; The first data to be written is assembled into the second data to be written according to the second preset format; Write the second data to be written into the second target data block.

8. The method according to claim 3, characterized in that, The step of determining the target data block identifier and the first physical block address corresponding to the data to be read based on the address information includes: Based on the address information, a third target data block containing the data to be read is determined; Use the identifier of the third target data block as the target data block identifier; The logical unit, logical partition, data page, and data frame corresponding to the data to be read are obtained from the address information. The address of the first physical block is determined based on the logical unit, the logical partition, the data page, and the data frame.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the data read request processing method according to any one of claims 1 to 8.

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