Cross-chip register access method and device based on target protocol and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to a cross-chip register access method and device based on a target protocol and a storage medium, and the method comprises the steps: configuring a group of on-chip interfaces on an adapter layer, and building a mapping relation between a plurality of pins of the on-chip interfaces and a plurality of fields of the target protocol on the adapter layer; when a cross-core register access transaction is sent, the upper layer configures an on-chip interface of the adapter layer; the adapter layer analyzes the on-chip interface to obtain configuration information, maps the configuration information into a field of a sideband mailbox transaction according to a first mapping relation, and initiates a sideband request transaction according to the field of the sideband mailbox transaction through a sideband processing module of the adapter layer; and when a sideband completion transaction is received, the adapter layer analyzes the field in the sideband completion transaction and maps the field in the sideband completion transaction to the corresponding pin of the on-chip interface according to the second mapping relation, so that the access time is shortened, and the communication delay and resource occupation are reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a cross-chip register access method, device and storage medium based on a target protocol. Background Art

[0002] UCIe (Universal Chiplet Interconnect Express) is an in-package interconnect standard designed specifically for chiplet technology. The UCIe protocol introduces an innovative dual-path communication mechanism within a multi-chiplet collaborative architecture within a package. Its core architecture consists of a mainband and sideband. The mainband handles high-performance data transmission, while the sideband serves as a secondary channel dedicated to control information exchange. To address cross-chiplet register access requirements, UCIe implements a mailbox mechanism over the sideband link, enabling indirect access to remote chips. However, the access steps based on the mailbox mechanism are relatively complex. Taking the write operation as an example, the upper layer of the transmitting chip performs the following configuration through the sideband signal of the FDI (Flit-Aware Die-to-Die Interface): the information to be accessed is configured in the mailbox index register (Sideband Mailbox Index) of the adapter layer (Die-to-Die Adapter), the write data to be accessed is configured in the mailbox data register of the adapter layer, the write / read trigger field (Write / Read trigger) in the sideband mailbox control register (Sideband Mailbox Control) is set to 1, and the sideband mailbox control register is continuously polled until the value of the write / read trigger field is 0, indicating that the mailbox access is completed; the adapter layer initiates a mailbox access request transaction to the physical layer; the physical layer sends it to the receiving chip via the UCIe sideband link; after processing at the receiving end, it returns the mailbox completion transaction to the physical layer of the transmitting chip via the UCIe sideband link, and the physical layer returns it to the adapter layer. The adapter layer updates the write / read trigger field of the mailbox control register to 0 and updates the sideband mailbox status register (Sideband Mailbox Status Register). MailboxStatus); The higher-level chip on the transmitting end reads the write / read trigger field value of the sideband mailbox control register via the sideband signal of the FDI interface and finds it is 0, indicating that the mailbox operation was successful. Therefore, for a complete sideband access transaction, the higher-level chip must access at least three adapter layer registers via sideband signals: the mailbox index register, the mailbox data register, and the sideband mailbox control register. A complete sideband access includes the sending and receiving of sideband request and completion transactions. Due to the low clock frequency of the sideband link, each sideband access takes a long time. Before the mailbox operation is complete, the protocol layer or software must continuously poll the mailbox control register via the FDI sideband interface, consuming significant resources and time.

[0003] Therefore, there is an urgent need for a cross-chip register access method that can shorten access time and reduce resource usage. Summary of the Invention

[0004] In response to the above technical problems, the present invention adopts a technical solution: a cross-chip register access method based on a target protocol, the method comprising the following steps: S100: Acquire a target protocol, where the target protocol includes a high layer and an adapter layer.

[0005] S200 , configuring a group of on-chip interfaces at the adapter layer, wherein the on-chip interfaces include a plurality of pins; and the adapter layer interacts with the higher layer via the on-chip interfaces.

[0006] S300, establish a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol at the adapter layer, the mapping relationship includes a first mapping relationship in the sending direction and a second mapping relationship in the receiving direction, the first mapping relationship is used to map the pin signals of the on-chip interface that complies with the on-chip protocol to the fields of the sideband request transaction that complies with the target protocol, and the second mapping relationship is used to map the fields in the sideband completion transaction that complies with the target protocol to the corresponding pins of the on-chip interface.

[0007] S400, when sending a cross-chip register access transaction, the high-level layer configures the on-chip interface of the adapter layer; the adapter layer parses the on-chip interface to obtain corresponding configuration information, maps the configuration information to the field of the sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction according to the field of the sideband mailbox transaction through the sideband processing module of the adapter layer.

[0008] S500, when receiving a sideband completion transaction, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to corresponding pins of the on-chip interface according to the second mapping relationship.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, which stores at least one instruction or at least one program, and the at least one instruction or at least one program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device including a processor and the above-mentioned non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects: The present invention provides a cross-chip register access method based on the target protocol, which establishes a mapping relationship between the on-chip interface and the target protocol at the adapter layer by multiplexing the on-chip interface. The on-chip interface is directly configured by the high-level layer. The adapter layer maps the signal of the on-chip interface to the field of the sideband transaction that complies with the target protocol, and generates a sideband transaction, thereby realizing sideband transaction interaction. By directly constructing a cross-chip communication path through high-level configuration, the configuration of the mailbox register is bypassed, and the dependence on the dedicated sideband mailbox mechanism is eliminated. No additional hardware is required, while maintaining full compatibility with the UCIe protocol. A single register access transaction can complete cross-chip data interaction, greatly shortening the access time, and significantly reducing communication delays and system resource usage. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 A flow chart of a cross-chip register access method based on UCIe is provided in an embodiment of the present invention; Figure 2 The flowchart of the entire access process in the traditional method is described by taking the target protocol as the UCIe protocol and a read request as an example; Figure 3 The flowchart of the entire access process in the method provided by the present invention is described by taking the target protocol as the UCIe protocol and a read request as an example; Figure 4 The following are the specific timing diagrams of the read and write operations on the on-chip interface, taking the APB interface as an example. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meanings as commonly understood by those skilled in the art.

[0016] See also Figure 1 , which shows a flow chart of a cross-chiplet register access method based on UCIe, the method comprising the following steps: S100: Acquire a target protocol, where the target protocol includes a high layer and an adapter layer.

[0017] In one embodiment, the target protocol is the UCIe protocol. Other types of inter-chiplet protocols with mailbox mechanisms fall within the scope of protection of the present invention.

[0018] The target protocol also includes a physical layer, and the adapter layer is located between the high layer and the physical layer.

[0019] In one embodiment, when the target protocol is the UCIe protocol, the UCIe protocol includes a high-level layer, an adapter layer, and a physical layer. The high-level layer, also known as the protocol layer, defines how to use underlying services to implement specific application requirements. It includes a transaction layer, which is responsible for processing high-level operations such as requests and responses and supports different protocols and data formats to facilitate interoperability in various application scenarios. The adapter layer is located between the protocol layer and the physical layer. Its main function is to convert different protocols from the protocol layer into a standard format that can be transmitted at the physical layer, and vice versa. The physical layer is directly responsible for the actual signal transmission between chips.

[0020] S200 , configuring a group of on-chip interfaces at the adapter layer, wherein the on-chip interfaces include a plurality of pins; the adapter layer interacts with the upper layer through the on-chip interfaces.

[0021] In one embodiment, the on-chip interface standard is AMBA APB (Advanced Microcontroller Bus Architecture - Advanced Peripheral Bus), AHB (Advanced High-performance Bus), AXI (Advanced eXtensible Interface), etc. Other types of standards also fall within the scope of protection of the present invention.

[0022] S300, establish a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol at the adapter layer, the mapping relationship includes a first mapping relationship in the sending direction and a second mapping relationship in the receiving direction, the first mapping relationship is used to map the pin signals of the on-chip interface that complies with the on-chip protocol to the fields of the sideband request transaction that complies with the target protocol, and the second mapping relationship is used to map the fields in the sideband completion transaction that complies with the target protocol to the corresponding pins of the on-chip interface.

[0023] Among them, the fields of the sideband transaction include the Opcode field, the BE field, the Addr field, and the data field. Among them, the Opcode field is used to distinguish the type of a single sideband transaction, and is used to indicate whether the current transaction is a read request, a write request, or other specific types of commands, such as a completion transaction or a message transaction. The BE field is Byte Enable, also known as the byte enable signal, which is used to specify which bytes are valid during data transmission; the Addr field is the address of the target register or memory accessed by the sideband mailbox, which specifies the specific location where the data will be read or written. The data field is the data. In a write request, the data field is the data to be written to the target address; in a read request, the data field may be empty or contain some predefined information; for a read completion transaction, this field contains the data read back from the target address. Sideband transactions that include other types of fields also fall within the scope of protection of the present invention.

[0024] In one embodiment, when the sending direction is a read operation, the first mapping relationship includes: the address configuration signal of the on-chip interface and the addr field of the sideband request transaction, and the read and write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction.

[0025] In one embodiment, when the sending direction is a write operation, the first mapping relationship includes: the address configuration signal of the on-chip interface is mapped to the addr field of the sideband request transaction, the read and write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction, the selection control signal of the on-chip interface is mapped to the BE field of the sideband request transaction, and the write data signal of the on-chip interface is mapped to the data field of the sideband request transaction.

[0026] In one embodiment, when the sending direction is a read operation, the second mapping relationship includes: the status field of the sideband completion transaction is mapped to the reply signal of the on-chip interface, and the data field of the sideband completion transaction is mapped to the read data signal of the on-chip interface.

[0027] In one embodiment, when a write operation is performed in the sending direction, the second mapping relationship includes: mapping a status field of the sideband completion transaction to a reply signal of the on-chip interface.

[0028] It should be noted that mapping relationships of other types of operations also fall within the protection scope of the present invention.

[0029] As an example, when the standard of the on-chip interface is the APB protocol and the target protocol is the UCIe protocol, when the sending direction is a read operation, the first mapping relationship includes: the PADDR signal of the APB is mapped to the addr field, and the PWRITE signal is mapped to the opcode field. When the sending direction is a write operation, the PADDR signal is mapped to the addr field, the PWRITE signal is mapped to the opcode field, the PSTRB signal is mapped to the BE field, and the PWDATA signal is mapped to the data field. When the sending direction is a read operation, the second mapping relationship includes: the status field is mapped to the PREADY signal and the PSLVERR signal, and the data field is mapped to the PRDATA signal. When the sending direction is a write operation, the second mapping relationship includes: the status field is mapped to the PREADY signal and the PSLVERR signal.

[0030] It should be noted that the adapter layer is responsible for protocol conversion between the target protocol and the on-chip interface protocol inside the chip, converting the data and control signals transmitted between chips into a format that complies with the local SoC internal bus standard, thereby achieving seamless communication and integration across chips.

[0031] S400, when sending a cross-chip register access transaction, the high-level layer configures the on-chip interface of the adapter layer; the adapter layer parses the on-chip interface to obtain corresponding configuration information, maps the configuration information to the field of the sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction according to the field of the sideband mailbox transaction through the sideband processing module of the adapter layer.

[0032] In one embodiment, when the sideband request transaction is a read request, the configuration information includes signals such as an address configuration signal and a read / write control signal. When the sideband request transaction is a write request, the configuration information includes signals such as an address configuration signal, a strobe control signal, a read / write control signal, and a write data signal. Other signal types in the configuration information also fall within the scope of protection of the present invention.

[0033] It should be noted that the sideband request transaction is a sideband transaction or a sideband mailbox transaction that complies with the target protocol.

[0034] S500, when receiving a sideband completion transaction, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to corresponding pins of the on-chip interface according to the second mapping relationship.

[0035] In one embodiment, when the sending direction is a read operation, the fields in the sideband completion transaction include a status field and a data field. When the sending direction is a write operation, the fields in the sideband completion transaction include a status field. Other signal types in the fields of the sideband completion transaction also fall within the scope of protection of the present invention.

[0036] It should be noted that, in order to better compare the traditional method with the method provided by the present invention, the following takes the target protocol as the UCIe protocol and a read request as an example to illustrate the entire access process. Figure 2 The specific steps are as follows: Step 1: During the sending phase of the transmitting chip: The transmitting chip's upper layer configures the required opcode, BE, address, and other information via the sideband signal of the FDI interface via the first transmission path 11 to the index register located in the transmitting chip's adapter layer. Simultaneously, it configures the write / read trigger field in the control register to 1 via the second transmission path 12. The control register is continuously polled via the fourth transmission path 14 until the write / read trigger field reaches 0, indicating the end of the mailbox access. The adapter layer processes the mailbox access information and initiates a mailbox access request transaction to the transmitting chip's physical layer via the fifth transmission path 15 via the RDI interface. The physical layer transmits the mailbox access request transaction to the receiving chip's physical layer via the UCIe sideband link 16. Step 2: During the receiving phase of the receiving chip: The receiving chip's physical layer transmits the mailbox access request transaction to the receiving chip's adapter layer via the RDI interface via the seventh transmission path 17. The adapter layer parses the mailbox access request transaction, completes the cross-chip register access, and initiates a mailbox access completion transaction to the receiving chip's physical layer via the eighth transmission path 18 via the RDI interface. The physical layer transmits the mailbox completion transaction to the physical layer of the sending chip through the UCIe sideband link 19. Step three, the sending chip receives the response phase: the sending chip physical layer transmits the mailbox completion transaction to the sending chip adapter layer through the RDI interface through the tenth transmission path 110. The adapter layer updates the write / read trigger field of the control register to 0, and updates the status register and data register. The upper layer reads the write / read trigger field value of the control register at the sideband signal of the FDI interface to be 0, indicating that the mailbox operation is successful. The sending chip upper layer reads the status register and data register through the sideband signal of the FDI interface through the eleventh transmission path 111. It should be noted that when it is a write operation, it is necessary to configure the data register at the adapter layer through the third transmission path 13. For the method provided by the present invention, please refer to Figure 3The specific steps are as follows: Step 1: During the sending phase of the transmitting chip: The transmitting chip's upper layer configures the on-chip interface at the adapter layer via the first path 1, including the address, data, and read / write operation type for cross-chip register access. The adapter layer processes the on-chip interface configuration information and initiates a mailbox access request to the transmitting chip's physical layer via the second path 2 at the RDI interface. The physical layer transmits the mailbox access request to the receiving chip's physical layer via the UCIe sideband link 3. Step 2: During the receiving phase of the receiving chip: The receiving chip's physical layer transmits the mailbox access request to the receiving chip's adapter layer via the fourth path 4 at the RDI interface. The adapter layer parses the mailbox access request transaction, completes the cross-chip register access, and initiates a mailbox access completion transaction to the receiving chip's physical layer via the fifth path 5 at the RDI interface. The physical layer transmits the mailbox completion transaction to the transmitting chip's physical layer via the UCIe sideband link 6. Step 3: During the transmitting chip's receiving response phase: The transmitting chip's physical layer transmits the mailbox completion transaction to the transmitting chip's adapter layer via the seventh path 7 at the RDI interface. The adapter layer parses the mailbox to complete the transaction, and responds to the upper layer through the eighth path 8 of the cross-chip register access result on the on-chip interface. From the perspective of the protocol layer or software, the traditional scheme for configuring mailbox registers requires at least three register configuration transactions before generating a sideband access transaction, such as configuring the index register, data register, and control register, where the index register stores the information of the Opcode field, BE field, and Addr field. In addition to these three register configuration transactions, it also includes a polling transaction for the control register. The system needs to continuously poll the status of the control register to detect whether the corresponding access transaction has returned. The embodiment of the present invention directly and significantly reduces the generation of sideband access transactions to only one mapping, that is, directly simplifying the original at least three transactions into one transaction, which not only improves the generation efficiency of access transactions, but also reduces the time of occupying hardware resources. Furthermore, traditional methods require at least three register configuration transactions, each consisting of a request transaction and a completion transaction. Each transaction takes 2-4 clock cycles, and multiple clock cycles are required between each two register configuration transactions. Therefore, three register configuration transactions take at least a dozen clock cycles. However, the present invention only requires one clock cycle to map signals to fields, significantly improving the efficiency of generating sideband access transactions. Furthermore, the on-chip interface boasts a higher clock frequency and faster processing speed, shortening the time required for cross-chip register access and improving both cross-chip register access efficiency and transmission efficiency.

[0037] As an example, take the APB interface as an example, the specific operation steps are as follows: Step 1: Based on the on-chip interface timing, configure the access address, write data and other information. Taking the APB interface and the write operation as an example, the specific timing diagram is as follows: Figure 4As shown in (a), from the clock signal (PCLK), it can be seen that at time T1, the target address ADDR1 is configured to the address signal (PADDR), and the write data WDATA1 is configured to the write data signal (PWDATA), and the selection signal (PSEL) is set at the same time; at time T2, the enable signal (PENABLE) is set to complete the interaction of related handshake signals. Step 2: Wait for the on-chip interface to return the completion signal. At time Tn, the adapter layer receives the mailbox to complete the transaction, and the ready signal (PREADY) is pulled high, indicating that the cross-chip register access is completed. The slave device error signal (PSLVERR) is not set, indicating that there is no error in the slave device. Taking the APB interface and the read operation as an example, the specific timing diagram is as follows Figure 4 As shown in (b), at time T1, the target address ADDR1 is assigned to the address signal (PADDR) and other signals, and the select signal (PSEL) is simultaneously set; at time T2, the enable signal (PENABLE) is set to complete the interaction of the relevant handshake signals. Step 2: Wait for the on-chip interface to return a completion signal. At time Tn, the adapter layer receives the mailbox completion transaction, pulls the ready signal (PREADY) high, indicating that the cross-chip register access is complete, and reads the read data (RDATA1) information via the read data signal (PRDATA). Compared with traditional mailbox operations, there is no need for software or higher-level layers to repeatedly poll the mailbox status register. Only a single register access transaction by the higher-level layer or software is required to complete the cross-chip register access, greatly simplifying the cross-chip register access process.

[0038] In one embodiment, when the on-chip interface uses a protocol that supports outstanding data transmission characteristics, S300 also includes: continuously sending multiple sideband request transactions and continuously monitoring the credit status of the receiving end through a detection module; wherein the credit status is used to record the ability of the remote end to receive sideband request transactions. When the credit status is greater than zero, the remote end can receive sideband request transactions; the adapter layer directly initiates sideband request transactions. When the credit status is zero, the remote end cannot receive sideband request transactions; the adapter layer temporarily stores new sideband request transactions in a local cache queue and continuously monitors the credit status of the receiving end; when the credit status releases the ability to receive a sideband request transaction, the adapter layer initiates a sideband request transaction. For example, when the on-chip interface supports the AXI protocol and the target protocol is the UCIe protocol, a multi-channel concurrent access mechanism can be constructed in the above manner: the outstanding data transmission characteristics of the AXI interface allow multiple new transaction access requests to be initiated before a single transaction is completed, forming a multi-level transmission queue. Combined with the end-to-end credit (E2E Credit) mechanism defined by the UCIe protocol, the AXI interface's transmission queue depth is mapped to the end-to-end credit value. The UCIe protocol's end-to-end credit value determines AXI's data over-issuance capability. This collaborative design enables: 1) multiple register access operations to proceed in parallel, eliminating the serial wait required by traditional solutions; 2) the credit mechanism ensures data integrity and prevents buffer overflows; 3) by dynamically adjusting the Outstanding queue and credit threshold, an optimal balance between link utilization and power consumption is achieved. This provides cross-chiplet communication capabilities with near-memory access efficiency for heterogeneous computing scenarios, shortening the time and improving the efficiency of cross-chiplet register access.

[0039] Other types of protocols supporting outstanding data transmission characteristics also fall within the protection scope of the present invention.

[0040] In summary, the cross-chip register access method based on the target protocol provided by the present invention establishes a mapping relationship between the on-chip interface and the target protocol at the adapter layer by multiplexing the on-chip interface, and directly configures the on-chip interface through the high-level layer. The adapter layer maps the signal of the on-chip interface to the field of the sideband transaction that complies with the target protocol, and generates a sideband transaction, thereby realizing sideband transaction interaction. By directly constructing a cross-chip communication path through high-level configuration, the configuration of the mailbox register is bypassed, and the dependence on the dedicated sideband mailbox mechanism is eliminated. No additional hardware is required, while maintaining full compatibility with the UCIe protocol. A single register access transaction can complete cross-chip data interaction, shorten the operation time, and significantly reduce communication delays and system resource occupancy; and it is fully compatible with software operation logic, supports the simultaneous initiation of multiple cross-chip register access operations, and provides a solution that combines technical innovation and engineering practicality for efficient communication between heterogeneous chips, effectively improving the overall energy efficiency of the system and reducing the complexity of integrated design.

[0041] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one program related to implementing a method in a method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0042] An embodiment of the present invention further provides an electronic device including a processor and the aforementioned non-transitory computer-readable storage medium.

[0043] An embodiment of the present invention further provides a computer program product comprising program code. When the program product is run on an electronic device, the program code is used to enable the electronic device to execute the steps of the method according to various exemplary embodiments of the present invention described above in this specification.

[0044] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0045] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A cross-chip register access method based on a target protocol, characterized in that: The method comprises the following steps: S100, obtaining a target protocol, where the target protocol includes a high layer and an adapter layer; S200, configuring a group of on-chip interfaces at the adapter layer, wherein the on-chip interfaces include a plurality of pins; The adapter layer interacts with the higher layer via the on-chip interface; S300, establishing, at the adapter layer, a mapping relationship between multiple pins of the on-chip interface and multiple fields of the target protocol, the mapping relationship including a first mapping relationship in a sending direction and a second mapping relationship in a receiving direction, the first mapping relationship being used to map pin signals of the on-chip interface that conforms to the on-chip protocol to fields of a sideband request transaction that conforms to the target protocol, and the second mapping relationship being used to map fields in a sideband completion transaction that conforms to the target protocol to corresponding pins of the on-chip interface; S400, when sending a cross-chip register access transaction, the upper layer configures the on-chip interface of the adapter layer; The adapter layer parses the on-chip interface to obtain corresponding configuration information, maps the configuration information to fields of a sideband mailbox transaction according to the first mapping relationship, and initiates the sideband request transaction according to the fields of the sideband mailbox transaction through the sideband processing module of the adapter layer; S500, when receiving a sideband completion transaction, the adapter layer parses the fields in the sideband completion transaction and maps the fields in the sideband completion transaction to corresponding pins of the on-chip interface according to the second mapping relationship.

2. The method according to claim 1, characterized in that S400 further includes: continuously sending multiple sideband request transactions and continuously monitoring the credit status of the receiving end through the detection module; wherein the credit status is used to record the ability to receive the sideband request transactions; When the credit status is greater than zero, a sideband request transaction can be received; the adapter layer directly initiates the sideband request transaction; When the credit status is zero, the sideband request transaction cannot be received; the on-chip interface temporarily stores the new sideband request transaction in a local cache queue and continuously monitors the credit status of the receiving end; when the credit status releases the ability to receive a sideband request transaction, the adapter layer initiates a sideband request transaction.

3. The method according to claim 1, characterized in that In S300 , when the sending direction is a read operation, the first mapping relationship includes: mapping the address configuration signal of the on-chip interface to the addr field of the sideband request transaction, and mapping the read and write control signal of the on-chip interface to the opcode field of the sideband request transaction.

4. The method according to claim 1, wherein In S300, when the sending direction is a write operation, the first mapping relationship includes: the address configuration signal of the on-chip interface and the addr field of the sideband request transaction, the read and write control signal of the on-chip interface is mapped to the opcode field of the sideband request transaction, the selection control signal of the on-chip interface is mapped to the BE field of the sideband request transaction, and the write data signal of the on-chip interface is mapped to the data field of the sideband request transaction.

5. The method according to claim 1, wherein In S300 , when the sending direction is a read operation, the second mapping relationship includes: mapping the status field of the sideband completion transaction to the reply signal of the on-chip interface, and mapping the data field of the sideband completion transaction to the read data signal of the on-chip interface.

6. The method according to claim 1, characterized in that In S300 , when a write operation is performed in the sending direction, the second mapping relationship includes mapping a status field of the sideband completion transaction to a reply signal of the on-chip interface.

7. The method according to claim 1, characterized in that The standard of the on-chip interface is AMBA APB, AHB, or AXI.

8. The method according to claim 1, characterized in that The target protocol is the UCIe protocol.

9. A non-transitory computer-readable storage medium, wherein at least one instruction or at least one program is stored in the storage medium, characterized in that: The at least one instruction or the at least one program is loaded and executed by a processor to implement the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The device comprises a processor and the non-transitory computer-readable storage medium as claimed in claim 9.

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