Resource allocation method and device and electronic equipment

Abstract

The invention discloses a resource allocation method and device and electronic equipment, and relates to the technical field of artificial intelligence, and the method comprises the steps: obtaining a shared memory address, and reading shared parameter information corresponding to the shared memory address; when the parameter type of the shared parameter information is a queue jumping type, inserting an NPU memory access request task corresponding to the shared parameter information into a head position of a task queue in a dynamic random access memory controller so as to preferentially process the NPU memory access request task; or, when the parameter type of the shared parameter information is a preemptive type, interrupting the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller, so as to preferentially process the NPU memory access request task. According to the embodiments of the present disclosure, it can be ensured that the NPU memory access request task can be efficiently executed, and the computing performance of the NPU is improved.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a resource allocation method, device, and electronic device. Background Art

[0002] In neural network processing unit (NPU) computing applications, the operation of neural network models typically involves the coordinated work of multiple modules and external devices. When executing an inference task, the central processing unit (CPU) first loads the model and data from the operating system (such as Linux) and notifies the hardware processor core (HCPU) in the NPU to begin executing the computing task by calling the NPU driver.

[0003] During model execution, the HCPU needs to access instruction data in the dynamic random access memory (DDR). Based on the instruction content, it can initiate high-performance direct memory access (HDMA) to move data from the DDR to the unified memory (UM). The HCPU continues to parse the instruction data in the DDR. The instruction data may include multiple tile instructions, and each tile instruction may contain a UM instruction. In this case, general streaming direct memory access (GSDMA) can be initiated to move the data from the UM back to the DDR.

[0004] Because tile instructions support the synchronization mechanism (SV) of computing units, multiple modules such as the CPU, HCPU, HDMA, and GSDMA will access the DDR simultaneously throughout the computing process. In addition, when the system is running at full load, other external devices such as direct memory access (DMA), image signal processor (ISP), universal flash storage (UFS), media access control (MAC), and universal serial bus (USB) will also access the DDR simultaneously.

[0005] In existing solutions, the DDR controller arbitrates access to the DDR ports based on the queue of requested tasks. However, if the DDR bandwidth is too large, this arbitration mechanism can cause the NPU to be blocked when executing computing units in parallel, thereby reducing the NPU's computing performance. Summary of the Invention

[0006] In view of this, the present application provides a resource allocation method, device and electronic device, the main purpose of which is to solve the current problem that multiple peripherals access DDR at the same time, resulting in excessive DDR bandwidth, causing the NPU to be blocked when accessing DDR, thereby reducing the computing performance of the NPU.

[0007] According to a first aspect of the present application, a resource allocation method is provided, comprising:

[0008] Get the shared memory address passed by the CPU;

[0009] Accessing the shared memory corresponding to the shared memory address to read shared parameter information in the shared memory, the shared parameter information including a parameter type, and the parameter type including a queue-jumping type and a preemption type;

[0010] In a case where the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, and the queue-jumping type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or,

[0011] In the case where the parameter type of the shared parameter information is a preemption type, the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller is interrupted, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0012] According to a second aspect of the present application, a resource allocation device is provided, comprising:

[0013] The acquisition module is used to obtain the shared memory address passed by the central processing unit;

[0014] An access module, configured to access the shared memory corresponding to the shared memory address to read shared parameter information in the shared memory, wherein the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type;

[0015] an insertion module, configured to insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller when the parameter type of the shared parameter information is a queue insertion type, wherein the queue insertion type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or

[0016] An interrupt module is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0017] According to a third aspect of the present application, there is provided a resource allocation system, comprising: a processing unit, a shared memory, and a monitoring unit;

[0018] The shared memory is connected to the processing unit, and the shared memory is used to store shared parameter information;

[0019] The monitoring unit is connected to the processing unit, and the monitoring unit is used to monitor the load status of the task queue of the dynamic random access memory controller;

[0020] The processing unit is used to obtain the shared memory address transmitted by the central processing unit, and access the shared memory corresponding to the shared memory address to read the shared parameter information in the shared memory;

[0021] The processing unit is configured to, when the parameter type of the shared parameter information is a queue-jumping type, insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller, wherein the queue-jumping type is used to indicate that the load state of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or

[0022] The processing unit is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load state of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0023] According to a fourth aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the resource allocation method described in the first aspect is implemented.

[0024] According to the fifth aspect of the present application, an electronic device is provided, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the resource allocation method described in the first aspect when executing the computer program.

[0025] According to the sixth aspect of the present application, the present disclosure provides a vehicle, comprising: the method as described in the first aspect, the device as described in the second aspect, or the computer-readable storage medium as described in the third aspect, or the electronic device as described in the fourth aspect.

[0026] By means of the above technical solution, a resource allocation method, device and electronic device provided in the present application can obtain a shared memory address transmitted by a central processing unit, access the shared memory corresponding to the shared memory address, and read the shared parameter information in the shared memory, where the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type; when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, and the queue-jumping type is used to characterize that the load of the task queue of the dynamic random access memory controller is less than the preset load, and the priority of the NPU memory access request task is higher than the preset priority; or, when the parameter type of the shared parameter information is a preemption type, the NPU memory access request task corresponding to the shared parameter information is interrupted in the corresponding task queue of the dynamic random access memory controller, where the request task is a request task in the task queue whose priority is lower than the preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority. For the embodiments of the present disclosure, the priority of resource allocation of the dynamic random access memory controller can be dynamically adjusted according to the load situation of the dynamic random access memory controller, that is, when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller so as to give priority to the NPU memory access request task, or, when the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information in the request task of the corresponding task queue of the dynamic random access memory controller is interrupted so as to give priority to the NPU memory access request task, thereby ensuring that the NPU memory access request task can be executed efficiently and improving the computing performance of the NPU.

[0027] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, which can be implemented in accordance with the contents of the specification, and to make the above and other purposes, features and advantages more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0029] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0030] Figure 1 A system architecture diagram of a resource allocation system provided in an embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of a flow chart of a resource allocation method provided in an embodiment of the present disclosure;

[0032] Figure 3 A flowchart of another resource allocation method provided in an embodiment of the present disclosure;

[0033] Figure 4 A flowchart of another resource allocation method provided in an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of collaboration between modules in a resource allocation system provided by an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of the structure of a resource allocation device provided in an embodiment of the present disclosure;

[0036] Figure 1 middle:

[0037] 1-processing unit DCPU;

[0038] 2- Shared memory RAM;

[0039] 3-Monitoring unit Watch. DETAILED DESCRIPTION

[0040] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, and they should be considered as merely exemplary. Therefore, it should be recognized by those skilled in the art that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other unless there is a conflict.

[0041] The resource allocation method, apparatus, and electronic device according to the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0042] In order to solve the problem that multiple peripherals access DDR at the same time, resulting in excessive DDR bandwidth, which blocks the NPU from accessing DDR and reduces the computing performance of the NPU. Figure 1 As shown, an embodiment of the present disclosure provides a resource allocation system, which includes: a processing unit 1, a shared memory 2, and a monitoring unit 3;

[0043] In a specific application scenario, the shared memory 2 is connected to the processing unit 1, and the shared memory 2 is used to store shared parameter information;

[0044] The monitoring unit 3 is connected to the processing unit 1 and is used to monitor the load status of the task queue of the dynamic random access memory controller;

[0045] The processing unit 1 is used to obtain the shared memory 2 address transmitted by the central processing unit, and access the shared memory 2 corresponding to the shared memory 2 address to read the shared parameter information in the shared memory 2;

[0046] The processing unit 1 is configured to insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller when the parameter type of the shared parameter information is a queue-jumping type, where the queue-jumping type is used to indicate that the load state of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than the preset priority; or,

[0047] The processing unit 1 is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load state of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0048] In the embodiment of the present disclosure, Figure 1 As shown in FIG, a dynamic random access memory controller (DDR Controller) is internally added with modules such as DCPU, RAM, and Watch.

[0049] The DCPU is a microprocessor or processing unit embedded in the DDR Controller, which can be used to execute firmware instructions loaded on the CPU side.

[0050] RAM (Random Access Memory) is used to temporarily store running programs and data. In a DDR controller, RAM can be used to store instructions, data, and buffer contents, providing the DCPU with fast-access local memory space for executing tasks and processing data.

[0051] Watch can be a monitoring module or monitoring unit. In a DDR Controller, the Watch module can be responsible for monitoring the health, performance, power status, and other key parameters of the DDR Controller to ensure data integrity and system reliability.

[0052] Specifically, such as Figure 1 As shown, the processing unit 1 (Directory Central Processing Unit, DCPU) of the dynamic random access memory controller (Double Data Rate Controller, DDR Controller) can obtain the shared memory address transmitted by the central processing unit (CPU) and access the shared memory 2 (Random Access Memory, RAM) corresponding to the shared memory address to read the shared parameter information in the shared memory. The RAM can be divided into different address spaces, for example, the RAM can be divided into a high address space and a low address space. The high address space can be used to store user data, application variables, etc. In this embodiment, it can be used as a shared memory that maps the shared memory address; the low address space can be used to store information such as instructions and program code.

[0053] The monitoring unit 3 (i.e., Watch) determines the current DDR Controller load status. If the DDR Controller load is not high (i.e., less than a preset load) and there are more resources to respond to requests, if a higher-priority task (such as an NPU memory access request task) needs to access the DDR Controller, and the currently executing task has a lower priority, the processing unit 1 can control the lower-priority task to give up DDR control rights, allowing the higher-priority task (such as the NPU memory access request task) to access the DDR Controller first, so that the higher-priority task (such as the NPU memory access request task) can be processed first.

[0054] Monitoring unit 3 (i.e., Watch) determines the current DDR Controller load status. If the DDR Controller load is high (i.e., greater than a preset load) and the DDR Controller memory in the system faces high concurrent access, that is, multiple tasks need to access the DDR Controller simultaneously, if a higher-priority task (such as an NPU memory access request task) needs to access the DDR Controller, processing unit 1 may suspend the low-priority task currently accessing the DDR Controller and then switch to the high-priority task (such as the NPU memory access request task) to prioritize the NPU memory access request task, ensuring that critical tasks such as the NPU can be executed efficiently.

[0055] like Figure 2 As shown, an embodiment of the present disclosure provides a resource allocation method, which can be applied to the above-mentioned resource allocation method system and executed by a processing unit in the resource allocation method system, wherein the resource allocation method may include:

[0056] Step 101: Obtain a shared memory address transmitted by a central processing unit, access a shared memory corresponding to the shared memory address, and read shared parameter information in the shared memory.

[0057] Among them, shared parameter information may include parameter type, and parameter type may include queue-jumping type and preemption type; shared memory address may be a kernel-state pointer pointing to a data area in memory for sharing; shared memory may be used to implement inter-process communication, allowing two or more processes to use memory areas to share data; shared parameter information may be data stored in shared memory.

[0058] For the embodiment of the present disclosure, the execution subject may be a processing unit (ie, DCPU) of a dynamic random access memory controller (ie, DDR Controller).

[0059] In this embodiment, the Directory Central Processing Unit (DCPU) of the Double Data Rate Controller (DDRController) can obtain the shared memory address transmitted by the Central Processing Unit (CPU) and access the Random Access Memory (RAM) corresponding to the shared memory address to read the shared parameter information within the shared memory. The RAM can be divided into different address spaces, for example, a high address space and a low address space. The high address space can be used to store user data, application variables, etc., and in this embodiment, can be used as the shared memory to map the shared memory address; the low address space can be used to store information such as instructions and program code.

[0060] In this embodiment, when the system starts, Figure 3 As shown, various registers of the DCPU can be initialized, the Bulletin Board System (BBS) can be initialized, the stack environment can be initialized, the Watch module can be initialized, and the Interrupt module can be initialized.

[0061] In this embodiment, all IP addresses that need to access the DDR Controller can be connected to the DDR Controller through a port connection (i.e., the external device is connected to the DDR Controller through a physical interface) or through an AXI Fabric (i.e., the external device is connected to the DDR Controller through the AXI bus protocol). The DDR Controller can obtain the ID information of the IP address currently accessing the DDR content.

[0062] Step 102: When the parameter type of the shared parameter information is a queue-jumping type, insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller.

[0063] The queue-jumping type indicates that the load of the dynamic random access memory controller's task queue is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority. The load can be the number of tasks in the dynamic random access memory controller's (DDR controller) task queue, reflecting how busy the task queue is. The preset priority can be a pre-set priority level used to determine the priority level of tasks that are queued to the front of the task queue.

[0064] The preset load can be a pre-set load threshold used to determine whether the task queue is in a lightly loaded state. If the number of tasks in the task queue is less than the preset load, new tasks (i.e., NPU memory access request tasks) are allowed to be queued to the front of the task queue to ensure higher responsiveness when the task queue is not too busy.

[0065] The NPU can be a neural network processor or unit used to accelerate machine learning algorithms and deep learning models; the NPU memory access request task can be an access task for the neural network processing unit (NPU) to request DDR memory to read or write data.

[0066] According to the embodiment of the present disclosure, when the system DDR load is not high and there are more resources to respond to requests, the present application can dynamically adjust the arbitration priority of the DDR Controller according to the priority of the task to improve the response speed and efficiency of the system.

[0067] Typically, tasks in the system access DDR memory in a predetermined order of priority. However, if a higher-priority task (such as an NPU memory access request) requires DDR access, and the currently executing task has a lower priority, the lower-priority task can relinquish control of the DDR, allowing the higher-priority task (such as the NPU memory access request) to access the DDR first. This queue-jumping approach reduces the time high-priority tasks wait for DDR resources, thereby improving the computing performance of high-priority external devices (such as the NPU).

[0068] Correspondingly, when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller so as to give priority to processing the NPU memory access request task.

[0069] The head position may be the starting point of the task queue, and the NPU memory access request task is inserted into the starting point, so that the NPU memory access request task becomes the next task to be processed.

[0070] Step 103: When the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller is interrupted.

[0071] Among them, the request task is a request task in the task queue whose priority is lower than the preset priority; the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0072] In the disclosed embodiment, when the DDR memory in the system faces high concurrent access, that is, multiple tasks need to access the DDR at the same time, resource competition may occur, resulting in certain critical tasks being unable to obtain the required memory access rights in a timely manner.

[0073] To solve this problem, this application proposes a method that can dynamically suspend low-priority tasks based on task priority. That is, when a high-priority task (such as an NPU memory access request task) needs to access the DDR, the low-priority task currently accessing the DDR will be suspended. Then, the system will switch to the high-priority task (such as the NPU memory access request task) to prioritize the NPU memory access request task. This preemptive access mechanism can ensure that critical tasks such as the NPU can access the DDR in real time, meet urgent needs for memory resources, and ensure that critical tasks such as the NPU can be executed efficiently.

[0074] Correspondingly, when the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information is interrupted in the corresponding task queue of the dynamic random access memory controller so as to give priority to the NPU memory access request task.

[0075] In summary, according to a resource allocation method disclosed in the present invention, a shared memory address passed by a central processing unit can be obtained, and the shared memory corresponding to the shared memory address can be accessed to read the shared parameter information in the shared memory, where the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type; when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, and the queue-jumping type is used to characterize that the load of the task queue of the dynamic random access memory controller is less than the preset load, and the priority of the NPU memory access request task is higher than the preset priority; or, when the parameter type of the shared parameter information is a preemption type, the NPU memory access request task corresponding to the shared parameter information is interrupted in the corresponding task queue of the dynamic random access memory controller, where the request task is a request task in the task queue whose priority is lower than the preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority. For the embodiments of the present disclosure, the priority of resource allocation of the dynamic random access memory controller can be dynamically adjusted according to the load situation of the dynamic random access memory controller, that is, when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller so as to give priority to the NPU memory access request task, or, when the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information in the request task of the corresponding task queue of the dynamic random access memory controller is interrupted so as to give priority to the NPU memory access request task, thereby ensuring that the NPU memory access request task can be executed efficiently and improving the computing performance of the NPU.

[0076] Furthermore, as a refinement and extension of the above embodiment, in order to fully illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following Figure 4 The specific method shown includes the following steps:

[0077] Step 201: triggering a cyclic redundancy check (CRC) process of the firmware program of the dynamic random access memory controller to determine whether the firmware program is legal; if the firmware program is legal, accessing the shared memory corresponding to the shared memory address to read the shared parameter information in the shared memory.

[0078] The cyclic redundancy check (CRC) is an error detection code used to detect errors in data storage or transmission. It calculates the cyclic redundancy check (CRC) of the data to detect changes in the data during transmission or storage. If the data changes, the CRC will also change, thus detecting the error and determining that the firmware program is illegal.

[0079] For the embodiment of the present disclosure, as a possible implementation method, a timer or event listener in the DDR Controller may trigger a cyclic redundancy check process in the firmware program of the DDR Controller.

[0080] like Figure 3 As shown, if the firmware's cyclic redundancy check (CRC) detects data corruption, meaning the firmware self-test has failed and is illegal, the firmware can record the error information in shared memory and send an interrupt to the CPU. If the CRC does not detect an error, meaning the firmware self-test has passed and is legal, the firmware can update the status in shared memory to indicate that the self-test has successfully completed. If the firmware is legal, the DDR controller's processing unit (Directory Central Processing Unit, DCPU) can read the shared parameter information from the shared memory.

[0081] Step 202a: When the parameter type of the shared parameter information is a queue-jumping type, read the corresponding first identification information of the shared parameter information whose parameter type is a queue-jumping type; in response to the first identification information, determine the task queue of the NPU memory access request task in the dynamic random access memory controller; and insert the NPU memory access request task of the first identification information into the head position of the task queue.

[0082] For the embodiments of the present disclosure, Figure 3 As shown, if the shared parameter information is not obtained and the parameter type of the obtained shared parameter information has not been set, the shared parameter information is continued to be obtained. At this time, the DDRController still executes tasks in sequence according to the queue tasks on each port (ie, physical interface) before.

[0083] like Figure 3As shown, when the parameter type of the obtained shared parameter information is a queue-jumping type, the DCPU of the DDRController can read the first identification information (i.e., ID information) of the IP address of the NPU memory access request task corresponding to the shared parameter information from the shared memory, and the DCPU can find the task queue of the corresponding Port port of the DDR Controller based on the first identification information, where each Port port can correspond to an associated task queue, which can be used to manage memory access requests.

[0084] The Watch module of the DDR Controller can refresh the task queue of the port to insert the NPU memory access request task with the first identification information into the head position of the task queue, wait for the currently executing task to be completed, and then process the newly inserted NPU memory access request task.

[0085] The queue-jumping mechanism of the present application can prioritize queue-jumping based on the priority of new memory access requests, thereby allowing the system to quickly respond to high-priority tasks.

[0086] In step 202b, which is parallel to step 202a, when the parameter type of the shared parameter information is a preemptive type, the corresponding second identification information of the shared parameter information whose parameter type is a preemptive type is read, and in response to the second identification information, the task queue of the NPU memory access request task in the dynamic random access memory controller is determined, and the request task in the task queue is interrupted.

[0087] In the disclosed embodiment, when the DDR memory in the system faces high concurrent access, that is, multiple tasks need to access the DDR at the same time, resource competition may occur, resulting in certain critical tasks not being able to obtain the required memory access rights in a timely manner. In order to solve this problem, the present application proposes a method for dynamically suspending low-priority tasks according to task priority and saving their current states. That is, when a high-priority task needs to access the DDR, the low-priority task currently accessing the DDR will be suspended, and its current processing state will be saved (for example, the location of read and write data, processing progress, etc.). Then, the system will switch to the high-priority task and let it execute first. After the high-priority task is completed, the previously suspended low-priority task will be restored from the saved state and continue to execute. This preemptive access mechanism can ensure that critical tasks such as the NPU can access the DDR in real time, meet the urgent needs of critical tasks such as the NPU for memory resources, and thus ensure the overall performance and response speed of the system.

[0088] Specifically, such as Figure 3As shown, when the parameter type of the obtained shared parameter information is a preemptive type, the DCPU of the DDRController can read the second identification information (i.e., ID information) of the IP address of the NPU memory access request task corresponding to the shared parameter information from the shared memory, and the DCPU can find the task queue of the corresponding port of the DDR Controller based on the second identification information.

[0089] The Watch module of the DDR Controller can refresh the task queue of the port to temporarily stop the task currently executed on the DDR Controller, save the corresponding processing data of the processed request task, and save the current status of the DDR Controller so that the request task can be reprocessed after the NPU memory access request task is processed.

[0090] When it decides to suspend a low-priority task, the DCPU can control the DDR Controller through the Watch module to refresh the pipeline of the current preempted task port, ensuring that the preempted task (i.e., the NPU memory access request task) can be executed from a clean state; after that, the DCPU can process the DDR access request of the IP address of the preempted task, that is, execute the NPU memory access request task.

[0091] After the waiting preempted task is completed, the port is released, the data of the interrupted task is restored to the buffer, and the information of the DDR Controller is restored to execute the interrupted task.

[0092] Step 203: Determine the load of the dynamic random access memory controller; if the load of the dynamic random access memory controller is greater than the preset load, suspend the request task with a priority lower than the preset priority in the shared parameter information until the NPU memory access request task is prioritized and completed.

[0093] For the embodiments of the present disclosure, Figure 3 As shown, the DDR Controller Watch module can be used to determine the current DDR Controller load. If the monitoring results show that the DDR Controller load exceeds the preset load threshold, it may indicate that the DDR Controller is processing a large number of memory access requests or performing a large amount of data transmission, resulting in resource shortage or reduced processing speed. The system can refer to the shared memory sharing parameter information to suspend low-priority tasks until the NPU memory access request tasks are prioritized and completed.

[0094] In specific application scenarios, from the perspective of the system, analyze the collaboration and division of labor between modules, such as Figure 5 As shown:

[0095] 1. The bootloader is software that runs before the operating system starts. It is used to initialize the hardware and start the operating system. The bootloader is responsible for configuring and starting the DDR controller and the DDR physical layer (DDRPhy) during system startup.

[0096] 2. In addition to initializing the NPU, the NPU driver in the Linux system also needs to initialize the DCPU and load the firmware running on the DCPU. It also needs to establish a handshake mechanism with the DCPU and record the DCPU operation parameters passed down from the application layer. When the NPU driver loads the corresponding inference task, it puts the corresponding parameters into the shared memory of the DCPU's RAM.

[0097] 3. The application (APP) can be responsible for loading the firmware program (Firmware) and parameter (Parameter) binary files stored in the file system into the NPU driver (driver).

[0098] In summary, according to a resource allocation method disclosed in the present invention, a shared memory address passed by a central processing unit can be obtained, and the shared memory corresponding to the shared memory address can be accessed to read the shared parameter information in the shared memory, where the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type; when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, and the queue-jumping type is used to characterize that the load of the task queue of the dynamic random access memory controller is less than the preset load, and the priority of the NPU memory access request task is higher than the preset priority; or, when the parameter type of the shared parameter information is a preemption type, the NPU memory access request task corresponding to the shared parameter information is interrupted in the corresponding task queue of the dynamic random access memory controller, where the request task is a request task in the task queue whose priority is lower than the preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority. For the embodiments of the present disclosure, the priority of resource allocation of the dynamic random access memory controller can be dynamically adjusted according to the load situation of the dynamic random access memory controller, that is, when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller so as to give priority to the NPU memory access request task, or, when the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information in the request task of the corresponding task queue of the dynamic random access memory controller is interrupted so as to give priority to the NPU memory access request task, thereby ensuring that the NPU memory access request task can be executed efficiently and improving the computing performance of the NPU.

[0099] Based on the above Figure 2 and Figure 4 The specific implementation of the method shown in this embodiment provides a resource allocation device, such as Figure 6 As shown, the device includes: an acquisition module 31, an access module 32, an insertion module 33, and an interruption module 34;

[0100] An acquisition module 31 is used to acquire the shared memory address transmitted by the central processing unit;

[0101] An access module 32 is configured to access the shared memory corresponding to the shared memory address to read shared parameter information in the shared memory, wherein the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type;

[0102] an insertion module 33, configured to insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller when the parameter type of the shared parameter information is a queue-jumping type, wherein the queue-jumping type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or

[0103] The interrupt module 34 is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

[0104] In a specific application scenario, the device further includes: a trigger module 35, a reading module 36;

[0105] a trigger module 35 for triggering a cyclic redundancy check (CRC) process of the firmware program of the dynamic random access memory controller to determine whether the firmware program is legal;

[0106] The reading module 36 is configured to access the shared memory corresponding to the shared memory address to read the shared parameter information in the shared memory if the firmware program is legal.

[0107] In a specific application scenario, the insertion module 33 may be configured to read corresponding first identification information of the shared parameter information whose parameter type is the queue-jumping type when the parameter type of the shared parameter information is the queue-jumping type;

[0108] In response to the first identification information, determining a task queue of an NPU memory access request task in the dynamic random access memory controller;

[0109] Insert the NPU memory access request task of the first identification information into the head position of the task queue.

[0110] In a specific application scenario, the interrupt module 34 may be configured to read corresponding second identification information of the shared parameter information of the preemptive type when the parameter type of the shared parameter information is the preemptive type;

[0111] In response to the second identification information, determining a task queue of an NPU memory access request task in the dynamic random access memory controller;

[0112] Interrupt the request task in the task queue.

[0113] In a specific application scenario, the device further includes: a saving module 37;

[0114] The saving module 37 is used to save the corresponding processing data of the processed request task and save the current state of the dynamic random access memory controller, so as to reprocess the request task after processing the NPU memory access request task.

[0115] In a specific application scenario, the device further includes: a determination module 38, a pause module 39;

[0116] A determination module 38, configured to determine a load condition of the dynamic random access memory controller;

[0117] The pause module 39 is configured to pause the request task with a priority lower than the preset priority in the shared parameter information if the load of the dynamic random access memory controller is greater than the preset load, until the NPU memory access request task is processed and completed with priority.

[0118] It should be noted that for other corresponding descriptions of the functional units involved in the resource allocation device provided in this embodiment, please refer to Figure 2 and Figure 4 The corresponding description of the method in will not be repeated here.

[0119] Based on the above Figure 2 and Figure 4 The method shown in FIG. 1 is a method for performing the above-mentioned steps. Accordingly, the present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the computer program can realize the above-mentioned steps. Figure 2 and Figure 4 The method shown.

[0120] Based on this understanding, the technical solution of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present disclosure.

[0121] Based on the above Figure 2 and Figure 4 The method shown, and Figure 5 In order to achieve the above-mentioned purpose, the embodiment of the present disclosure further provides an electronic device that can be configured on the vehicle (such as an electric vehicle) side, the device including a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 2 and Figure 4 The method shown.

[0122] Optionally, the physical device may further include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a Wi-Fi module, and the like. The user interface may include a display, an input unit such as a keyboard, and the like. The optional user interface may also include a USB interface, a card reader interface, and the like. The network interface may optionally include a standard wired interface, a wireless interface (such as a Wi-Fi interface), and the like.

[0123] Those skilled in the art will understand that the above-mentioned physical device structure provided by the present disclosure does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different component arrangements.

[0124] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the physical device, supporting the execution of information processing programs and other software and / or programs. The network communication module is used to enable communication between components within the storage medium, as well as with other hardware and software within the physical information processing device.

[0125] Through the description of the above embodiments, those skilled in the art can clearly understand that the present disclosure can be implemented by means of software plus a necessary general hardware platform, or can be implemented by hardware. The resource allocation method, device, and electronic device provided by the present disclosure, compared with the prior art, access the shared memory corresponding to the shared memory address by obtaining the shared memory address transmitted by the central processing unit to read the shared parameter information in the shared memory, where the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type. When the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, where the queue-jumping type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than the preset priority. Alternatively, when the parameter type of the shared parameter information is a preemption type, the NPU memory access request task corresponding to the shared parameter information is interrupted in the corresponding task queue of the dynamic random access memory controller, where the request task is a request task in the task queue whose priority is lower than the preset priority, and the preemption type is used to indicate that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority. For the embodiments of the present disclosure, the priority of resource allocation of the dynamic random access memory controller can be dynamically adjusted according to the load situation of the dynamic random access memory controller, that is, when the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller so as to give priority to the NPU memory access request task, or, when the parameter type of the shared parameter information is a preemptive type, the NPU memory access request task corresponding to the shared parameter information in the request task of the corresponding task queue of the dynamic random access memory controller is interrupted so as to give priority to the NPU memory access request task, thereby ensuring that the NPU memory access request task can be executed efficiently and improving the computing performance of the NPU.

[0126] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0127] The above are merely specific embodiments of the present application, which are intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to these embodiments herein, but rather will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A resource allocation method, characterized in that: The method comprises: Get the shared memory address passed by the CPU; Accessing the shared memory corresponding to the shared memory address to read shared parameter information in the shared memory, the shared parameter information including a parameter type, and the parameter type including a queue-jumping type and a preemption type; In a case where the parameter type of the shared parameter information is a queue-jumping type, the NPU memory access request task corresponding to the shared parameter information is inserted into the head position of the corresponding task queue in the dynamic random access memory controller, and the queue-jumping type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or, In the case where the parameter type of the shared parameter information is a preemption type, the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller is interrupted, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

2. The method according to claim 1, characterized in that Before accessing the shared memory corresponding to the shared memory address, the method further includes: triggering a cyclic redundancy check (CRC) process of a firmware program of the dynamic random access memory controller to determine whether the firmware program is legal; If the firmware program is legal, the shared memory corresponding to the shared memory address is accessed to read the shared parameter information in the shared memory.

3. The method according to claim 1, characterized in that When the parameter type of the shared parameter information is a queue-jumping type, inserting the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller includes: In a case where the parameter type of the shared parameter information is a queue-jumping type, reading corresponding first identification information of the shared parameter information whose parameter type is a queue-jumping type; In response to the first identification information, determining a task queue of an NPU memory access request task in the dynamic random access memory controller; Insert the NPU memory access request task of the first identification information into the head position of the task queue.

4. The method according to claim 1, wherein When the parameter type of the shared parameter information is a preemptive type, interrupting the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller includes: In a case where the parameter type of the shared parameter information is a preemptive type, reading corresponding second identification information of the shared parameter information whose parameter type is a preemptive type; In response to the second identification information, determining a task queue of an NPU memory access request task in the dynamic random access memory controller; Interrupt the request task in the task queue.

5. The method according to claim 4, characterized in that After interrupting the request task in the task queue, the method further includes: The corresponding processing data of the processed request task is saved, and the current state of the dynamic random access memory controller is saved, so as to reprocess the request task after the NPU memory access request task is processed.

6. The method according to claim 1, characterized in that The method further comprises: Determining a load condition of the dynamic random access memory controller; If the load of the dynamic random access memory controller is greater than the preset load, the request task with a priority lower than the preset priority in the shared parameter information is suspended until the NPU memory access request task is processed and completed with priority.

7. A resource allocation device, characterized in that: The device comprises: The acquisition module is used to obtain the shared memory address passed by the central processing unit; An access module, configured to access the shared memory corresponding to the shared memory address to read shared parameter information in the shared memory, wherein the shared parameter information includes a parameter type, and the parameter type includes a queue-jumping type and a preemption type; an insertion module, configured to insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller when the parameter type of the shared parameter information is a queue insertion type, wherein the queue insertion type is used to indicate that the load of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or An interrupt module is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

8. A resource allocation system, characterized in that: The system includes: a processing unit, a shared memory and a monitoring unit; The shared memory is connected to the processing unit, and the shared memory is used to store shared parameter information; The monitoring unit is connected to the processing unit, and the monitoring unit is used to monitor the load status of the task queue of the dynamic random access memory controller; The processing unit is used to obtain the shared memory address transmitted by the central processing unit, and access the shared memory corresponding to the shared memory address to read the shared parameter information in the shared memory; The processing unit is configured to, when the parameter type of the shared parameter information is a queue-jumping type, insert the NPU memory access request task corresponding to the shared parameter information into the head position of the corresponding task queue in the dynamic random access memory controller, wherein the queue-jumping type is used to indicate that the load state of the task queue of the dynamic random access memory controller is less than a preset load, and the priority of the NPU memory access request task is higher than a preset priority; or The processing unit is used to interrupt the request task of the NPU memory access request task corresponding to the shared parameter information in the corresponding task queue of the dynamic random access memory controller when the parameter type of the shared parameter information is a preemption type, wherein the request task is a request task in the task queue with a priority lower than a preset priority, and the preemption type is used to characterize that the load state of the task queue of the dynamic random access memory controller is greater than the preset load, and the priority of the NPU memory access request task is higher than the preset priority.

9. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein: When the processor executes the computer program, the method according to claims 1 to 6 is implemented.

10. A vehicle, characterized in that: include: The resource allocation method according to any one of claims 1 to 6, or the apparatus according to claim 7, or the computer-readable storage medium according to claim 8, or the electronic device according to claim 9.

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