Methods, devices, computer equipment, and storage media for tuning memory timing parameters.

Abstract

This application discloses a method, apparatus, computer device, and storage medium for optimizing memory timing parameters, relating to the field of server memory technology. By establishing an automated closed-loop process of parameter configuration, signal measurement, condition verification, and parameter optimization, it dynamically correlates timing parameter combinations with memory interface signal quality. Based on actual measurement results, it accurately judges parameter suitability and drives a parameter optimization mechanism to automatically iterate and generate new candidate parameter combinations. This eliminates reliance on manual experience and overcomes the limitations of traditional methods, such as low efficiency and difficulty in handling dynamic changes in complex parameter spaces. Therefore, it solves the technical problems of low efficiency, poor suitability, and insufficient stability in existing memory timing parameter optimization technologies, achieving significant improvements in memory signal integrity, enhanced server operational stability, and increased energy efficiency of the memory subsystem.

Description

Technical Field

[0001] This application relates to the field of memory server technology, and in particular to methods, apparatus, computer equipment and storage media for optimizing memory timing parameters. Background Technology

[0002] In the rapidly growing data center ecosystem with its rapidly increasing computing power demands, memory signal integrity has become a core physical layer constraint determining the overall performance and stability of servers. The precision of memory timing parameter selection directly affects the signal quality margin, dynamic power efficiency, and system-level fault tolerance of memory channels. With the continuous improvement of DDR bus speeds and the introduction of new memory architectures such as 3D stacked memory, the number and complexity of memory timing parameters have increased significantly, making traditional parameter selection methods increasingly inadequate to meet the requirements.

[0003] Existing methods for selecting memory timing parameters have significant shortcomings. Coarse-grained tuning based on empirical rules relies on conservative timings, resulting in energy waste in high-frequency scenarios and failing to adapt to the dynamic balancing requirements under mixed loads. Brute-force searches lacking physical constraints are extremely inefficient in a vast parameter space and are prone to getting trapped in local optima. Static parameters struggle to cope with dynamic disturbances such as temperature drift, leading to decreased system stability over long-term operation. These issues all negatively impact the efficiency and accuracy of memory timing parameter tuning. Summary of the Invention

[0004] This application provides a method, apparatus, computer device, and storage medium for tuning memory timing parameters, in order to at least solve the problems in related technologies where coarse-grained tuning based on empirical rules is energy-inefficient and has poor adaptability, low search efficiency and prone to local optima, and static parameters are difficult to cope with dynamic interference, resulting in decreased stability and affecting the efficiency and accuracy of memory timing parameter tuning.

[0005] This application provides a method for tuning memory timing parameters, including:

[0006] Configure candidate timing parameter combinations for the memory controller in the server to be optimized, and obtain the candidate signal measurement results of the memory interface when the memory controller is running under the candidate timing parameter combinations;

[0007] Verify whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions;

[0008] If the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified. The configuration and verification operations are repeated until the target signal measurement result that meets the preset tuning conditions is output. The candidate timing parameter combination corresponding to the target signal measurement result is then used as the target timing parameter combination.

[0009] This application also provides a device for tuning memory timing parameters, including:

[0010] The configuration module is used to configure candidate timing parameter combinations for the memory controller in the server to be optimized, and to obtain the candidate signal measurement results of the memory interface when the memory controller runs under the candidate timing parameter combinations.

[0011] The verification module is used to verify whether the measurement results of candidate signals of the memory interface meet the preset tuning conditions.

[0012] The trigger module is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met. The configuration and verification operations are repeated until the target signal measurement result that meets the preset tuning conditions is output, and the candidate timing parameter combination corresponding to the target signal measurement result is used as the target timing parameter combination.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the above-described method for optimizing memory timing parameters when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described memory timing parameter tuning methods.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described memory timing parameter tuning methods.

[0016] This application establishes a complete closed-loop tuning mechanism encompassing parameter configuration, signal measurement, condition verification, and parameter optimization. This mechanism dynamically correlates parameter combinations with signal quality, accurately assesses parameter suitability based on actual measurement results, and automatically performs iterative optimization. This approach effectively avoids the limitations of traditional methods that rely on human experience, solves the problem of low tuning efficiency due to insufficient human experience, and overcomes the inability of traditional methods to handle dynamic changes. Therefore, it addresses the technical problems of low efficiency, poor suitability, and insufficient stability in memory timing parameter tuning in existing technologies, ultimately achieving significant improvements in memory signal quality, enhanced system stability, and increased energy efficiency. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating the method for optimizing memory timing parameters provided in this application embodiment;

[0019] Figure 2 A schematic diagram illustrating another method for tuning memory timing parameters provided in an embodiment of this application;

[0020] Figure 3 A schematic diagram of the structure of a memory timing parameter tuning system provided in an embodiment of this application;

[0021] Figure 4 A schematic diagram of the structure of the memory timing parameter tuning device provided in the embodiments of this application;

[0022] Figure 5 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0024] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0025] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The specific application environment architecture or specific hardware architecture on which the optimization methods for memory timing parameters depend is described here.

[0027] This embodiment provides a method for optimizing memory timing parameters. Figure 1 This is a flowchart of a memory timing parameter tuning method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0028] Step S101: Configure candidate timing parameter combinations for the memory controller in the server to be optimized, and obtain the candidate signal measurement results of the memory interface when the memory controller is running under the candidate timing parameter combinations.

[0029] In this embodiment, firstly, a parameter optimization mechanism (such as a Bayesian optimization algorithm or a trained deep neural network) generates a candidate timing parameter combination (i.e., a set of memory timing parameters to be tested, including key parameters such as tCL, tRCD, and tRP, whose value range is determined based on the debugging range in the debugging command); then, the scheduling PC transmits the candidate timing parameter combination to the baseboard management controller (BMC) of the server to be optimized via the Intelligent Platform Management Interface (IPMI) command. When the server to be optimized is powered on, the Basic Input / Output System (BIOS) obtains the candidate timing parameter combination from the BMC and writes it into the register of the memory controller (the hardware unit responsible for managing memory read and write operations), completing the parameter configuration; finally, the scheduling subsystem initiates signal integrity (Signal)... Integrity (SI) measurement tools are used to measure the memory interface (the signal transmission interface between the memory and the memory controller, including signal lines such as data signals (DQ) and address signals (Addr)). The measurement tools obtain data on whether each DQ / Addr signal can be effectively acquired under different delays under the candidate timing parameter combination. After analysis, the measurement results of candidate signals reflecting the signal quality are obtained (the core of which is the effective delay width of each signal, that is, the delay range in which the signal can stably acquire data).

[0030] Step S102: Verify whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions.

[0031] In this embodiment, multiple signals of the memory interface (such as DQ data signals, Addr address signals, etc.) are first extracted from the candidate signal measurement results. Then, the effective delay width of each signal (i.e., the delay range in which the signal can stably acquire data) is calculated, and it is verified whether it meets the corresponding delay characteristics. Specifically, the type of signal (such as DQ signal or Addr signal) is first determined, and then the delay threshold corresponding to the type of signal is found according to the preset correlation between the signal type and the preset delay threshold. It is then detected whether the delay threshold falls into the central region of the effective delay width (the central region refers to the middle 50% range of the effective delay width) to obtain the verification result of a single signal. Finally, based on the verification results of all signals, it is determined whether the preset tuning conditions are met (the preset tuning conditions refer to the minimum effective delay width requirement suggested by the memory controller designer or the qualified standard set according to the actual scenario requirements): if the effective delay width of all signals meets the corresponding delay characteristics (i.e., their respective delay thresholds all hit the central region), then the candidate signal measurement results are determined to meet the preset tuning conditions; if any signal does not meet the conditions, then it is determined that the conditions are not met.

[0032] In step S103, if the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified. The configuration and verification operations are repeated until the target signal measurement result that meets the preset tuning conditions is output. The candidate timing parameter combination corresponding to the target signal measurement result is used as the target timing parameter combination.

[0033] In this embodiment, if the verification result shows that the candidate signal measurement result does not meet the preset tuning conditions (i.e., the effective delay width of at least one memory interface signal does not meet the corresponding delay characteristics), the parameter optimization mechanism is triggered: First, the current candidate timing parameter combination and its corresponding candidate signal measurement result are added to the training dataset to form an updated training dataset; then, the target signal evaluation model (such as a deep neural network with a hybrid CNN-LSTM architecture) is retrained using the updated dataset to obtain an optimized target signal evaluation model; then, the next set of candidate timing parameter combinations to be verified is predicted and selected using the optimized model. Afterward, the process of configuring new candidate timing parameter combinations to the memory controller, obtaining the corresponding candidate signal measurement results, and verifying the new measurement results is repeated. This process is repeated until a verification result meets the preset tuning conditions. At this point, the signal measurement result that meets the conditions is determined as the target signal measurement result, and its corresponding candidate timing parameter combination is the target timing parameter combination (referring to a set of memory timing parameters that can be directly used for memory controller configuration and can guarantee signal integrity).

[0034] In this embodiment of the application, before configuring candidate timing parameter combinations to the server to be optimized, such as Figure 2 As shown, the method also includes:

[0035] Step S201: Detect debugging commands for the server to be optimized.

[0036] In this embodiment, the scheduling subsystem monitors in real time for debugging instructions targeting the server to be optimized (the server requiring memory timing parameter tuning) through preset interfaces (such as network communication interfaces, local command-line interfaces, or graphical user interfaces). Debugging instructions trigger the memory timing parameter tuning process and typically include key information such as the tuning objective (e.g., improving signal integrity, reducing power consumption), the tuning range of timing parameters (e.g., the value range of parameters such as tCL and tRCD), and the tuning termination condition (e.g., the maximum number of iterations, the target signal quality threshold). Upon detecting the instruction, the scheduling subsystem verifies its validity (e.g., whether the format is correct and whether it contains necessary parameters). If the verification is successful, the instruction content is recorded, providing a basis for subsequently initiating the parameter optimization mechanism.

[0037] Step S202: Based on the parameter optimization mechanism triggered by the debugging instruction, candidate timing parameter combinations are generated according to the debugging range of the timing parameter combinations in the debugging instruction.

[0038] In this embodiment, upon detecting a debugging instruction, a parameter optimization mechanism (a collaborative optimization mechanism integrating Bayesian optimization algorithm and deep learning model) is triggered based on the instruction. The specific process is as follows: First, the debugging range of the timing parameter combination in the debugging instruction is analyzed (i.e., the value range of timing parameters such as tCL, tRCD, and tRP, such as the ±50% safety margin of JEDEC standard timing). Then, based on the debugging range, an initial first timing parameter combination is generated within the range using a Bayesian optimization algorithm (based on a Gaussian process model). After being configured into the memory controller, the corresponding first signal measurement result is obtained. Then, the second timing parameter combination and signal result are iteratively predicted and verified until a training dataset containing a sufficient number of parameter-signal mapping relationships is formed. Next, the initial signal evaluation model (an untrained 1DCNN and LSTM hybrid architecture model) is trained using this training dataset to obtain a target signal evaluation model that can evaluate signal quality. Finally, the target signal evaluation model scores the signal quality of the parameter combinations in the training dataset, and the parameter combinations with higher scores are selected as candidate timing parameter combinations.

[0039] By detecting debugging commands, we can accurately respond to the tuning needs of the server to be optimized, ensuring that the tuning direction is consistent with the actual tuning goals. By generating candidate timing parameter combinations based on the debugging range in the debugging commands, we can avoid the blindness of parameter exploration, reduce invalid parameter configurations, and thus improve the targeting and initial efficiency of memory timing parameter tuning.

[0040] In this embodiment of the application, generating candidate timing parameter combinations based on the debugging range of timing parameter combinations in the debugging instructions includes the following steps A1-A3:

[0041] Step A1: Analyze the debugging range of timing parameter combinations in the debugging instructions.

[0042] Specifically, the instruction parsing module in the scheduling subsystem performs structured parsing on the acquired debugging instructions, extracting the debugging range of the timing parameter combinations contained therein—that is, clarifying the allowed value ranges (such as minimum and maximum values) of various timing parameters such as tCL (CAS Latency), tRCD (RAS-to-CASDelay), and tRP (RAS Precharge Time). During the parsing process, the legality of each parameter range needs to be verified to ensure that it does not exceed the limits specified by the memory hardware specifications (e.g., tCL must not be less than the minimum latency supported by the memory chip), and the parsing results are converted into boundary conditions of the parameter space (e.g., tCL∈[30T,50T], tRCD∈[35T,45T]), providing a constraint basis for subsequently generating timing parameter combinations within this range (e.g., selecting the first timing parameter combination in step A21).

[0043] Step A2: Construct a training dataset based on the debugging range, and use the training dataset to train the initial signal evaluation model to obtain the target signal evaluation model.

[0044] Specifically, based on the debugging range (the range of time-series parameter values) obtained through analysis, a training dataset is first constructed: Within the debugging range, a first combination of time-series parameters is selected using a Bayesian optimization algorithm, configured into the memory controller of the server to be optimized, and the corresponding first signal measurement result is obtained. Then, a Gaussian process model is constructed based on the first parameter combination and the first signal result to predict the next set of second time-series parameter combinations. This iterative process of configuration, measurement, and prediction is repeated until the preset sampling conditions are met, forming a training dataset (containing the mapping relationship between time-series parameter combinations and corresponding signal measurement results). Subsequently, this training dataset is used to train the initial signal evaluation model (an untrained 1D convolutional neural network and long short-term memory network hybrid architecture used to evaluate signal quality): The network parameters (such as CNN convolutional kernel weights and LSTM hidden layer parameters) are adjusted using a backpropagation algorithm to minimize the loss function (such as mean square error and quantile loss weighted sum) between the model's output signal quality score and the actual signal measurement results, ultimately obtaining a target signal evaluation model that can accurately evaluate signal quality.

[0045] In this embodiment of the application, the training dataset is constructed based on the debugging range, including the following steps A21-A24:

[0046] Step A21: Select the first timing parameter combination within the debugging range.

[0047] Specifically, within the debugging range (i.e., the allowed value range of each timing parameter, such as tCL∈[30T,50T], tRCD∈[35T,45T]), the initial sampling module of the Bayesian optimization algorithm selects the first combination of timing parameters (referring to the first set of memory timing parameters when constructing the training dataset, including key parameters such as tCL, tRCD, and tRP). A random sampling strategy is used during selection, randomly generating specific values ​​from the value range of each parameter, while removing the minimum and maximum values ​​within the range (to avoid signal quality anomalies that may be caused by extreme values). If specific prior knowledge is preset (such as parameter values ​​that performed well in historical optimization), then values ​​near the prior knowledge will be prioritized for selection, ensuring that the first combination of timing parameters is within the safe operating range of the hardware, providing a foundation for subsequent configuration and signal measurement.

[0048] Step A22: Configure the first timing parameter combination to the memory controller in the server to be optimized, and obtain the first signal measurement result of the memory interface when the memory controller is running under the first timing parameter combination.

[0049] Specifically, firstly, the scheduling module transmits the selected first timing parameter combination (an initial set of memory timing parameters) to the baseboard management controller of the server to be optimized via intelligent platform management commands. After the server to be optimized is powered on, the basic input / output system obtains the first timing parameter combination from the baseboard management controller through the in-band intelligent platform management interface and writes it into the memory controller, completing the parameter configuration. Subsequently, the scheduling subsystem starts the SI measurement tool to measure the memory interface signals: by detecting whether each memory interface signal can be effectively acquired at different delays relative to the clock signal, the delay range in which the signal can be stably acquired is recorded, and after extraction by the analysis program, the first signal measurement result corresponding to the first timing parameter combination is obtained (the core is the effective delay width of each signal, i.e., the quantitative indicator of signal quality).

[0050] Step A23: Construct a Gaussian process model based on the first combination of time-series parameters and the first signal measurement results, and predict the next set of second combination of time-series parameters to be debugged through the Gaussian process model.

[0051] In this embodiment of the application, constructing a Gaussian process model based on a first combination of time-series parameters and a first signal measurement result includes: establishing an initial Gaussian process model based on the first combination of time-series parameters and the first signal measurement result; configuring the stochastic dynamic characteristics between each time-series parameter in the first combination of time-series parameters and the preset acquisition strategy of the time-series parameters in the initial Gaussian process model to obtain the Gaussian process model.

[0052] An initial Gaussian process model is established based on the first time series parameter combination and results, providing a basic framework for parameter prediction. The stochastic dynamic characteristics between parameters are configured to make the model more consistent with the dynamic changes of parameters during memory operation. The preset acquisition strategy can guide the model to efficiently explore the parameter space, and the resulting Gaussian process model has higher prediction accuracy and stronger practicality.

[0053] The initial Gaussian process model is established based on the first time series parameter combination and the first signal measurement result, including: establishing a parameter space and a corresponding index space based on the debugging range in the debugging instruction; writing the first time series parameter combination into the parameter space, writing the first signal measurement result into the index space, and establishing a probabilistic mapping between the parameter space and the index space according to the mapping relationship between the first time series parameter combination and the first signal measurement result, so as to obtain the initial Gaussian process model.

[0054] Based on the debugging range, parameter space and index space are established to make the correspondence between parameters and signal results more structured and clear. Data is written into the space and a probabilistic mapping is established to quantify the uncertainty relationship between parameters and signal results, so that the initial Gaussian process model has probabilistic prediction capability and provides a scientific mathematical basis for subsequent parameter prediction.

[0055] Specifically, firstly, a parameter space (the set of value intervals for each timing parameter) and a corresponding index space (the set of ranges for signal measurement results) are established based on the debugging range specified in the debugging instructions. The first combination of timing parameters is written into the parameter space, and the first signal measurement results (such as the effective delay width of each signal) are written into the index space. A probabilistic mapping between the parameter space and the index space is established according to their mapping relationship (i.e., describing the correlation between parameter combinations and signal quality through probability distribution), resulting in an initial Gaussian process model. Subsequently, the initial model is configured with the stochastic dynamic characteristics of each parameter in the first combination of timing parameters (the dynamic correlation characteristics between parameters that change with the environment or themselves, such as the coupling relationship between tRCD and tWR) and a preset acquisition strategy (a strategy used to balance the "exploration" and "utilization" of the parameter space, such as a hybrid strategy of expected improvement in EI and probabilistic improvement in PI), forming a complete Gaussian process model. Afterward, the preset acquisition strategy in the model is invoked to select the parameter combination with the greatest potential for signal quality improvement from the parameter space as the next set of timing parameter combinations to be debugged.

[0056] In this embodiment of the application, predicting the next set of second time series parameter combinations to be debugged using a Gaussian process model includes: calling a preset acquisition strategy in the Gaussian process model; and using the preset acquisition strategy to filter out the next set of second time series parameter combinations to be debugged from the parameter space in the Gaussian process model.

[0057] Specifically, firstly, the pre-configured acquisition strategy in the Gaussian process model is invoked (referring to the rules used to balance the "exploration" and "utilization" of the parameter space, such as a hybrid strategy that integrates expected improvement in EI and probabilistic improvement in PI, where EI is used to evaluate the potential benefit of parameter combinations in improving signal quality, and PI is used to evaluate the probability of improving signal quality). Then, the parameter space of the Gaussian process model (the set of value intervals of each time series parameter) is evaluated using this pre-configured acquisition strategy, and the comprehensive "exploration-utilization" score of each potential parameter combination is calculated. Parameter combinations with high potential for signal quality improvement (high EI value) and high uncertainty (unknown areas to be explored) are selected first and determined as the second set of time series parameter combinations to be debugged, so as to improve the tuning efficiency while avoiding getting trapped in local optima.

[0058] Calling the preset acquisition strategy can give parameter screening a clear optimization goal and direction; using the strategy to screen the second time series parameter combination from the parameter space can prioritize the parameter combination with the most exploration value for testing, avoid invalid parameter attempts, improve parameter exploration efficiency, and speed up the construction of the training dataset.

[0059] Step A24: Configure the second timing parameter combination to the memory controller in the server to be optimized, obtain the second signal measurement results of the memory interface when the memory controller is running under the second timing parameter combination, iteratively execute parameter prediction and configuration operations until the preset sampling conditions are reached, and generate a training dataset using the mapping relationship between the timing parameter combination and the measurement results.

[0060] Specifically, firstly, following the same configuration process as step A22, the second timing parameter combination predicted by the Gaussian process model in step A23 is written to the memory controller register of the server to be optimized via the BMC and BIOS using IPMI commands. Then, the SI measurement tool is started to measure the memory interface signals, and the SI analysis program extracts the second signal measurement results corresponding to this parameter combination (the core being the effective delay width of each DQ / Addr signal). Next, the operation of predicting new timing parameter combinations using the Gaussian process model, configuring them to the memory controller, and obtaining the corresponding signal measurement results is iteratively executed until the preset sampling conditions are met (e.g., the number of mapping relationships between parameter combinations and measurement results reaches 100 sets, or the improvement in signal quality indicators is less than 1% for 5 consecutive times). Finally, all timing parameter combinations generated during the iteration process and their corresponding signal measurement results are compiled into a dataset containing mapping relationships, i.e., a training dataset is generated.

[0061] Within the debugging range, the first combination of time-series parameters is selected and the corresponding signal results are obtained to provide initial data support for model construction. Based on the initial data, a Gaussian process model is constructed, which can effectively capture the nonlinear relationship between parameters and signals. By predicting the second combination of time-series parameters through the model and iteratively sampling, the parameter space can be explored efficiently within a limited range, avoiding redundant testing. The final training dataset is more representative and comprehensive, laying a high-quality data foundation for subsequent model training.

[0062] Step A3: Use the target signal evaluation model to determine the candidate time series parameter combinations.

[0063] Analyzing the debugging range can clarify the boundaries of parameter exploration, providing a precise direction for subsequent optimization; building a training dataset based on the debugging range and training the target signal evaluation model can learn the correlation between parameters and signals in a data-driven manner, improving the scientific nature of parameter evaluation; using the target signal evaluation model to determine candidate combinations can reduce reliance on human experience, improve the quality and screening efficiency of candidate parameters, and accelerate the optimization process.

[0064] In this embodiment of the application, candidate time series parameter combinations are determined using a target signal evaluation model, including the following steps A31-A33:

[0065] Step A31: Convert the mapping relationships in the training dataset into feature vectors.

[0066] Specifically, numerical features of key parameters such as tCL and tRCD are extracted from the combination of timing parameters; from the signal measurement results, the time-domain statistical features (such as eye height, eye width, and Q factor) and frequency-domain features (such as noise power spectral density) of the signal eye diagram are extracted through sliding window sampling (window length 1000ns, step size 50ns), while incorporating the effective delay width (margin) features of each DQ / Addr signal; these extracted features are integrated and standardized according to a preset dimension (such as 32 dimensions) to form a feature vector that can be input into a deep neural network, realizing the numerical expression of the mapping relationship.

[0067] Step A32: Use the target signal evaluation model to evaluate each feature vector and obtain the signal quality score of each feature vector.

[0068] In this embodiment of the application, the target signal evaluation model is used to evaluate each feature vector to obtain the signal quality score of each mapping relationship, including: extracting local signal features and time-dependent features from the feature vector; analyzing the local signal features and time-dependent features to obtain the analysis results; and determining the signal quality score of the feature vector based on the analysis results.

[0069] Specifically, a target signal evaluation model composed of a 1D convolutional neural network (CNN) and a long short-term memory network (LSTM) is used to evaluate the feature vector. First, local signal features (such as impulse response spikes, noise spikes, and other local signal patterns) are extracted from the feature vector through CNN layers (using multi-scale convolutional kernels such as 3×1 and 5×1). Then, LSTM layers (containing 256 hidden units) capture the temporal dependent features in the feature vector (such as the temporal correlation between parameters like the dynamic interaction effect between tCL and tRCD). Subsequently, the model fuses and analyzes the extracted local signal features and temporal dependent features, and combines the mapping calculation of the fully connected layers to obtain the signal quality score corresponding to the feature vector (this score is formed based on big data training and reflects the comprehensive signal quality of the mapping relationship between the combination of temporal parameters and the signal measurement results).

[0070] Extracting local features of a signal can capture its detailed characteristics, while extracting time-dependent features can reflect the correlation patterns of the signal over time. Combining the two makes feature analysis more comprehensive. Analyzing features can delve into the mechanisms by which parameters affect signal quality. Determining scores based on the analysis results can make the scores more closely match the actual signal performance, thereby improving the accuracy and reliability of model evaluation.

[0071] Step A33: Select candidate combinations of time-series parameters from the training dataset based on signal quality scores.

[0072] Specifically, a screening threshold for signal quality scores is set (this threshold can be determined based on the margin range set by the memory controller and actual needs, such as not lower than 80 points). Timing parameter combinations in the training dataset that have signal quality scores that reach or exceed this threshold are selected as candidate timing parameter combinations. The signal measurement results corresponding to these combinations (such as the effective delay width of each DQ / Addr signal) must meet the preset standards (at least the minimum recommended value set by the memory controller).

[0073] Converting the mapping relationship into feature vectors facilitates the model's quantification of the correlation between parameters and signals; using the target signal to evaluate the model and obtain a signal quality score allows for an objective quantitative assessment of the effect of parameter combinations; and selecting candidate combinations based on the score can accurately retain high-quality parameter combinations, reduce the verification cost of low-quality parameters, and improve the accuracy and efficiency of optimization.

[0074] In this embodiment of the application, verifying whether the candidate signal measurement results meet the preset tuning conditions includes the following steps B1-B3:

[0075] Step B1: Extract multiple memory interface signals from the candidate signal measurement results.

[0076] Specifically, multiple signals of the memory interface are extracted from the candidate signal measurement results corresponding to the candidate timing parameter combinations. These signals are specifically the DQ signal (data signal) and Addr signal (address signal) specified in the memory specification standard (Spec). The extraction is based on the quality characteristics such as the effective delay width (Margin) of each signal obtained after the measurement records obtained by the SI measurement tool are processed by the SI analysis program. By screening out these DQ / Addr signals that meet the signal quality standards under the candidate combinations, a set of multiple memory interface signals for subsequent analysis is formed.

[0077] Step B2: Calculate the effective delay width of the memory interface signal and verify whether the effective delay width of the memory interface signal meets the corresponding delay characteristics, and obtain the verification result.

[0078] Specifically, the effective delay width of the memory interface signal is first calculated. This width refers to the delay range within which the memory interface signal can stably acquire data under different delays relative to the clock signal. This is determined by analyzing the measurement data of the memory interface signal using the SI analysis program. Next, it is verified whether this effective delay width meets the corresponding delay characteristics. These delay characteristics are determined based on the correlation between preset signal types and preset delay thresholds, representing the delay standard that the memory interface signal should meet. In the specific verification process, the signal type of the memory interface signal is first obtained, then the corresponding delay threshold is found based on the correlation, and finally, it is checked whether this delay threshold hits the center region of the effective delay width. If it does, the verification result is satisfactory; otherwise, it is unsatisfactory.

[0079] In this embodiment of the application, verifying whether the effective delay width of the memory interface signal meets the corresponding delay characteristics and obtaining the verification result includes the following steps B21-B23:

[0080] Step B21: Obtain the signal type of the memory interface signal.

[0081] Specifically, the signal type of the memory interface signal is obtained. The signal type refers to the category of the memory interface signal according to its function and role, such as data signals (DQ signal) and address signals (Addr signal). Specifically, the signal type of each memory interface signal is determined by parsing the classification definition of memory interface signals in the memory specification and combining the identification information of each signal (such as signal name, transmission content characteristics, etc.) in the candidate signal measurement results obtained by the SI measurement tool.

[0082] Step B22: Determine the delay threshold corresponding to the signal type based on the correlation between the preset signal type and the preset delay threshold.

[0083] Specifically, preset signal types refer to predefined memory interface signal categories (such as DQ signals, Addr signals, etc.); preset delay thresholds are benchmark values ​​set for different signal types to measure whether the effective delay width meets the standard, usually determined based on the pre-set margin range of the memory controller and the actual application scenario requirements; the association relationship refers to a pre-established correspondence that maps each preset signal type to its corresponding preset delay threshold (which can be stored as a mapping table or database). After obtaining the signal type of the memory interface signal, querying this association relationship will yield the preset delay threshold corresponding to that signal type.

[0084] Step B23: Verify the effective delay width based on the delay threshold to obtain the verification result.

[0085] Obtaining signal type can clarify the characteristic differences of different signals; determining the corresponding delay threshold based on the correlation makes the threshold setting more in line with the actual needs of different signals and avoids the irrationality of a uniform threshold; verifying the effective delay width with the threshold as a benchmark can improve the pertinence and accuracy of the verification and ensure that the signal evaluation meets its own characteristic requirements.

[0086] In this embodiment of the application, the effective delay width is verified based on the delay threshold to obtain the verification result, including: detecting whether the delay threshold hits the center region of the effective delay width; if it hits the center region of the effective delay width, the verification result is determined to be that the effective delay width meets the delay characteristics; or, if it does not hit the center region of the effective delay width, the verification result is determined to be that the effective delay width does not meet the delay characteristics.

[0087] Specifically, the effective delay width is verified based on a delay threshold. The central region refers to the middle part of the effective delay width (the center position can be determined by calculating the average of the starting and ending values ​​of the effective delay width; the central region is usually a certain range based on this center position). During verification, it is checked whether the delay threshold falls within the central region of the effective delay width. If it does, the effective delay width is determined to meet the delay characteristics, and the verification result is passed; if it does not, the effective delay width is determined to not meet the delay characteristics, and the verification result is failed.

[0088] By detecting whether the latency threshold hits the center region of the effective latency width, it can be determined whether the signal has sufficient timing margin. If it hits the center region, it is determined that the latency characteristics are met, which can ensure that the signal has strong anti-interference ability during operation, reduce errors caused by timing fluctuations, and improve the stability of memory operation. If it does not hit the center region, it is determined that the latency characteristics are not met, which can promptly identify signals with insufficient timing margin, avoid using parameter combinations that may lead to signal instability, thereby eliminating memory operation risks in advance and ensuring the reliability of the server memory system.

[0089] Step B3: If the verification result shows that the effective delay width of each memory interface signal meets the corresponding delay characteristics, then the candidate signal measurement result is determined to meet the preset tuning conditions; or, if the verification result shows that the effective delay width of any memory interface signal does not meet the corresponding delay characteristics, then the candidate signal measurement result is determined to not meet the preset tuning conditions.

[0090] Extracting multiple memory interface signals allows for a comprehensive assessment of memory operation status, avoiding the limitations of evaluating a single signal. Calculating the effective delay width quantifies the timing margin of the signal, and verifying whether it meets the delay characteristics can accurately determine whether the signal quality meets the standards. Based on the verification results, it can be determined whether the tuning conditions are met, making the tuning judgment more objective and accurate, and ensuring the effectiveness of the tuning results.

[0091] Specifically, after all memory interface signals have been verified, if the verification results show that the effective delay width meets the corresponding delay characteristics (i.e., the delay threshold of each signal hits the center region of its effective delay width), then the measurement result of the candidate signal is determined to meet the preset tuning conditions. The preset tuning conditions refer to the standards pre-set by the system for judging whether the measurement results of candidate signals meet the criteria, which must be met by all memory interface signals through verification. If, in the verification results of all memory interface signals, the effective delay width of one or more signals does not meet the corresponding delay characteristics (i.e., the delay threshold of that signal does not hit the center region of its effective delay width), then the measurement result of that candidate signal is determined to have not met the preset tuning conditions, and further parameter optimization is required.

[0092] When the effective delay width of all memory interface signals meets the corresponding delay characteristics, the tuning conditions are met. This ensures that all critical signals of the memory system are in a stable state, preventing local signal problems from affecting overall memory performance and guaranteeing the comprehensive reliability of the tuning results. Conversely, if any memory interface signal does not meet the delay characteristics, the tuning conditions are not met. This allows for strict control of signal quality, timely elimination of parameter combinations with potential problems, and prevention of memory errors or performance degradation due to individual signal anomalies, ensuring the rigor of the tuning process.

[0093] In this embodiment of the application, the trigger parameter optimization mechanism generates the next set of candidate timing parameter combinations to be verified, including the following steps C1-C3:

[0094] Step C1: Add the candidate time series parameter combinations and candidate signal measurement results to the training dataset to obtain the updated training dataset.

[0095] Specifically, candidate timing parameter combinations (the set of memory timing parameters to be verified) and corresponding candidate signal measurement results (signal measurement data of the memory interface under the parameter combination) are added to the existing training dataset (the set of timing parameters and measurement results used to train the signal evaluation model), thereby forming an updated training dataset, which provides richer training data for subsequent model optimization.

[0096] Step C2: Train the target signal evaluation model based on the updated training dataset to obtain the optimized target signal evaluation model.

[0097] Specifically, the target signal evaluation model (the model initially trained to evaluate signal quality) is retrained based on the updated training dataset. During training, the model parameters are adjusted using the backpropagation algorithm, enabling the model to more accurately learn the mapping relationship between time-series parameters and signal measurement results. Ultimately, an optimized target signal evaluation model is obtained, improving its prediction accuracy.

[0098] Step C3: Use the optimized target signal evaluation model to determine the next set of candidate timing parameter combinations to be verified.

[0099] Specifically, the optimized target signal evaluation model is used to evaluate the combination of time-series parameters in the parameter space. The model outputs the signal quality-related prediction results of each combination based on the learned mapping relationship. Based on this, a set of time-series parameter combinations with high signal quality potential is selected as the next set of candidate time-series parameter combinations to be verified, thus promoting the continuous optimization process.

[0100] Adding candidate combinations and signal results to the training dataset can enrich the diversity and timeliness of the dataset; optimizing the target signal evaluation model based on the updated dataset can enable the model to continuously learn new parameter-signal correlation patterns and improve prediction accuracy; using the optimized model to determine the next set of candidate combinations can make parameter exploration more targeted, accelerate the finding of the optimal time series parameter combination, and improve the overall tuning efficiency.

[0101] Embodiments of this application also provide a memory timing parameter tuning system, such as... Figure 3 As shown, it includes: servers to be optimized and equipment to be tuned;

[0102] The server to be optimized is used to receive candidate timing parameter combinations sent by the tuning device, load the parameter combination through the memory controller and run it, and at the same time feed back the signal measurement results of the memory interface to the tuning device. Finally, the memory configuration is completed based on the target timing parameter combination determined by the tuning device.

[0103] The tuning equipment is used to generate candidate timing parameter combinations and send them to the server to be optimized. It receives and analyzes the signal measurement results fed back by the server to be optimized, and iteratively optimizes the parameter combinations through a parameter optimization mechanism until the target timing parameter combination that meets the preset tuning conditions is determined.

[0104] The server to be optimized includes: a baseboard management controller and a basic input / output module;

[0105] The baseboard management controller is used to receive candidate timing parameter combinations sent by the tuning equipment, configure them into the memory controller, monitor the operating status of the memory controller, collect raw signal data of the memory interface and feed it back to the tuning equipment.

[0106] The basic input / output module provides low-level hardware interface support for the parameter configuration of the memory controller, initializes the memory operating environment, and ensures that candidate timing parameter combinations can be correctly loaded and executed by the memory controller.

[0107] The tuning equipment includes: a parameter generation module, a signal measurement module, a signal analysis module, and a target signal evaluation model;

[0108] The parameter generation module is used to parse the debugging range of timing parameters based on debugging instructions and trigger the parameter optimization mechanism; it predicts and generates candidate timing parameter combinations through a Gaussian process model, updates the training dataset in conjunction with signal measurement results during the iteration process, and generates the next set of parameter combinations to be verified.

[0109] The signal measurement module is used to receive the raw signal data fed back by the server to be optimized, preprocess it, and generate standardized candidate signal measurement results.

[0110] The signal analysis module is used to verify whether the measurement results of candidate signals meet the preset optimization conditions: extract the effective delay width of the memory interface signal, match the corresponding delay threshold according to the signal type, verify whether the effective delay width hits the center area of ​​the threshold, and determine whether the optimization conditions are met based on the verification results.

[0111] The target signal evaluation model is trained on a training dataset. It converts the mapping relationship between time series parameter combinations and signal measurement results into feature vectors, extracts and analyzes local signal features and time-dependent features, and outputs a signal quality score. Based on the score, it selects candidate time series parameter combinations from the training dataset and optimizes the model performance in iterations using updated training datasets.

[0112] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0113] Embodiments of this application also provide a memory timing parameter tuning device, such as... Figure 4 As shown, it includes:

[0114] Configuration module 41 is used to configure candidate timing parameter combinations for the memory controller in the server to be optimized, and to obtain the candidate signal measurement results of the memory interface when the memory controller is running under the candidate timing parameter combinations.

[0115] Verification module 42 is used to verify whether the measurement results of candidate signals of the memory interface meet the preset tuning conditions;

[0116] The trigger module 43 is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met, and to repeatedly perform the configuration and verification operations until the target signal measurement result that meets the preset tuning conditions is output, and the candidate timing parameter combination corresponding to the target signal measurement result is used as the target timing parameter combination.

[0117] Furthermore, the device also includes:

[0118] The detection module is used to detect debugging commands for the server to be optimized.

[0119] The generation module is used to trigger the parameter optimization mechanism based on the debugging instructions and generate candidate timing parameter combinations according to the debugging range of timing parameter combinations in the debugging instructions.

[0120] Furthermore, the generation module includes:

[0121] The parsing submodule is used to parse the debugging range of timing parameter combinations in debugging instructions;

[0122] The training submodule is used to build a training dataset based on the debugging range and use the training dataset to train the initial signal evaluation model to obtain the target signal evaluation model.

[0123] The first determination submodule is used to determine candidate combinations of timing parameters using the target signal evaluation model.

[0124] Furthermore, the training submodule includes:

[0125] The selection unit is used to select the first timing parameter combination within the debugging range;

[0126] The configuration unit is used to configure a first timing parameter combination to the memory controller in the server to be optimized, and to obtain the first signal measurement result of the memory interface when the memory controller is running under the first timing parameter combination.

[0127] The construction unit is used to construct a Gaussian process model based on the first combination of time-series parameters and the first signal measurement results, and to predict the next set of second combination of time-series parameters to be debugged through the Gaussian process model.

[0128] The generation unit is used to configure the second timing parameter combination to the memory controller in the server to be optimized, obtain the second signal measurement result of the memory interface when the memory controller is running under the second timing parameter combination, iteratively execute parameter prediction and configuration operations until the preset sampling conditions are reached, and generate a training dataset using the mapping relationship between the timing parameter combination and the measurement results.

[0129] Furthermore, a construction unit is used to establish an initial Gaussian process model based on the first combination of time-series parameters and the measurement results of the first signal; in the initial Gaussian process model, the stochastic dynamic characteristics between each time-series parameter in the first combination of time-series parameters and the preset acquisition strategy of the time-series parameters are configured to obtain the Gaussian process model.

[0130] Furthermore, the construction unit is also used to establish a parameter space and a corresponding index space based on the debugging range in the debugging instructions; write the first time-series parameter combination into the parameter space, write the first signal measurement result into the index space, and establish a probabilistic mapping between the parameter space and the index space according to the mapping relationship between the first time-series parameter combination and the first signal measurement result to obtain the initial Gaussian process model.

[0131] Furthermore, the sub-modules are identified, including:

[0132] Transformation unit, used to convert the mapping relationships in the training dataset into feature vectors;

[0133] The evaluation unit is used to evaluate each feature vector using the target signal evaluation model and obtain the signal quality score of each feature vector.

[0134] The filtering unit is used to select candidate combinations of time-series parameters from the training dataset based on signal quality scores.

[0135] Furthermore, the evaluation unit is used to extract local signal features and time-dependent features from the feature vector; analyze the local signal features and time-dependent features to obtain analysis results; and determine the signal quality score of the feature vector based on the analysis results.

[0136] Furthermore, the verification module 42 includes:

[0137] The extraction submodule is used to extract multiple memory interface signals from the candidate signal measurement results;

[0138] The calculation submodule is used to calculate the effective delay width of the memory interface signal and verify whether the effective delay width of the memory interface signal meets the corresponding delay characteristics, and obtain the verification result.

[0139] The second determining submodule is used to determine whether the candidate signal measurement results meet the preset tuning conditions based on the verification results. If the verification results show that the effective delay width of each memory interface signal meets the corresponding delay characteristics, then the candidate signal measurement results meet the preset tuning conditions. Alternatively, if the verification results show that the effective delay width of any memory interface signal does not meet the corresponding delay characteristics, then the candidate signal measurement results do not meet the preset tuning conditions.

[0140] Furthermore, the computation submodule also includes:

[0141] The acquisition unit is used to acquire the signal type of the memory interface signal;

[0142] The matching unit is used to determine the delay threshold corresponding to the signal type based on the correlation between the preset signal type and the preset delay threshold;

[0143] The verification unit is used to verify the effective delay width based on the delay threshold and obtain the verification result.

[0144] Furthermore, the verification unit is used to detect whether the delay threshold hits the center region of the effective delay width; if it hits the center region of the effective delay width, the verification result is determined to be that the effective delay width meets the delay characteristics; or, if it does not hit the center region of the effective delay width, the verification result is determined to be that the effective delay width does not meet the delay characteristics.

[0145] Furthermore, the trigger module 43 is used to add the candidate time series parameter combinations and candidate signal measurement results to the training dataset to obtain an updated training dataset; to train the target signal evaluation model based on the updated training dataset to obtain an optimized target signal evaluation model; and to use the optimized target signal evaluation model to determine the next set of candidate time series parameter combinations to be verified.

[0146] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 5As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0147] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0148] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0149] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0150] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0151] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0152] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0153] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for optimizing memory timing parameters, characterized in that, include: Configure candidate timing parameter combinations for the memory controller in the server to be optimized, and obtain candidate signal measurement results of the memory interface when the memory controller is running under the candidate timing parameter combinations; Verify whether the candidate signal measurement results of the memory interface meet the preset tuning conditions; If the preset tuning conditions are not met, the parameter optimization mechanism is triggered to generate the next set of candidate timing parameter combinations to be verified. The configuration and verification operations are repeated until the target signal measurement result that meets the preset tuning conditions is output. The candidate timing parameter combination corresponding to the target signal measurement result is taken as the target timing parameter combination. Before configuring candidate timing parameter combinations to the server to be optimized, the method further includes: detecting debugging instructions for the server to be optimized; triggering a parameter optimization mechanism based on the debugging instructions, and generating candidate timing parameter combinations according to the debugging range of the timing parameter combinations in the debugging instructions; wherein, generating candidate timing parameter combinations according to the debugging range of the timing parameter combinations in the debugging instructions includes: parsing the debugging range of the timing parameter combinations in the debugging instructions; constructing a training dataset based on the debugging range, and training an initial signal evaluation model using the training dataset to obtain a target signal evaluation model; and determining candidate timing parameter combinations using the target signal evaluation model. The step of constructing a training dataset based on the debugging range includes: selecting a first combination of timing parameters within the debugging range; configuring the first combination of timing parameters on the memory controller in the server to be optimized, and obtaining the first signal measurement result of the memory interface when the memory controller is running under the first combination of timing parameters; constructing a Gaussian process model based on the first combination of timing parameters and the first signal measurement result, and predicting the next second combination of timing parameters to be debugged through the Gaussian process model; configuring the second combination of timing parameters on the memory controller in the server to be optimized, and obtaining the second signal measurement result of the memory interface when the memory controller is running under the second combination of timing parameters, iteratively executing parameter prediction and configuration operations until a preset sampling condition is reached, and generating a training dataset using the mapping relationship between the combination of timing parameters and the measurement results.

2. The method according to claim 1, characterized in that, The step of determining candidate time series parameter combinations using the target signal evaluation model includes: Convert the mapping relationships in the training dataset into feature vectors; The target signal evaluation model is used to evaluate each of the feature vectors to obtain a signal quality score for each feature vector. Candidate combinations of time-series parameters are selected from the training dataset based on the signal quality score.

3. The method according to claim 2, characterized in that, The step of evaluating each feature vector using the target signal evaluation model to obtain a signal quality score for each feature vector includes: Extract the signal local features and time-dependent features from the feature vector; The local features of the signal and the time-dependent features are analyzed to obtain the analysis results; The signal quality score of the feature vector is determined based on the analysis results.

4. The method according to claim 1, characterized in that, The construction of the Gaussian process model based on the first combination of time-series parameters and the first signal measurement result includes: An initial Gaussian process model is established based on the first combination of timing parameters and the first signal measurement results; The initial Gaussian process model is obtained by configuring the stochastic dynamic characteristics between each time series parameter in the first time series parameter combination and the preset acquisition strategy of the time series parameters in the initial Gaussian process model.

5. The method according to claim 4, characterized in that, The establishment of the initial Gaussian process model based on the first combination of time-series parameters and the first signal measurement result includes: Establish a parameter space and a corresponding index space based on the debugging range in the debugging instructions; The first time series parameter combination is written into the parameter space, the first signal measurement result is written into the index space, and a probabilistic mapping between the parameter space and the index space is established according to the mapping relationship between the first time series parameter combination and the first signal measurement result to obtain the initial Gaussian process model.

6. The method according to claim 1, characterized in that, The verification of whether the candidate signal measurement results meet the preset optimization conditions includes: Extract multiple memory interface signals from the candidate signal measurement results; Calculate the effective delay width of the memory interface signal and verify whether the effective delay width of the memory interface signal meets the corresponding delay characteristics, and obtain the verification result; If the verification result is that the effective delay width of each memory interface signal meets the corresponding delay characteristics, then the candidate signal measurement result is determined to meet the preset tuning conditions; or, if the verification result is that the effective delay width of any memory interface signal does not meet the corresponding delay characteristics, then the candidate signal measurement result is determined to not meet the preset tuning conditions.

7. The method according to claim 6, characterized in that, The verification process, which verifies whether the effective delay width of the memory interface signal meets the corresponding delay characteristics and obtains the verification result, includes: Obtain the signal type of the memory interface signal; The delay threshold corresponding to the signal type is determined based on the correlation between the preset signal type and the preset delay threshold; The effective delay width is verified based on the delay threshold, and the verification result is obtained.

8. The method according to claim 7, characterized in that, The verification of the effective delay width based on the delay threshold, to obtain the verification result, includes: Detect whether the delay threshold hits the center region of the effective delay width; If the center region of the effective delay width is hit, the verification result is determined to be that the effective delay width satisfies the delay feature; or, if the center region of the effective delay width is not hit, the verification result is determined to be that the effective delay width does not satisfy the delay feature.

9. The method according to claim 1, characterized in that, The trigger parameter optimization mechanism generates the next set of candidate timing parameter combinations to be verified, including: The candidate time series parameter combination and the candidate signal measurement results are added to the training dataset to obtain the updated training dataset. The target signal evaluation model is trained based on the updated training dataset to obtain an optimized target signal evaluation model. The optimized target signal evaluation model is used to determine the next set of candidate timing parameter combinations to be verified.

10. A device for tuning memory timing parameters, characterized in that, include: The configuration module is used to configure candidate timing parameter combinations for the memory controller in the server to be optimized, and to obtain the candidate signal measurement results of the memory interface when the memory controller runs under the candidate timing parameter combinations. The verification module is used to verify whether the measurement results of the candidate signals of the memory interface meet the preset tuning conditions. The triggering module is used to trigger the parameter optimization mechanism to generate the next set of candidate timing parameter combinations to be verified if the preset tuning conditions are not met. The configuration and verification operations are repeated until the target signal measurement result that meets the preset tuning conditions is output, and the candidate timing parameter combination corresponding to the target signal measurement result is used as the target timing parameter combination. The device further includes: The detection module is used to detect debugging commands for the server to be optimized; A generation module is used to trigger a parameter optimization mechanism based on the debugging instruction, and generate candidate timing parameter combinations according to the debugging range of the timing parameter combinations in the debugging instruction; wherein, generating candidate timing parameter combinations according to the debugging range of the timing parameter combinations in the debugging instruction includes: parsing the debugging range of the timing parameter combinations in the debugging instruction; constructing a training dataset based on the debugging range, and training an initial signal evaluation model using the training dataset to obtain a target signal evaluation model; and determining candidate timing parameter combinations using the target signal evaluation model. The step of constructing a training dataset based on the debugging range includes: selecting a first combination of timing parameters within the debugging range; configuring the first combination of timing parameters on the memory controller in the server to be optimized, and obtaining the first signal measurement result of the memory interface when the memory controller is running under the first combination of timing parameters; constructing a Gaussian process model based on the first combination of timing parameters and the first signal measurement result, and predicting the next second combination of timing parameters to be debugged through the Gaussian process model; configuring the second combination of timing parameters on the memory controller in the server to be optimized, and obtaining the second signal measurement result of the memory interface when the memory controller is running under the second combination of timing parameters, iteratively executing parameter prediction and configuration operations until a preset sampling condition is reached, and generating a training dataset using the mapping relationship between the combination of timing parameters and the measurement results.

11. An electronic device, characterized in that, include: A memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, the processor executing the computer instructions to perform the method of any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method of any one of claims 1 to 9.

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