Transmitter circuit and method of adapting different protocol standards
By designing a transmitter circuit compatible with multiple memory interface standards and adjusting the output signal using duty cycle and delay control signals, the problem of signal duty cycle offset in existing technologies is solved, thereby improving signal transmission quality and adaptability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INNOGRIT TECH CO LTD
- Filing Date
- 2025-06-13
- Publication Date
- 2026-07-24
AI Technical Summary
Existing transmitter circuits can only adapt to a single type or standard memory protocol, and cannot flexibly switch between different standards. Furthermore, the duty cycle of the output signal is prone to deviation, affecting the signal transmission quality.
Design a transmitter circuit that includes a driver circuit module and a pre-amplifier unit. Adjust the duty cycle and delay of the output signal through duty cycle control signals and delay control signals to adapt to different impedance matching methods and be compatible with multiple memory interface standards.
It enables precise adjustment of the signal duty cycle under different memory interface standards, improves signal transmission quality, adapts to different power supply voltages and impedance matching methods, and reduces design costs.
Smart Images
Figure CN120705091B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a transmitter circuit and a method for adapting to different protocol standards. Background Technology
[0002] In modern computing systems, data transfer between the central processing unit (CPU) and memory is a key factor affecting overall system performance. To meet the ever-increasing demands for memory read / write speeds in high-performance computing, artificial intelligence, and big data processing, the speed and stability of the memory interface have become paramount. As a core component of the memory controller interface circuit, the transmitter circuit's performance directly impacts signal transmission quality and system stability.
[0003] In recent years, with the continuous evolution of memory standards, DDR (Double Data Rate) synchronous dynamic random access memory (SDRAM) has developed to its fifth generation (DDR5), with data transfer rates reaching 6400Mbps or even higher, significantly increasing bandwidth, and gradually reducing I / O voltage. Meanwhile, NAND Flash, as another type of non-volatile memory, has been widely used in solid-state drives (SSDs), embedded systems, mobile terminals, and other fields, and has also developed high-speed interface specifications such as ONFI, Toggle DDR, and NV-DDR3 / 4. Its interface transfer rates and electrical parameters are also trending towards design requirements similar to DDR memory.
[0004] However, traditional transmitter circuits generally only adapt to a single type or standard memory protocol, that is, only one operating mode of DDR or NAND Flash, and cannot flexibly switch between different standards. More importantly, the termination impedance matching method of the output port is different in different memory operating modes, which will cause the duty cycle of the output signal to shift. For example, pull-up termination impedance matching tends to result in a larger duty cycle, while pull-down termination impedance matching tends to result in a smaller duty cycle.
[0005] Furthermore, some existing designs adjust the duty cycle by changing the number of parallel output MOSFETs. This method often affects the output impedance, causing signal reflection and a decrease in transmission quality, especially in high-speed interfaces. Therefore, designing a transmitter circuit that is compatible with multiple memory interface standards, adapts to different impedance matching methods, and has high-precision duty cycle adjustment capabilities has become one of the key technical issues in current chip interface design. Summary of the Invention
[0006] The purpose of this application is to provide a transmitter circuit that is compatible with multiple memory interface standards, adapts to different impedance matching methods, and has high-precision duty cycle adjustment capability.
[0007] A first aspect of this application provides a transmitter circuit, including at least one driving circuit module, wherein each driving circuit module includes:
[0008] The first pre-amplification unit receives a first input signal, a first delay control signal, and a duty cycle control signal, and outputs a pair of differential pull-up signals.
[0009] The first pull-up transistor and the second pull-up transistor have their gates receiving the pair of differential pull-up signals respectively. The source of the first pull-up transistor and the drain of the second pull-up transistor are connected to the power supply voltage.
[0010] A pull-up resistor, one end of which is connected to the drain of the first pull-up transistor and the source of the second pull-up transistor, and the other end is connected to the output port;
[0011] The second pre-amplification unit receives the second input signal, the second delay control signal and the duty cycle control signal and outputs a pull-down signal.
[0012] A pull-down transistor, wherein the gate of the pull-down transistor receives the pull-down signal, and the source is connected to ground;
[0013] A pull-down resistor, one end of which is connected to the drain of the pull-down transistor, and the other end of which is connected to the output port.
[0014] In a preferred embodiment, the transmitter circuit includes multiple drive circuit modules connected in parallel.
[0015] In a preferred embodiment, the first pull-up transistor is a PMOS transistor, and the second pull-up transistor and the first pull-down transistor are NMOS transistors.
[0016] In a preferred embodiment, the first pre-amplification unit includes:
[0017] The first conversion and adjustment unit receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal.
[0018] The first inverter has its input terminal connected to the output terminal of the first conversion adjustment unit and outputs the inverted signal of the first amplified signal, thereby obtaining a pair of first differential amplified signals;
[0019] A first front driver receives the pair of first differential amplified signals (and outputs the pair of differential pull-up signals).
[0020] In a preferred embodiment, the first conversion adjustment unit includes:
[0021] A duty cycle adjustment unit receives the first input signal and adjusts the duty cycle of the first input signal according to the duty cycle control signal;
[0022] A level converter that receives the output of the duty cycle adjustment unit and converts the voltage domain of the first input signal;
[0023] A delay adjustment unit receives the output of the level converter, adjusts the delay of the first input signal according to the first delay control signal, and outputs the first amplified signal.
[0024] In a preferred embodiment, the second pre-amplification unit includes:
[0025] The second conversion and adjustment unit receives the second input signal, adjusts the duty cycle of the second input signal according to the duty cycle control signal, converts the voltage domain of the second input signal, adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal.
[0026] The second front driver receives the second amplified signal and outputs the pull-down signal.
[0027] In a preferred embodiment, the second conversion adjustment unit includes:
[0028] A duty cycle adjustment unit receives the second input signal and adjusts the duty cycle of the second input signal according to the duty cycle control signal;
[0029] A level converter that receives the output of the duty cycle adjustment unit and converts the voltage domain of the second input signal;
[0030] A delay adjustment unit receives the output of the level converter and adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal.
[0031] In a preferred embodiment, the duty cycle adjustment unit includes:
[0032] The second inverter receives the first input signal at its input terminal.
[0033] The first transistor, second transistor, third transistor, and fourth transistor have their gates coupled to the output of the second inverter. The source of the first transistor is coupled to the digital domain power supply voltage. The source of the second transistor is coupled to the digital domain power supply voltage via a first switch. The source of the third transistor is coupled to ground. The source of the fourth transistor is coupled to ground via a second switch. The drains of the first to fourth transistors are connected and coupled to the input of the level converter. The first and second switches are controlled by the duty cycle control signal.
[0034] In a preferred embodiment, when the first switch is closed and the second switch is open, the duty cycle of the positive phase amplification signal in the pair of first differential amplification signals increases, and the duty cycle of the negative phase amplification signal decreases; when the first switch is open and the second switch is closed, the duty cycle of the positive phase amplification signal in the pair of first differential amplification signals decreases, and the duty cycle of the negative phase amplification signal increases; when the first switch and the second switch are closed or open simultaneously, the duty cycle of the pair of differential first amplification signals remains unchanged.
[0035] In a preferred embodiment, when the first switch is closed and the second switch is open, the duty cycle of the second amplified signal increases; when the first switch is open and the second switch is closed, the duty cycle of the second amplified signal decreases; when the first switch and the second switch are closed or open simultaneously, the duty cycle of the second amplified signal remains unchanged.
[0036] In a preferred embodiment, the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.
[0037] In a preferred embodiment, the first switch is a PMOS transistor.
[0038] In a preferred embodiment, the second switch is an NMOS transistor.
[0039] In a preferred embodiment, the delay adjustment unit includes:
[0040] A third inverter, the input of which is coupled to the output of the level converter;
[0041] The fifth, sixth, seventh, and eighth transistors have their gates coupled to the output of the third inverter. The source of the fifth transistor is coupled to the analog domain power supply voltage. The source of the sixth transistor is coupled to the analog domain power supply voltage via a third switch. The source of the seventh transistor is coupled to the ground terminal. The source of the eighth transistor is coupled to the ground terminal via a fourth switch. The drains of the fifth to eighth transistors are connected and output either the positive-inverting amplified signal or the second amplified signal in the pair of first differential amplified signals. The third and fourth switches are controlled by the first delay control signal or the second delay control signal.
[0042] In a preferred embodiment, when the third switch and the fourth switch are simultaneously open, the delay of the pair of first differential amplified signals relative to the first input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the pair of first differential amplified signals relative to the first input signal remains unchanged.
[0043] In a preferred embodiment, when the third switch and the fourth switch are simultaneously open, the delay of the second amplified signal relative to the second input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the second amplified signal relative to the second input signal remains unchanged.
[0044] In a preferred embodiment, the third switch is a PMOS transistor.
[0045] In a preferred embodiment, the fourth switch is an NMOS transistor.
[0046] In a preferred embodiment, the fifth and sixth transistors are PMOS transistors, and the seventh and eighth transistors are NMOS transistors.
[0047] In a preferred embodiment, the first pre-amplification unit includes:
[0048] The first conversion and adjustment unit receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal.
[0049] A first front driver receives the first amplified signal and outputs a first pull-up signal;
[0050] A first inverter, the input of which is connected to the output of the first front driver and outputs the inverted signal of the first pull-up signal, thereby obtaining the pair of differential pull-up signals.
[0051] A second aspect of this application provides a method for adapting the above-described transmitter circuit to different protocol standards, the method comprising:
[0052] When the power supply voltage is a higher voltage protocol standard, the first pull-up transistor is turned on and the second pull-up transistor is turned off; when the power supply voltage is a lower voltage protocol standard, the first pull-up transistor is turned off and the second pull-up transistor is turned on.
[0053] In a preferred embodiment, under different impedance matching modes, the method further includes:
[0054] The duty cycle of the output port signal is coarsely adjusted by increasing, decreasing, or not changing the duty cycle of the pair of pull-up and pull-down signals using the duty cycle adjustment signal.
[0055] The time interval between the pair of pull-up and pull-down signals is adjusted by adjusting the delay of the pair of pull-up and pull-down signals relative to the first and second input signals, respectively, through the first delay control signal and the second delay control signal, thereby fine-tuning the duty cycle of the signal at the output port.
[0056] In a preferred embodiment, the higher voltage is a voltage greater than 1V, and the lower voltage is a voltage less than or equal to 0.6V.
[0057] It should be understood that, within the scope of this invention, the above-described technical features of this invention and the technical features specifically described below (such as in the embodiments) can be combined with each other to form new or preferred technical solutions. Due to space limitations, they will not be described in detail here. Attached Figure Description
[0058] Figure 1 This is a schematic diagram of the transmitter circuit according to one embodiment of this application.
[0059] Figure 2 This is a schematic diagram of the drive circuit module according to one embodiment of this application.
[0060] Figure 3 This is a schematic diagram of the structure of the first conversion adjustment unit according to one embodiment of this application.
[0061] Figure 4 This is a schematic diagram of the structure of the second conversion adjustment unit according to one embodiment of this application.
[0062] Figure 5 This is a schematic diagram of the drive circuit module according to another embodiment of this application. Detailed Implementation
[0063] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0064] The following is a summary of some of the innovative aspects of the implementation methods of this application:
[0065] The transmitter circuit of this application includes two pull-up transistors and one pull-down transistor. The first pull-up transistor, the second pull-up transistor, and the pull-down transistor can be activated in both higher and lower power supply voltage operating modes, respectively, making the transmitter circuit compatible with different power supply voltage operating modes. Furthermore, by setting different register values (i.e., the values of the delay control signal and the duty cycle control signal), the duty cycle and time interval of the pull-up and pull-down signals can be changed, thereby adjusting the duty cycle of the transmitter circuit's output signal.
[0066] Furthermore, this application allows for second-order adjustment of the duty cycle of the transmitter's output signal. A first adjustment (coarse adjustment) is performed using the value of the duty cycle control signal, and a second adjustment (fine adjustment) is performed using the value of the delay control signal, thereby bringing the duty cycle of the output signal closer to the target value.
[0067] Compared with the prior art, the transmitter circuit of this application has at least the following advantages:
[0068] 1) Traditional transmitter circuits can only be applied to one working mode. The transmitter circuit of this invention can be compatible with multiple memory interface standards, such as DDR4, LPDDR4, DDR5, LPDDR4X, LPDDR5, NV-DDR3, NV-LPDDR4, etc., thereby saving design costs.
[0069] 2) The transmitter circuit of the present invention adjusts the duty cycle of the transmitter output signal without changing the impedance of the transmitter output terminal. Furthermore, the duty cycle can be adjusted for different deviations from the signal duty cycle, meaning the duty cycle of the transmitter terminal signal can be adjusted for different operating modes.
[0070] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0071] Figure 1This is a schematic diagram of the transmitter circuit 1 in one embodiment of the present invention. The transmitter circuit 1 includes at least one driving circuit module 100. In this specific embodiment, the transmitter circuit 1 is composed of multiple driving circuit modules 100 connected in parallel, and the driving circuit modules 100 are multiplexed.
[0072] Figure 2 This is a schematic diagram of the drive circuit module 100. The drive circuit module 100 includes registers DELAY_CTR_P, DELAY_CTR_N, DUTY_CTR<1:0>, a first pre-amplification unit 101, a first pull-up transistor Mp1, a second pull-up transistor Mn1, a pull-up resistor R1, a second pre-amplification unit 102, a pull-down transistor Mn2, a pull-down resistor R2, and an output port DQ. The first pull-up transistor Mp1 is a PMOS transistor, and the second pull-up transistor Mn1 and pull-down transistor Mn2 are NMOS transistors.
[0073] The input terminal of the first pre-amplification unit 101 is connected to the first input signal DATAP, the register DELAY_CTR_P, and the register DUTY_CTR<1:0>. Its differential output terminals are connected to the gates of pull-up PMOS transistor Mp1 and pull-up NMOS transistor Mn1, respectively. The gate of the pull-up PMOS transistor Mp1 is connected to the output terminal PU of the first pre-amplification unit 101, its source is connected to the power supply voltage VDDQ, and its drain is connected to the first terminal of the pull-up resistor R1. The gate of the pull-up NMOS transistor Mn1 is connected to the output terminal PUB of the first pre-amplification unit 101, its drain is connected to the power supply voltage VDDQ, and its source is connected to the first terminal of the pull-up resistor R1. The first terminal of the pull-up resistor R1 is connected to the drain of the pull-up PMOS transistor Mp1 and the source of the pull-up NMOS transistor Mn1, and its second terminal is connected to the output port DQ.
[0074] The input terminal of the second pre-amplification unit 102 is connected to the second input signal DATAN, the register DELAY_CTR_N, and the register DUTY_CTR<1:0>, and the output terminal is connected to the gate of the pull-down NMOS transistor Mn2. The gate of the pull-down NMOS transistor Mn2 is connected to the output terminal of the second pre-amplification unit 102, its source is grounded to VSSQ, and its drain is connected to the first end of the pull-down resistor R2. The second end of the pull-down resistor R2 is connected to the output port DQ.
[0075] As used below, the terms "output port DQ" and "signal DQ" are used interchangeably, referring to the signal on the output port, which serves as the output signal of the drive circuit module. The terms "output terminal PU," "signal PU," and "pull-up signal PU" are used interchangeably, referring to the signal on the output terminal of the first pre-amplifier unit, which serves as the control signal for the first pull-up transistor. The terms "output terminal PUB," "signal PUB," and "pull-up signal PUB" are used interchangeably, referring to the signal on the output terminal of the first pre-amplifier unit, which serves as the control signal for the second pull-up transistor. The terms "output terminal PD," "signal PD," and "pull-down signal PD" are used interchangeably, referring to the signal on the output terminal of the second pre-amplifier unit, which serves as the control signal for the pull-down transistor. The terms "register DUTY_CTR<1:0>" and "duty cycle control signal" are used interchangeably, referring to the value of the register, which serves as the control signal for the duty cycle adjustment unit. The terms "register DELAY_CTR_P" and "first delay control signal" are used interchangeably, referring to the value of the register, which serves as the control signal for delay adjustment in the first pre-amplifier unit. The terms "register DELAY_CTR_N" and "second delay control signal" are used interchangeably, referring to the value of the register, which serves as the control signal for delay adjustment in the second preamplification unit.
[0076] Continue to refer to Figure 2 As shown, the first pre-amplification unit 101 includes at least one first conversion adjustment unit 103, a first pre-driver 104, and a first inverter 107. The first conversion adjustment unit 103, the first inverter 107, and the first pre-driver 104 are connected sequentially. Specifically, the input terminal of the first conversion adjustment unit 103 is connected to the input signal DATAP, the register DELAY_CTR_P, and the register DUTY_CTR<1:0>, and the output terminal is connected to the input terminal of the first inverter 107 and one input terminal of the first pre-driver 104, respectively. The output terminal of the first inverter 107 is connected to the other input terminal of the first pre-driver 104. The differential output terminal of the first pre-driver 104 is connected to the gates of the pull-up PMOS transistor Mp1 and the pull-up NMOS transistor Mn1, respectively.
[0077] The second pre-amplification unit 102 includes at least one second conversion adjustment unit 105 and a second pre-driver 106. The second conversion adjustment unit 105 and the second pre-driver 106 are connected sequentially. Specifically, the input terminal of the second conversion adjustment unit 105 is connected to the input signal DATAN, the register DELAY_CTR_N, and the register DUTY_CTR<1:0>, and the output terminal is connected to the input terminal of the second pre-driver 106. The output terminal of the second pre-driver 106 is connected to the gate of the pull-down NMOS transistor Mn2.
[0078] The input signals DATAP and DATAN of the transmitter circuit are two identical signals that have passed through the previous stage circuit and been serialized. The first conversion and adjustment unit 103 amplifies the input signal DATAP and outputs a first amplified signal DATAP_bur. The first inverter 107 outputs the inverted signal of the first amplified signal DATAP_bur, thus forming two differential amplified signals DATAP_bur and DATAPB_bur. The first amplified signal DATAP_bur has the same polarity as the input signal DATAP, or is called a positive-phase amplified signal. The inverted signal DATAPB_bur has the opposite polarity to the input signal DATAP, or is called a negative-phase amplified signal. The register DUTY_CTR<1:0> is used to adjust the duty cycle of the two differential amplified signals DATAP_bur and DATAPB_bur. Specifically, when DUTY_CTR<1:0> = 10, the duty cycle of the positive-phase amplified signal DATAP_bur can be increased and the duty cycle of the negative-phase amplified signal DATAPB_bur can be decreased. Setting DUTY_CTR<1:0> = 01 decreases the duty cycle of the positive-phase amplified signal DATAP_bur and increases the duty cycle of the negative-phase amplified signal DATAPB_bur. Setting DUTY_CTR<1:0> = 00 or 11 does not change the duty cycles of the amplified signals DATAP_bur and DATAPB_bur. Furthermore, the DELAY_CTR_P register is used to adjust the delay time of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP. Setting DELAY_CTR_P = 1 increases the delay time of the positive-phase amplified signal DATAP_bur and the negative-phase amplified signal DATAPB_bur relative to the input signal DATAP. Setting DELAY_CTR_P = 0 does not change the delay time of the amplified signals DATAP_bur and DATAPB_bur relative to the input signal DATAP. The first pre-driver 104 is used to enhance the driving capability of the amplified signals DATAP_bur and DATAPB_bur. The output signal PU is used as the driving signal for the pull-up PMOS transistor Mp1, and the output signal PUB is used as the driving signal for the pull-up NMOS transistor Mn1. The polarity of PU is opposite to that of the positive-phase amplified signal DATAP_bur, and the polarity of PUB is opposite to that of the negative-phase amplified signal DATAPB_bur.
[0079] The second conversion adjustment unit 105 amplifies the input signal DATAN and outputs a second amplified signal DATAN_bur, which has the same polarity as the input signal DATAN. The register DUTY_CTR<1:0> is used to adjust the duty cycle of the second amplified signal DATAN_bur. Setting DUTY_CTR<1:0> = 10 increases the duty cycle of the second amplified signal DATAN_bur. Setting DUTY_CTR<1:0> = 01 decreases the duty cycle of the second amplified signal DATAN_bur. Setting DUTY_CTR<1:0> = 00 or 11 does not change the duty cycle of the second amplified signal DATAN_bur. The register DELAY_CTR_N is used to adjust the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN. Setting DELAY_CTR_N = 1 increases the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN. When DELAY_CTR_N = 0, the delay time of the second amplified signal DATAN_bur relative to the input signal DATAN is not changed. The second pre-driver 106 is used to enhance the driving capability of the second amplified signal DATAN_bur, and the output signal PD serves as the driving signal for the pull-down NMOS transistor Mn2. The polarity of PD is opposite to that of the amplified signal DATAN_bur.
[0080] For operating modes with a relatively high power supply voltage VDDQ, such as DDR4, LPDDR4, DDR5, NVDDR3, and NVLPDDR4, the pull-up PMOS transistor Mp1 is turned on while the pull-up NMOS transistor Mn1 is turned off. For operating modes with a relatively low power supply voltage VDDQ, such as LPDDR4X and LPDDR5, the pull-up PMOS transistor Mp1 is turned off while the pull-up NMOS transistor Mn1 is turned on. Therefore, the transmitter circuit of this invention can operate normally regardless of whether it is operating in a high VDDQ DDR5 mode or a low VDDQ LPDDR5 mode.
[0081] For different operating modes, the duty cycle and time interval of the pull-up signals PU, PUB and pull-down signals PD are changed by setting different register values, thereby adjusting the duty cycle of the transmitter circuit output port DQ. The principle of the transmitter circuit adjusting the duty cycle of the output signal DQ is explained in detail below.
[0082] When the output port DQ is pull-up resistor matched, the transmitter has a strong pull-up resistor and a weak pull-down resistor, resulting in a higher (or larger) duty cycle of the output signal. Assuming the input signals DATAP and DATAN have a duty cycle of 50%, the first step is to coarsely adjust the output signal's duty cycle: set DUTY_CTR<1:0> = 01, decrease the duty cycle of the positive phase amplification signal DATAP_bur and the second amplification signal DATAN_bur, increase the duty cycle of the negative phase amplification signal DATAPB_bur (i.e., increase the duty cycle of the pull-up signals PU and PD), decrease the duty cycle of the pull-up signal PUB, and thus decrease the duty cycle of signal DQ. The second step is to fine-tune the duty cycle of the output signal: If the duty cycle of signal DQ is still greater than 50%, DELAY_CTR_P = 1 can be set to increase the delay time of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP. DELAY_CTR_N = 0 is set to not change the delay time of the second amplification signal DATAN_bur relative to the input signal DATAN. In this case, the pull-up signals PU and PUB lag behind the pull-down signal PD. The pull-up PMOS transistor Mp1 or pull-up NMOS transistor Mn1 turns on after the pull-up transistor Mn2 turns on first. That is, the pull-up resistor becomes weaker while the pull-down resistor becomes stronger. The pull-up resistor becomes stronger, thus reducing the duty cycle of DQ. If the duty cycle of DQ is less than 50% at this time, setting DELAY_CTR_P = 0 does not change the delay time of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP. Setting DELAY_CTR_N = 1 increases the delay time of the second amplification signal DATAN_bur relative to the input signal DATAN. At this time, PU and PUB lead PD, and the pull-up PMOS transistor Mp1 or pull-up NMOS transistor Mn1 turns on first and the pull-down NMOS transistor Mn2 turns on later. That is, the pull-up resistor becomes stronger and the pull-down resistor becomes weaker, thereby increasing the duty cycle of signal DQ. In this invention, the register DUTY_CTR<1:0> performs the first adjustment of the duty cycle of signal DQ, and the registers DELAY_CTR_P and DELAY_CTR_N perform the second adjustment of the duty cycle of signal DQ, so that the duty cycle of signal DQ is closer to 50%.
[0083] When the output port DQ is pull-down matched, the transmitter's pull-up resistor is weak while the pull-down resistor is strong, thus reducing the duty cycle of signal DQ. Assuming the input signals DATAP and DATAN have a duty cycle of 50%, setting DUTY_CTR<1:0> = 10 increases the duty cycle of the positive-phase amplified signal DATAP_bur and the second amplified signal DATAN_bur, decreases the duty cycle of the negative-phase amplified signal DATAPB_bur, i.e., decreases the duty cycle of the pull-up signal PU and the pull-down signal PD, and increases the duty cycle of the pull-up signal PUB, thereby increasing the duty cycle of signal DQ. If the duty cycle of signal DQ is still less than 50% at this time, DELAY_CTR_P = 0 can be set to not change the delay time of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP, and DELAY_CTR_N = 1 can be set to increase the delay time of the second amplification signal DATAN_bur relative to the input signal DATAN. At this time, the pull-up signals PU and PUB lead the pull-down signal PD. The pull-up PMOS transistor Mp1 or pull-up NMOS transistor Mn1 turns on first and the pull-down NMOS transistor Mn2 turns on later. That is, the pull-up resistor becomes stronger and the pull-down resistor becomes weaker, thereby increasing the duty cycle of signal DQ. If the duty cycle of signal DQ is greater than 50% at this time, DELAY_CTR_P = 1 can be set to increase the delay time of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP. Setting DELAY_CTR_N = 0 will not change the delay time of the second amplification signal DATAN_bur relative to the input signal DATAN. In this case, the pull-up signals PU and PUB lag behind the pull-down signal PD. The pull-up PMOS transistor Mp1 or pull-up NMOS transistor Mn1 turns on later, while the pull-down NMOS transistor Mn2 turns on first. That is, the pull-up resistor becomes weaker and the pull-down resistor becomes stronger, thereby reducing the duty cycle of signal DQ. The register DUTY_CTR<1:0> performs the first adjustment to the duty cycle of signal DQ, and the registers DELAY_CTR_P and DELAY_CTR_N perform the second adjustment, thus bringing the duty cycle of signal DQ closer to 50%.
[0084] When the output port DQ has both pull-up and pull-down resistors matched, the pull-up and pull-down resistor strengths are the same, so the duty cycle of signal DQ remains unchanged. Assuming the duty cycle of input signals DATAP and DATAN is 50%, setting DUTY_CTR<1:0> = 00 or 11, register DELAY_CTR_P = 0, and register DELAY_CTR_N = 0 will not change the duty cycle of signal DQ.
[0085] Figure 3This is a schematic diagram of the first conversion and adjustment unit 103. The first conversion and adjustment unit 103 includes a first duty cycle adjustment unit 108, a first level converter 109, and a first delay adjustment unit 110. The input terminal of the first duty cycle adjustment unit 108 is connected to the input signal DATAP, and its output terminal is connected to the input terminal of the first level converter 109. The output terminal of the first level converter 109 is connected to the input terminal of the first delay adjustment unit 110. The output terminal of the first delay adjustment unit 110 outputs a positive-inverting amplified signal DATAP_bur, and its output terminal is connected to the input terminal of the first inverter 107 to obtain a negative-inverting amplified signal DATAB_bur.
[0086] Furthermore, the first duty cycle adjustment unit 108 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a second inverter 111. The first delay adjustment unit 110 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a second inverter 112. Wherein, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 are PMOS transistors, and the third transistor M3, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8 are NMOS transistors. The input terminal of the second inverter 111 is connected to the input signal DATAP, and the output terminal is connected to the gates of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. The drains of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are connected together and connected to the input terminal of the first level converter 109. The source of the first transistor M1 is connected to the digital domain power supply voltage DVDD. The drain of the second transistor M2 is connected to the first terminal of the first switch s1, and the other terminal of the first switch s1 is connected to the digital domain power supply voltage DVDD. The source of the third transistor M3 is grounded. The source of the fourth transistor M4 is connected to the first terminal of the second switch s2, and the other terminal of the second switch s2 is grounded. The output of the first level converter 109 is connected to the input of the second inverter 112. The gates of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected together and connected to the output of the second inverter 112. The drains of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are connected together and output a positive-inverting amplified signal DATAP_bur. The source of the fifth transistor M5 is connected to the analog domain power supply voltage AVDD. The source of the sixth transistor M6 is connected to the first terminal of the third switch s3. The other terminal of the third switch s3 is connected to the analog domain power supply voltage AVDD. The source of the seventh transistor M7 is grounded. The source of the eighth transistor M8 is connected to the first terminal of the fourth switch s4. The other terminal of the fourth switch s4 is grounded. The input of the first inverter 107 is connected to the positive-inverting amplified signal DATAP_bur, and the output terminal outputs a negative-inverting amplified signal DATAPB_bur.
[0087] In one embodiment, the first switch s1, the second switch s2, the third switch s3, and the fourth switch s4 can be MOS transistors. For example, the first switch s1 and the third switch s3 are PMOS transistors, and the second switch s2 and the fourth switch s4 are NMOS transistors.
[0088] Furthermore, the first switch s1 is controlled by the register DUTY_CTR <1> Controlled by the second switch s2, which is controlled by the DUTY_CTR register. <0> Control. When register DUTY_CTR<1:0> = 10, the first switch s1 is open and the second switch s2 is closed. The output of the first duty cycle adjustment unit 108 has a strong charging capability but a weak discharging capability, and the duty cycle of the output signal out1 increases, that is, the duty cycle of the output signal DATAP_bur increases while the duty cycle of DATAPB_bur decreases. When register DUTY_CTR<1:0> = 01, the first switch s1 is closed and the second switch s2 is open. The output of the first duty cycle adjustment unit 108 has a weak charging capability but a strong discharging capability, and the duty cycle of the output signal out1 decreases, that is, the duty cycle of the positive phase amplification signal DATAP_bur decreases while the duty cycle of the negative phase amplification signal DATAPB_bur increases. When register DUTY_CTR<1:0> = 00 or 11, the first switch s1 and the second switch s2 are simultaneously closed or opened, and the duty cycles of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur remain unchanged. The third switch s3 and the fourth switch s4 are controlled by the register DELAY_CTR_P. When the register DELAY_CTR_P = 1, the third switch s3 and the fourth switch s4 are closed, increasing the delay of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP. When the register DELAY_CTR_P = 0, the third switch s3 and the fourth switch s4 are open, without changing the delay of the positive phase amplification signal DATAP_bur and the negative phase amplification signal DATAPB_bur relative to the input signal DATAP.
[0089] Figure 4 This is a schematic diagram of the second conversion and adjustment unit 105. The second conversion and adjustment unit 105 includes a second duty cycle adjustment unit 113, a second level converter 114, and a second delay adjustment unit 115. The input terminal of the second duty cycle adjustment unit 113 is connected to the input signal DATAN, and its output terminal is connected to the input terminal of the second level converter 114. The output terminal of the second level converter 114 is connected to the input terminal of the second delay adjustment unit 115, and the output terminal of the second delay adjustment unit 115 outputs the second amplified signal DATAN_bur.
[0090] It should be noted that the second conversion adjustment unit 105 and the first conversion adjustment unit 103 can adopt the same structure. That is, the structure and control method of the second duty cycle adjustment unit 113 can be the same as the first duty cycle adjustment unit 108, the structure of the second level converter 114 can be the same as the first level converter 109, and the structure and control method of the second delay adjustment unit 115 can be the same as the first delay adjustment unit 110.
[0091] Furthermore, the second duty cycle adjustment unit 113 includes a first transistor M1', a second transistor M2', a third transistor M3', a fourth transistor M4', and a second inverter 111'. The second delay adjustment unit 115 includes a fifth transistor M5', a sixth transistor M6', a seventh transistor M7', an eighth transistor M8', and a second inverter 112'. The first transistor M1', second transistor M2', fifth transistor M5', and sixth transistor M6' are PMOS transistors, and the third transistor M3', fourth transistor M4', seventh transistor M7', and eighth transistor M8' are NMOS transistors. The input terminal of the second inverter 111' is connected to the input signal DATAN, and the output terminal is connected to the gates of the first transistor M1', the second transistor M2', the third transistor M3', and the fourth transistor M4'. The drains of the first transistor M1', the second transistor M2', the third transistor M3', and the fourth transistor M4' are connected together and connected to the input terminal of the second level converter 114. The source of the first transistor M1' is connected to the digital domain power supply voltage DVDD. The source of the second transistor M2' is connected to the first terminal of the first switch s1'. The other terminal of the first switch s1' is connected to the digital domain power supply voltage DVDD. The source of the third transistor M3' is grounded. The source of the fourth transistor M4' is connected to the first terminal of the second switch s2'. The other terminal of the second switch s2' is grounded. The output of the second level converter 114 is connected to the input of the second inverter 112'. The gates of the fifth transistor M5', the sixth transistor M6', the seventh transistor M7', and the eighth transistor M8' are connected together and connected to the output of the second inverter 112'. The drains of the fifth transistor M5', the sixth transistor M6', the seventh transistor M7', and the eighth transistor M8' are connected together and output the second amplified signal DATAN_bur. The source of the fifth transistor M5' is connected to the analog domain power supply voltage AVDD. The source of the sixth transistor M6' is connected to the first terminal of the third switch s3'. The other terminal of the third switch s3' is connected to the analog domain power supply voltage AVDD. The source of the seventh transistor M7' is grounded. The source of the eighth transistor M8' is connected to the first terminal of the fourth switch s4'. The other terminal of the fourth switch s4' is grounded.
[0092] Furthermore, the first switch s1' is controlled by the register DUTY_CTR <1> Control, the second switch s2' is controlled by the DUTY_CTR register <0> Control. When register DUTY_CTR<1:0> = 10, the first switch s1' is open and the second switch s2' is closed. The output of the second duty cycle adjustment unit 113 has a strong charging capability but a weak discharging capability, and the duty cycle of the output signal out1' increases, which means the duty cycle of the second amplified signal DATAN_bur increases. When register DUTY_CTR<1:0> = 01, the first switch s1' is closed and the second switch s2' is open. The output of the second duty cycle adjustment unit 113 has a weak charging capability but a strong discharging capability, and the duty cycle of the output signal out1' decreases, which means the duty cycle of the second amplified signal DATAP_bur decreases. When register DUTY_CTR<1:0> = 00 or 11, the first switch s1' and the second switch s2' are simultaneously closed or opened, and the duty cycle of the second amplified signal DATAP_bur remains unchanged. The third switch s3' and the fourth switch s4' are controlled by the register DELAY_CTR_N. When the register DELAY_CTR_N = 1, the third switch s3' and the fourth switch s4' are closed, increasing the delay of the second amplified signal DATAN_bur relative to the input signal DATAN. When the register DELAY_CTR_N = 0, the third switch s3' and the fourth switch s4' are open, without changing the delay of the second amplified signal DATAN_bur relative to the input signal DATAN.
[0093] Figure 5 This is a schematic diagram of the drive circuit module 100' according to another embodiment of this application. The difference between the drive circuit module 100' and the drive circuit module 100 is that the first inverter 107' is not located between the first conversion adjustment unit 103 and the first front driver 104, but is located after the first front driver 104. The first front driver 104 outputs a first pull-up signal PU to the first inverter 107'. The first inverter 107' inverts the first pull-up signal PU and obtains a pull-up signal PUB, thereby obtaining a pair of differential pull-up signals.
[0094] Other embodiments of this application also disclose a method for adapting the above-described transmitter circuit to different protocol standards. The method includes: when the power supply voltage VDDQ is a relatively high voltage (e.g., greater than 1V) for a protocol standard (such as DDR5, NVLPDDR4, etc.), the first pull-up transistor Mp1 is turned on and the second pull-up transistor Mn1 is turned off. When the power supply voltage is a relatively low voltage (e.g., less than or equal to 0.6V) for a protocol standard (such as LPDDR5, LPDDR4X, etc.), the first pull-up transistor Mp1 is turned off and the second pull-up transistor Mn1 is turned on.
[0095] The transmitter circuit can adjust the duty cycle of the output signal DQ under different impedance matching modes. First, the duty cycle of the output signal DQ is coarsely adjusted by increasing, decreasing, or leaving unchanged the duty cycles of the pair of pull-up signals PU and PUB and the pull-down signal PD. Then, the time interval between the pull-up signals PU and PUB and the pull-down signal PD is adjusted by using a first delay control signal to adjust the delay of the pair of pull-up signals PU and PUB relative to the first input signal DATAP, and by using a second delay control signal to adjust the delay of the pull-down signal PD relative to the second input signal DATAN. This fine-tunes the duty cycle of the output signal DQ.
[0096] In summary, the transmitter of this invention is compatible with multiple memory interface standards, thereby saving design costs. The duty cycle of the transmitter output signal can be adjusted without changing the impedance of the transmitter output terminal. Furthermore, the duty cycle of the transmitter terminal signal can be adjusted for different operating modes.
[0097] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.
[0098] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described.
[0099] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.
Claims
1. A transmitter circuit, characterized in that, Includes at least one drive circuit module, wherein each drive circuit module includes: The first pre-amplification unit receives a first input signal, a first delay control signal, and a duty cycle control signal, and outputs a pair of differential pull-up signals. A first pull-up transistor and a second pull-up transistor, the gates of the first pull-up transistor and the second pull-up transistor respectively receive the pair of differential pull-up signals, the source of the first pull-up transistor and the drain of the second pull-up transistor are connected to the power supply voltage, wherein the first pull-up transistor is a PMOS transistor and the second pull-up transistor is an NMOS transistor; A pull-up resistor, one end of which is connected to the drain of the first pull-up transistor and the source of the second pull-up transistor, and the other end is connected to the output port; The second pre-amplification unit receives the second input signal, the second delay control signal and the duty cycle control signal and outputs a pull-down signal. A pull-down transistor, wherein the gate of the pull-down transistor receives the pull-down signal, and the source is connected to ground; A pull-down resistor, one end of which is connected to the drain of the pull-down transistor, and the other end of which is connected to the output port; Specifically, the duty cycle of the output port signal is coarsely adjusted by regulating the duty cycle of the pair of differential pull-up signals and the pull-down signals using the duty cycle control signal, and finely adjusted by regulating the delay of the pair of differential pull-up signals and the pull-down signals relative to the first input signal and the second input signal using the first delay control signal and the second delay control signal, respectively.
2. The transmitter circuit as described in claim 1, characterized in that, The first pre-amplification unit includes: The first conversion and adjustment unit receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal. A first inverter, the input of which is connected to the output of the first conversion adjustment unit and outputs the inverted signal of the first amplified signal, thereby obtaining a pair of first differential amplified signals; A first front driver receives the pair of first differential amplified signals and outputs the pair of differential pull-up signals.
3. The transmitter circuit as described in claim 2, characterized in that, The first conversion adjustment unit includes: A duty cycle adjustment unit receives the first input signal and adjusts the duty cycle of the first input signal according to the duty cycle control signal; A level converter that receives the output of the duty cycle adjustment unit and converts the voltage domain of the first input signal; A delay adjustment unit receives the output of the level converter, adjusts the delay of the first input signal according to the first delay control signal, and outputs the first amplified signal.
4. The transmitter circuit as described in claim 1, characterized in that, The second pre-amplification unit includes: The second conversion and adjustment unit receives the second input signal, adjusts the duty cycle of the second input signal according to the duty cycle control signal, converts the voltage domain of the second input signal, adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal. The second front driver receives the second amplified signal and outputs the pull-down signal.
5. The transmitter circuit as described in claim 4, characterized in that, The second conversion adjustment unit includes: A duty cycle adjustment unit receives the second input signal and adjusts the duty cycle of the second input signal according to the duty cycle control signal; A level converter that receives the output of the duty cycle adjustment unit and converts the voltage domain of the second input signal; A delay adjustment unit receives the output of the level converter and adjusts the delay of the second input signal according to the second delay control signal, and outputs the second amplified signal.
6. The transmitter circuit as described in claim 3 or 5, characterized in that, The duty cycle adjustment unit includes: The second inverter receives the first input signal at its input terminal. The first transistor, second transistor, third transistor, and fourth transistor have their gates coupled to the output of the second inverter. The source of the first transistor is coupled to the digital domain power supply voltage. The source of the second transistor is coupled to the digital domain power supply voltage via a first switch. The source of the third transistor is coupled to ground. The source of the fourth transistor is coupled to ground via a second switch. The drains of the first to fourth transistors are connected and coupled to the input of the level converter. The first and second switches are controlled by the duty cycle control signal.
7. The transmitter circuit as described in claim 6, characterized in that, When the first switch is closed and the second switch is open, the duty cycle of the positive phase amplification signal in the pair of first differential amplification signals increases, and the duty cycle of the negative phase amplification signal decreases; when the first switch is open and the second switch is closed, the duty cycle of the positive phase amplification signal in the pair of first differential amplification signals decreases, and the duty cycle of the negative phase amplification signal increases; when the first switch and the second switch are closed or open simultaneously, the duty cycle of the pair of first differential amplification signals remains unchanged.
8. The transmitter circuit as described in claim 3 or 5, characterized in that, The delay adjustment unit includes: A third inverter, the input of which is coupled to the output of the level converter; The fifth, sixth, seventh, and eighth transistors are provided, with their gates all coupled to the output of the third inverter. The source of the fifth transistor is coupled to the analog domain power supply voltage. The source of the sixth transistor is coupled to the analog domain power supply voltage via a third switch. The source of the seventh transistor is coupled to ground. The source of the eighth transistor is coupled to ground via a fourth switch. The drains of the fifth to eighth transistors are connected. The third and fourth switches are controlled by either the first or the second delay control signal.
9. The transmitter circuit as described in claim 8, characterized in that, When the third switch and the fourth switch are simultaneously open, the delay of the pair of first differential amplified signals relative to the first input signal is increased; when the third switch and the fourth switch are simultaneously closed, the delay of the pair of first differential amplified signals relative to the first input signal remains unchanged.
10. The transmitter circuit as claimed in claim 1, characterized in that, The first pre-amplification unit includes: The first conversion and adjustment unit receives the first input signal, adjusts the duty cycle of the first input signal according to the duty cycle control signal, converts the voltage domain of the first input signal, adjusts the delay of the first input signal according to the first delay control signal, and outputs a first amplified signal. A first front driver receives the first amplified signal and outputs a first pull-up signal; A first inverter, the input of which is connected to the output of the first front driver and outputs the inverted signal of the first pull-up signal, thereby obtaining the pair of differential pull-up signals.
11. A method for adapting a transmitter circuit to different protocol standards as described in any one of claims 1 to 10, characterized in that, The method includes: When the power supply voltage is a higher voltage protocol standard, the first pull-up transistor is turned on and the second pull-up transistor is turned off; when the power supply voltage is a lower voltage protocol standard, the first pull-up transistor is turned off and the second pull-up transistor is turned on.
12. The method as described in claim 11, characterized in that, In different impedance matching modes, the method further includes: The duty cycle of the output port signal is coarsely adjusted by increasing, decreasing, or not changing the duty cycle of the pair of differential pull-up signals and the pull-down signals using the duty cycle control signal. The time interval between the pair of differential pull-up signals and the pull-down signals is adjusted by respectively using the first delay control signal and the second delay control signal to adjust the delay of the pair of differential pull-up signals relative to the first input signal and the second input signal, thereby fine-tuning the duty cycle of the signal at the output port.