AXI4_Lite bus usage optimization method, device and medium

Abstract

The application discloses an AXI4_Lite bus use optimization method and device and a medium. By acquiring signals respectively sent by a write address channel and a write data channel in real time, a data address write effective joint signal is obtained, the signal is written and a write operation completion signal is generated; when it is determined that the write operation completion signal is in an effective state, a write automatic response method is used to process the write signal, write anti-hang judgment logic is combined, and automatic response of each channel signal is completed; when it is determined that the read operation completion signal is in an effective state, a read automatic response method is used to process the read signal, read anti-hang judgment logic is combined, and automatic response of each channel signal is completed, so that the use of the write channel and the read channel of the AXI4_Lite bus is optimized. The problems of more signal ports, more complex use and greater difficulty are solved, the signal ports are simplified, and the use complexity and difficulty are reduced.

Description

An optimization method, apparatus, and medium for using the AXI4_Lite bus Technical Field

[0001] This invention relates to the field of communication protocol data processing technology, and in particular to an AXI4_Lite bus usage optimization method, apparatus and medium. Background Technology

[0002] In the AXI bus, AXI4_Lite is a lightweight address-mapped single-transfer bus that can communicate on the device or server side. It occupies very few logic units and features low latency and low power consumption, making it suitable for simple, low-throughput memory-mapped communication, such as logic control and status registers.

[0003] In the process of realizing this invention, the inventors discovered the following defects in the prior art: At present, AXI4_Lite communication follows the AXI4 specification, and each channel has an independent handshake mechanism. Therefore, users need to control a lot of signal ports, which is more complicated and difficult to use, and the port usage flexibility is poor. Summary of the Invention

[0004] This invention provides an AXI4_Lite bus usage optimization method, apparatus, and medium to effectively simplify signal ports and reduce usage complexity and difficulty.

[0005] According to one aspect of the present invention, an AXI4_Lite bus usage optimization method is provided, comprising: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel;

[0006] The signals emitted in real time from the write address channel and the write data channel are obtained respectively. If the signal is a valid signal, a valid joint signal for writing data address is obtained by using a pre-set valid signal combination method. Under the condition that the valid joint signal for writing data address satisfies the validity condition, the valid joint signal for writing data address is written and a write operation completion signal is generated.

[0007] Once the write operation completion signal is confirmed to be valid, the pre-set automatic write response method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with the pre-set write anti-crash judgment logic, the automatic response of each channel signal is completed to optimize the use of the AXI4_Lite bus write channel.

[0008] Obtain and generate a read operation completion signal based on the read address validity signal in the read address channel;

[0009] Once the read operation completion signal is confirmed to be valid, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed by a pre-set automatic read response method. Combined with the pre-set read anti-crash judgment logic, the automatic response of each channel signal is completed to optimize the use of the AXI4_Lite bus read channels.

[0010] According to another aspect of the present invention, an AXI4_Lite bus usage optimization device is provided, comprising: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel;

[0011] The write operation completion signal generation module is used to acquire the signals emitted in real time from the write address channel and the write data channel respectively. If the signal is a valid signal, a data address write valid joint signal is obtained through a pre-set valid signal combination method. Under the condition that the data address write valid joint signal satisfies the validity condition, the data address write valid joint signal is written and a write operation completion signal is generated.

[0012] The write channel optimization module is used to process the preparation signals in the write address channel and write data channel, as well as the feedback handshake valid signal in the write response channel, through a pre-set write automatic acknowledgment method when the write operation completion signal is determined to be valid. Combined with the pre-set write anti-crash judgment logic, it completes the automatic acknowledgment of each channel signal to optimize the use of the AXI4_Lite bus write channel.

[0013] The read operation completion signal generation module is used to obtain and generate a read operation completion signal based on the read address valid signal in the read address channel;

[0014] The read channel optimization module is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a pre-set automatic read response method when the read operation completion signal is determined to be valid. Combined with the pre-set read anti-crash judgment logic, it completes the automatic response of each channel signal to optimize the use of the AXI4_Lite bus read channel.

[0015] According to another aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the AXI4_Lite bus usage optimization method according to any embodiment of the present invention.

[0016] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the AXI4_Lite bus usage optimization method according to any embodiment of the present invention.

[0017] The technical solution of this invention involves acquiring signals emitted in real time from the write address channel and the write data channel. If the signal is valid, a data address write valid combined signal is obtained through a pre-set valid signal combination method. Under the condition that the data address write valid combined signal satisfies validity, the data address write valid combined signal is written, and a write operation completion signal is generated. If the write operation completion signal is determined to be valid, a pre-set automatic write acknowledgment method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with a pre-set write anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus write channel. A read operation completion signal is generated based on the read address valid signal in the read address channel. If the read operation completion signal is determined to be valid, a pre-set automatic read acknowledgment method is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel. Combined with a pre-set read anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus read channel. It solves the problems of having many signal ports, making their use more complicated and difficult. It simplifies the signal ports, reduces the complexity and difficulty of use, and improves the flexibility of port usage.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 is a flowchart of an AXI4_Lite bus usage optimization method provided according to Embodiment 1 of the present invention;

[0021] Figure 2 is a schematic diagram of an AXI4_Lite bus usage optimization device provided according to Embodiment 2 of the present invention;

[0022] Figure 3 is a schematic diagram of the structure of an electronic device provided according to Embodiment 3 of the present invention. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "target," "current," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] Example 1

[0026] Figure 1 is a flowchart of an AXI4_Lite bus usage optimization method provided in Embodiment 1 of the present invention. This embodiment is applicable to the use optimization of the AXI4_Lite bus. The method can be executed by an AXI4_Lite bus usage optimization device, which can be implemented in hardware and / or software.

[0027] The AXI4_Lite bus includes a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel.

[0028] Accordingly, as shown in Figure 1, the method includes:

[0029] S110. Obtain the signals emitted in real time from the write address channel and the write data channel respectively. If the signal is a valid signal, obtain the data address write valid combined signal by a pre-set valid signal combination method. Under the condition that the data address write valid combined signal satisfies the validity condition, write the data address write valid combined signal and generate a write operation completion signal.

[0030] Optionally, the write address channel includes a write address prepare signal and a write address valid signal; the write data channel includes a write data prepare signal and a write data valid signal; the write response channel includes a feedback handshake prepare signal and a feedback handshake valid signal; the read address channel includes a read address prepare signal and a read address valid signal; and the read data channel includes a read data prepare signal and a read data valid signal.

[0031] In this embodiment, each channel in the AXI4_Lite bus includes different signals.

[0032] In addition, the write address channel also includes a write address channel address interface signal; the write data channel also includes a write data channel data interface signal; the read address channel also includes a read address channel address interface signal; and the read data channel also includes a read data channel data interface signal and a read address channel response interface signal.

[0033] Optionally, the valid signals include a write address valid signal and a write data valid signal; the step of acquiring the signals emitted in real time from the write address channel and the write data channel respectively, and if the signal is a valid signal, obtaining a data address write valid combined signal through a pre-set valid signal combination method, and writing the data address write valid combined signal under the condition that the data address write valid combined signal satisfies validity, and generating a write operation completion signal, includes: acquiring the signals emitted in real time from the write address channel and the write data channel respectively; if the signal is a write address valid signal or a write data valid signal, combining the write address valid signal and the write data valid signal through a pre-set valid signal combination method to obtain a data address write valid combined signal; writing the data address write valid combined signal under the condition that the data address write valid combined signal satisfies validity, and delaying the data address write valid combined signal to generate a write operation completion signal.

[0034] For example, assume the write address valid signal is axi_awvalid; the write data valid signal is axi_wvalid; the data address write valid combined signal is wreq; and the write data channel data interface signal is axi_wdata.

[0035] Specifically, the signals emitted in real time from the write address channel and the write data channel are obtained separately. If the signals are axi_awvalid and axi_wvalid, they need to be combined and merged using the valid signal combination method to obtain wreq.

[0036] Furthermore, determine whether wreq is valid. If wreq meets the validity condition, then axi_wdata on the data line needs to be written.

[0037] Correspondingly, the write-valid joint signal wreq is delayed to generate a write operation completion signal, which can be set to wack.

[0038] The advantage of this setup is that it allows multiple interfaces to be represented by writing data addresses into valid joint signals, simplifying the acquisition of signals from multiple interfaces and simplifying the usage steps.

[0039] S120. Once the write operation completion signal is determined to be valid, the pre-set automatic write response method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with the pre-set write anti-crash judgment logic, the automatic response of each channel signal is completed to optimize the use of the AXI4_Lite bus write channel.

[0040] In this embodiment, the write address prepare signal, write data prepare signal, and feedback handshake valid signal need to be converted into automatic acknowledgment signals. Specifically, the process of converting the feedback handshake valid signal into an automatic acknowledgment signal needs to be considered in conjunction with the specific circumstances of the feedback handshake prepare signal.

[0041] Optionally, upon determining that the write operation completion signal is valid, the pre-set automatic write acknowledgment method is used to process the preparation signals in the write address channel and the write data channel respectively, and combined with the pre-set write anti-crash judgment logic, to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channels. This includes: upon determining that the write operation completion signal is valid, the pre-set automatic write acknowledgment method is used to determine whether the write address preparation signal or the write data preparation signal is pulled high; if so, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current automatic acknowledgment processing operation ends; if the write address preparation signal or the write data preparation signal is pulled low, the pre-set automatic acknowledgment method is used to determine whether the write address preparation signal or the write data preparation signal is pulled low. If the readiness signal is not high, and the write operation completion signal is high, then the write address readiness signal or write data readiness signal will be pulled high at the next moment, and the current automatic acknowledgment process will end. If the write address readiness signal or write data readiness signal is not high, and the write operation completion signal is not high, then a pre-set write operation allowed cycle threshold will be obtained. Combined with a pre-set write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, then the write operation completion signal will be pulled high, and the current automatic acknowledgment process will end. This completes the automatic acknowledgment of the write address channel and the write data channel, thereby optimizing the use of the AXI4_Lite bus write channels.

[0042] In this embodiment, the automatic response processing method for the write address preparation signal and the write data preparation signal is the same.

[0043] Continuing with the previous example, taking the write data preparation signal as an example, where the write data preparation signal is axi_wready. First, it's necessary to determine if wack is valid. If wack is valid, then the automatic acknowledgment method is used to check if axi_wready is high. If it is, then at the next moment, axi_wready is pulled low, and the current automatic acknowledgment operation ends.

[0044] Furthermore, if axi_wready is not in a high state, and wack is in a high state, then axi_wready will be pulled into a high state in the next moment, and the current automatic response processing operation will end.

[0045] Correspondingly, if `axi_wready` is not high, and if `wack` is not high, the write operation allowed cycle threshold is obtained. Assuming the allowed cycle threshold is 20 cycles, and the current total number of write operation cycles is 21 cycles, combined with the write anti-crash judgment logic, since the current total number of write operation cycles exceeds the allowed cycle threshold, `wack` is raised to a high state, ending the current automatic acknowledgment process. This completes the automatic acknowledgment for both the write address channel and the write data channel, optimizing the use of the AXI4_Lite bus write channels. This way, by comparing the cycle thresholds and raising `wack`, the current automatic acknowledgment operation can be forcibly terminated, avoiding waste of memory resources.

[0046] Optionally, upon determining that the write operation completion signal is valid, the feedback handshake valid signal in the write response channel is processed using a pre-set write automatic acknowledgment method, and combined with pre-set write anti-crash judgment logic, automatic acknowledgment of each channel signal is completed to optimize the use of the AXI4_Lite bus write channel. This includes: upon determining that the write operation completion signal is valid, the pre-set write automatic acknowledgment method is used to determine whether both the feedback handshake valid signal and the feedback handshake preparation signal in the write response channel are pulled high. If so, the feedback handshake valid signal is pulled low at the next moment, and the current automatic acknowledgment processing operation ends; if both the feedback handshake valid signal and the feedback handshake preparation signal in the write response channel are pulled low, the automatic acknowledgment processing operation ends. If the hand-ready signal is not met, the handshake signal is pulled high. If the write operation complete signal is pulled high, and the feedback handshake valid signal is pulled high at the next moment, the current automatic response processing operation ends. If the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both pulled high, and the write operation complete signal is not pulled high, the pre-set write operation allowed cycle threshold is obtained. Combined with the pre-set write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, the write operation complete signal is pulled high, and the current automatic response processing operation ends. The automatic response of the write response channel is completed to optimize the use of the AXI4_Lite bus write channel.

[0047] Continuing from the previous example, let's assume the handshake validity signal is axi_bvalid and the handshake readiness signal is axi_bready.

[0048] Specifically, it is necessary to first determine whether the 'wack' is in a valid state. If the 'wack' is in a valid state, then by writing the automatic response method, it is necessary to determine whether both 'axi_bvalid' and 'axi_bready' are in a high state. If so, then at the next moment, 'axi_bvalid' will be pulled low and the current automatic response processing operation will end.

[0049] Furthermore, if both axi_bvalid and axi_bready are not in a high state, and wack is in a high state, then axi_bvalid will be processed to be in a high state at the next moment, and the current automatic response processing operation will end.

[0050] Correspondingly, if both `axi_bvalid` and `axi_bready` are in a high state, and if `wack` is not in a high state, the write operation allowed cycle threshold is obtained. Combined with the write anti-crash judgment logic, if the total number of current write operation cycles exceeds the write operation allowed cycle threshold, `wack` is brought high, ending the current automatic acknowledgment process. This completes the automatic acknowledgment of the write response channel, thus optimizing the use of the AXI4_Lite bus write channel. The write anti-crash judgment logic here is the same as the preparation signal processing method in the write address channel and write data channel, and will not be elaborated further.

[0051] S130. Obtain and generate a read operation completion signal based on the read address valid signal in the read address channel.

[0052] Optionally, the step of acquiring and generating a read operation completion signal based on the read address valid signal in the read address channel includes: acquiring and obtaining a read operation flag signal based on the read address valid signal in the read address channel; and performing delay processing on the read operation flag signal to generate the read operation completion signal.

[0053] In this embodiment, it is assumed that the read address valid signal is axi_arvalid and the read operation flag signal is rreq. Since the read operation flag signal is equal to the read address valid signal, axi_arvalid needs to be assigned to rreq.

[0054] Furthermore, the rreq is delayed to generate a read operation completion signal.

[0055] S140. Once the read operation completion signal is determined to be valid, the read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed by a pre-set automatic read response method. Combined with the pre-set read anti-crash judgment logic, the automatic response of each channel signal is completed to optimize the use of the AXI4_Lite bus read channel.

[0056] Optionally, upon determining that the read operation completion signal is valid, a pre-set automatic read response method is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel, respectively. Combined with a pre-set read anti-crash judgment logic, automatic response for each channel signal is completed to optimize the use of the AXI4_Lite bus read channels. This includes: upon determining that the read operation completion signal is valid, the pre-set automatic read response method is used to determine whether the read address preparation signal is in a high state. If so, the read address preparation signal is pulled low at the next moment, and the current automatic response operation ends. If the read address preparation signal is not in a high state, the read operation completion signal is determined to be in a high state. If so, the read address preparation signal is pulled high at the next moment, and the current automatic response operation ends. If the read operation completion signal is not in a high state, a pre-set read operation allowable cycle threshold is obtained. Combined with the pre-set read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowable cycle threshold, the read operation completion signal is processed. The signal is pulled high to end the current automatic response process. If the read operation completion signal is confirmed to be valid, the pre-set automatic response method checks whether both the read address preparation signal and the read data valid signal are pulled high. If so, the read data valid signal and the read data channel interface signal are pulled low in the next step, and the current automatic response process ends. If the read address preparation signal or the read data valid signal is not confirmed to be high, the read operation completion signal is checked. If so, the read data is sent to the read data channel interface. If the read address preparation signal is confirmed to be valid, the read data valid signal is pulled low in the next step, and the current automatic response process ends. If the read operation completion signal is not confirmed to be high, a pre-set read operation allowed cycle threshold is obtained. Combined with a pre-set read anti-crash judgment logic, if the total number of current read operation cycles exceeds the read operation allowed cycle threshold, the read operation completion signal is pulled high, and the current automatic response process ends, thus optimizing the use of the AXI4_Lite bus read channel.

[0057] For example, assume the read address read preparation signal is axi_arready; the read data valid signal is axi_rvalid; and the read operation complete signal is rack.

[0058] For the automatic response processing of axi_arready, it is first necessary to determine whether the rack is in a valid state. If the rack is in a valid state, the automatic response method is read to determine whether axi_arready is in a high state. If so, the next step is to pull axi_arready to a low state and end the current automatic response processing operation.

[0059] Furthermore, if it is determined that axi_arready is not in a high state, then it is determined whether rack is in a high state. If so, then axi_arready is processed to be in a high state at the next time step, and the current automatic response processing operation is terminated.

[0060] Accordingly, if the rack is not in a high state, the allowed read operation cycle threshold is obtained. Combined with the read operation anti-crash judgment logic, if the total number of current read operation cycles exceeds the allowed read operation cycle threshold, the read operation completion signal is pulled high, ending the current automatic response processing operation. Specifically, assuming the allowed read operation cycle threshold is 10 and the current total number of read operation cycles is 11, since the current total number of read operation cycles exceeds the allowed read operation cycle threshold, the rack is pulled high, ending the current automatic response processing operation.

[0061] For the automatic response processing of axi_rvalid, it is first necessary to determine whether the rack is in a valid state. If the rack is in a valid state, the automatic response method is read to determine whether both axi_arready and axi_rvalid are in a high state. If so, the next step is to pull axi_rvalid low and also pull the data interface signal of the read data channel low, and then end the current automatic response processing operation.

[0062] Furthermore, if it is determined that axi_arready or axi_rvalid is not in a high state, then it is determined whether rack is in a high state. If so, the current data read is sent to the data interface axi_rdata of the data reading channel. When axi_arready is in a valid state, axi_rvalid is pulled low in the next moment, and the current automatic response processing operation ends.

[0063] Correspondingly, if the rack is not in a high state, the allowable read operation cycle threshold is obtained. Combined with the read anti-crash judgment logic, if the total number of current read operation cycles is greater than the allowable read operation cycle threshold, the rack is pulled high to end the current automatic response processing operation, so as to complete the optimization of the read channel of the AXI4_Lite bus.

[0064] In this embodiment, for write data operations on the device side using the AXI4_Lite bus, a valid wreq signal indicates that the server has successfully written data to the write address. For read data operations on the device side using the AXI4_Lite bus, a valid rreq signal updates the read data, thus successfully completing the server's read operation at the read address.

[0065] The technical solution of this invention involves acquiring signals emitted in real time from the write address channel and the write data channel. If the signal is valid, a data address write valid combined signal is obtained through a pre-set valid signal combination method. Under the condition that the data address write valid combined signal satisfies validity, the data address write valid combined signal is written, and a write operation completion signal is generated. If the write operation completion signal is determined to be valid, a pre-set automatic write acknowledgment method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with a pre-set write anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus write channel. A read operation completion signal is generated based on the read address valid signal in the read address channel. If the read operation completion signal is determined to be valid, a pre-set automatic read acknowledgment method is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel. Combined with a pre-set read anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus read channel. It solves the problems of having many signal ports, making their use more complicated and difficult. It simplifies the signal ports, reduces the complexity and difficulty of use, and improves the flexibility of port usage.

[0066] Example 2

[0067] Figure 2 is a schematic diagram of an AXI4_Lite bus usage optimization device provided in Embodiment 2 of the present invention. The AXI4_Lite bus usage optimization device provided in this embodiment can be implemented by software and / or hardware, and can be configured in a terminal device or server to implement an AXI4_Lite bus usage optimization method according to the present invention. As shown in Figure 2, the device includes: a write operation completion signal generation module, a write channel usage optimization module, a read operation completion signal generation module, and a read channel usage optimization module.

[0068] The AXI4_Lite bus includes: write address channel, write data channel, write response channel, read address channel, and read data channel.

[0069] The write operation completion signal generation module is used to acquire the signals emitted in real time from the write address channel and the write data channel respectively. If the signal is a valid signal, a data address write valid joint signal is obtained through a pre-set valid signal combination method. Under the condition that the data address write valid joint signal satisfies the validity condition, the data address write valid joint signal is written and a write operation completion signal is generated.

[0070] The write channel optimization module is used to process the preparation signals in the write address channel and write data channel, as well as the feedback handshake valid signal in the write response channel, through a pre-set write automatic acknowledgment method when the write operation completion signal is determined to be valid. Combined with the pre-set write anti-crash judgment logic, it completes the automatic acknowledgment of each channel signal to optimize the use of the AXI4_Lite bus write channel.

[0071] The read operation completion signal generation module is used to obtain and generate a read operation completion signal based on the read address valid signal in the read address channel;

[0072] The read channel optimization module is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a pre-set automatic read response method when the read operation completion signal is determined to be valid. Combined with the pre-set read anti-crash judgment logic, it completes the automatic response of each channel signal to optimize the use of the AXI4_Lite bus read channel.

[0073] The technical solution of this invention involves acquiring signals emitted in real time from the write address channel and the write data channel. If the signal is valid, a data address write valid combined signal is obtained through a pre-set valid signal combination method. Under the condition that the data address write valid combined signal satisfies validity, the data address write valid combined signal is written, and a write operation completion signal is generated. If the write operation completion signal is determined to be valid, a pre-set automatic write acknowledgment method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with a pre-set write anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus write channel. A read operation completion signal is generated based on the read address valid signal in the read address channel. If the read operation completion signal is determined to be valid, a pre-set automatic read acknowledgment method is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel. Combined with a pre-set read anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus read channel. It solves the problems of having many signal ports, making their use more complicated and difficult. It simplifies the signal ports, reduces the complexity and difficulty of use, and improves the flexibility of port usage.

[0074] Based on the above embodiments, the write address channel includes a write address preparation signal and a write address valid signal; the write data channel includes a write data preparation signal and a write data valid signal; the write response channel includes a feedback handshake preparation signal and a feedback handshake valid signal; the read address channel includes a read address preparation signal and a read address valid signal; and the read data channel includes a read data preparation signal and a read data valid signal.

[0075] Based on the above embodiments, the valid signals include a write address valid signal and a write data valid signal.

[0076] Based on the above embodiments, the write operation completion signal generation module can be specifically used to: acquire signals emitted in real time from the write address channel and the write data channel respectively; if the signal is a write address valid signal or a write data valid signal, combine the write address valid signal and the write data valid signal using a pre-set valid signal combination method to obtain a data address write valid joint signal; under the condition that the data address write valid joint signal satisfies validity, write the data address write valid joint signal, and perform delay processing on the data address write valid joint signal to generate a write operation completion signal.

[0077] Based on the above embodiments, the write channel optimization module can be specifically used to: when the write operation completion signal is determined to be valid, determine whether the write address preparation signal or the write data preparation signal is high using a pre-set write automatic acknowledgment method; if so, pull the write address preparation signal or the write data preparation signal low at the next moment and end the current automatic acknowledgment process; if the write address preparation signal or the write data preparation signal is not high, but the write operation completion signal is high, pull the write address preparation signal or the write data preparation signal high at the next moment and end the current automatic acknowledgment process; if the write address preparation signal or the write data preparation signal is not high, and the write operation completion signal is not high, obtain a pre-set write operation allowed cycle threshold, and combine it with a pre-set write anti-crash judgment logic; if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, pull the write operation completion signal high and end the current automatic acknowledgment process; thus completing the automatic acknowledgment of the write address channel and the write data channel to optimize the use of the AXI4_Lite bus write channel.

[0078] Based on the above embodiments, the write channel optimization module can also be specifically used for: when the write operation completion signal is determined to be valid, determining whether the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are both high using a pre-set write automatic acknowledgment method; if so, the feedback handshake valid signal is pulled low at the next moment, and the current automatic acknowledgment processing operation ends; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both high, but the write operation completion signal is high, and the feedback handshake valid signal is pulled high at the next moment, and the current automatic acknowledgment processing operation ends; if the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are not both high, and the write operation completion signal is not high, obtaining a pre-set write operation allowed cycle threshold, and combining it with a pre-set write anti-crash judgment logic; if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, then the write operation completion signal is pulled high, and the current automatic acknowledgment processing operation ends; thus completing the automatic acknowledgment of the write response channel to optimize the use of the AXI4_Lite bus write channel.

[0079] Based on the above embodiments, the read operation completion signal generation module can be specifically used to: obtain a read operation flag signal based on the read address valid signal in the read address channel; perform delay processing on the read operation flag signal to generate the read operation completion signal.

[0080] Based on the above embodiments, the read channel uses an optimization module, which can be specifically used to: when the read operation completion signal is determined to be valid, determine whether the read address preparation signal is in a high state using a pre-set automatic read response method; if so, perform a low state processing operation on the read address preparation signal at the next moment and end the current automatic response processing operation; if the read address preparation signal is not in a high state, determine whether the read operation completion signal is in a high state; if so, perform a high state processing operation on the read address preparation signal at the next moment and end the current automatic response processing operation; if the read operation completion signal is not in a high state, obtain a pre-set read operation allowed cycle threshold, and combine it with a pre-set read anti-crash judgment logic; if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, perform a high state processing operation on the read operation completion signal and end the current automatic response processing operation; when the read operation completion signal is determined to be valid, perform a low state processing operation on the read address preparation signal using a pre-set automatic read response method. The response method involves checking whether both the read address preparation signal and the read data valid signal are in a high state. If so, the read data valid signal and the read data channel data interface signal are pulled low in the next step, and the current automatic response process ends. If neither the read address preparation signal nor the read data valid signal is in a high state, the method checks whether the read operation completion signal is in a high state. If so, the read data is sent to the read data channel data interface. When the read address preparation signal is in a valid state, the read data valid signal is pulled low in the next step, and the current automatic response process ends. If the read operation completion signal is not in a high state, the method obtains a pre-set read operation allowed cycle threshold and combines it with a pre-set read anti-crash judgment logic. If the total number of current read operation cycles exceeds the read operation allowed cycle threshold, the read operation completion signal is pulled high, and the current automatic response process ends, thus optimizing the use of the AXI4_Lite bus read channel.

[0081] The AXI4_Lite bus usage optimization device provided in this embodiment of the invention can execute the AXI4_Lite bus usage optimization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0082] Example 3

[0083] Figure 3 shows a schematic diagram of the structure of an electronic device 10 that can be used to implement Embodiment 3 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0084] As shown in Figure 3, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer programs stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0085] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0086] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the optimized methods used on the AXI4_Lite bus.

[0087] In some embodiments, the AXI4_Lite bus usage optimization method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the AXI4_Lite bus usage optimization method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the AXI4_Lite bus usage optimization method by any other suitable means (e.g., by means of firmware).

[0088] The method includes: acquiring signals emitted in real time from the write address channel and the write data channel respectively; if the signal is valid, obtaining a valid data address write joint signal through a pre-set valid signal combination method; and writing the valid data address write joint signal under the condition that the valid data address write joint signal satisfies the validity condition, and generating a write operation completion signal; if the write operation completion signal is determined to be valid, processing the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel, through a pre-set automatic write acknowledgment method, and combining it with a pre-set write anti-crash judgment logic to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channel; acquiring and generating a read operation completion signal based on the valid read address signal in the read address channel; if the read operation completion signal is determined to be valid, processing the read address preparation signal in the read address channel and the valid read data signal in the read data channel, through a pre-set automatic read acknowledgment method, and combining it with a pre-set read anti-crash judgment logic to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus read channel.

[0089] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0093] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0094] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0095] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0096] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0097] Example 4

[0098] Embodiment 4 of the present invention also provides a computer-readable storage medium, wherein the computer-readable instructions, when executed by a computer processor, are used to execute an AXI4_Lite bus usage optimization method. The method includes: acquiring signals emitted in real time from the write address channel and the write data channel respectively; if the signals are valid, obtaining a data address write valid combined signal using a pre-set valid signal combination method; and, under the condition that the data address write valid combined signal satisfies validity, writing the data address write valid combined signal and generating a write operation completion signal; and, if the write operation completion signal is determined to be valid, then, using a pre-set write automatic acknowledgment method, respectively acknowledging the write address channel and the write data channel... The system processes the preparation signal and the feedback handshake valid signal in the write response channel, and combines this with pre-set write anti-crash judgment logic to complete the automatic response of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channel; it acquires and generates a read operation completion signal based on the read address valid signal in the read address channel; when the read operation completion signal is determined to be valid, it processes the read address preparation signal in the read address channel and the read data valid signal in the read data channel respectively through a pre-set automatic read response method, and combines this with pre-set read anti-crash judgment logic to complete the automatic response of each channel signal, thereby optimizing the use of the AXI4_Lite bus read channel.

[0099] Of course, the computer-executable instructions provided in the embodiments of the present invention, which include a computer-readable storage medium, are not limited to the method operations described above, but can also perform related operations in the AXI4_Lite bus usage optimization provided in any embodiment of the present invention.

[0100] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0101] It is worth noting that in the above-described optimized embodiment of the AXI4_Lite bus, the various units and modules are divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the scope of protection of this invention.

[0102] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An optimization method for using the AXI4_Lite bus, characterized in that, The AXI4_Lite bus includes: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel. Signals emitted in real-time from the write address channel and the write data channel are acquired. If a signal is valid, a pre-set valid signal combination method is used to obtain a valid data address write joint signal. If the valid data address write joint signal satisfies the validity condition, the data address write joint signal is written, and a write operation completion signal is generated. If the write operation completion signal is confirmed to be valid, a pre-set automatic write acknowledgment method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. Combined with pre-set write anti-crash judgment logic, automatic acknowledgment of each channel signal is achieved, thus optimizing the use of the AXI4_Lite bus write channels. A read operation flag signal is obtained based on the valid read address signal in the read address channel. The read operation flag signal is delayed to generate a read operation completion signal. If the read operation completion signal is confirmed to be valid, the pre-set automatic read acknowledgment method is used to process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel. The read address preparation signal in the read address channel and the read data valid signal in the read data channel are processed, and combined with a pre-set read anti-crash judgment logic, automatic response of each channel signal is completed to optimize the use of the AXI4_Lite bus read channels. Specifically, the process of acquiring the signals emitted in real time from the write address channel and the write data channel, and if the signal is valid, obtaining a data address write valid combined signal using a pre-set valid signal combination method, and writing the data address write valid combined signal under the condition that the data address write valid combined signal satisfies validity, and generating a write operation completion signal, includes: acquiring the signals emitted in real time from the write address channel and the write data channel; if the signal is a write address valid signal or a write data valid signal, combining the write address valid signal and the write data valid signal using a pre-set valid signal combination method to obtain a data address write valid combined signal; writing the data address write valid combined signal under the condition that the data address write valid combined signal satisfies validity, and delaying the data address write valid combined signal to generate a write operation completion signal.

2. The method according to claim 1, characterized in that, The write address channel includes a write address ready signal and a write address valid signal; the write data channel includes a write data ready signal and a write data valid signal; the write response channel includes a feedback handshake ready signal and a feedback handshake valid signal. The read address channel includes a read address ready signal and a read address valid signal; The data read channel includes a data read preparation signal and a data read valid signal.

3. The method according to claim 2, characterized in that, When the write operation completion signal is determined to be valid, the pre-set write auto-acknowledgment method processes the preparation signals in the write address channel and write data channel respectively, and combines them with the pre-set write anti-crash judgment logic to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channels. This includes: when the write operation completion signal is determined to be valid, the pre-set write auto-acknowledgment method determines whether the write address preparation signal or the write data preparation signal is pulled high; if so, the write address preparation signal or the write data preparation signal is pulled low at the next moment, and the current auto-acknowledgment processing operation ends; if the write address preparation signal or the write data preparation signal is not pulled high, the pre-set write auto-acknowledgment method determines whether the write address preparation signal or the write data preparation signal is pulled low. If the write operation completion signal is not high, and the write address preparation signal or write data preparation signal is high, then the write address preparation signal or write data preparation signal will be pulled high at the next moment, and the current automatic acknowledgment process will end. If the write address preparation signal or write data preparation signal is not high, and the write operation completion signal is not high, then a pre-set write operation allowed cycle threshold will be obtained. Combined with a pre-set write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, then the write operation completion signal will be pulled high, and the current automatic acknowledgment process will end. This completes the automatic acknowledgment of the write address channel and the write data channel, thereby optimizing the use of the AXI4_Lite bus write channels.

4. The method according to claim 2, characterized in that, When the write operation completion signal is determined to be valid, the pre-set write automatic acknowledgment method processes the feedback handshake valid signal in the write response channel, and combines it with the pre-set write anti-crash judgment logic to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channel. This includes: when the write operation completion signal is determined to be valid, the pre-set write automatic acknowledgment method determines whether both the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are pulled high. If so, the feedback handshake valid signal is pulled low at the next moment, and the current automatic acknowledgment processing operation ends; if both the feedback handshake valid signal and the feedback handshake ready signal in the write response channel are pulled low, the automatic acknowledgment process ends. If the backup signal is not in a high state, and the write operation completion signal is in a high state, the feedback handshake valid signal will be pulled high at the next moment, and the current automatic response processing will end. If the feedback handshake valid signal and feedback handshake ready signal in the write response channel are not both in a high state, and the write operation completion signal is not in a high state, then the pre-set write operation allowed cycle threshold is obtained. Combined with the pre-set write anti-crash judgment logic, if the total number of current write operation cycles is greater than the write operation allowed cycle threshold, then the write operation completion signal will be pulled high, and the current automatic response processing will end. The automatic response of the write response channel is completed to optimize the use of the AXI4_Lite bus write channel.

5. The method according to claim 2, characterized in that, When the read operation completion signal is determined to be valid, a pre-set automatic read response method is used to process the read address preparation signal in the read address channel and the read data valid signal in the read data channel, respectively. Combined with pre-set read anti-crash judgment logic, automatic response is performed on each channel signal to optimize the use of the AXI4_Lite bus read channels. This includes: when the read operation completion signal is determined to be valid, the pre-set automatic read response method is used to determine whether the read address preparation signal is in a high state. If so, the read address preparation signal is pulled low at the next moment, and the current automatic response operation ends. If the read address preparation signal is not in a high state, the read operation completion signal is determined to be high. If so, the read address preparation signal is pulled high at the next moment, and the current automatic response operation ends. If the read operation completion signal is not in a high state, a pre-set read operation allowed cycle threshold is obtained. Combined with the pre-set read anti-crash judgment logic, if the total number of current read operation cycles is greater than the read operation allowed cycle threshold, the read operation completion signal is... The process involves several steps: First, a high-state processing is performed to terminate the current automatic response operation. If the read operation completion signal is confirmed to be valid, a pre-set automatic response method is used to determine if both the read address preparation signal and the read data valid signal are high. If so, the read data valid signal and the read data channel interface signal are pulled low at the next moment, and the current automatic response operation ends. If either the read address preparation signal or the read data valid signal is not high, the read operation completion signal is checked. If it is, the read data is sent to the read data channel interface. If the read address preparation signal is valid, the read data valid signal is pulled low at the next moment, and the current automatic response operation ends. If the read operation completion signal is not high, a pre-set read operation allowed cycle threshold is obtained. Combined with pre-set read anti-crash judgment logic, if the total number of current read operation cycles exceeds the read operation allowed cycle threshold, the read operation completion signal is pulled high, and the current automatic response operation ends, thus optimizing the use of the AXI4_Lite bus read channel.

6. An AXI4_Lite bus optimization device, characterized in that, The AXI4_Lite bus includes: a write address channel, a write data channel, a write response channel, a read address channel, and a read data channel; a write operation completion signal generation module, used to acquire signals emitted in real time from the write address channel and the write data channel respectively; if the signal is valid, a data address write valid joint signal is obtained through a pre-set valid signal combination method; and under the condition that the data address write valid joint signal satisfies validity, the data address write valid joint signal is written, and a write operation completion signal is generated; a write channel usage optimization module, used to, when the write operation completion signal is determined to be valid, process the preparation signals in the write address channel and the write data channel, as well as the feedback handshake valid signal in the write response channel, respectively, through a pre-set write automatic acknowledgment method, and combine with a pre-set write anti-crash judgment logic to complete the automatic acknowledgment of each channel signal, thereby optimizing the use of the AXI4_Lite bus write channels; a read operation completion signal generation module, used to acquire and obtain a read operation flag signal based on the read address valid signal in the read address channel; The read operation flag signal is delayed to generate the read operation completion signal. The read channel optimization module, upon determining that the read operation completion signal is valid, processes the read address preparation signal in the read address channel and the read data valid signal in the read data channel using a pre-set automatic read response method, and combines this with pre-set read anti-crash judgment logic to automatically respond to each channel signal, thereby optimizing the use of the AXI4_Lite bus read channels. The write operation completion signal generation module is used to: acquire the signals emitted in real time from the write address channel and the write data channel; if the signal is a write address valid signal or a write data valid signal, combine the write address valid signal and the write data valid signal using a pre-set valid signal combination method to obtain a data address write valid joint signal; under the condition that the data address write valid joint signal satisfies validity, write the data address write valid joint signal, and delay the data address write valid joint signal to generate the write operation completion signal.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements an AXI4_Lite bus usage optimization method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute an AXI4_Lite bus usage optimization method as described in any one of claims 1-5.

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