Register array-based random verification method, electronic device and medium

Abstract

This invention relates to the field of chip verification technology, and more particularly to a random verification method, electronic device, and medium based on register arrays. S1: Set m=1, execute S2; S2: Send data to RA in the target register array. m and RB m Input the same random test stimulus; S3, RA m Predict the random write value, and set F m Updated to RA m Predicted random write values; S4, RB m Write random numbers based on the input random test stimulus; S5, read the currently stored data in the RTL instances of all registers in the chip under test design in random order and compare it with the corresponding reference value. If they are all the same, proceed to S6; otherwise, the verification fails and the process ends; S6, compare m and M. If m

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a random verification method based on a register array, an electronic device and a medium. BACKGROUND

[0002] At present, in the process of chip verification, a universal verification methodology (UVM) needs to be used to generate a UVM RAL (Universal Verification Methodology) register model in a verification environment, and the UVM RAL register model is used to verify a hardware register model in a DUT. In a graphics processing unit (GPU) system, a case of one address mapping multiple registers often occurs, multiple registers corresponding to one address form a register array, and the GPU system needs to access multiple different register entities in the register array using the same address. However, the existing register addressing is address addressing, one address corresponds to one register, and there is only one register entity in the UVM RAL for the same address. Therefore, based on the existing UVM RAL, only random verification containing a single register can be implemented, and random verification containing a register array cannot be implemented. Therefore, how to implement random verification containing a register array becomes a problem to be solved. SUMMARY

[0003] The present application aims to provide a random verification method based on a register array, an electronic device and a medium, which can implement random verification containing a register array.

[0004] According to a first aspect of the present application, a random verification method based on a register array is provided, comprising:

[0005] Step S1, initially setting m=1, and performing step S2;

[0006] Step S2, inputting the same random test stimulus into a UVM RAL model instance RA m and an RTL instance RB m corresponding to the mth register in the target register array;

[0007] Step S3, predicting a random write value based on the input random test stimulus, and updating F m in {F1, F2,..., F m ,..., F M} to RA m based on the random write value. mpredicted random write values, {F1, F2,..., F m ,...,F M} are the reference values stored in the preset cache area of the RA m corresponding reference value sequence, F m are the reference values stored in the RA m ;

[0008] Step S4, the RB m writes random numbers based on the input random test excitation;

[0009] Step S5, the out-of-order reading compares the current data stored in the RTL instance of all registers in the chip design under test with the current corresponding reference values, and if all are the same, step S6 is executed, otherwise, the verification fails and the process ends;

[0010] Step S6, compare m and M, if m < M, set m = m + 1, return to execute step S2, if m = M, end the random verification of the target register array.

[0011] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method of the first aspect of the present application.

[0012] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions, and the computer instructions are used to execute the method of the first aspect of the present application.

[0013] Compared with the prior art, the present application has obvious advantages and beneficial effects. By the above technical scheme, the random verification method based on register array, electronic device and medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value, which at least has the following beneficial effects:

[0014] The reference values of the register array are pre-stored in the preset cache area and updated in real time in the embodiment of the present application, which ensures that the reference values of the register array are accurate and easy to obtain, and realizes the random verification of the register array. In addition, when each register in the register array is completely and randomly written, the current data stored in the RTL instance of all registers in the chip design under test is compared with the current corresponding reference values, which can improve the efficiency and accuracy of debugging. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to make the technical solutions in the embodiments of the present application clearer, the accompanying drawings needed in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only represent some of the embodiments of the present application, and all other embodiments obtained by those skilled in the art without creative efforts based on these accompanying drawings also belong to the protection scope of the present application.

[0016] Figure 1 A flow chart of a random verification method based on a register array is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts also belong to the protection scope of the present application.

[0018] The embodiments of the present application provide a random verification method based on a register array, as shown in the following formula (1), which comprises the following steps. Figure 1

[0019] Step S1, initially setting m=1, and performing step S2.

[0020] It should be noted that the register array comprises M registers, m is the register number in the register array, and M is the total number of registers in the register array.

[0021] Step S2, inputting the same random test excitation into the UVM RAL model instance RA m and the RTL (Register Transfer Level) instance RB m corresponding to the mth register in the target register array.

[0022] It should be noted that each register in the chip design under test has a corresponding UVM RAL model instance and RTL instance, and RA m and RB m are in one-to-one correspondence. Generally, the verification code drives the UVM RAL model to predict the random write value based on the corresponding address and attribute, and the UVM RAL model inputs the same random test excitation into the RTL instance based on the verification component to perform the random write operation in the RTL instance. The chip design under test can be a GPU chip design.

[0023] Step S3, RA m predicts the random write value based on the input random test excitation, and inputs the predicted random write value {F1, F2,..., F m ,..., F​M F in} m Updated to RA m Predicted random write values, {F1,F2,...,F m ,...,F M} is the RA stored in the preset cache area m The corresponding reference value sequence, F m For RA m The reference value stored in it.

[0024] It should be noted that the values ​​in the UVM RAL model are standard values. If the value written in the RTL instance is consistent with the standard value in the UVM RAL model, it is correct; otherwise, the verification fails. Since the register array corresponds to only one register address, it is impossible to directly obtain the reference value in the UVM RAL model for each register in the register array. Based on this, this invention sets the reference value {F1, F2, ..., F...} corresponding to the register array in the preset cache area. m ,...,F M It is updated in real time to ensure the accuracy of the reference values ​​stored in the preset cache area and to make them easy to access.

[0025] Step S4, RB m Write random numbers based on the random test stimulus from the input.

[0026] Step S5: Read the currently stored data in the RTL instance of all registers in the chip under test design in random order and compare it with the corresponding reference value. If they are all the same, proceed to step S6; otherwise, the verification fails and the process ends.

[0027] It should be noted that, under normal circumstances, RB m The RA should be written in m The predicted random write value may vary depending on the actual situation, causing RB to fail. m The value written in is not equal to RA m Predicted random write values ​​may also exhibit RA. m The predicted random write value was incorrectly written to a non-RB. m The corresponding address may also appear in RA. m Predicted random write value written to RB m At the same time, RA will also be included. m Since the predicted random write value was written to another address, in order to ensure accuracy, step S5 requires reading the currently stored data in the RTL instance of all registers and comparing it with the corresponding reference value.

[0028] Further, in the step S5, the data currently stored in each randomly read RTL instance of the register is compared with the currently corresponding reference value, if different, the verification fails, otherwise, the data currently stored in the next randomly read RTL instance of the register is read and compared with the currently corresponding reference value, until the data currently stored in all the RTL instances of the registers in the chip design under test is read and compared with the currently corresponding reference value. It should be noted that in the prior art, the data currently stored in all the RTL instances of the registers in the chip design under test is read in sequence and compared with the currently corresponding reference value, but in some application scenarios, some problems exist in a window period. For example, in one application scenario, the problem is exposed within 5 cycles after writing the register, and the problem can be recovered by other read / write operations after 5 cycles, therefore, if the problem position cannot be read after 5 cycles, the problem cannot be verified. In addition, if the problem position is at the rear position, the sequential reading will consume a lot of time. Based on the above reasons, the present application adopts the random reading, that is, the data currently stored in all the RTL instances of the registers in the chip design under test is read in random and compared with the currently corresponding reference value, which can improve the efficiency and accuracy of debugging.

[0029] Step S6, comparing m and M, if m

[0030] In the chip design under test, in addition to the register group, there is also a single register, and the random verification of the single register type and the register group type needs to be performed in different ways. As an embodiment, the method further comprises:

[0031] Step S10, initially setting n=1, and taking R n ,...,R N} in the chip design under test as the target register instance, performing step S20, wherein R n is the nth register instance corresponding to the chip design under test, the value range of n is 1 to N, N is the total number of register instances corresponding to the chip design under test, and R n corresponding type is a single register or a register array. n

[0032] It should be noted that R n may be a single register or a register array composed of multiple registers.

[0033] Step S20, if the type corresponding to R n is a single register, step S30 is performed, and if the type corresponding to R n ​If the corresponding type is a register array, R n As the target register array, steps S1-S6 are executed, and then step S70 is executed.

[0034] Step S30, R n The corresponding UVM RAL model instance RC n and the RTL instance RD n Input the same random test stimulus.

[0035] It should be noted that each register in the chip design under test has a corresponding UVM RAL model instance and RTL instance, RC n and RD n are in one-to-one correspondence. Generally, the verification code drives the UVM RAL model to predict random write values based on the corresponding address and attribute, and the UVM RAL model inputs the same random test stimulus to the RTL instance based on the verification component to perform random write operations in the RTL instance.

[0036] Step S40, RC n predicts random write values based on the input random test stimulus, and updates the predicted random write values to RC n .

[0037] It should be noted that the R n of a single register type corresponds to RC n , which can be directly accessed based on the address, so for the R n of a single register type, the predicted random write values are directly updated to RC n as reference values.

[0038] Step S50, RD n writes random numbers based on the input random test stimulus.

[0039] Step S60, compare the current data stored in the RTL instance of all registers in the chip design under test with the current corresponding reference values in random order, if all are the same, execute step S70, otherwise, the verification fails, and the process ends.

[0040] Among them, each time the current data stored in the RTL instance of a register is randomly read, it is compared with the current corresponding reference value, if they are different, the verification fails, otherwise, the current data stored in the RTL instance of the next register is randomly read, until the current data stored in the RTL instance of all registers in the chip design under test is read and compared with the current corresponding reference value.

[0041] Step S70, comparing n and N, if n < N, setting n = n + 1, returning to execute step S20, if n = N, the verification is passed, and the flow is ended.

[0042] For the register array, there is a special copy operation to copy the data in a register in the register array to another array of the register group, and the operation can be applied to all register arrays in the chip design under test to realize efficient batch operation. For such application scenarios, the embodiment of the present application also provides a corresponding random test method. As an embodiment, the step S6 further includes:

[0043] Step S100, obtaining a register array copy instruction, the register array copy instruction being applied to all register arrays, the register array copy instruction including a first register serial number and a second register serial number.

[0044] The first register serial number is the register serial number corresponding to the source address, and the second register serial number is the register serial number corresponding to the target address. The data stored in the source address in each register array needs to be copied to the target address.

[0045] Step S200, updating the values of F1, F2,..., F m ,..., F M} corresponding to all register arrays in the chip design under test to the values of F1, F2,..., F m ,..., F m} corresponding to the first register serial number.

[0046] It should be noted that through the step S200, the values of F1, F2,..., F m ,..., F M} corresponding to all register arrays can be quickly and accurately updated.

[0047] Step S300, writing the values in the register RTL instance corresponding to the first register serial number in the RTL instance of all register arrays in the chip design under test into the register RTL instance corresponding to the second register serial number.

[0048] Step S400, comparing the currently stored data in the RTL instance of all registers in the chip design under test with the currently corresponding reference values in a disordered manner, if all are the same, the register data copy verification is passed, otherwise, the register data copy verification fails.

[0049] If the data currently stored in the RTL instance of each randomly read register is compared with the current corresponding reference value, and they are different, the verification fails, otherwise, the data currently stored in the RTL instance of the next randomly read register is read until the data currently stored in the RTL instance of all registers in the chip design under test is read and compared with the current corresponding reference value.

[0050] It should be noted that, under normal circumstances, the register array copy instruction should write the value in the register RTL instance corresponding to the first register sequence number in the RTL instance of all register arrays in the chip design under test into the register RTL instance corresponding to the second register sequence number. However, in the actual execution process, there may be exceptions, for example, there may be a situation that the value in the register RTL instance corresponding to the first register sequence number is written into the register RTL instance corresponding to the second register sequence number, and the writing value is wrong. It may also appear that the value in the register RTL instance corresponding to the first register sequence number is written into the register RTL instance corresponding to the second register sequence number. It may also appear that the value in the register RTL instance corresponding to the first register sequence number is written into the register RTL instance corresponding to the second register sequence number, and the value in the register RTL instance corresponding to the first register sequence number is also written into the register RTL instance corresponding to the second register sequence number. Therefore, in order to ensure accuracy, the data currently stored in the RTL instance of all registers in step S400 needs to be read and compared with the current corresponding reference value.

[0051] As an embodiment, in steps S5, S60 and S400, the out-of-order reading of the data currently stored in the RTL instance of all registers in the chip design under test and the current corresponding reference value includes:

[0052] In step S51, the data currently stored in the RTL instance of the register in the chip design under test is read out-of-order. If the currently read RTL instance of the register is the RTL instance of a register of the type of a single register, step S52 is performed, and if the currently read RTL instance of the register is the RTL instance of a register in a register array, step S53 is performed.

[0053] In step S52, the data stored in the UVM RAL model instance corresponding to the currently read register is obtained as a reference value and compared with the data currently stored in the RTL instance of the register.

[0054] In step S53, the corresponding reference value of the UVM RAL model instance corresponding to the currently read register in {F1, F2,..., F m ,...,F M} is obtained and compared with the data currently stored in the RTL instance of the register.

[0055] It is to be understood that some of the example embodiments are described in terms of a process or method depicted as a flowchart. Although a flowchart can describe a process as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps can be re-arranged. A process can be terminated when its operations are completed, but could also occur under some other condition or event, such as in response to a termination instruction. The processes can correspond in part to method steps for implementing the described functionality.

[0056] The embodiment of the present application further provides an electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are arranged to execute the method according to the embodiment of the present application.

[0057] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method according to the embodiment of the present application.

[0058] The embodiment of the present application pre-stores the reference values of the register arrays in the preset cache area and updates in real time, ensures that the reference values of the register arrays are accurate and easy to obtain, and realizes random verification of the register arrays. In addition, when each register in the register array is completely randomly written, the current stored data in the RTL instance of all registers in the chip design under test is compared with the current corresponding reference value, which can improve the efficiency and accuracy of debugging.

[0059] The above description is only the preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed as the above preferred embodiment, it is not intended to limit the present application. Any skilled person in the art can make some changes or modifications to the above disclosed technical content to make equivalent embodiments with equivalent changes, but as long as the content of the technical solution of the present application is not deviated, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present application are still within the scope of the technical solution of the present application.

Claims

1. A random verification method based on a register array, comprising: Step S1, initially setting m=1, and executing Step S2; Step S2, the UVM RAL model instance RA corresponding to the mth register in the target register array is set to 0 m and the RTL instance RB m input the same random test stimulus; Step S3, RA m Based on the input random test stimulus, predict the random write value, and set {F1,F2,...,F...} m ,...,F M F in} m Updated to RA m Predicted random write values, {F1,F2,...,F m ,...,F M } is the RA stored in the preset cache area m The corresponding reference value sequence, F m For RA m The reference value stored in the array is m, where m is the register number in the register array and M is the total number of registers in the register array. Step S4, RB m write a random number based on the input random test stimulus; Step S5, comparing the currently stored data in the RTL instances of all registers in the chip design under test with the current corresponding reference values, and if all are the same, executing Step S6, otherwise, the verification fails, and the process ends; Step S6, comparing m and M, if m 2. The method of claim 1, wherein the method further comprises: Step S60, comparing the currently stored data in the RTL instances of all registers in the chip design under test with the current corresponding reference values, and if all are the same, executing Step S70, otherwise, the verification fails, and the process ends; Step S10: Initial setting n=1, set the register instance set {R1,R2,...,R...} corresponding to the chip under test design. n ,...,R N R in} n As an instance of the target register, step S20 is executed, where R n This refers to the nth register instance corresponding to the chip under test design, where n ranges from 1 to N, and N is the total number of register instances corresponding to the chip under test design. R n The corresponding types are a single register or an array of registers; Step S20, if R n corresponding type is single register, then step S30 is executed, if R n corresponding type is register array, then R n as target register array, steps S1-S6 are executed, and then step S70 is executed; Step S30, to R n Corresponding UVM RAL model instance RC n And RTL instance RD n Same random test stimulus is input; Step S40, RC n Based on the input random test stimulus, predict random write values. Update the predicted random write values to RC n In; Step S50, RD n Write a random number based on the input random test stimulus; Step S70, comparing n and N, if n 3. The method of claim 2, wherein after Step S6, the method further comprises: Step S100, obtaining a register array copy instruction, the register array copy instruction being effective for all register arrays, the register array copy instruction comprising a first register sequence number and a second register sequence number; Step S300, writing the value in the register RTL instance corresponding to the first register sequence number in the RTL instances of all register arrays in the chip design under test into the register RTL instance corresponding to the second register sequence number; Step S400, comparing the currently stored data in the RTL instances of all registers in the chip design under test with the current corresponding reference values, and if all are the same, the register data copy verification passes, otherwise, the register data copy verification fails. Step S200, updating the value of F in the {F1, F2,..., F in the corresponding register array of all registers in the chip design to be tested, where the value of F is updated to the value of F corresponding to the first register sequence number. m M m m ​​​​ 4. The method of claim 3, wherein in Steps S5, S60, and S400, after randomly reading the currently stored data in the RTL instance of one register, the currently stored data is compared with the current corresponding reference value, if they are different, the verification fails, otherwise, the currently stored data in the RTL instance of the next register is randomly read, until the currently stored data in the RTL instances of all registers in the chip design under test is read and compared with the current corresponding reference value.

5. The method of claim 3, wherein in Steps S5, S60, and S400, the comparing the currently stored data in the RTL instances of all registers in the chip design under test with the current corresponding reference values comprises: Step S51, randomly reading the currently stored data in the RTL instances of registers in the chip design under test, if the currently read RTL instance of the register is a RTL instance of a register of a single register type, executing Step S52, if the currently read RTL instance of the register is a RTL instance of a register in a register array, executing Step S53; ​ ​ ​ ​ Step S52, obtaining the data stored in the UVM RAL model instance corresponding to the current read register as a reference value and comparing the current stored data in the register RTL instance; Step S53, compare the reference value corresponding to the UVM RAL model instance of the current read register in {F1, F2,..., F m ,...,F M} with the data currently stored in the RTL instance of the register.

6. The method of claim 1, wherein, The chip design to be tested is a GPU chip design.

7. An electronic device, comprising: Comprise: at least one processor; and a memory connected in communication with the at least one processor; Wherein, the memory stores instructions executable by the at least one processor, the instructions are set to execute the method of any one of the preceding claims 1-6.

8. A computer-readable storage medium, characterized in that, Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-6.

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