Method for automatically generating register verification model, electronic equipment and medium

Abstract

The invention relates to the technical field of chip verification, in particular to a method for automatically generating a register verification model, electronic equipment and a medium. S2, analyzing the register definition file based on a preset script, obtaining attribute information corresponding to a register module and attribute information corresponding to each register contained in the register module, and storing the attribute information and the attribute information in an action range of the UVM; step S3, adopting a preset script to construct a corresponding UVM class type statement; s4, constructing a corresponding UVM class type statement by adopting a preset script, and instantiating each register in the UVM class type statement corresponding to the register module; and S5, generating a register verification model based on the UVM class type statement corresponding to the register module. The efficiency and the accuracy of automatically generating the register verification model are improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a method, electronic equipment, and medium for automatically generating a register verification model. Background Art

[0002] Register verification is a crucial component of chip verification. Conventional technologies employ the Universal Verification Methodology (UVM) to verify registers. Within the verification environment, the UVM RAL (Register Abstraction Layer) library is used to generate a UVM RAL register model. This UVM RAL register model is then used to verify registers within the chip's Design Under Test (DUT). Conventional technologies typically use the vcsralgen tool or the Cadence reg_verifier tool to automatically generate UVM RAL register models. However, these tools require input in the form of Extensible Markup Language (XML) files. Therefore, if the original input file is not an XML file, it must first be converted to XML. Furthermore, the vcsralgen tool must convert the XML file to a ralf file, and then convert the ralf file to a uvm_ral file. As chip sizes continue to grow, the number of registers in designs under test is also increasing. Automated generation of UVM RAL register models using tools like vcs ralgen or Cadence reg_verifier requires extensive file conversion, resulting in low efficiency and error-prone generation of register verification models. Therefore, improving the efficiency and accuracy of automated register verification model generation has become a pressing technical challenge. Summary of the Invention

[0003] The present invention aims to provide a method, electronic device and medium for automatically generating a register verification model, thereby improving the efficiency and accuracy of automatically generating a register verification model.

[0004] According to a first aspect of the present invention, a method for automatically generating a register verification model is provided, comprising: Step S1: Obtain a register definition file, wherein the register definition file is a file in JSON format and includes attribute information corresponding to a register module and attribute information corresponding to each register included in the register module; Step S2, parsing the register definition file based on a preset script, obtaining attribute information corresponding to the register module and attribute information corresponding to each register contained in the register module and storing them in the UVM scope; Step S3: constructing a corresponding UVM class type declaration based on the attribute information corresponding to each register included in the register module using a preset script; Step S4, constructing a corresponding UVM class type declaration based on the attribute information corresponding to the register module using a preset script, and instantiating each register in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module; Step S5: Generate a register verification model based on the UVM class type declaration corresponding to the register module.

[0005] According to a second aspect of the present invention, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0006] According to a third aspect of the present invention, a computer-readable storage medium is provided, storing computer-executable instructions, wherein the computer instructions are used to execute the method according to the first aspect of the present invention.

[0007] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the method, electronic device, and medium provided by the present invention for automatically generating a register verification model can achieve considerable technological advancement and practicality, and have wide industrial application value, with at least the following beneficial effects: The present invention uses a preset script to process the register definition file in JSON format, and can generate a register verification model without converting other file types in the middle, reducing the file conversion operations in the register verification model generation process and improving the efficiency of automatically generating the register verification model. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 A flow chart of a method for automatically generating a register verification model provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0011] The embodiment of the present invention provides a method for automatically generating a register verification model, such as Figure 1 As shown, including: Step S1: Obtain a register definition file, wherein the register definition file is a file in json format, and the register definition file includes attribute information corresponding to a register module and attribute information corresponding to each register included in the register module.

[0012] The register module includes at least one register.

[0013] Step S2: parsing the register definition file based on a preset script, obtaining attribute information corresponding to the register module and attribute information corresponding to each register contained in the register module and storing them in the UVM scope.

[0014] It should be noted that in step S2 , the attribute information corresponding to the register module may be obtained first, and then the attribute information corresponding to each register included in the register module may be obtained in a loop X times, where X is the number of registers included in the register module.

[0015] Wherein, the preset script can specifically be a perl script, a python script, etc. Preferably, the preset script is a python script, because the python script has a parse json module that can be directly called, and the parsejson module can be directly called to parse the register definition file. The attribute information corresponding to the register module obtained by parsing and the attribute information corresponding to each register included in the register module are stored in the scope of UVM, which is convenient for generating a register verification model and obtaining the required information during the verification process.

[0016] As an embodiment, the attribute information corresponding to the register module and the attribute information corresponding to each register contained in the register module can be stored in a preset cache area in the form of an associative array. Step S3: Based on the attribute information corresponding to each register included in the register module, a preset script is used to construct a corresponding UVM class type declaration.

[0017] It should be noted that step S3 specifically can pre-build the universal UVM code architecture corresponding to the register verification model, set the attribute information corresponding to the register to be filled in field, adopt preset script to read the attribute information corresponding to each register included in the register module from the scope of UVM, fill in the universal UVM code architecture corresponding to the register verification model, generate the UVM class type declaration corresponding to each register included in the register module.Step S3 needs to loop and execute X times to establish the UVM class type declaration corresponding to each register included in the register module.

[0018] Step S4: construct a corresponding UVM class type declaration based on the attribute information corresponding to the register module using a preset script, and instantiate each register in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module.

[0019] It should be noted that, specifically, a general UVM code architecture corresponding to the register module can be pre-constructed, the attribute information corresponding to the register module can be set as a field to be filled in, and a preset script is used to read the attribute information corresponding to the register module from the UVM scope and fill it into the UVM class type declaration corresponding to the register module. Based on the UVM class type declaration corresponding to each register included in the register module, each register is instantiated in the UVM class type declaration corresponding to the register module.

[0020] Step S5: Generate a register verification model based on the UVM class type declaration corresponding to the register module.

[0021] It should be noted that the register verification model generated based on the UVM class type declaration corresponding to the register module includes all registers in the register module. The present invention can directly generate the register verification model based on a file in json format, without converting it to an XML file or going through multiple rounds of other file type conversions, thereby improving the generation efficiency and accuracy of the register verification model.

[0022] As an embodiment, step S1 includes: Step S11: extracting register module attribute information and register attribute information from the design text information corresponding to the design to be tested.

[0023] Step S12: Use json to store register module attribute information and register attribute information to generate the register definition file, and the register attribute information contained in the register module in the register definition file is nested in the register module attribute information.

[0024] As an embodiment, the attribute information corresponding to the register module includes path information, constraint information, and function coverage information; the attribute information corresponding to the register includes path information, constraint information, function coverage information, register group type, and register group depth. If there is no corresponding register group for a register, the register group type and register group depth are set to empty.

[0025] The constraint information corresponding to the registers is used to generate random test stimuli for the registers. The constraint information corresponding to the register modules is used to generate random test stimuli for the registers based on the constraint relationships between the different registers included in the register modules. The functional coverage information corresponding to the registers is used to set the functional coverage points and cross-functional coverage point information corresponding to the registers. The functional coverage information corresponding to the register modules is used to set the functional coverage points and cross-functional coverage point information between the different registers included in the register modules.

[0026] As an embodiment, the attribute information corresponding to the register module also includes the register module name, address mapping information, reset information, address width, data width, access attributes, etc. The attribute information corresponding to the register also includes the register description information, address mapping information, access attributes, data width, address offset, reset information, etc. The above attribute information can be extracted from the design text information corresponding to the design under test, and fields in the register definition file can be added or deleted according to specific application requirements.

[0027] As an embodiment, step S3 includes: Step S31 : configuring each register to enable backdoor access through command line parameters preset in the preset script; if the register configuration enables backdoor access, executing step S32 .

[0028] Step S33: Concatenate the path information corresponding to the register module and the path information corresponding to the register to generate a backdoor access path corresponding to the register.

[0029] Step S34: Setting a backdoor access declaration in the UVM class type declaration corresponding to the register based on the backdoor access path corresponding to the register.

[0030] It should be noted that backdoor access is used in the simulation verification process. In the prior art, if backdoor access is involved, verification engineers need to manually write the path corresponding to each backdoor access, which is inefficient, error-prone and has high maintenance costs. In the embodiment of the present invention, after the register definition file is set up, the design and verification are both performed based on the register definition file, that is, the design and verification are based on the same source information, so the hierarchy and name of the same register corresponding to the design and verification are consistent. The present invention provides corresponding path information in the register module and the attribute information of each register. The path information corresponding to the register module and the path information corresponding to the register are automatically spliced ​​through a preset script, and the backdoor access path corresponding to each register can be obtained without the need for manual writing by verification engineers. It is efficient and not prone to errors.

[0031] As an embodiment, step S3 includes: Step C31: Whether the register module supports factory override is configured through command line parameters preset in the preset script. If supported, factory registration is performed in the UVMclass type declaration corresponding to each register included in the register module. If not supported, factory registration is not required to be performed in the UVMclass type declaration corresponding to each register included in the register module.

[0032] It should be noted that in many cases, register verification does not require the factory override function. By flexibly configuring whether the register module supports factory override through the preset command line parameters in the preset script, the factory override function can be turned off, which can greatly improve system performance and the construction speed of the register verification model.

[0033] Step C32: setting the constraint information corresponding to the register in the UVM class type declaration corresponding to the register.

[0034] Step C33: setting the function coverage information corresponding to the register in the UVM class type declaration corresponding to the register.

[0035] It should be noted that in the prior art, constrained random verification of registers and acquisition of functional coverage are performed based on the verification engineer's understanding of the design intent of the design architecture. However, the verification engineer's understanding may not be accurate, information barriers may exist, and the workload is very large. In the embodiment of the present invention, the constraint information and functional coverage information corresponding to the register are directly and uniformly set in the register definition file, and then the constraint information and functional coverage information are set in the UVM class type declaration corresponding to the register. In the subsequent process of generating the register verification model, the constraint information and functional coverage information are also directly set in the register verification model.

[0036] As an embodiment, step S4 includes: Step S41: Use a preset script to add attribute information corresponding to the register module to the UVM class type declaration corresponding to the register module.

[0037] It should be noted that in step S41 , the constraint information, function coverage points, and cross-function coverage point information between different registers included in the register module are also added as attribute information to the UVM class type declaration corresponding to the register module.

[0038] Step S42: If the register does not have a corresponding register group, add a corresponding register instance to the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to the register.

[0039] Step S43: If the register has a corresponding register group, then based on the register group type, register group depth, and UVM class type declaration corresponding to the register, add a corresponding register array instance to the UVM class type declaration corresponding to the register module.

[0040] As an embodiment, after the register verification model is generated in step S5, if constrained random verification is required for a register, it is first determined whether constraint information corresponding to the register exists in the register module. If so, it indicates that the register is associated with other registers when generating constrained random test stimuli. Therefore, it is necessary to generate a random test stimulus corresponding to the register based on simultaneously satisfying the corresponding constraint information in the register module and the corresponding constraint information in the register to implement constrained random verification of the register. If the constraint information corresponding to the register does not exist in the register module, a random test stimulus corresponding to the register is generated based only on the corresponding constraint information in the register to implement constrained random verification of the register.

[0041] As an embodiment, after the register verification model is generated in step S5, if it is necessary to obtain the functional coverage of a register, it is first determined whether the functional coverage information corresponding to the register exists in the register module. If so, it indicates that the register is associated with other registers when obtaining the functional coverage. Therefore, it is necessary to obtain the functional coverage corresponding to the register based on the corresponding functional coverage information in the register module and the corresponding functional coverage information in the register. If the functional coverage information corresponding to the register does not exist in the register module, the functional coverage corresponding to the register is obtained based only on the corresponding functional coverage information in the register.

[0042] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of the steps can be performed in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. A process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. A process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0043] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0044] An embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0045] The embodiment of the present invention uses a preset script to process a register definition file in JSON format, and can generate a register verification model without converting other file types in the middle, thereby reducing the file conversion operations in the register verification model generation process and improving the efficiency of automatically generating the register verification model.

[0046] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for automatically generating a register verification model, characterized in that: include: Step S1: Obtain a register definition file, wherein the register definition file is a file in JSON format and includes attribute information corresponding to a register module and attribute information corresponding to each register included in the register module; Step S2, parsing the register definition file based on a preset script, obtaining attribute information corresponding to the register module and attribute information corresponding to each register contained in the register module and storing them in the UVM scope; Step S3: constructing a corresponding UVM class type declaration based on the attribute information corresponding to each register included in the register module using a preset script; Step S4, constructing a corresponding UVM class type declaration based on the attribute information corresponding to the register module using a preset script, and instantiating each register in the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to each register included in the register module; Step S5: Generate a register verification model based on the UVM class type declaration corresponding to the register module.

2. The method according to claim 1, characterized in that The step S1 comprises: Step S11: extracting register module attribute information and register attribute information from the design text information corresponding to the design to be tested; Step S12: Use json to store register module attribute information and register attribute information to generate the register definition file, and the register attribute information contained in the register module in the register definition file is nested in the register module attribute information.

3. The method according to claim 1, characterized in that The attribute information corresponding to the register module includes path information, constraint information, and function coverage information. The attribute information corresponding to the register includes path information, constraint information, function coverage information, register group type, and register group depth. If there is no corresponding register group for a register, the register group type and register group depth are set to empty; The constraint information corresponding to the register is used to generate a random test stimulus for the register, and the constraint information corresponding to the register module is used to generate a random test stimulus for the register based on the constraint relationship between different registers included in the register module; The function coverage information corresponding to the register is used to set the function coverage points and cross-function coverage point information corresponding to the register, and the function coverage information corresponding to the register module is used to set the function coverage points and cross-function coverage point information between different registers included in the register module.

4. The method according to claim 1, wherein In step S2, the preset script is a python script.

5. The method according to claim 1, wherein In step S2, the attribute information corresponding to the register module and the attribute information corresponding to each register included in the register module are stored in a preset cache area in the form of an associative array.

6. The method according to claim 3, characterized in that The step S3 comprises: Step S31, configuring each register to enable backdoor access through the command line parameters preset in the preset script, if the register is configured to enable backdoor access, executing step S32; Step S33: Concatenate the path information corresponding to the register module and the path information corresponding to the register to generate a backdoor access path corresponding to the register; Step S34: Setting a backdoor access declaration in the UVM class type declaration corresponding to the register based on the backdoor access path corresponding to the register.

7. The method according to claim 3, characterized in that The step S3 comprises: Step C31: configuring whether the register module supports factory override through command line parameters preset in the preset script; if supported, performing factory registration in the UVM class type declaration corresponding to each register included in the register module; Step C32: setting the constraint information corresponding to the register in the UVM class type declaration corresponding to the register; Step C33: setting the function coverage information corresponding to the register in the UVM class type declaration corresponding to the register.

8. The method according to claim 3, characterized in that The step S4 comprises: Step S41: using a preset script to add attribute information corresponding to the register module to the UVM class type declaration corresponding to the register module; Step S42: If the register does not have a corresponding register group, then add a corresponding register instance to the UVM class type declaration corresponding to the register module based on the UVM class type declaration corresponding to the register; Step S43: If the register has a corresponding register group, then based on the register group type, register group depth, and UVM class type declaration corresponding to the register, add a corresponding register array instance to the UVM class type declaration corresponding to the register module.

9. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are configured to execute the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-executable instructions are stored, and the computer-executable instructions are used to execute the method according to any one of the preceding claims 1 to 8.

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