Capacitor design structure and method, printed circuit board and electronic equipment

Abstract

The invention discloses a design structure and method of a capacitor, a printed circuit board and electronic equipment, and relates to the technical field of circuit design, the design structure comprises a hollow structure, a preset medium and a transmission line, the hollow structure is arranged between a first signal layer and a second signal layer of the printed circuit board, and the preset medium with a specific dielectric constant is filled, so that the transmission line is formed. According to the invention, the function of constructing a required target capacitance value under the condition of not introducing an additional via hole is realized, and meanwhile, the transmission line and the hollow structure are integrated in the same interlayer structure, so that smooth transition and structural symmetry of a link are kept. According to the invention, the problems of discontinuous impedance and signal loss caused by the increase of via holes in the traditional AC coupling capacitor design are solved, and the technical effects of improving the signal integrity, the transmission stability and the design success rate of a signal link and reducing the risk of product development are achieved.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a capacitor design structure, method, printed circuit board, and electronic equipment. Background Art

[0002] In traditional digital system design, high-speed interconnects have a minimal impact on system performance, often negligible. However, with the advancement of computer technology, high-speed interconnects have become the dominant factor in determining system performance, and the unforeseen problems they cause significantly increase the complexity of system design. Therefore, when verifying high-speed link designs, it is necessary to fully consider the interactions between modules and utilize testing and evaluation methods to ensure the stability of high-speed signal links, thereby improving the success rate of overall system design and shortening the R&D cycle.

[0003] Taking server system design as an example, the loss and impedance characteristics of high-speed signal links are directly related to signal quality, and the impedance consistency and low loss characteristics of the link must be maintained. In some high-speed interconnect architectures, some do not require the addition of coupling capacitors (such as Figure 1 ), some require adding coupling capacitors to the link (such as Figure 2 ), and when designing the capacitor, two vias need to be added in the link, which not only destroys the impedance consistency of the link, but also increases the loss, seriously affecting the signal quality and greatly increasing the risk of product design failure. Summary of the Invention

[0004] The present application provides a capacitor design structure, method, printed circuit board, and electronic device to at least solve the impedance discontinuity and signal loss problems caused by adding vias in the traditional AC coupling capacitor design in the related art, thereby achieving the technical effect of improving signal integrity and transmission stability, improving the design success rate of the signal link, and reducing the risk of product development.

[0005] The present application provides a capacitor design structure, including: a hollow structure, arranged between a first signal layer and a second signal layer of a printed circuit board; a preset medium, used to fill the hollow structure; the dielectric constant of the preset medium is determined according to a target capacitance value and the size of the hollow structure, and the actual capacitance value corresponding to the overall structure of the hollow structure and the preset medium is equal to the target capacitance value; at least two transmission lines, respectively arranged on both sides of the hollow structure and with surfaces parallel to the surface of the first signal layer, and respectively connected to a first external device and a second external device; the first external device and the second external device are electrically connected to the hollow structure through the transmission lines.

[0006] The present application also provides a capacitor design method, including: obtaining a target capacitance value and size parameters of a printed circuit board; determining a dielectric constant of a preset medium based on the size parameters of the printed circuit board and the target capacitance value, wherein the preset medium is used to fill the hollow structure; performing a hollowing operation between the first signal layer and the second signal layer of the printed circuit board according to the size of the hollow structure using a preset process method; electroplating the hollow structure, and after the electroplating is completed, filling the hollow structure with a preset medium with a determined dielectric constant; arranging transmission lines on both sides of the hollow structure so that two external devices are connected to the hollow structure through the transmission lines; and pressing the overall structure between the first signal layer and the second signal layer with the filled hollow structure with other signal layers and / or power supply layers.

[0007] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned capacitor design methods when executing the computer program.

[0008] This application provides a hollow structure between the first and second signal layers of a printed circuit board and fills it with a predetermined dielectric with a specific dielectric constant, thereby achieving the desired target capacitance without introducing additional vias. Furthermore, the transmission line and the hollow structure are integrated into the same interlayer structure, maintaining a smooth transition and structural symmetry within the link. This application addresses the impedance discontinuity and signal loss issues associated with the addition of vias in traditional AC coupling capacitor designs, achieving the technical benefits of improving signal integrity and transmission stability, increasing the design success rate of signal links, and reducing product development risks. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 This is a schematic diagram of a related art that does not require the design of coupling capacitors;

[0011] Figure 2 A schematic diagram of a related art requiring design of a coupling capacitor;

[0012] Figure 3 A schematic diagram of a capacitor design structure provided in an embodiment of the present application;

[0013] Figure 4 A side view of a hollowed-out structure provided in an embodiment of the present application;

[0014] Figure 5 A top view of a hollowed-out structure provided in an embodiment of the present application;

[0015] Figure 6 A schematic diagram of a hollow structure in a printed circuit board provided in an embodiment of the present application;

[0016] Figure 7 A schematic diagram of processing a hollow structure in a printed circuit board provided in an embodiment of the present application;

[0017] Figure 8 A schematic diagram of capacitance value testing of a hollowed-out structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0019] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0020] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] like Figure 3 , an embodiment of the present application provides a capacitor design structure, including: a hollow structure 11, arranged between a first signal layer and a second signal layer of a printed circuit board; a preset medium, used to fill the hollow structure 11; the dielectric constant of the preset medium is determined according to a target capacitance value and a size of the hollow structure 11, and the actual capacitance value corresponding to the overall structure of the hollow structure 11 and the preset medium is equal to the target capacitance value; at least two transmission lines 12, respectively arranged on both sides of the hollow structure 11 and with surfaces parallel to the surface of the first signal layer, and respectively connected to a first external device and a second external device; the first external device and the second external device are electrically connected to the hollow structure 11 through the transmission lines 12.

[0022] The capacitor design structure in this application mainly realizes the required AC coupling capacitor function through the combination of "hollow structure 11 + preset medium + parallel transmission line 12" without introducing traditional surface-mount capacitors or additional vias.

[0023] Specifically, the design creates a three-dimensional cavity between two signal layers within a printed circuit board (PCB). This cavity is then filled with a predetermined dielectric with a known dielectric constant. The dimensions of the cavity (length, width, thickness (height)) and the dielectric constant of the selected dielectric determine the capacitance of the resulting structure 11. During design, the required structural parameters can be reverse-calculated based on the target capacitance. This design essentially replaces traditional discrete capacitors with an equivalent inter-plane capacitance structure embedded within the PCB. Its distributed nature further facilitates impedance continuity control during high-speed signal transmission.

[0024] Furthermore, two transmission lines 12 are routed above and below the hollowed-out structure 11, respectively, for connecting to a first external device and a second external device located at the edge of the PCB. These two transmission lines 12 form a complete signal coupling path with the capacitor structure in the middle. Because the signal layers on which these two transmission lines 12 reside remain on the same physical layer or between adjacent layers, the vias required to connect discrete AC capacitors in traditional designs are avoided, significantly reducing the impedance jumps, signal reflections, and excess losses introduced by vias.

[0025] Assuming the first signal layer is L9 and the second signal layer is L11, the core principle of the capacitor structure is to hollow out the area of ​​layer L10 between L9 and L11 to form a local cavity structure. This cavity is then filled with a predetermined dielectric with a known dielectric constant, thereby establishing a controllable inter-plane coupling capacitor structure between L9 and L11. By precisely designing the area and thickness of the hollowed-out region and selecting an appropriate dielectric material (such as a low-loss resin or ceramic powder blend), the equivalent capacitance of this structure can be adjusted to meet the target AC coupling requirements, typically in the tens of picofarads (pF). Compared to the traditional method of using surface-mount capacitors and routing vias between L9 and L11, this design is completely embedded in the PCB, eliminating the need for additional vias.

[0026] Furthermore, a transmission line 12 can be laid out on L9 and L11 (or two transmission lines 12 can be laid out on L10). In addition to connecting to the hollowed-out structure 11, these two transmission lines 12 also connect to the first external device and the second external device, respectively, forming a complete high-speed signal channel. Taking the example of a transmission line 12 laid out on L9 and L11, during circuit operation, the signal is transmitted from the first external device via the L9 transmission line 12 to an end electrode in the L9 layer, coupled to the L11 layer through the intermediate embedded capacitor structure, and then transmitted to the second device via the transmission line 12 on L11. Because there is no traditional through-hole structure between L9 and L11, this symmetrical, parallel, and inter-plane coupled signal path maintains the impedance consistency and lateral structural continuity of the link, significantly reducing the risk of reflections, crosstalk, and signal distortion. More importantly, this structure has better parasitic parameter control capabilities at high-speed signal frequencies, which is beneficial for system EMI suppression and signal integrity optimization. It is particularly suitable for the link design requirements of high-speed interconnect-intensive devices such as servers and switches.

[0027] In summary, through this embedded design structure, the entire signal chain can embed AC coupling capabilities while maintaining physical continuity, effectively improving the signal integrity and EMI performance of the link. It is particularly suitable for servers or high-speed communication systems with extremely high signal quality requirements.

[0028] like Figure 4 In an exemplary embodiment, the hollowing height of the hollowing structure 11 perpendicular to the signal layer is determined according to the height between the first signal layer and the second signal layer.

[0029] Specifically, the vertical height of the hollow structure 11 (i.e., the hollow height in the thickness direction from the first signal layer L9 to the second signal layer L11 of the PCB) is determined based on the actual distance between the two signal layers, which is one of the key factors in achieving precise capacitance value control in the entire embedded capacitor design. Since the size of the inter-surface capacitance is determined by the electrode area, dielectric constant, and the vertical distance between the electrodes, when the distance between the first signal layer L9 and the second signal layer L11 (i.e., the thickness of the dielectric layer between L9-L11 in the PCB) is fixed, this distance naturally becomes the physical upper limit for the vertical height of the designed embedded capacitor. When constructing the hollow structure 11, the designer needs to fully consider this spacing, combine the target capacitance value with the dielectric constant of the selected dielectric material, solve the required hollow area area or optimize the dielectric parameters, so as to achieve structural capacitance matching.

[0030] Furthermore, this design method of determining the thickness of the hollowed-out structure 11 based on the actual height between signal layers not only helps to ensure the accuracy of the embedded capacitor value, but also physically minimizes the interference of the hollowed-out structure 11 on other signal layers of the PCB. In the design of high-speed signal links, any asymmetric structure or thickness change may cause impedance discontinuity, which in turn causes problems such as signal reflection and increased loss. In this application, the capacitor structure is strictly controlled between L9 and L11, so that its vertical hollowing height is consistent with the height of the original dielectric layer, thereby maintaining the structural symmetry and impedance continuity of the signal channel to the greatest extent. At the same time, since the capacitor structure is distributed in the local area between L9 and L11, it does not affect the wiring and electrical performance of other upper and lower signal layers, and also simplifies the overall stacking design and manufacturing process of the PCB, thereby improving the feasibility and engineering reliability of the design.

[0031] In summary, maintaining the vertical height of the hollowed-out structure 11 consistent with the interlayer thickness between L9 and L11 is a key design measure for ensuring embedded capacitor accuracy, electrical performance consistency, and process controllability. This meticulous design of the coupling relationship between physical dimensions and electrical performance enables high-speed signal links to achieve AC coupling while maintaining excellent signal integrity and manufacturing repeatability, significantly improving the application of high-speed PCB design in high-end systems such as servers and switching equipment.

[0032] like Figure 5 In an exemplary embodiment, when the projection of the hollow structure 11 on a plane parallel to the signal layer is a rectangle, the width of the rectangle is determined according to the line spacing of the differential lines on the first signal layer and / or the line spacing of the differential lines on the second signal layer.

[0033] Specifically, when the projection of the hollowed-out structure 11 onto a plane parallel to the signal layer (i.e., the XY plane) is rectangular, its width (i.e., the short side of the rectangle, denoted as L2) is determined based on the line spacing of the differential signal lines on the first or second signal layer. Differential lines are a common form of signal transmission in high-speed links, and their line spacing directly affects electromagnetic coupling strength, impedance matching, and crosstalk characteristics. Therefore, when designing the embedded capacitor structure, it is necessary to maintain matching with the differential line routing in the L2 direction to avoid local geometric asymmetry or uneven electric field distribution, which can lead to signal integrity issues.

[0034] Specifically, the line spacing of conventional differential lines is generally between 5mil and 15mil. If the L2 of the capacitor structure is much larger than the line spacing, it may introduce unnecessary parasitic capacitance and destroy the symmetry of the transmission line 12. If L2 is too small, the coupling surface will be insufficient and the target capacitance value cannot be achieved. Therefore, in actual design, L2 should be combined with the differential line layout and maximized while ensuring wiring compatibility. The default setting is 15mil to improve coupling capability and capacitance.

[0035] Furthermore, the choice of L2 not only affects the size of the inter-surface capacitance value, but is also a key parameter for balancing wiring compatibility and target capacitance value. Under the differential line wiring rules, L2 is usually set between signal lines or slightly extended to the edge of the signal line, and should not exceed too much to avoid affecting the wiring channels of adjacent line pairs. At the same time, if the designer needs to increase the total capacitance value of the embedded capacitor, the size of the rectangular structure in the L1 direction (that is, the length direction of the rectangle) can be increased to compensate for the insufficient capacitance area of ​​L2 due to wiring restrictions. In addition, under the premise of keeping L2 within the differential line spacing limit, the capacitance density per unit area can be increased by selecting a preset medium with a higher dielectric constant, reducing the thickness of the layer between L9 and L11, etc., thereby achieving a larger coupling capacitance under a limited size.

[0036] In summary, when embedding capacitor structures in high-speed PCBs, L2, as a key geometric parameter of planar capacitor structures, must adhere to the routing rules for differential signal lines to ensure signal symmetry while also maximizing the capacitance value. Using 15 mil as the default value not only conforms to current mainstream differential routing rules but also provides a good structural foundation for capacitance, achieving a design balance between high-speed signal integrity, capacitor functionality, and routing feasibility.

[0037] like Figure 5 In an exemplary embodiment, when the projection of the hollow structure 11 on a plane parallel to the signal layer is a rectangle, the length of the rectangle is determined according to a preset processing standard.

[0038] Specifically, when the projection of the hollowed-out structure 11 of the embedded capacitor on a plane parallel to the signal layer (XY plane) is rectangular, the setting of its length direction (denoted as L1) is mainly determined by the preset processing standards in the PCB manufacturing process. Unlike the width L2 (limited by the line spacing of the differential lines), the setting of L1 has fewer constraints on wiring compatibility and more flexible design space, but it is also limited by process factors such as processing accuracy, etching control, and dielectric filling stability. Generally speaking, the smaller L1, the shorter the distance between the plates of the planar capacitor, which can more effectively enhance the electric field strength per unit area under the same area and dielectric conditions, thereby obtaining a larger coupling capacitance value. However, if L1 is designed to be too small, it may exceed the minimum processing width limit of the PCB manufacturer, resulting in process problems such as structural processing difficulties, residual adhesive or voids, and uneven dielectric filling, thereby affecting the consistency and reliability of the final capacitor.

[0039] Therefore, balancing capacitance performance with manufacturing process feasibility, this embodiment recommends controlling the L1 value range between 2 mils and 10 mils. 2 mils is the common minimum etching width lower limit for high-density PCBs (such as multi-layer boards for servers and network equipment), making it an extreme design option for achieving higher capacitance. 10 mils, on the other hand, provides a more generous design option under conventional processes, suitable for scenarios with moderate capacitance requirements or where structural stability is more important. Designers can flexibly select the L1 value to achieve target capacitance performance based on multiple parameters, including the specific capacitance requirement, the dielectric constant of the pre-set dielectric, the L2 width, and the thickness of the L9-L11 interlayer. For example, when the dielectric layer is thin or the dielectric constant is high, a smaller L1 value can be selected to achieve a compact and efficient coupling structure. When processing yield or consistency are high, a larger L1 value can be selected to enhance structural manufacturability and reliability.

[0040] In summary, the L1 configuration principle reflects the design philosophy of this application's structure, which strikes a balance between high capacitance density and manufacturability. By limiting L1 to a reasonable range of 2 to 10 mils, it not only meets the stringent requirements for AC coupling capacitor accuracy and density in high-speed interconnects, but also takes into account the current technical capabilities of PCB manufacturing, ensuring the consistency and stability of the capacitor structure in mass production, thereby providing strong electrical support for the design and implementation of high-speed signal links.

[0041] In an exemplary embodiment, the projection of the hollow structure 11 on a plane parallel to the signal layer is a rectangle; the dielectric constant of the preset medium is determined according to the target capacitance value, the dielectric constant of free space, the side area of ​​the hollow structure 11 and the length of the rectangle; the side area of ​​the hollow structure 11 is the product of the hollow height of the hollow structure 11 perpendicular to the signal layer and the width of the rectangle; the dielectric constant of the preset medium is determined according to Determine, C is the target capacitance value, is the free space dielectric constant, is the dielectric constant of the preset medium, A is the side area of ​​the hollow structure 11, and L1 is the length of the rectangle.

[0042] Specifically, the hollow structure 11 is projected as a rectangle on a plane parallel to the signal layer, and the structural parameters of the rectangle are closely related to the realization of the capacitance value. In particular, the dielectric constant of the preset medium ( ) is not chosen arbitrarily, but is based on the target capacitance value (C), the free space dielectric constant ( ), the lateral area (A) of the hollow structure 11, and the length (L1) of the rectangle. Here, the lateral area of ​​the hollow structure 11 refers to the effective coupling area of ​​the structure in the vertical direction of the signal layer. This is the product of the hollow height (i.e., the distance between the first and second signal layers) and the width (L2) of the rectangle, expressed as: A = height × width = h × L2.

[0043] like Figure 6 On this basis, the entire capacitor structure is equivalent to an inter-surface capacitor structure consisting of two metal plates (transmission line 12 of layers L9 and L11, respectively) sandwiching a dielectric layer (preset dielectric). Therefore, during the design process, in order to achieve the specified coupling capacitance value C, the designer can first determine the value of A based on the structural limitations of the PCB (such as the hollowing height h and the differential line spacing L2); then set the L1 value based on the minimum rectangular length L1 (i.e., L1) that can be manufactured on the PCB; and finally substitute the above formula into the reverse solution to obtain the required dielectric constant. , and select the preset dielectric material that meets the parameter requirements (such as special low-loss resin, ceramic filler dielectric, etc.).

[0044] This precise structural-material collaborative design approach, leveraging capacitor physics models, ensures that the designed embedded capacitor structure achieves target capacitance while maintaining excellent controllability and consistency. By adjusting the coupling relationship between geometric dimensions and material properties, stable, continuous, and via-free AC coupling is achieved in high-speed links, meeting electrical performance requirements while also balancing manufacturing feasibility, significantly improving system design success rates and signal integrity.

[0045] The present application also provides a printed circuit board, including the capacitor design structure described above. The present application also provides a printed circuit board, including the capacitor design structure described above, which realizes the embedded AC coupling capacitor function by providing a hollow structure 11 between internal signal layers and filling it with a preset medium, effectively improving the impedance consistency and transmission stability of the signal link, and is suitable for high-speed interconnect circuit applications.

[0046] like Figure 7 , the present application also provides a capacitor design method, including:

[0047] Obtain the target capacitance value and printed circuit board dimensions. This step is the starting point for capacitor design. Based on the AC coupling or filtering performance requirements of the actual circuit, the target capacitance value C (e.g., tens of pF to hundreds of pF) is determined. This capacitance value directly determines subsequent structural parameter calculations and material selection, and is the core basis for the entire embedded capacitor structure design. This value is typically derived from electrical simulations of high-speed signal links, protocol requirements, or SI engineering design specifications.

[0048] This step also collects physical information related to capacitor design within the current PCB stackup structure, such as the vertical distance between the first and second signal layers (e.g., the thickness between L9 and L11), the spacing between differential lines, available space between layers, board thickness, and tolerances. These parameters determine the available space and fabrication feasibility of the hollowed-out structure and serve as the physical boundary conditions for structural design.

[0049] Determining the dielectric constant of a preset medium according to the size parameters of the printed circuit board and the target capacitance value, where the preset medium is used to fill the hollow structure; determining the size of the hollow structure according to the size parameters of the printed circuit board and the target capacitance value specifically includes: determining the size of the hollow structure according to the size parameters of the printed circuit board; and determining the dielectric constant of the preset medium according to the size of the hollow structure and the target capacitance value.

[0050] This step calculates the three-dimensional dimensions of the cutout structure: length (L1), width (L2), and height (h). Based on the previously acquired PCB dimensions, such as layer height and routing constraints, the cutout structure is calculated. For example, the height is the distance between L9 and L11, the width is set to 5–15 mils based on differential trace spacing, and the length is controlled within 2–10 mils based on process capabilities. The goal is to determine a three-dimensional space that structurally meets process capabilities and electrically achieves the required capacitance.

[0051] Based on the capacitance formula , substitute the target capacitance value C, side area A (height × width) and length (L1) into the calculation to reverse the required dielectric constant Then, within the actual material range, select a dielectric that meets the dielectric constant (such as ceramic mixed filler, low-loss resin, etc.) to ensure the accuracy of the designed capacitance value.

[0052] Performing a hollowing operation on the first signal layer and the second signal layer of the printed circuit board according to the size of the hollowed structure using a preset process method;

[0053] Through processes such as mechanical drilling, laser windowing, or chemical etching, a three-dimensional cavity of the designed dimensions is precisely carved out in the dielectric layer between the laminated layers L9 and L11. This cavity provides the geometric support framework for the capacitor structure and serves as the physical foundation for the entire embedded structure.

[0054] The hollow structure is electroplated; after the electroplating is completed, a predetermined dielectric having a predetermined dielectric constant is filled into the hollow structure;

[0055] To make the walls of the hollowed-out area conductive and couple with the signal lines, this step uses electroplating techniques (such as copper electroplating) to form a continuous metal conductive surface on the inner wall of the hollowed-out cavity. These metal walls will eventually serve as electrodes for the inter-surface capacitor, forming a complete capacitive path with the transmission lines on the upper and lower layers. The selected dielectric material is then filled into the electroplated hollowed-out cavity to form a capacitor dielectric layer. This dielectric not only determines the capacitance value but also must meet reliability requirements such as long-term stability and thermal expansion compatibility.

[0056] wiring on both sides of the hollow structure so that two external devices are connected to the hollow structure through the transmission line;

[0057] The overall structure between the first signal layer and the second signal layer with the filled hollow structure is laminated with other signal layers and / or power layers.

[0058] Finally, differential pair transmission lines are laid out on the L9 and L11 layers (or on the L10 layer, located on both sides of the hollowed-out structure), connected to the two electrodes of the hollowed-out structure respectively, and signal coupling between the two devices is achieved through pre-buried capacitors.

[0059] The hollowed-out and filled middle layers (e.g., L9–L11) are laminated with the rest of the PCB (e.g., layers 1–8, 12–14) to restore the complete multilayer structure. This process requires strict control over stack alignment, flatness, and adhesive residue to ensure the electrical performance and mechanical strength of the hollowed-out structure are not affected.

[0060] This structure is equivalent to an embedded AC coupling capacitor, achieving coordinated optimization of signal integrity and structural integration, and avoiding the additional vias and impedance discontinuity problems caused by traditional surface-mount capacitors.

[0061] like Figure 8 In an exemplary embodiment, after the electroplating process is completed, a preset medium with a determined dielectric constant is filled into the hollow structure, and the method further includes: using a preset measuring device to test the actual capacitance value of the filled hollow structure; judging whether the actual capacitance value is equal to the target capacitance value; if they are equal, entering the step of pressing the overall structure between the first signal layer and the second signal layer with the filled hollow structure with other signal layers and / or power layers.

[0062] Furthermore, in order to ensure that the embedded capacitor structure has precise electrical properties, a capacitance detection link needs to be introduced after the electroplating treatment of the hollowed-out structure is completed and filled with the preset medium. Specifically, a preset measuring device (such as an impedance analyzer, LCR tester or radio frequency probe) is used to perform online testing on the capacitor structure formed in the hollowed-out area to obtain its actual capacitance value. The core principle of this step is that although the target capacitance value has been accurately calculated through structural parameters and dielectric constants during the design process, due to minor tolerances in the manufacturing process (such as hollowing size deviation, dielectric filling uniformity, electroplating thickness fluctuations, etc.), the actual capacitance value may deviate from the design value. Therefore, it is necessary to confirm through actual measurement to ensure that the structural accuracy meets the electrical index requirements.

[0063] When the actual measured capacitance value is equal to the set target capacitance value or within the tolerance range, it indicates that the hollowed-out structure has successfully achieved the expected electrical coupling performance. At this point, the next step can be carried out, that is, the middle layer containing the structure (such as L9-L11) and the other layers (such as L1-L8, L12-L14) are pressed together as a whole to complete the structural integration of the entire multi-layer PCB. If the measured capacitance value does not meet the design requirements, the capacitance value can be adjusted to the target indicator by removing the original filling dielectric material and re-selecting a new preset dielectric with a suitable dielectric constant for filling. This process allows for effective correction of capacitance performance during the manufacturing stage, ensuring that the final embedded capacitor structure meets the designed electrical performance requirements and improving product reliability and consistency.

[0064] This test confirmation step not only improves the consistency and reliability of embedded capacitors, but also provides a stable electrical foundation for subsequent high-speed signal transmission, avoiding signal distortion or system anomalies caused by capacitance deviation during later debugging, thereby improving the success rate of the entire board design and product yield.

[0065] Furthermore, a test board employs an embedded capacitor structure that is repeatedly tested and filled. This structure adds a temporary, removable dielectric encapsulation window above the hollowed-out structure, and features test lead copper pillars on the sidewalls of the structure, facilitating access to impedance measurement equipment via an external fixture.

[0066] Specifically, in order to facilitate repeated testing and debugging of the embedded capacitor structure during the R&D and testing phases, the designers introduced a reusable capacitor structure design into the test board. Based on the traditional hollow structure, this structure adds a temporary removable dielectric packaging window on top of it. The window is sealed with a hot-melt peelable packaging material or a mechanical snap-on structure, allowing it to be disassembled and refilled with dielectric materials of different dielectric constants multiple times without damaging the surrounding laminate structure. This design allows researchers to quickly iterate and verify a variety of dielectric formulas and capacitor structure sizes without replacing the entire board, thereby accurately matching the AC coupling requirements in high-speed links.

[0067] In addition, test lead-out copper pillars or gold-plated test contacts are pre-arranged on the side walls of the hollowed-out structure and connected to the external test connector area through blind holes or through holes, so that the capacitor structure can be conveniently connected to impedance measuring equipment such as network analyzers and LCR meters through dedicated external fixtures. Compared with the traditional system-level measurement method that only relies on chip loading, this structure can realize independent testing, capacitance scanning and dielectric tuning of embedded capacitors at the board level. Through structural decoupling and test lead-out design, this embodiment greatly improves the debugging efficiency and precision control capability of embedded capacitor design, and is particularly suitable for scenarios such as high-speed signal board prototype development and material performance experimental verification.

[0068] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the capacitor design method described above. For descriptions of features corresponding to the embodiments of the electronic device, refer to the descriptions of the embodiments corresponding to the capacitor design method, and are not further elaborated here.

[0069] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned capacitor design method embodiments.

[0070] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above capacitor design method embodiments when run.

[0071] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0072] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above capacitor design method embodiments are implemented.

[0073] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of any of the above-mentioned capacitor design method embodiments are implemented.

[0074] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0075] The above is a detailed introduction to the design structure, method, printed circuit board and electronic device of a capacitor provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A capacitor design structure, characterized in that: include: A hollow structure is provided between a first signal layer and a second signal layer of the printed circuit board; A preset medium is used to fill the hollow structure; The dielectric constant of the preset medium is determined according to the target capacitance value and the size of the hollow structure, and the actual capacitance value corresponding to the overall structure of the hollow structure and the preset medium is equal to the target capacitance value; At least two transmission lines are respectively arranged on both sides of the hollow structure and have surfaces parallel to the surface of the first signal layer, and are respectively connected to a first external device and a second external device; the first external device and the second external device are electrically connected to the hollow structure through the transmission lines.

2. The capacitor design structure according to claim 1, characterized in that: A hollowing height of the hollowing structure perpendicular to the signal layer is determined according to a height between the first signal layer and the second signal layer.

3. The capacitor design structure according to claim 1, characterized in that: When the projection of the hollow structure on a plane parallel to the signal layer is a rectangle, the width of the rectangle is determined according to the line spacing of the differential lines on the first signal layer and / or the line spacing of the differential lines on the second signal layer.

4. The capacitor design structure according to claim 1, characterized in that: When the projection of the hollow structure on a plane parallel to the signal layer is a rectangle, the length of the rectangle is determined according to a preset processing standard.

5. The capacitor design structure according to any one of claims 1 to 4, characterized in that: The projection of the hollow structure on a plane parallel to the signal layer is a rectangle; The dielectric constant of the preset medium is determined specifically according to the target capacitance value, the dielectric constant of free space, the side area of ​​the hollowed-out structure, and the length of the rectangle; The side area of ​​the hollow structure is the product of the hollow height of the hollow structure perpendicular to the signal layer and the width of the rectangle.

6. The capacitor design structure according to claim 5, characterized in that: The dielectric constant of the predetermined medium is based on Determine, C is the target capacitance value, is the free space dielectric constant, is the dielectric constant of the preset medium, A is the side area of ​​the hollow structure, and L1 is the length of the rectangle.

7. A printed circuit board, characterized in that: The invention comprises a design structure of a capacitor as described in any one of claims 1 to 6.

8. A method for designing a capacitor, characterized in that: include: Obtain target capacitance value and size parameters of printed circuit board; determining a dielectric constant of a preset medium according to the size parameters of the printed circuit board and the target capacitance value, wherein the preset medium is used to fill the hollow structure; Performing a hollowing operation between the first signal layer and the second signal layer of the printed circuit board according to the size of the hollowed structure using a preset process method; performing electroplating on the hollow structure, and after the electroplating is completed, filling the hollow structure with a predetermined medium having a determined dielectric constant; Transmission lines are arranged on both sides of the hollow structure so that two external devices are connected to the hollow structure through the transmission lines; The overall structure between the first signal layer and the second signal layer with the filled hollow structure is laminated with other signal layers and / or power layers.

9. The capacitor design method according to claim 8, characterized in that: After the electroplating process is completed, a predetermined dielectric having a determined dielectric constant is filled into the hollow structure, and the method further includes: Using a preset measuring device, the actual capacitance value of the filled hollow structure is tested; Determining whether the actual capacitance value is equal to the target capacitance value; If they are equal, the step of pressing the entire structure between the first signal layer and the second signal layer with the filled hollow structure with other signal layers and / or power layers is performed.

10. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the capacitor design method according to claim 8 or 9 when executing the computer program.

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