Dynamic calibration method and device and chip system

Abstract

The invention provides a dynamic calibration method and device and a chip system, and relates to the field of integrated circuits. The method comprises the following steps: acquiring the temperature of a general core particle interconnection physical layer between chips and the voltage change amplitude of the core particle interconnection physical layer; according to the temperature and the voltage change amplitude, determining a time sequence offset of a general core particle interconnection physical interface; and if the offset is greater than an offset threshold, calibrating the core particle interconnection physical layer. Thus, after the temperature and voltage parameters are obtained, the time sequence offset of the current interface is calculated in combination with the preset voltage-temperature-time sequence offset three-dimensional mapping relation; and judging that a potential communication risk exists through the time sequence offset, and then triggering a calibration operation before a data transmission error does not occur. Forward movement on a calibration machine is realized, so that the system stability and the communication reliability are effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and more specifically, to a dynamic calibration method, device, and chip system. Background Art

[0002] The Universal Chiplet Interconnect Express PHY (UCIePHY) is the physical layer interface module in the UCIe protocol architecture. It is used to enable high-speed interconnect communication between multiple chips (including homogeneous and heterogeneous chiplets) using advanced packaging technologies. The "PHY" here refers to the "Physical Layer," the lowest hardware implementation in the data link. It is primarily responsible for basic transmission functions such as sending and receiving electrical signals, clock recovery, and signal integrity assurance.

[0003] UCIe PHY is widely used in today's advanced semiconductor system designs, particularly in high-performance computing platforms based on chiplet architectures, such as AI accelerators, data center processors, high-end graphics processing units (GPUs), and network switching chips. As single-chip performance reaches a bottleneck, integrating multiple functional modules into a single package through advanced packaging is becoming a mainstream trend. UCIe PHY is one of the key communication interfaces supporting this interconnection method.

[0004] In the high-speed interconnect communication scenario between chips involved in UCIe PHY, there are analog modules and digital modules. Figure 1 As shown in FIG, the digital module includes submodules such as a clock gating cell 11 (Clock Gating Cell, CGC), a delay line 12 (DelayLine, DL), a duty cycle adjustment circuit 13 (Duty Cycle Adjustment, DCA) and a duty cycle detection circuit 14 (Duty Cycle Detection, DCD). Figure 2 As shown, the analog module includes submodules such as the Impedance Calibration Module 21 (ZCAL) and the Reference Voltage Source 22 (VREF). These modules may experience performance deviations during actual operation due to factors such as process deviations, operating temperature variations, or power supply voltage fluctuations.

[0005] However, most current UCIe PHY designs only perform a one-time calibration of the analog circuits during initialization. When the chip operates under non-nominal conditions for an extended period, circuit parameters can gradually deviate from design expectations, ultimately leading to data transmission errors and link outages. Summary of the Invention

[0006] To overcome at least one of the deficiencies in the prior art, the present application provides a dynamic calibration method, device, chip system, device, storage medium, and electronic device, specifically including: In a first aspect, the present application provides a dynamic calibration method, the method comprising: Acquire a temperature variation of a common core particle interconnection physical layer between chips and a voltage variation amplitude of the core particle interconnection physical layer; Determining a timing offset of a universal core particle interconnection physical interface according to the temperature variation and the voltage variation; If the offset is greater than an offset threshold, the chip interconnection physical layer is calibrated.

[0007] In a second aspect, the present application provides a dynamic calibration device, wherein the dynamic calibration chip includes a dynamic mapping prediction module, an environmental parameter monitoring module communicatively connected to the dynamic mapping prediction module, and a calibration execution module; The environmental parameter monitoring is in communication with the temperature variation sensor and the voltage sensor, and is used to obtain the temperature variation of the common core grain interconnection physical layer between chips and the voltage variation amplitude of the core grain interconnection physical layer; The dynamic mapping prediction module is used to determine the timing offset of the universal chiplet interconnect physical interface according to the temperature variation and the voltage variation; if the offset is greater than the offset threshold, the calibration execution module is notified to calibrate the chiplet interconnect physical layer.

[0008] In a third aspect, the present application provides a chip system, which includes a dynamic calibration device.

[0009] Compared with the prior art, this application has the following beneficial effects: The present application provides a dynamic calibration method, device and chip system, which obtains the temperature of the universal core particle interconnection physical layer between chips and the voltage variation amplitude of the core particle interconnection physical layer; determines the timing offset of the universal core particle interconnection physical interface based on the temperature and voltage variation amplitude; if the offset is greater than the offset threshold, calibrates the core particle interconnection physical layer. In this way, after obtaining the temperature and voltage parameters, the timing offset of the current interface is calculated in combination with the preset voltage-temperature-timing offset three-dimensional mapping relationship; the timing offset is used to determine the presence of potential communication risks, and then triggers the calibration operation before a data transmission error occurs. This achieves an advance in the calibration timing, thereby effectively improving system stability and communication reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic diagram of a digital module provided in an embodiment of the present application; Figure 2 A schematic diagram of a simulation module provided in an embodiment of the present application; Figure 3 A flow chart of a dynamic calibration method provided in an embodiment of the present application; Figure 4 This is a structural diagram of the dynamic calibration device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present application (hereinafter referred to as the embodiments) more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of them. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0013] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0014] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0015] In the description of this application, it should be noted that the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be understood as indicating or implying relative importance. In addition, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0016] Based on the above statement, as described in the background, most current UCIe PHY designs only perform a one-time calibration of the analog circuitry during initialization. When the chip operates under non-nominal conditions for an extended period, circuit parameters may gradually deviate from design expectations, ultimately leading to data transmission errors and abnormal link interruptions.

[0017] It can be understood that the current UCIe PHY design lacks a mechanism for dynamic updates based on actual environmental parameter changes during operation. This means that the system lacks the ability to predict errors in advance and can only passively wait for errors to occur before initiating recovery processes. This not only affects the reliability of the communication link but also limits the overall performance of the system.

[0018] Based on the discovery of the above technical problems, the following technical solutions are proposed after creative work to solve or improve the above problems. It should be noted that the defects existing in the solutions in the above prior art are the results obtained after practice and careful study. Therefore, the discovery process of the above problems and the solutions proposed in the embodiments of this application for the above problems below should be regarded as contributions to this application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0019] In view of this, this embodiment provides a dynamic calibration method applied to a dynamic calibration device. Figure 3 As shown, the method includes: S1, obtaining the temperature of the physical layer of the common core particle interconnection between chips and the voltage variation amplitude of the physical layer of the core particle interconnection; S2, determining a timing offset of a universal chiplet interconnection physical interface according to the temperature and voltage variation; S3: If the offset is greater than the offset threshold, calibrate the chiplet interconnection physical layer.

[0020] After acquiring temperature and voltage parameters, the system calculates the current interface's timing offset based on a pre-defined three-dimensional mapping of voltage, temperature, and timing offset. This offset identifies potential communication risks and triggers calibration before data transmission errors occur. This shifts the timing of calibration earlier, effectively improving system stability and communication reliability.

[0021] To make the solution provided by this embodiment clearer, Figure 3 Each step shown is described in detail. However, it should be understood that the operations of the flowchart can be implemented in any order, and steps that have no logical contextual relationship can be reversed or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart or remove one or more operations from the flowchart under the guidance of the content of this application. Figure 3 , the method comprising: S1, obtaining the temperature variation of the physical layer of the common core particle interconnection between chips and the voltage variation amplitude of the physical layer of the core particle interconnection.

[0022] In this embodiment, the dynamic calibration device obtains the temperature variation of the package substrate of the chip interconnection physical layer; and uses the temperature variation of the package substrate as the temperature variation of the chip interconnection physical layer.

[0023] During the execution of the above steps, the dynamic calibration device collects temperature variation information through the temperature variation sensor embedded in the package substrate, thereby obtaining the actual thermal state of the environment in which the UCIe PHY is located. The "package substrate" here is defined as the physical basic platform that carries the interconnection structure between chips. Its temperature variation can effectively reflect the thermal changes of the UCIe PHY during operation. It should be pointed out that in actual application scenarios, due to the high thermal coupling characteristics between the package substrate and the UCIe PHY, by measuring the temperature variation of the package substrate, the temperature variation distribution of the UCIe PHY itself can be more accurately inferred.

[0024] This avoids the need for additional temperature variation sensors within the UCIe PHY, thereby reducing hardware complexity and power consumption. In this embodiment, the sampling frequency of the temperature variation data is set to ≤ 10ms, thereby achieving a highly sensitive response to changes in ambient temperature variation.

[0025] In addition, the "voltage variation amplitude" in this embodiment is defined as the maximum deviation of the core power supply voltage from its nominal value, which is obtained by collecting the power supply voltage signal in real time and calculating its fluctuation percentage relative to the rated voltage value.

[0026] Based on the above description of the temperature variation and voltage variation, the following is a description of the Figure 3 Step S2 in the following is explained: S2, determining the timing offset of the universal chiplet interconnection physical interface according to the temperature change and the voltage change amplitude.

[0027] In this embodiment, the dynamic calibration device can match the temperature change and voltage change amplitude with the timing offset table to obtain the timing offset of the chip interconnection physical interface, wherein the timing offset table records the mapping relationship between the temperature change, voltage change amplitude and timing offset.

[0028] During the above steps, the dynamic calibration device inputs the temperature change and voltage variation as input values ​​into a timing offset table for matching. The "timing offset table" herein specifically comprises a three-dimensional lookup table structure that records the mapping relationship between temperature change, voltage variation, and timing offset. In this embodiment, the timing offset table is embedded within the dynamic mapping prediction unit in the form of hardware logic or firmware, enabling rapid querying of the expected timing offset based on the current voltage and temperature change parameters.

[0029] It should be understood that the timing offset table can be constructed based on experience or rigorous mathematical derivation. For example, the empirical construction process can be based on actual silicon test data and simulation analysis results, thereby accurately reflecting the impact of environmental parameter changes on link timing performance.

[0030] Based on the description of the timing offset in the above embodiment, we will continue to interpret Figure 3 Step S3 in: S3: If the offset is greater than the offset threshold, the chiplet interconnection physical layer is calibrated.

[0031] In this embodiment, the dynamic calibration device can calibrate the chiplet interconnect physical layer by adjusting the transmit drive strength and calibrating the clock phase offset of the chiplet interconnect physical layer. Thus, by adjusting the transmit drive strength and calibrating the clock phase offset, the electrical and timing parameters of the communication link are actively corrected to maintain signal integrity.

[0032] It should be noted that the "transmitter drive strength" here refers to the current or voltage amplitude used to drive the transmission line, which directly affects the quality of signal propagation in the package substrate and interconnect channels. Meanwhile, the "clock phase offset" reflects the synchronization status between the receiver and transmitter, and is often affected by factors such as temperature variation, power supply fluctuations, and process differences. These correction operations are consistent with the correction operations performed when the UCIe PHY is first powered on. This embodiment monitors information such as voltage and temperature variation in real time, and when an anomaly is detected, triggers the UCIe PHY to perform another correction during operation.

[0033] For example, in actual application, if the impedance of the interconnect line changes due to changes in temperature, thereby affecting the driving capability, the transmitting end drive strength is automatically increased according to the current link status to compensate for signal attenuation; similarly, if the clock jitter is aggravated due to voltage fluctuations, the clock phase relationship between the transmitting end and the receiving end is recalibrated to restore the stability of the data sampling window.

[0034] It should be understood that during UCIe PHY operation, temperature and voltage parameters experience a certain degree of dynamic fluctuation due to factors such as the thermal capacitance of the package substrate, transient response of the power supply network, and changes in external loads. In some cases, these fluctuations may be minor and insufficient to materially impact link timing stability. However, if calibration triggers for these parameter changes are not established, the system may frequently enter the calibration process, introducing additional power consumption, latency, and control overhead.

[0035] In view of this, Figure 3 Before step S2, the method further includes: S1.5, determine whether the temperature change is greater than a temperature change threshold or whether the voltage change amplitude is greater than a change threshold.

[0036] If yes, then step S2 is executed; otherwise, the temperature variation and voltage variation of the UCIe PHY are continuously monitored.

[0037] It's important to note that the temperature and voltage change thresholds here aren't arbitrary; they're key criteria determined by the thermodynamic characteristics and electrical stability requirements of the Universal Chip Interconnect physical layer under typical operating conditions. In practice, a temperature change exceeding 5°C or a voltage change exceeding ±3% indicates a significant disturbance in the UCIe PHY's operating environment, sufficient to cause a shift in link timing characteristics, potentially affecting data transmission reliability. At this point, the conditions for triggering calibration are considered met, and subsequent operations to determine the timing offset based on the temperature and voltage changes will proceed.

[0038] In actual applications, it is found that due to batch differences, device aging caused by long-term use, or changes in the deployment environment, the preset timing offset table may not work well. For example, when the chip is deployed in a high-temperature environment and runs for a period of time, if it is found that the original timing offset table cannot accurately predict the timing offset, the prediction model can be corrected by injecting new mapping data, thereby improving the accuracy of the calibration trigger and system stability. In view of this, the dynamic calibration method provided in this embodiment also includes: S4, receiving configuration information of the timing offset table.

[0039] S5: Update the timing offset according to the configuration information to obtain a new timing offset table.

[0040] In this embodiment, the dynamic mapping prediction unit storing the timing offset table can be a field-programmable non-volatile memory (FPM). This memory can store a three-dimensional mapping relationship table between voltage, temperature variation, and timing offset, and supports parameter updates and reconfiguration after silicon fabrication (i.e., after chip manufacturing).

[0041] During the above steps, the dynamic calibration device receives timing offset table configuration information provided by an external system or local control logic. Specifically, this configuration information can be sent to the dynamic mapping prediction unit via a debug interface, firmware upgrade module, or on-chip management controller. This configuration information includes new mapping relationships for specific process corners, operating conditions, or application scenarios, such as timing offset trends corresponding to different temperature variation ranges and compensation coefficients for different voltage fluctuation amplitudes.

[0042] Based on the received configuration information, the dynamic calibration device's internal field-programmable non-volatile memory performs a write operation, replacing the original timing offset table with an updated version. The updated timing offset table can then be used for subsequent lookup operations, ensuring that the predicted link timing deviation trends accurately reflect the latest environmental conditions and device characteristics.

[0043] It should be understood that improvements to a technology can be categorized as hardware improvements (e.g., improvements to circuit structures such as diodes, transistors, and switches) and software improvements (improvements to process flows). However, with technological advancements, many process flow improvements can now be considered direct improvements to hardware circuit structures. Designers almost always create the corresponding hardware circuit structure by programming the improved process flow into the hardware circuit. Therefore, it cannot be said that a process flow improvement cannot be implemented using physical hardware modules. For example, a programmable logic device (PLD), such as a field programmable gate array (FPGA), is an integrated circuit whose logical function is determined by user programming. Designers can integrate a digital system onto a PLD through their own programming, eliminating the need for chip manufacturers to design and manufacture dedicated integrated circuit chips. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly performed using "logic compiler" software. This is similar to the software compiler used during program development. Before compilation, the original code must also be written in a specific programming language, called a hardware description language (HDL). There is not just one HDL, but many, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Among them, VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog are currently the most commonly used. Those skilled in the art will also understand that by simply programming the method flow in one of these hardware description languages ​​and programming it into an integrated circuit, a hardware circuit that implements the logic method flow can be easily obtained.

[0044] Therefore, based on the same inventive concept as the above-mentioned dynamic correction method, this embodiment also provides a dynamic calibration device. Figure 4 As shown, the dynamic calibration chip includes a dynamic mapping prediction module 32, an environmental parameter monitoring module 31 in communication with the dynamic mapping prediction module 32, and a calibration execution module 33; The environmental parameter monitoring is connected to the temperature change sensor and the voltage sensor to obtain the temperature change of the general core particle interconnection physical layer between chips and the voltage change amplitude of the core particle interconnection physical layer; The dynamic mapping prediction module 32 is used to determine the timing offset of the universal chiplet interconnect physical interface according to the temperature variation and the voltage variation; if the offset is greater than the offset threshold, the calibration execution module 33 is notified to calibrate the chiplet interconnect physical layer.

[0045] As an optional implementation, the dynamic mapping prediction module 32 is further specifically used to match the temperature change and the voltage change amplitude with the timing offset table to obtain the timing offset of the core particle interconnection physical interface, wherein the timing offset table records the mapping relationship between the temperature change, the voltage change amplitude and the timing offset.

[0046] As an optional implementation, the calibration execution module 33 is further specifically configured to adjust the drive strength of the chip interconnect physical layer transmitter and calibrate the clock phase offset of the chip interconnect physical layer.

[0047] As an optional implementation, the timing deviation table is stored in a programmable non-volatile memory, and the dynamic mapping prediction module 32 is further used to: Receive configuration information of the timing bias table; According to the configuration information, the timing offset is updated to obtain a new timing offset table.

[0048] The dynamic mapping prediction module 32 is further configured to determine whether the temperature is greater than a temperature threshold or whether the voltage variation is greater than a variation threshold. If so, the timing offset of the universal chiplet interconnection physical interface is determined based on the temperature and voltage variation.

[0049] The environmental parameter monitoring module 31 is further specifically configured to obtain the temperature of the package substrate of the chip interconnect physical layer; and use the temperature of the package substrate as the temperature of the chip interconnect physical layer.

[0050] The calibration execution module 33 is further specifically configured to adjust the drive strength of the chip interconnect physical layer transmitter and calibrate the clock phase offset of the chip interconnect physical layer.

[0051] In addition, this embodiment also provides a chip system, which includes the dynamic calibration device.

[0052] In this embodiment, the chip system includes multiple chiplets that communicate via UCIe PHY, along with an integrated dynamic calibration device to maintain the stability of the communication links between the chiplets. This can be understood as a multi-chiplet architecture, where each chiplet relies on UCIe PHY for high-speed data transmission. Because different chiplets may experience varying thermal environments and power supply conditions, temperature changes and voltage fluctuations can easily cause physical layer timing drift during operation, impacting communication quality.

[0053] Therefore, a dynamic calibration device is integrated into the chip system, which includes an environmental parameter monitoring module 31, a dynamic mapping prediction module 32 and a calibration execution module 33. The environmental parameter monitoring module 31 periodically obtains the temperature data and power supply voltage information on the package substrate, and generates a trigger signal when it detects a temperature change ΔT ≥ 5°C or a voltage fluctuation of more than 3%. The dynamic mapping prediction module 32 looks up the table based on the current voltage and temperature parameters to predict the link timing deviation trend, and notifies the calibration execution module 33 to start the calibration operation when the deviation exceeds the set threshold. The calibration execution module 33 adjusts the transmitting end drive strength and the calibration clock phase offset accordingly to compensate for the link timing drift and restore communication stability.

[0054] It should be understood that the devices and methods disclosed in the above embodiments may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the devices, methods, and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented using a dedicated hardware-based system that performs a specified function or action, or may be implemented using a combination of dedicated hardware and computer instructions.

[0055] The above descriptions are merely examples of various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be readily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A dynamic calibration method, characterized in that: The method comprises: Acquire a temperature variation of a common core particle interconnection physical layer between chips and a voltage variation amplitude of the core particle interconnection physical layer; Determining a timing offset of a universal core particle interconnection physical interface according to the temperature variation and the voltage variation; If the offset is greater than an offset threshold, the chip interconnection physical layer is calibrated.

2. The dynamic calibration method according to claim 1, characterized in that: Determining a timing offset of a universal core particle interconnection physical interface according to the temperature variation and the voltage variation, including: The temperature variation and the voltage variation amplitude are matched with a timing offset table to obtain a timing offset of the core particle interconnection physical interface, wherein the timing offset table records a mapping relationship between the temperature variation, the voltage variation amplitude and the timing offset.

3. The dynamic calibration method according to claim 2, characterized in that: The timing deviation table is stored in a programmable non-volatile memory, and the method further includes: receiving configuration information of the timing offset table; According to the configuration information, the timing offset is updated to obtain a new timing offset table.

4. The dynamic calibration method according to claim 1, wherein: The method further comprises: Determining whether the temperature change is greater than a temperature change threshold or whether the voltage change amplitude is greater than a change threshold; If so, determining the timing offset of the universal chip interconnection physical interface according to the temperature variation and the voltage variation.

5. The dynamic calibration method according to claim 1, characterized in that: Obtain the temperature variation of the physical layer of the common core interconnect between chips, including: Acquire a temperature variation of a packaging substrate of the chip interconnection physical layer; The temperature variation of the package substrate is used as the temperature variation of the chip interconnection physical layer.

6. The dynamic calibration method according to claim 1, characterized in that: Calibrate the chiplet interconnection physical layer, including: The driving strength of the transmitting end of the chip interconnection physical layer is adjusted, and the clock phase offset of the chip interconnection physical layer is calibrated.

7. A dynamic calibration device, characterized in that: The dynamic calibration device includes a dynamic mapping prediction module, an environmental parameter monitoring module in communication with the dynamic mapping prediction module, and a calibration execution module; The environmental parameter monitoring is in communication with the temperature variation sensor and the voltage sensor, and is used to obtain the temperature variation of the common core grain interconnection physical layer between chips and the voltage variation amplitude of the core grain interconnection physical layer; The dynamic mapping prediction module is used to determine the timing offset of the universal chiplet interconnect physical interface according to the temperature variation and the voltage variation; if the offset is greater than the offset threshold, the calibration execution module is notified to calibrate the chiplet interconnect physical layer.

8. The dynamic calibration device according to claim 7, characterized in that: The dynamic mapping prediction module is further specifically used to match the temperature change and the voltage change amplitude with the timing offset table to obtain the timing offset of the core particle interconnection physical interface, wherein the timing offset table records the mapping relationship between the temperature change, the voltage change amplitude and the timing offset.

9. The dynamic calibration device according to claim 7, characterized in that: The calibration execution module is further specifically configured to adjust the driving strength of the transmitting end of the chip interconnection physical layer and calibrate the clock phase offset of the chip interconnection physical layer.

10. A chip system, characterized in that: The chip system includes the dynamic calibration device according to any one of claims 7 to 9.

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