Storage device

Abstract

According to one embodiment, a memory device includes a memory cell, a first wiring, a second wiring, a first switch, a current mirror circuit, and a sense amplifier circuit. The memory cell has a first end and a second end. The first wiring is connected to the first end. The second wiring is connected to the second end. The first switch is connected between the second wiring and a third wiring receiving the first voltage. The current mirror circuit has a third end and a fourth end, is connected to the first wiring at the third end, and outputs an output current having a first current flowing through the first wiring as a reference current at the fourth end. The sensing amplifying circuit is connected with the fourth end.

Description

Technical Field

[0001] Embodiments generally relate to storage devices. Background Art

[0002] Examples of storage devices include magnetic storage devices, which use the magnetoresistive effect to store data. Summary of the Invention

[0003] A memory device according to one embodiment includes a memory cell, a first wiring, a second wiring, a first switch, a current mirror circuit, and a sense amplifier circuit. The memory cell has a first terminal and a second terminal. The first wiring is connected to the first terminal. The second wiring is connected to the second terminal. The first switch is connected between the second wiring and a third wiring that receives a first voltage. The current mirror circuit has a third terminal and a fourth terminal. The third terminal is connected to the first wiring, and the fourth terminal outputs an output current using a first current flowing in the first wiring as a reference current. The sense amplifier circuit is connected to the fourth terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 Functional blocks of the storage device according to the first embodiment are shown.

[0005] Figure 2 This is a circuit diagram of a memory cell array of the memory device according to the first embodiment.

[0006] Figure 3 This is a perspective view of a portion of the memory cell array of the memory device according to the first embodiment.

[0007] Figure 4 A cross section showing an example of the structure of a memory cell of the memory device according to the first embodiment.

[0008] Figure 5 An example of a curve showing characteristics of voltage and current of a memory cell of the memory device according to the first embodiment is shown.

[0009] Figure 6 An example of components of a read circuit of the memory device according to the first embodiment and connections of the components is shown.

[0010] Figure 7 The states of several signals during the data read period of the storage device according to the first embodiment are shown along time.

[0011] Figure 8 An example of components of a readout circuit of a reference memory device and connections of the components is shown.

[0012] Figure 9An example of components of a read circuit of a memory device according to a modification of the first embodiment and connections of the components is shown. DETAILED DESCRIPTION

[0013] A memory device according to one embodiment includes a memory cell, a first wiring, a second wiring, a first switch, a current mirror circuit, and a sense amplifier circuit. The memory cell has a first terminal and a second terminal. The first wiring is connected to the first terminal. The second wiring is connected to the second terminal. The first switch is connected between the second wiring and a third wiring that receives a first voltage. The current mirror circuit has a third terminal and a fourth terminal. The third terminal is connected to the first wiring, and the fourth terminal outputs an output current using a first current flowing in the first wiring as a reference current. The sense amplifier circuit is connected to the fourth terminal.

[0014] In some cases, a number or letter may be added to the end of a reference numeral to distinguish a plurality of components having substantially the same function and configuration in a certain embodiment or in different embodiments.

[0015] In this specification and claims, a first element being “connected” to a second element includes the first element being connected to the second element directly, always, or selectively via a conductive element.

[0016] First embodiment

[0017] Figure 1 The functional blocks of the storage device of the first embodiment are shown. The storage device 1 is a device for storing data. The storage device 1 is a magnetic storage device that stores data using a stack of magnetic materials that exhibit dynamically variable resistance. Figure 1 As shown, the memory device 1 includes a memory cell array 11 , an input / output circuit 12 , a control circuit 13 , a row selection circuit 14 , a column selection circuit 15 , a write circuit 16 , a read circuit 17 , and a voltage generation circuit 18 .

[0018] The memory cell array 11 is a collection of a plurality of arranged memory cells MC. The memory cell MC is capable of storing data in a non-volatile manner. A plurality of first-type wirings and a plurality of second-type wirings are located in the memory cell array 11. In the following description, one of the first-type wirings and the second-type wirings is referred to as a word line WL, and the other is referred to as a bit line BL. The following description is based on an example in which the word line WL is associated with a row and the bit line BL is associated with a column. Each memory cell MC is connected to one word line WL and one bit line BL. One memory cell MC is selected by selecting one row and one column.

[0019] The input / output circuit 12 inputs and outputs data and signals. The input / output circuit 12 receives control signals CNT, commands CMD, address information ADD, and data DAT from outside the memory device 1, for example, from a memory controller. The input / output circuit 12 outputs data DAT.

[0020] The voltage generating circuit 18 generates voltages of various magnitudes using voltages received from outside the memory device 1. The voltage generating circuit 18 outputs one or more voltages of a fixed magnitude for data reading. The voltage generating circuit 18 also outputs a fixed magnitude voltage and a dynamically variable magnitude voltage for data writing.

[0021] The write circuit 16 controls the writing of data into the memory cell MC. It receives write data DAT from the input / output circuit 12 and a voltage for data writing from the voltage generating circuit 18. Based on the control of the control circuit 13 and the write data DAT, the write circuit 16 outputs the voltage and current used for data writing.

[0022] Read circuit 17 controls the reading of data from memory cell MC. Read circuit 17 receives a voltage for data reading from voltage generator circuit 18. Based on control from control circuit 13, read circuit 17 uses the voltage for data reading to determine (or determine) the data stored in memory cell MC. Read circuit 17 includes a plurality of sense amplifier circuits SAC (not shown).

[0023] The row select circuit 14 is a circuit for selecting a row of memory cells MC. The row select circuit 14 receives address information ADD from the input / output circuit 12. The row select circuit 14 receives a voltage for data write from the write circuit 16. The row select circuit 14 receives a voltage for data read from the read circuit 17. During a data write period, the row select circuit 14 uses the voltage for data write to select one or more word lines WL associated with the row specified by the received address information ADD. During a data read period, the row select circuit 14 uses the voltage for data read to select one or more word lines WL associated with the row specified by the received address information ADD.

[0024] The column select circuit 15 is a circuit for selecting a column of memory cells MC. The column select circuit 15 receives address information ADD from the input / output circuit 12. The column select circuit 15 receives a voltage for data write from the write circuit 16. The column select circuit 15 receives a voltage for data read from the read circuit 17. During a data write period, the column select circuit 15 uses the voltage for data write to select one or more bit lines BL associated with the column identified by the received address information ADD. During a data read period, the column select circuit 15 uses the voltage for data read to select one or more bit lines BL associated with the column identified by the received address information ADD.

[0025] The control circuit 13 controls the operation of the memory device 1. It receives a control signal CNT and a command CMD from the input / output circuit 12. Based on the control signal CNT and the command CMD, the control circuit 13 controls the write circuit 16 and the read circuit 17. Specifically, the control circuit 13 controls the write circuit 16 so that, during the data write period in the memory cell MC, the voltage received by the write circuit 16 from the voltage generation circuit 18 is supplied to the row select circuit 14 and the column select circuit 15. The control circuit 13 controls the read circuit 17 so that, during the data read period in the memory cell MC, the voltage received by the read circuit 17 from the voltage generation circuit 18 is supplied to the row select circuit 14 and the column select circuit 15.

[0026] 1.1.2. Circuit Configuration of Memory Cell Array

[0027] Figure 2 FIG. 1 is a circuit diagram of a memory cell array of a memory device according to the first embodiment. Figure 2 As shown, M+1 word lines WL (ie, WL_0, WL_1, ..., and WL_M) and N+1 bit lines BL (ie, BL_0, BL_1, ..., and BL_N) are located in the memory cell array 11. M and N are each positive numbers.

[0028] Each memory cell MC is connected to one word line WL and one bit line BL. Each memory cell MC includes one MTJ element MTJ and one switching element SE. In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SE of each memory cell MC is connected to one word line WL. The MTJ element MTJ of each memory cell MC is connected to one bit line BL.

[0029] The MTJ element MTJ exhibits a tunnel magnetoresistance effect, and is, for example, an element including a magnetic tunnel junction (MTJ). The MTJ element MTJ is also called a magnetoresistance effect element MTJ. The MTJ element MTJ is a variable resistance element that can switch between a low resistance state and a high resistance state. The MTJ element MTJ can store 1 bit of data by utilizing the difference between the two resistance states. In one example, the MTJ element MTJ utilizes a low resistance state to store "0" data and utilizes a high resistance state to store "1" data.

[0030] The switching element SE has two terminals and is an element that electrically connects or disconnects the two terminals. When the voltage applied between the two terminals in a first direction is lower than a certain threshold voltage, the switching element SE is in a high-resistance state, such as an electrically non-conductive state (or an off state). When the voltage applied between the two terminals rises and becomes higher than the threshold voltage, the switching element SE enters a low-resistance state, such as an electrically conductive state (or an on state). When the voltage applied between the two terminals of the switching element SE in the low-resistance state decreases and becomes lower than the threshold voltage, the switching element SE enters a high-resistance state. The switching element SE also has the same function of switching between a high-resistance state and a low-resistance state based on the magnitude of the voltage applied in the first direction in a second direction, which is opposite to the first direction. In other words, the switching element SE is a bidirectional switching element. By turning the switching element SE on or off, it is possible to control whether current is supplied to the MTJ element MTJ connected to the switching element SE, that is, whether the MTJ element MTJ is selected or not.

[0031] 1.1.3. Memory Cell Array Structure

[0032] Figure 3 FIG is a perspective view of a portion of a memory cell array of a memory device according to the first embodiment. Figure 3 As shown, a plurality of conductors 21 and a plurality of conductors 22 are provided.

[0033] The conductors 21 are linear and extend along the x-axis. The conductors 21 are arranged along the y-axis, which is perpendicular to the x-axis. Each conductor 21 functions as a word line WL.

[0034] Conductor 22 is located above conductor 21 on the z-axis. The z-axis is perpendicular to the x-axis and y-axis. Conductor 22 has a linear shape, extending along the y-axis and arranged along the x-axis. Each conductor 22 functions as a bit line BL.

[0035] A memory cell MC is provided at each intersection of the conductor 21 and the conductor 22. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as the switching element SE and the structure that functions as the MTJ element MTJ each include one or more layers. In one example, the structure that functions as the MTJ element MTJ is located on the upper surface of the structure that functions as the switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of one conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of one conductor 22.

[0036] 1.1.4. Storage Unit

[0037] Figure 4 A cross section showing an example of the structure of a memory cell of the memory device according to the first embodiment.

[0038] The switching element SE includes a variable resistance material 32. The variable resistance material 32 is a material that exhibits dynamically variable resistance and, in one example, has a layered shape. The variable resistance material 32 is a two-terminal switching element, wherein the first terminal is one of the upper and lower surfaces of the variable resistance material 32, and the second terminal is the other of the upper and lower surfaces of the variable resistance material 32. When the voltage applied between the two terminals is lower than a certain threshold voltage, the variable resistance material 32 is in a high resistance state, such as an electrically non-conductive state. When the voltage applied between the two terminals increases and becomes higher than the threshold voltage, the variable resistance material 32 is in a low resistance state, such as an electrically conductive state. When the voltage applied between the two terminals of the variable resistance material 32 in the low resistance state decreases and becomes lower than the threshold voltage, the variable resistance material 32 is in a high resistance state.

[0039] In one example, variable resistor material 32 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator may include, for example, an oxide, such as a material formed of SiO2, or a material formed essentially of SiO2. In one example, the dopant includes arsenic (As) or germanium (Ge). The phrase "formed essentially of" and similar phrases permit unintended impurities to be present in the component "formed essentially of."

[0040] The switching element SE may further include a lower electrode 31 and an upper electrode 33 . Figure 4 In the example shown, the variable resistance material 32 is located on the upper surface of the lower electrode 31 , and the upper electrode 33 is located on the upper surface of the variable resistance material 32 .

[0041] The MTJ element MTJ includes a ferromagnetic layer 35, an insulating layer 36, and a ferromagnetic layer 37. As an example, Figure 4As shown, the insulating layer 36 is located on the upper surface of the ferromagnetic layer 35 , and the ferromagnetic layer 37 is located on the upper surface of the insulating layer 36 .

[0042] The ferromagnetic layer 35 is a layer made of a ferromagnetic material. The ferromagnetic layer 35 has an easy magnetization axis that extends along the interface between the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37. This ensures that the magnetization direction of the ferromagnetic layer 35 does not change during data reading and writing in the memory cell MC. The ferromagnetic layer 35 functions as a so-called reference layer. The ferromagnetic layer 35 may also include multiple layers. Hereinafter, the ferromagnetic layer 35 may sometimes be referred to as the reference layer RL.

[0043] The insulating layer 36 is an insulating layer and contains, for example, magnesium oxide (MgO) or is substantially composed of MgO, and functions as a so-called tunnel barrier (TB).

[0044] Ferromagnetic layer 37 is a layer made of a ferromagnetic material. Ferromagnetic layer 37 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or consist essentially of CoFeB or FeB. Ferromagnetic layer 37 has an easy magnetization axis extending along the interface between ferromagnetic layer 35, insulating layer 36, and ferromagnetic layer 37. The magnetization direction of ferromagnetic layer 37 changes as data is written to memory cell MC, and ferromagnetic layer 37 functions as a so-called storage layer (SL). Hereinafter, ferromagnetic layer 37 may be referred to as storage layer SL.

[0045] When the direction of magnetization of the storage layer SL is parallel to the direction of magnetization of the reference layer RL, the MTJ element MTJ has a certain low resistance. When the direction of magnetization of the storage layer SL is antiparallel to the direction of magnetization of the reference layer RL, the MTJ element MTJ has a higher resistance than the resistance in the case where the direction of magnetization of the storage layer SL is antiparallel to the direction of magnetization of the reference layer RL.

[0046] When a current of a certain magnitude or greater flows from the storage layer SL toward the reference layer RL, the direction of magnetization of the storage layer SL becomes parallel to the direction of magnetization of the reference layer RL. When a current of a certain other magnitude or greater flows from the reference layer RL toward the storage layer SL, the direction of magnetization of the storage layer SL becomes antiparallel to the direction of magnetization of the reference layer RL.

[0047] The MTJ element MTJ may also include more layers.

[0048] Figure 5 This graph shows an example of the voltage-current characteristics of a memory cell in the memory device according to the first embodiment. The horizontal axis of the graph represents the magnitude of the terminal voltage of the memory cell MC (i.e., the difference in potential between its terminals). The vertical axis of the graph represents the magnitude of the current flowing through the memory cell MC on a logarithmic scale. Figure 5 The dotted lines indicate hypothetical characteristics that do not actually appear. Figure 5 It shows the case where the memory cell MC is in a low resistance state and the case where it is in a high resistance state.

[0049] When the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. Before the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is turned off, that is, non-conductive.

[0050] When the voltage is further increased and reaches the threshold voltage Vth, that is, when it reaches point A, the relationship between voltage and current changes discontinuously, exhibiting the characteristics shown at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly higher than the magnitude of the current at point A. This sudden change in current is due to the conduction of the switching element SE of the memory cell MC. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.

[0051] When the voltage is reduced from a state where the switching element SE is on, for example, from a state where the voltage and the current exhibit a relationship represented by point B1 or point B2 and a point where the voltage is higher than these, the current continues to decrease.

[0052] When the voltage is further reduced and reaches a certain level, the relationship between the voltage and the current shows a discontinuous change. The voltage at which the relationship between the voltage and the current begins to show discontinuity depends on the terminal voltage of the MTJ element MTJ of the memory cell MC, that is, it depends on whether the MTJ element MTJ is in a high resistance state or a low resistance state. When the MTJ element MTJ is in a low resistance state, the relationship between the voltage and the current shows discontinuity from point C1. When the MTJ element MTJ is in a high resistance state, the relationship between the voltage and the current shows discontinuity from point C2. When the relationship between the voltage and the current reaches points C1 and C2, it shows the characteristics represented by points D1 and D2, respectively. The magnitude of the current at points D1 and D2 is significantly smaller than the magnitude of the current at points C1 and C2, respectively. This sharp change in current is based on the cutoff of the switching element SE of the memory cell MC.

[0053] The terminal voltage at point D1 of the memory cell MC including the MTJ element MTJ in the low resistance state is called the low hold voltage VhdL. The terminal voltage at point D2 of the memory cell MC including the MTJ element MTJ in the high resistance state is called the high hold voltage VhdH.

[0054] 1.1.5. Readout Circuit

[0055] Figure 6 An example of components of a read circuit of the memory device according to the first embodiment and connections of the components is shown. Figure 6 As a representative example, one sense amplifier circuit SAC is shown, and a state in which one memory cell MC is selected is shown. Figure 1 As described above, a word line WL is selected by the row selection circuit 14, and a bit line BL is selected by the column selection circuit 15. A memory cell MC connected to the selected word line WL and the selected bit line BL is selected, and data is read from the selected memory cell MC. Figure 6 The word line WL, bit line BL, and memory cell MC shown are in a selected state. Hereinafter, a word line WL in a selected state may be referred to as a selected word line WL. A bit line BL in a selected state may be referred to as a selected bit line BL. A memory cell MC in a selected state may be referred to as a selected memory cell MC.

[0056] like Figure 6 As shown, the readout circuit 17 is connected to the word line WL via the turned-on switch SW1 in the row select circuit 14. In one example, the switch SW1 is a p-type or n-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the switch SW1 is a set of a p-type MOSFET and an n-type MOSFET connected in parallel, each receiving signals of opposite logic (or complementary) at its gate. The switch SW1 receives a signal S1. While receiving the high (or "H") level signal S1, the switch SW1 is turned on, maintaining a state in which one end of the switch SW1 is electrically connected to the other end. While receiving the low (or "L") level signal S1, the switch SW1 is turned off, maintaining a state in which one end of the switch SW1 is electrically disconnected from the other end.

[0057] The same applies to the switch SWn and signal Sn described later, where n is an integer greater than or equal to 2. That is, for the switch SWn, the description of the switch SW1 is replaced with the description of the switch SWn, and for the signal Sn, the description of the signal S1 is replaced with the description of the signal Sn.

[0058] The read circuit 17 is also connected to the bit line BL via the turned-on switch SW2 in the column selection circuit 15 .

[0059] The readout circuit 17 includes a sense amplifier circuit SAC, switches SW3 to SW5 , a current mirror circuit CM, an n-type MOSFET (transistor) TN1 , wirings L1 to L3 and DL, and a readout control circuit RCC.

[0060] The wiring L1 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to the word line WL.

[0061] The wiring L2 is connected to one end of the switch SW2, and the other end of the switch SW2 is connected to the bit line BL.

[0062] Switch SW3 is connected between wiring L1 and a node receiving non-select voltage VUSEL. The node receiving non-select voltage VUSEL functions as a node supplying non-select voltage VUSEL. In one example, non-select voltage VUSEL is supplied from voltage generating circuit 18. In one example, non-select voltage VUSEL has a constant magnitude. Non-select voltage VUSEL has a magnitude between ground voltage VSS and voltage VHH. Voltage VHH is an internal power supply voltage and has a positive magnitude. In one example, non-select voltage VUSEL has a magnitude half that of voltage VHH. In one example, voltage VHH is supplied from voltage generating circuit 18.

[0063] The switch SW4 is connected between the wiring L2 and a node receiving the non-select voltage VUSEL.

[0064] The switch SW5 is connected between the wiring L2 and the wiring L3.

[0065] Transistor TN1 is connected between wiring L3 and a node receiving ground voltage VSS. Transistor TN1 receives voltage VCLAMP at its gate. Voltage VCLAMP has a certain magnitude. Wiring L3 receives voltage VCALMP via transistor TN1.

[0066] The current mirror circuit CM includes terminals E1, E2, E3, and E4. The current mirror circuit CM receives a current and a voltage at the terminals E1 and E2.

[0067] The current mirror circuit CM outputs a current to the terminal E3. The current flowing through the terminal E3 functions as a reference current for the current mirror circuit CM. The terminal E3 is connected to the wiring L1.

[0068] The current mirror circuit CM outputs an output current at terminal E4. The output current is based on a reference current and has substantially the same magnitude as the reference current. In this specification and claims, "substantially identical" means that two or more elements, while intended to be identical, are not identical due to limitations in manufacturing and / or measurement technology. Terminal E4 is connected to wiring DL.

[0069] In one example, the current mirror circuit CM includes p-type MOSFETs (transistors) TP1 and TP2. The transistor TP1 is connected between the terminal E1 and the terminal E3, and has a gate connected to the wiring L1.

[0070] Transistor TP2 is connected between terminal E2 and terminal E4, and has its gate connected to wiring L1 and the gate of transistor TP1. In one example, when transistors TP1 and TP2 receive the same terminal voltage and the same voltage at their gates, substantially the same drain current flows. In one example, transistor TP2 has substantially the same characteristics as transistor TP1. Examples of such characteristics include transistor gate width and transistor gate length.

[0071] The switch SW6 is connected between the node receiving the voltage VHH and the terminal E1. The node receiving the voltage VHH functions as a node supplying the voltage VHH.

[0072] The switch SW7 is connected between the node receiving the voltage VHH and the terminal E2.

[0073] The sense amplifier circuit SAC is a circuit that uses a voltage based on the data stored in the memory cell MC being read to output data determined to be stored in the memory cell MC being read. In one example, the sense amplifier circuit SAC includes an operational amplifier OP and a resistor R1. The non-inverting input of the operational amplifier OP is connected to a wiring DL. The inverting input of the operational amplifier OP is connected to one end of the resistor R1. The other end of the resistor R1 is connected to a node connected to the ground voltage VSS. In one example, the inverting input of the operational amplifier OP has a potential between the high holding voltage VhdH and the low holding voltage VhdL. The resistor R1 has a value that enables the inverting input of the operational amplifier OP to have this potential.

[0074] The read control circuit RCC outputs signals S1 to S7.

[0075] 1.2. Action

[0076] Figure 7 The states of several signals during the data read period of the storage device according to the first embodiment are shown along time. Figure 7 Shown as Figure 6 As shown in FIG. 1 , a certain memory cell MC as a data read target is selected. Figure 7 The period shown is Figure 6 The switches SW1 and SW2 connected to the selected memory cell MC are both turned on. Figure 6 The word line WL and the bit line BL shown are selected word line WL and selected bit line BL respectively. When data reading is started in a state where the memory cell MC as the data reading target is selected, Figure 7 The operation during the indicated period begins.

[0077] At time t0, the voltages and currents of the signals, nodes, and nodes are in the following states: Signals S3 and S4 are at a high level, and signals S5, S6, and S7 are at a low level. Therefore, switches SW3 and SW4 are on, and switches SW4, SW5, and SW7 are off.

[0078] With switches SW6 and SW7 turned off and switch SW3 turned on, the selected word line WL receives the non-select voltage VUSEL. Consequently, the selected word line potential VWL reaches the non-select potential VUSEL. The selected word line potential VWL is the potential of the selected word line WL. The non-select potential VUSEL is the potential that the wiring has while receiving the non-select voltage VUSEL. In one example, it has substantially the same magnitude as the non-select voltage VUSEL. With the selected word line WL reaching the non-select potential VUSEL, transistors TP1 and TP2 are turned on.

[0079] Since the switch SW5 is turned off and the switch SW4 is turned on, the selected bit line BL receives the non-selection voltage VUSEL, whereby the selected bit line potential VBL has the non-selection potential VUSEL. The selected bit line potential VBL is the potential of the selected bit line BL.

[0080] Because the selected word line WL and the selected bit line BL have the non-select potential VUSEL, the terminal voltage of the switching element SE of the selected memory cell MC falls below the threshold voltage Vth. Consequently, the switching element SE of the selected memory cell MC is turned off. Consequently, the cell current Icell does not flow. The cell current Icell is the current flowing in the selected memory cell MC.

[0081] At time t1, signal S4 is set to a low level, and signal S5 is set to a high level. This turns off switch SW4 and turns on switch SW5. Consequently, the selected bit line BL no longer receives the unselected voltage VUSEL and instead receives the voltage received by wiring L3, namely, voltage VCLAMP. Voltage VCLAMP is lower than the unselected voltage VUSEL. This precharges the selected bit line BL to a potential lower than the unselected voltage VUSEL.

[0082] At time t2, the signal S5 is set to a low level, thereby turning off the switch SW5 and placing the selected bit line BL in an electrically floating state.

[0083] At time t3, signal S3 is set to a low level, and signal S6 is set to a high level. Consequently, switch SW3 is turned off, and switch SW6 is turned on. Consequently, the selected word line WL no longer receives the application of the unselected voltage VUSEL, and instead receives the voltage VHH. Consequently, current flows through transistor TP1. Consequently, the selected word line potential VWL is precharged to the potential VHH. The potential VHH has substantially the same magnitude as the voltage VHH.

[0084] When the selected word line potential VWL rises and the difference between the selected word line potential VWL and the selected bit line potential VBL reaches the threshold voltage Vth, the switching element SE of the selected memory cell MC turns on. This causes a cell current Icell to flow from the selected word line WL to the selected bit line BL. Cell current Icellll1 rises sharply from time t3, reaching a peak value. The current flowing through transistor TP1 after the switching element SE of the selected memory cell MC turns on is substantially the same as the cell current Icell.

[0085] The peak value of the cell current Icell depends on whether the MTJ element MTJ of the selected memory cell MC is in a low resistance state or a high resistance state. The peak value of the cell current Icell when the MTJ element MTJ of the selected memory cell MC is in a low resistance state is greater than the peak value of the cell current Icell when the MTJ element MTJ of the selected memory cell MC is in a high resistance state.

[0086] The cell current Icell charges the selected bit line BL. As a result, the selected bit line potential VBL rises from time t3. The rate of rise in the selected bit line potential VBL depends on whether the MTJ element MTJ of the selected memory cell MC is in a low resistance state or a high resistance state. The selected bit line potential VBL rises faster when the MTJ element MTJ of the selected memory cell MC is in a low resistance state than when the MTJ element MTJ of the selected memory cell MC is in a high resistance state.

[0087] The cell current Icell reaches a peak immediately after time t3 and then decreases. The rate of decrease of the cell current Icell depends on whether the MTJ element MTJ of the selected memory cell MC is in a low resistance state or a high resistance state. The cell current Icell decreases faster when the MTJ element MTJ of the selected memory cell MC is in a low resistance state than when the MTJ element MTJ of the selected memory cell MC is in a high resistance state. This is because the selected bit line potential VBL rises faster when the MTJ element MTJ of the selected memory cell MC is in a low resistance state than when the MTJ element MTJ of the selected memory cell MC is in a high resistance state.

[0088] At time t4, signal S7 is set to a high level. This turns on switch SW7. Consequently, a current (i.e., cell current Icell) substantially equal to the current flowing through transistor TP1 (i.e., cell current Icell) flows through transistor TP2. The cell current Icell flowing through transistor TP2 charges wiring DL, raising the potential VDL. The potential VDL is the potential of wiring DL.

[0089] The rate at which the potential VDL rises depends on whether the MTJ element MTJ of the selected memory cell MC is in a low resistance state or a high resistance state. When the MTJ element MTJ of the selected memory cell MC is in a low resistance state, the potential VDL rises faster than when the MTJ element MTJ of the selected memory cell MC is in a high resistance state.

[0090] At time t5, when the MTJ element MTJ of the selected memory cell MC is in a low-resistance state, the difference between the selected bit line potential VBL and the selected word line potential VWL, which has been rising since time t3, reaches the low holding voltage VhdL. Consequently, the switching element SE of the selected memory cell MC is turned off, and the cell current Icell becomes zero. With the cell current Icell at zero, charging of the wiring DL ceases. As a result, the potential VDL becomes a certain value, VDLL.

[0091] At time t6, when the MTJ element MTJ of the selected memory cell MC is in the high-resistance state, the difference between the selected bit line potential VBL and the selected word line potential VWL, which has been rising since time t3, reaches the high holding voltage VhdH. Consequently, the switching element SE of the selected memory cell MC is turned off, and the cell current Icell becomes zero. With the cell current Icell becoming zero, charging of the wiring DL ceases. As a result, the potential VDL becomes a certain value, VDLH. The potential VDLH is higher than the potential VDL by the difference SGV.

[0092] After time t6, sense amplifier circuit SAC outputs data determined to be stored in the selected memory cell MC, based on potential VDL. In one example, when potential VDL is VDLL, that is, when the difference between the selected word line potential VWL and the selected bit line potential VBL is the low hold voltage VhdL, sense amplifier circuit SAC outputs a low-level signal. When potential VDL is VDLH, that is, when the difference between the selected word line potential VWL and the selected bit line potential VBL is the high hold voltage VhdH, sense amplifier circuit SAC outputs a high-level signal.

[0093] 1.3. Advantages (Effects)

[0094] According to the first embodiment, as described below, it is possible to provide a storage device that can ensure a large signal difference and read data with high precision under easy control.

[0095] Data can be read from memory cell MC using a voltage. In this case, the selected word line WL is connected to a sense amplifier circuit SAC. After being precharged by receiving a voltage higher than the unselected voltage VUSEL, the selected word line WL is placed in an electrically floating state. Subsequently, a voltage lower than the unselected voltage VUSEL is continuously applied to the selected bit line BL. As a result, the selected word line potential VWL decreases. When the difference between the selected word line potential VWL and the selected bit line potential VBL reaches the low holding voltage VhdL or the high holding voltage VhdH, the switching element SE turns off, and the decrease in the selected word line potential VWL stops. The selected word line potential VWL at the point where the decrease stops is used as a signal. The difference between the selected word line potential VWL in the low resistance state and the high resistance state corresponds to the signal difference. However, particularly in the high resistance state, the timing of the switching element SE turning off is later than expected. Therefore, the selected word line potential VWL is lower after the switching element SE turns off in the high resistance state. As a result, the signal difference is small.

[0096] To address this issue, one approach might be to stop applying voltage to the selected bit line BL. This causes the switching element SE to turn off before automatically turning off due to reaching the holding voltage (low holding voltage VhdL or high holding voltage VhdH). Therefore, in the high-resistance state, the selected word line potential VWL is high after the switching element SE is turned off, enabling a greater signal difference. However, the voltage (clamping voltage) applied to the gate of the transistor used to precharge the selected word line WL may vary, and thus, the potential of the precharged selected word line WL may also vary. When the switching element SE automatically turns off due to reaching the holding voltage, since the turn-off of the switching element SE depends not on the clamping voltage but on the holding voltage, variations in the clamping voltage do not affect the timing of the turn-off of the switching element SE. On the other hand, when the switching element SE is turned off by stopping the application of voltage to the selected bit line BL, variations in the clamping voltage can affect the selected word line potential VWL at the time the switching element SE is turned off. Taking this into consideration and the inevitable performance variations of the memory cells MC, it is difficult to determine the appropriate timing for applying a voltage to the selected bit line BL.

[0097] On the other hand, in order to obtain a large signal difference, it is possible to use current to read out data. In this case, Figure 8As shown, unlike when connected to the sense amplifier circuit SAC when voltage is used, word line WL is connected to the gate of transistor TN12, which is connected between the node receiving voltage VHH and the sense amplifier circuit SAC. To charge the wiring DL connected to the sense amplifier circuit SAC with the cell current Icell, precharging of the selected bit line BL begins, and switch SW7 is turned on. Therefore, from the start of precharging of the selected bit line BL, current continues to flow through transistor TN12, resulting in high current consumption.

[0098] The memory device 1 of the first embodiment includes a current mirror circuit CM that uses the cell current Icell as a reference current and supplies an output current, a replica of the reference current, to a wiring DL connected to a sense amplifier circuit SAC. Consequently, the voltage received by the sense amplifier circuit SAC is formed by integrating the current, which is a replica of the cell current Icell. Therefore, even with a small replica current, the potential VDL increases quickly. This results in a large signal difference SVG. This enables a high margin in data reading and high data read performance.

[0099] In addition, the stopping of the output current when the MTJ element MTJ is in the low resistance state and the stopping of the output current when the MTJ element MTJ is in the high resistance state occur automatically according to the resistance state of the MTJ element MTJ. Therefore, there is no need to control the stopping of the output current, and the necessity of ensuring a margin for the timing of controlling the stopping of the output current in order to cope with the inevitable deviation of the characteristics of the memory cell MC and (or) the misreading of data caused by the lack of margin can be suppressed. On the contrary, by utilizing the situation in which the output current is stopped based on the resistance state of the MTJ element MTJ, the current flows only during the period of the high resistance state ( Figure 7 By charging the wiring DL from time t5 to time t6, a large difference between the potential VDLL and the potential VDLH, that is, a large signal difference SGV, can be obtained. Thus, a memory device 1 that is easy to control and can read data with high accuracy is provided.

[0100] Furthermore, by using the current mirror circuit CM, the wiring DL is formed by the output current that is a replica of the cell current Icell, not the cell current Icell itself. Therefore, the start of output of the output current of the current mirror circuit CM can be delayed from the start of data reading. Consequently, the current for charging the wiring DL does not need to flow continuously from the start of data reading. This allows for a memory device 1 with low current consumption.

[0101] Furthermore, the start of output current output, that is, the turning on of switch SW7, requires control. Therefore, the need to control the timing of turning on switch SW7 to ensure a margin for the timing of turning on switch SW7 may complicate the control of memory device 1. However, as described above, the potential of wiring DL is generated by integrating over a longer duration when the MTJ element MTJ is in a high-resistance state than when it is in a low-resistance state, making it easier to obtain a large signal difference SVG. Consequently, even if the timing of turning on switch SW7 varies slightly, a large signal difference SVG can be maintained, making control easier.

[0102] In addition, Figure 8 In the illustrated configuration, the precharge circuit for word line WL (i.e., transistor TN11 and the wiring for the transmission clamp voltage VCLAMP1) is located near the sense amplifier circuit SAC. In contrast, in the first embodiment, the precharge circuit (i.e., transistor TN1 and the wiring for the transmission voltage VLCAMP) is connected to the bit line BL, eliminating the need for such a location near the sense amplifier circuit SAC. Sense amplifier circuit SAC and its vicinity contain wiring with frequently fluctuating potentials. Therefore, placing a precharge circuit near the sense amplifier circuit SCA can easily affect the precharge circuit. In the first embodiment, transistor TN1 can be located away from the sense amplifier circuit, thus mitigating this effect.

[0103] 1.4. Modifications

[0104] The current mirror circuit CM may also be formed of an n-type MOSFET. Figure 9 This example shows the components of the readout circuit of the memory device according to the modification of the first embodiment and an example of the connection of the components. Figure 9 As shown, the current mirror circuit CM of the memory device 1 of the modified example includes transistors TN3 and TN4 in place of transistors TP1 and TP2, respectively. The gate of transistor TN3 is connected to the drain of transistor TN3. In one example, when transistors TN3 and TN4 receive a terminal voltage of the same magnitude and a voltage of the same magnitude at their gates, substantially the same drain current flows. In one example, transistor TN4 has substantially the same characteristics as transistor TN3. Examples of characteristics include transistor gate width and transistor gate length. The use of transistors TN3 and TN4 also provides the same advantages as the use of transistors TP1 and TP2.

[0105] Transistor TP1 and transistor TP2 may also have characteristics such that different drain currents flow when their gates receive a certain terminal voltage of the same magnitude and a certain voltage of the same magnitude. In one example, transistor TP2 flows a drain current greater than the drain current of transistor TP1 when its gate receives a certain terminal voltage of the same magnitude and a certain voltage of the same magnitude. In one example, transistor TP2 has a gate width greater than the gate width of transistor TP1, or (and) has a gate length smaller than the gate length of transistor TP1. In one example, transistor TP2 has a gate width that is n times the gate width of transistor TP1, or (and) has a gate length that is n times the gate length of transistor TP1. n is a number greater than 1. As a result, the charging of wiring DL is advanced, and a larger signal difference SGV can be obtained. When the current mirror circuit CM is composed of transistors TN3 and TN4, transistors TN3 and TN4 may also have the same relationship as that of transistors TP1 and TP2.

[0106] The memory cell MC may include any variable resistance element instead of the MTJ element MTJ. A variable resistance element, like the MTJ element MTJ, is an element that can dynamically switch between two resistance states. Like the MTJ element MTJ, a variable resistance element switches between two resistance states based on the current flowing through the variable resistance element and / or the voltage applied to the variable resistance element.

[0107] While several embodiments of the present invention have been described, these embodiments are presented merely as examples and are not intended to limit the scope of the invention. The novel embodiments described herein may be implemented in a variety of other ways; furthermore, the embodiments described herein may be omitted, replaced, or modified in various ways without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are encompassed by the invention as set forth in the claims and their equivalents.

Claims

1. A storage device comprising: A storage unit having a first end and a second end; a first wiring connected to the first end; a second wiring connected to the second end; a first switch connected between the second wiring and a third wiring receiving the first voltage; a current mirror circuit having a third terminal and a fourth terminal, wherein the third terminal is connected to the first wiring, and the fourth terminal outputs an output current using the first current flowing in the first wiring as a reference current; as well as The sensing amplifier circuit is connected to the fourth terminal.

2. The storage device according to claim 1, The current mirror circuit further comprises: a fifth terminal connectable to a first node receiving a second voltage higher than the first voltage; and The sixth terminal is connectable to the second node receiving the second voltage.

3. The storage device according to claim 2, further comprising: a second switch connected between the first node and the fifth terminal; and The third switch is connected between the second node and the sixth end.

4. The storage device according to claim 3, The second switch and the third switch are turned on at different timings.

5. The storage device according to claim 4, further comprising: a fourth switch connected between the first wiring and a third node receiving a third voltage, wherein the third voltage has a level between the first voltage and the second voltage; and The fifth switch is connected between the second wiring and a fourth node receiving the third voltage.

6. The storage device according to claim 5, The fourth switch and the fifth switch are turned on. The fifth switch is turned off, and the first switch is turned off after being turned on. After the first switch is turned off, the fourth switch is turned off and the second switch is turned on. After the second switch is turned on, the third switch is turned on.

7. The storage device according to claim 6, While the second switch is on, the third switch is kept off until it is turned on.

8. The storage device according to claim 1, The current mirror circuit outputs the output current having a magnitude different from that of the first current.

9. The storage device according to claim 1, The memory cell includes a variable resistance material, The variable resistance material includes a 7th end and an 8th end. When a positive 4th voltage is received from the 7th end toward the 8th end, a 1st resistance is provided between the 7th end and the 8th end. When a positive 5th voltage lower than the 4th voltage is received from the 7th end toward the 8th end, a 2nd resistance lower than the 1st resistance is provided between the 7th end and the 8th end. When a positive 6th voltage is received from the 8th end toward the 7th end, a 3rd resistance is provided between the 7th end and the 8th end. When a positive 7th voltage lower than the 6th voltage is received from the 8th end toward the 7th end, a 4th resistance lower than the 3rd resistance is provided between the 7th end and the 8th end.

10. The storage device according to claim 9, wherein the storage unit further comprises: 1st ferromagnetic layer; a second ferromagnetic layer; as well as an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.

11. The storage device according to claim 2, The current mirror circuit includes a first p-type transistor and a second p-type transistor, The first p-type transistor is connected between the fifth terminal and the third terminal, and includes a first gate connected to the third terminal. The second p-type transistor is connected between the sixth terminal and the fourth terminal, and includes a second gate connected to the first gate.

12. The storage device according to claim 11, The second p-type transistor has a gate length or gate width different from that of the first p-type transistor.

13. The storage device according to claim 11, The memory cell includes a variable resistance material, The variable resistance material includes a 7th end and an 8th end. When a positive 4th voltage is received from the 7th end toward the 8th end, a 1st resistance is provided between the 7th end and the 8th end. When a positive 5th voltage lower than the 4th voltage is received from the 7th end toward the 8th end, a 2nd resistance lower than the 1st resistance is provided between the 7th end and the 8th end. When a positive 6th voltage is received from the 8th end toward the 7th end, a 3rd resistance is provided between the 7th end and the 8th end. When a positive 7th voltage lower than the 6th voltage is received from the 8th end toward the 7th end, a 4th resistance lower than the 3rd resistance is provided between the 7th end and the 8th end.

14. The storage device according to claim 13, The storage unit further includes: 1st ferromagnetic layer; a second ferromagnetic layer; as well as an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.

15. The storage device according to claim 2, The current mirror circuit includes a first n-type transistor and a second n-type transistor, The first n-type transistor is connected between the fifth terminal and the third terminal, and includes a first gate connected to the third terminal. The second n-type transistor is connected between the sixth terminal and the fourth terminal, and includes a second gate connected to the first gate.

16. The storage device according to claim 15, The second n-type transistor has a gate length or gate width different from that of the first n-type transistor.

17. The storage device according to claim 15, The memory cell includes a variable resistance material, The variable resistance material includes a 7th end and an 8th end. When a positive 4th voltage is received from the 7th end toward the 8th end, a 1st resistance is provided between the 7th end and the 8th end. When a positive 5th voltage lower than the 4th voltage is received from the 7th end toward the 8th end, a 2nd resistance lower than the 1st resistance is provided between the 7th end and the 8th end. When a positive 6th voltage is received from the 8th end toward the 7th end, a 3rd resistance is provided between the 7th end and the 8th end. When a positive 7th voltage lower than the 6th voltage is received from the 8th end toward the 7th end, a 4th resistance lower than the 3rd resistance is provided between the 7th end and the 8th end.

18. The storage device according to claim 17, The storage unit further includes: 1st ferromagnetic layer; a second ferromagnetic layer; as well as an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.

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