Magnetic memory device

Abstract

A magnetic memory device includes: a substrate; and a memory cell array on the substrate, the memory cell array including memory unit cells and one-time programmable (OTP) unit cells. The memory unit cell includes: a first magnetic tunnel junction element on the substrate; and a wiring structure connecting the substrate and the first magnetic tunnel junction element. The OTP unit cell includes: a connection wiring on the substrate; a second magnetic tunnel junction element and a third magnetic tunnel junction element spaced apart from each other on the connection wiring; a first lower wiring structure and a second lower wiring structure connecting the substrate and the connection wiring, the first lower wiring structure and the second lower wiring structure being spaced apart from each other; and a first upper wiring structure connecting the connection wiring and the second magnetic tunnel junction element.

Description

[0001] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2024-0040418 filed on March 25, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0055509 filed on April 25, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to magnetic memory devices. Background Art

[0003] With the high speed and low power requirements of electronic devices, memory devices embedded in these devices require fast read / write operations and low operating voltages. Magnetic memory devices have been studied as memory devices that meet these requirements. Magnetic memory devices are nonvolatile and capable of high-speed operation, and therefore have attracted attention as next-generation memory.

[0004] As magnetic memory devices become increasingly highly integrated, research is underway into spin transfer torque (STT) magnetic random access memory (MRAM) for storing information using the spin transfer torque (STT) phenomenon. STT-MRAM stores information by applying a direct current to a magnetic tunnel junction element to induce magnetization reversal. Highly integrated STT-MRAM requires high-speed operation and low current operation.

[0005] Meanwhile, one-time programmable (OTP) memory is a non-volatile memory that permanently maintains data in a single program. OTP is typically designed to record specific information only once and be read continuously, and is widely used in applications where data stability and security are important. Because OTP can only be programmed once, its information cannot be altered, ensuring data integrity and stability. OTP is primarily used in applications requiring reliability and security. For example, OTP is used to store information such as digital security tokens, smart cards, keys and passwords, boot codes, and production / manufacturing settings, and can be embedded as part of a semiconductor chip or provided as a standalone chip. When embedded as part of the chip and fully compatible with logic complementary metal oxide semiconductor (CMOS) processes, OTP can be implemented and used effectively at low cost without affecting the performance of the core logic. Summary of the Invention

[0006] An object of the present disclosure is to provide a magnetic memory device that improves product reliability.

[0007] The objects of the present disclosure are not limited to those mentioned above, and additional objects of the present disclosure that are not mentioned herein will be clearly understood by those skilled in the art from the following description of the present disclosure.

[0008] According to an exemplary embodiment of the present disclosure, a magnetic memory device includes a substrate; and a memory cell array comprising memory unit cells and one-time programmable (OTP) unit cells and located on the substrate. The memory unit cells include a first magnetic tunnel junction element located on the substrate; and a wiring structure connecting the substrate to the first magnetic tunnel junction element. The OTP unit cells include a connection wiring located on the substrate; a second magnetic tunnel junction element and a third magnetic tunnel junction element spaced apart from each other on the connection wiring; a first lower wiring structure and a second lower wiring structure connecting the substrate to the connection wiring and spaced apart from each other; and a first upper wiring structure connecting the connection wiring to the second magnetic tunnel junction element.

[0009] According to an example embodiment of the present disclosure, a magnetic memory device includes: a memory unit cell including a first magnetic tunnel junction element connected to a first bit line; and a first cell transistor connecting the first magnetic tunnel junction element to a first source line; and a one-time programmable (OTP) unit cell including second to fourth magnetic tunnel junction elements connected to a second bit line; and second to fourth cell transistors connecting the second source line to the second magnetic tunnel junction element. The third and fourth magnetic tunnel junction elements are not connected to the second to fourth cell transistors.

[0010] According to an example embodiment of the present disclosure, a magnetic memory device includes: a plurality of memory unit cells connected between a first bit line and a first source line; a plurality of one-time programmable (OTP) unit cells connected between a second bit line and a second source line; and a peripheral circuit connected to the plurality of memory unit cells and the plurality of OTP unit cells. Each of the plurality of memory unit cells includes: a first magnetic tunnel junction element connected to the first bit line; and a first cell transistor connecting the first magnetic tunnel junction element to the first source line. Each of the plurality of OTP unit cells includes: second to fourth magnetic tunnel junction elements connected to the second bit line; and second to fourth cell transistors connecting the second source line to the second magnetic tunnel junction element. The third and fourth magnetic tunnel junction elements are not connected to the second to fourth cell transistors.

[0011] According to an exemplary embodiment of the present disclosure, a magnetic memory device includes a substrate and a memory cell array on the substrate, the memory cell array including a memory unit cell and a one-time programmable (OTP) unit cell. The memory unit cell includes a first transistor on the substrate, a first magnetic tunnel junction element on the first transistor, and a wiring structure connecting the first magnetic tunnel junction element to the first transistor. The OTP cell includes a second transistor on the substrate, a second magnetic tunnel junction element on the second transistor, a third transistor on the substrate, a third magnetic tunnel junction element on the third transistor, and a first wiring structure connecting the second magnetic tunnel junction element to the second and third transistors. One of the magnetic patterns of the third magnetic tunnel junction element, facing the substrate, is electrically floating. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0013] Figure 1 is an exemplary block diagram of a magnetic memory device according to some embodiments.

[0014] Figure 2 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments.

[0015] Figure 3 and Figure 4 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments.

[0016] Figure 5 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments.

[0017] Figure 6 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments.

[0018] Figure 7 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments.

[0019] Figure 8 yes Figure 3 Magnified view of area S1.

[0020] Figure 9 yes Figures 4 to 7 Magnified view of area S2.

[0021] Figure 10 yes Figure 3 Magnified view of area S3.

[0022] Figure 11 yes Figures 4 to 7 Magnified view of area S4.

[0023] Figure 12 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments.

[0024] Figure 13 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments.

[0025] Figure 14 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments.

[0026] Figure 15 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments. DETAILED DESCRIPTION

[0027] Figure 1 is an exemplary block diagram of a magnetic memory device according to some embodiments.

[0028] Reference Figure 1 , a magnetic memory device according to some embodiments may include a memory cell array 10 , a row decoder 20 , a column decoder 30 , a write driver 40 , a sensing circuit 50 , a source line driver 60 , an input / output circuit 70 , and control logic 80 .

[0029] The memory cell array 10 may include a plurality of word lines WL, WL_O_1, WL_O_2, WL_O_3, a plurality of bit lines BL, and a plurality of source lines SL. Figure 2 Memory unit cells MC and OTP unit cells (OTPC) can be connected to intersections of word lines WL, WL_O_1, WL_O_2, and WL_O_3 with bit lines BL. Each memory cell can be configured to store data. The memory cell may include, for example, a variable resistance element (e.g., a magnetic tunnel junction (MTJ) element), where the value of stored data is determined by its resistance.

[0030] For example, the memory cell may include resistive RAM (ReRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), and may also include magnetic random access memory (MRAM) such as spin transfer torque magnetic random access memory (STT-MRAM), spin torque transfer magnetization switching RAM (Spin-RAM), and spin momentum transfer RAM (SMT-RAM).

[0031] The row decoder 20 may select (or drive) word lines WL, WL_O_1, WL_O_2, and WL_O_3 connected to memory cells performing a read operation or a program operation based on a row address RA and a row control signal R_CTRL. The row decoder 20 may provide a driving voltage received from the control logic 80 to the selected word line.

[0032] The column decoder 30 may select a bit line BL and / or a source line SL connected to a memory cell performing a read operation or a program operation based on a column address CA and a column control signal C_CTRL. The column decoder 30 may connect the selected bit line BL and the selected source line SL to the data line DL.

[0033] During a program operation, the write driver 40 may drive a program voltage (or a write current) for storing write data in a memory cell selected by the row decoder 20 and the column decoder 30. For example, during a program operation, the write driver 40 may control a voltage of the data line DL based on write data I / O DATA input from the input / output circuit 70 through the write input / output line WIO to store the write data I / O DATA in the selected memory cell.

[0034] During a read operation, the sensing circuit 50 can determine the value of the data stored in the memory cell by sensing the signal output via the data line DL. The sensing circuit 50 can be connected to the column decoder 30 via the data line DL and can be connected to the input / output circuit 70 via the read input / output line RIO. The sensing circuit 50 can input the sensed read data I / O DATA to the input / output circuit 70 via the read input / output line RIO.

[0035] The source line driver 60 may drive the source lines SL at a specific voltage level under the control of the control logic 80. For example, the source line driver 60 may receive a voltage for driving the source lines SL from the control logic 80.

[0036] The input / output circuit 70 may transfer write data I / O DATA input from the outside to the write driver 40 and output read data I / O DATA input from the sensing circuit 50 to the outside.

[0037] The control logic 80 can control the overall operation of the magnetic memory device. For example, the control logic 80 can control the row decoder 20, the column decoder 30, the write driver 40, the sensing circuit 50, the source line driver 60, the input / output circuit 70, etc. At the same time, the control logic 80 can operate in response to a command CMD or control signal input from the outside. The command CMD can include a read command, a write command, etc.

[0038] Figure 2 is an exemplary circuit diagram illustrating a magnetic memory device according to some embodiments.

[0039] Reference Figure 2 In some embodiments, the memory cell array 10 includes a plurality of memory cells arranged along row and column directions. The plurality of memory cells includes a plurality of memory unit cells MC and a plurality of OTP unit cells OTPC.

[0040] A plurality of memory unit cells MC may be connected to a first word line WL, a bit line BL, and a source line SL. Each memory unit cell MC may include a first magnetic tunnel junction element MTJ1 and first cell transistors CT11 and CT12.

[0041] The memory unit cell MC can be programmed multiple times. The memory unit cell MC can be switched to two resistance states by an electric pulse applied to the first magnetic tunnel junction element MTJ1. The memory unit cell MC can be used as an MRAM.

[0042] In some embodiments, the memory unit cell MC may have a structure in which the first cell transistors CT11 and CT12 are connected to one magnetic tunnel junction element MTJ1. For example, the memory unit cell MC may include two first cell transistors CT11 and CT12. The number of cell transistors included in the memory unit cell MC is not limited thereto and may vary.

[0043] One end of the first magnetic tunnel junction element MTJ1 is connected to the bit line BL, and the other end of the first magnetic tunnel junction element MTJ1 is connected to one end of the (1-1)th cell transistor CT11 and one end of the (1-2)th cell transistor CT12. The other end of the (1-1)th cell transistor CT11 and the other end of the (1-2)th cell transistor CT12 are connected to the source line SL. The gate electrode of the (1-1)th cell transistor CT11 and the gate electrode of the (1-2)th cell transistor CT12 may be connected to the first word line WL. The (1-1)th cell transistor CT11 and the (1-2)th cell transistor CT12 may be turned on or off by a signal (or voltage) provided via the first word line WL.

[0044] A plurality of OTP unit cells OTPC may be connected to second to fourth word lines WL_O_1, WL_O_2, and WL_O_3, a bit line BL, and a source line SL. Each of the OTP unit cells OTPC may include a second magnetic tunnel junction element MTJ2, second cell transistors CT21 and CT22, a third magnetic tunnel junction element MTJ3, third cell transistors CT31 and CT32, a fourth magnetic tunnel junction element MTJ4, and fourth cell transistors CT41 and CT42.

[0045] The OTP unit cell OTPC can be programmed only once. The programmed second magnetic tunnel junction element MTJ2 may have an irreversible resistance state. The OTP unit cell OTPC may be used as an OTP.

[0046] The OTP unit cell OTPC according to some embodiments may have a structure in which a plurality of cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 are connected to one magnetic tunnel junction element MTJ2. For example, the OTP unit cell OTPC may include six cell transistors CT21, CT22, CT31, CT32, CT41, and CT42. The second cell transistors CT21 and CT22, the third cell transistors CT31 and CT32, and the fourth cell transistors CT41 and CT42 may be connected in parallel. The number of cell transistors included in the OTP unit cell OTPC is not limited thereto and may vary.

[0047] One end of the second magnetic tunnel junction element MTJ2 is connected to the bit line BL, and the other end of the second magnetic tunnel junction element MTJ2 is connected to one end of the (2-1)th cell transistor CT21 and one end of the (2-2)th cell transistor CT22. The other end of the (2-1)th cell transistor CT21 and the other end of the (2-2)th cell transistor CT22 are connected to the source line SL. The gate electrode of the (2-1)th cell transistor CT21 and the gate electrode of the (2-2)th cell transistor CT22 may be connected to the second word line WL_O_1. The (2-1)th cell transistor CT21 and the (2-2)th cell transistor CT22 may be turned on or off by a signal (or voltage) provided via the second word line WL_O_1.

[0048] One end of the third magnetic tunnel junction element MTJ3 is connected to the bit line BL. The other end of the third magnetic tunnel junction element MTJ3 is not connected to one end of the (3-1)th cell transistor CT31 and one end of the (3-2)th cell transistor CT32, and the third magnetic tunnel junction element MTJ3 is electrically isolated from the third cell transistors CT31 and CT32. One end of the (3-1)th cell transistor CT31 and one end of the (3-2)th cell transistor CT32 are connected to the other end of the second magnetic tunnel junction element MTJ2. The other end of the (3-1)th cell transistor CT31 and the other end of the (3-2)th cell transistor CT32 are connected to the source line SL. The gate electrode of the (3-1)th cell transistor CT31 and the gate electrode of the (3-2)th cell transistor CT32 can be connected to the third word line WL_O_2. The (3-1)th cell transistor CT31 and the (3-2)th cell transistor CT32 can be turned on or off by a signal (or voltage) provided via the third word line WL_O_2.

[0049] One end of the fourth magnetic tunnel junction element MTJ4 is connected to the bit line BL, and the other end of the fourth magnetic tunnel junction element MTJ4 is not connected to one end of the (4-1)th cell transistor CT41 and one end of the (4-2)th cell transistor CT42. The fourth magnetic tunnel junction element MTJ4 is electrically isolated from the fourth cell transistors CT41 and CT42. One end of the (4-1)th cell transistor CT41 and one end of the (4-2)th cell transistor CT42 are connected to the other end of the second magnetic tunnel junction element MTJ2. The other end of the (4-1)th cell transistor CT41 and the other end of the (4-2)th cell transistor CT42 are connected to the source line SL. The gate electrode of the (4-1)th cell transistor CT41 and the gate electrode of the (4-2)th cell transistor CT42 can be connected to the fourth word line WL_O_3. The (4-1)th cell transistor CT41 and the (4-2)th cell transistor CT42 can be turned on or off by a signal (or voltage) provided via the fourth word line WL_O_3.

[0050] The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be dummy magnetic tunnel junction elements.The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be unused magnetic tunnel junction elements.

[0051] The second magnetic tunnel junction element MTJ2 and the pair of second cell transistors CT21 and CT22, the third magnetic tunnel junction element MTJ3 and the pair of third cell transistors CT31 and CT32, and the fourth magnetic tunnel junction element MTJ4 and the pair of fourth cell transistors CT41 and CT42 of the OTP unit cell OTPC may be respectively arranged in the memory cell array 10 to have the same repetition periodicity as the first magnetic tunnel junction element MTJ1 and the pair of first cell transistors CT11 and CT12 of the memory unit cell MC.

[0052] Each of the first to fourth cell transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42 may include, for example, at least one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an N-channel metal oxide semiconductor (NMOS) field effect transistor, and a P-channel metal oxide semiconductor (PMOS) field effect transistor.

[0053] In some embodiments, the memory cell array 10 may include a first region R1 used as an MRAM and a second region R2 used as an OTP. A plurality of memory unit cells MC are provided in the first region R1, and a plurality of OTP unit cells OTPC are provided in the second region R2.

[0054] In some embodiments, memory unit cells MC constituting one row and memory unit cells MC constituting another row may share one source line SL. OTP unit cells OTPC constituting one row and OTP unit cells OTPC constituting another row may share one source line SL.

[0055] In some embodiments, the read path and write path of the OTP unit cell OTPC may be separated from each other. During a read operation of the OTP unit cell OTPC, a portion of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 of the OTP unit cell OTPC may be used, and during a write operation of the OTP unit cell OTPC, another portion of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 of the OTP unit cell OTPC may be used. In some embodiments, at least one of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 may be turned on during a read operation of the OTP unit cell OTPC.

[0056] For example, the second cell transistors CT21 and CT22 connected to the second word line WL_O_1 may be used during a read operation of the OTP unit cell OTPC, and the third cell transistors CT31 and CT32 connected to the third word line WL_O_2 and the fourth cell transistors CT41 and CT42 connected to the fourth word line WL_O_3 may be used during a write operation of the OTP unit cell OTPC.

[0057] For example, the third word line WL_O_2 may be connected to the fourth word line WL_O_3. The third word line WL_O_2 and the fourth word line WL_O_3 may be the same word line. The gates of the third cell transistors CT31 and CT32 and the gates of the fourth cell transistors CT41 and CT42 may be operated by the same word line voltage and may be operated by a word line voltage different from that of the gates of the second cell transistors CT21 and CT22.

[0058] Alternatively, the second to fourth word lines WL_O_1, WL_O_2, and WL_O_3 may be different word lines. The gates of the second cell transistors CT21 and CT22, the gates of the third cell transistors CT31 and CT32, and the gates of the fourth cell transistors CT41 and CT42 may be operated by different word line voltages.

[0059] In some embodiments, the read path and the write path of the OTP unit cell OTPC may not be separated from each other. The second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 of the OTP unit cell OTPC may be used during both the read and write operations of the OTP unit cell OTPC.

[0060] The memory cell array 10 may be electrically connected to peripheral circuits. The peripheral circuits may include, for example, Figure 1 The memory unit cell MC and the OTP unit cell OTPC may be electrically connected to a peripheral circuit. In other words, the memory unit cell MC and the OTP unit cell OTPC may share a peripheral circuit.

[0061] In some embodiments, the OTP unit cell OTPC may be connected to specific word lines (eg, second to fourth word lines WL_O_1 , WL_O_2 , and WL_O_3 ).

[0062] A first word line WL and a memory unit cell MC connected to the first word line WL may be provided in a first region R1, and an OTP unit cell OTPC connected to a second word line WL_O_1 and a third word line WL_O_2 may be provided in a second region R2. Only the memory unit cell MC may be connected to the first word line WL, and only the OTP unit cell OTPC may be connected to the second to fourth word lines WL_O_1, WL_O_2, and WL_O_3. The memory unit cell MC and the OTP unit cell OTPC may be connected to one bit line BL.

[0063] The arrangement of the first region R1 and the second region R2 in the memory cell array 10 may vary. For example, the second region R2 may be provided at an edge portion of the memory cell array 10. The OTP unit cells OTPC may be connected to the second to fourth word lines WL_O_1, WL_O_2, and WL_O_3 provided at the edge portion of the memory cell array 10.

[0064] Since the OTP unit cell OTPC is connected to specific word lines (eg, second to fourth word lines WL_O_1 , WL_O_2 , and WL_O_3 ), an error correction code ECC may be performed on the OTP unit cell OTPC as well as the memory unit cell MC.

[0065] In addition, the voltage applied to the second to fourth word lines WL_O_1, WL_O_2 and WL_O_3 can be increased during the write operation of the OTP unit cell OTPC, whereby the resistance of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41 and CT42 of the OTP unit cell OTPC can be reduced without stress of the memory unit cell MC.

[0066] Figure 3 and Figure 4 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments.

[0067] Figure 3 Includes connection to Figure 2 An exemplary cross-sectional view of a portion of three memory unit cells MC of one bit line in FIG. Figure 4 Includes connection to Figure 2 An exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG. Figure 3 and Figure 4 Omitted Figure 2 source line.

[0068] Reference Figures 2 to 4 According to some embodiments, the magnetic memory device may include a substrate 100, first to fourth cell transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, CT42, an insulating film 200, a wiring structure 210, first to third lower wiring structures 220l, 230l and 240l, first to third upper wiring structures 220u, 230u and 240u, first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3 and MTJ4, first to fourth upper electrodes TE1, TE2, TE3 and TE4, and a first bit line BL1 and a second bit line BL2. Figure 2 The bit lines BL may include a first bit line BL1 connected to the memory unit cell MC and a second bit line BL2 connected to the OTP unit cell OTPC.

[0069] Each memory unit cell MC may include first cell transistors CT11 and CT12 , a wiring structure 210 , a first magnetic tunnel junction element MTJ1 , and a first upper electrode TE1 .

[0070] Each OTP unit cell OTPC may include second to fourth unit transistors CT21, CT22, CT31, CT32, CT41 and CT42, a connecting wiring 110, a first lower wiring structure to a third lower wiring structure 220l, 230l and 240l, a first upper wiring structure to a third upper wiring structure 220u, 230u and 240u, a second magnetic tunnel junction element to a fourth magnetic tunnel junction element MTJ2, MTJ3 and MTJ4, and a second upper electrode to a fourth upper electrode TE2, TE3 and TE4.

[0071] The substrate 100 may be, for example, a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a display glass substrate, or may be a semiconductor-on-insulator (SOI) substrate, but is not limited thereto.

[0072] The first to fourth cell transistors CT11, CT12, CT21, CT22, CT31, CT32, CT41, and CT42 may be formed on a substrate 100. A first impurity region 102a may be formed on the substrate 100 at both sides of the first cell transistors CT11 and CT12. The first impurity region 102a may be provided as a source region or a drain region of the first cell transistors CT11 and CT12. A second impurity region 102b may be formed on the substrate 100 at both sides of each of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42. The second impurity region 102b may be provided as a source region or a drain region of each of the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42. The first impurity region 102a and the second impurity region 102b may each include an N-type impurity or a P-type impurity.

[0073] In some embodiments, the first to fourth cell transistors CT11 , CT12 , CT21 , CT22 , CT31 , CT32 , CT41 , and CT42 may have the same threshold voltage.

[0074] An insulating film 200 may be formed on the substrate 100. The insulating film 200 may cover the first cell transistors CT11 and CT12. The connection wiring 110, the first to third lower wiring structures 220l, 230l, and 240l, the first to third upper wiring structures 220u, 230u, and 240u, the first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4, and the first to fourth upper electrodes TE1, TE2, TE3, and TE4 may be formed in the insulating film 200. The insulating film 200 may include, for example, silicon oxide or silicon oxynitride. The insulating film 200 may have a multilayer structure.

[0075] First to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 may be formed on substrate 100. First to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 may be formed at the same height from substrate 100.

[0076] The wiring structure 210 , first to third lower wiring structures 220 l , 230 l , and 240 l , and first to third upper wiring structures 220 u , 230 u , and 240 u may be formed on the substrate 100 .

[0077] The wiring structure 210 may connect the substrate 100 to the first magnetic tunnel junction element MTJ1. The wiring structure 210 may include a (1-1)th via 112a, a (1-1)th wiring 114a, a (2-1)th via 122a, a (2-1)th wiring 124a, a (3-1)th via 132a, a (3-1)th wiring 134a, a (4-1)th via 142a, a first landing pad (also referred to as a landing pad) LP1, and a first lower electrode BE1, which are sequentially stacked on the substrate 100. The (1-1)th via 112a may be connected to the first impurity region 102a. The (2-1)th via 122a may connect the (1-1)th wiring 114a to the (2-1)th wiring 124a. The (3-1)th via 132a may connect the (2-1)th wiring 124a to the (3-1)th wiring 134a. The (4-1)th via 142a may connect the (3-1)th wiring 134a to the first bonding pad LP1. The first lower electrode BE1 may connect the first bonding pad LP1 to the first magnetic tunnel junction element MTJ1.

[0078] A first upper electrode TE1 may be formed on the first magnetic tunnel junction element MTJ1. The first upper electrode TE1 may be connected to the first magnetic tunnel junction element MTJ1. A first bit line BL1 may be formed on the first upper electrode TE1. The first bit line BL1 may be connected to the first upper electrode TE1. The first magnetic tunnel junction element MTJ1 may be electrically connected to the first cell transistors CT11 and CT12 via the wiring structure 210, and may be electrically connected to the first bit line BL1 via the first upper electrode TE1.

[0079] The connection wiring 110 may be provided on the substrate 100. In some embodiments, the connection wiring 110 may be provided at the lowest metal height among the wirings. The connection wiring 110 may be the wiring closest to the substrate 100. The second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 may be electrically connected to each other through the connection wiring 110 having the metal height closest to the substrate 100. The connection wiring 110 may be formed at the same height as the height of the (1-1)th wiring 114a from the substrate 100. That is, the wirings provided at the same metal height as the metal height of the (1-1)th wiring 114a may be directly connected to each other below the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4.

[0080] The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be separated from the connection wiring 110 at a metal height higher than the metal height of the connection wiring 110. In some embodiments, vias having the same metal height as that of vias in direct contact with the connection wiring 110 may be omitted between the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110. For example, vias having the same metal height as that of the (2-2)th via 122 b may be omitted between the third magnetic tunnel junction element MTJ3 and the connection wiring 110 and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110.

[0081] Providing a metal height of the connection wiring 110 and omitting a metal height of vias (or wirings) between the third magnetic tunnel junction element MTJ3 and the connection wiring 110 and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110 may vary according to the design of the magnetic memory device.

[0082] The first to third lower wiring structures 2201 , 2301 , and 2401 may be spaced apart from each other in a horizontal direction. Each of the first to third lower wiring structures 2201 , 2301 , and 2401 may connect the substrate 100 with the connection wiring 110 .

[0083] The first lower wiring structure 220l may include a (1-2)th via 112b. The second lower wiring structure 230l may include a (1-3)th via 112c. The third lower wiring structure 240l may include a (1-4)th via 112d. Each of the (1-2)th to (1-4)th vias 112b, 112c, and 112d may connect the second impurity region 102b to the connection wiring 110. The (1-1)th to (1-4)th vias 112a, 112b, 112c, and 112d may be formed at the same height from the substrate 100.

[0084] The first to third upper wiring structures 220u, 230u, and 240u may be formed on the connection wiring 110. The first to third upper wiring structures 220u, 230u, and 240u may be spaced apart from each other in the horizontal direction. The first to third upper wiring structures 220u, 230u, and 240u may be connected to the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4, respectively.

[0085] The first upper wiring structure 220u may be provided between the connection wiring 110 and the second magnetic tunnel junction element MTJ2. The first upper wiring structure 220u may connect the connection wiring 110 to the second magnetic tunnel junction element MTJ2. The first upper wiring structure 220u may include a (2-2)th via 122b, a (2-2)th wiring 124b, a (3-2)th via 132b, a (3-2)th wiring 134b, a (4-2)th via 142b, a second bonding pad LP2, and a second lower electrode BE2. The (2-2)th via 122b may connect the connection wiring 110 to the (2-2)th wiring 124b. The (3-2)th via 132b may connect the (2-2)th wiring 124b to the (3-2)th wiring 134b. The (4-2)th via 142b may connect the (3-2)th wiring 134b to the second bonding pad LP2. The second lower electrode BE2 may connect the second bonding pad LP2 with the second magnetic tunnel junction element MTJ2 .

[0086] The second upper wiring structure 230u may be disposed between the connection wiring 110 and the third magnetic tunnel junction element MTJ3. The second upper wiring structure 230u may be spaced apart from the connection wiring 110 and may be connected to the third magnetic tunnel junction element MTJ3. The second upper wiring structure 230u may include a (2-3)th wiring 124c, a (3-3)th via 132c, a (3-3)th wiring 134c, a (4-3)th via 142c, a third bonding pad LP3, and a third lower electrode BE3 sequentially stacked on the connection wiring 110. The (2-3)th wiring 124c may be spaced apart from the connection wiring 110. The (2-3)th wiring 124c may not be in direct contact with the connection wiring 110. The (3-3)th via 132c may connect the (2-3)th wiring 124c to the (3-3)th wiring 134c. The (4-3)th via hole 142c may connect the (3-3)th wiring 134c to the third bonding pad LP3. The third lower electrode BE3 may connect the third bonding pad LP3 to the third magnetic tunnel junction element MTJ3.

[0087] The third upper wiring structure 240u may be disposed between the connection wiring 110 and the fourth magnetic tunnel junction element MTJ4. The third upper wiring structure 240u may be spaced apart from the connection wiring 110 and may be connected to the fourth magnetic tunnel junction element MTJ4. The third upper wiring structure 240u may include a (2-4)th wiring 124d, a (3-4)th via 132d, a (3-4)th wiring 134d, a (4-4)th via 142d, a fourth bonding pad LP4, and a fourth lower electrode BE4 sequentially stacked on the connection wiring 110. The (2-4)th wiring 124d may be spaced apart from the connection wiring 110. The (2-4)th wiring 124d may not be in direct contact with the connection wiring 110. The (3-4)th via 132d may connect the (2-4)th wiring 124d to the (3-4)th wiring 134d. The (4-4)th via hole 142d may connect the (3-4)th wiring 134d to the fourth bonding pad LP4. The fourth lower electrode BE4 may connect the fourth bonding pad LP4 to the fourth magnetic tunnel junction element MTJ4.

[0088] The (2-1)th via hole 122a and the (2-2)th via hole 122b may be formed at the same height from the substrate 100. The (2-1)th wiring to the (2-4)th wiring 124a, 124b, 124c, and 124d may be formed at the same height from the substrate 100. The (3-1)th via hole to the (3-4)th via hole 132a, 132b, 132c, and 132d may be formed at the same height from the substrate 100. The (3-1)th wiring to the (3-4)th wiring 134a, 134b, 134c, and 134d may be formed at the same height from the substrate 100. The (4-1)th to the (4-4)th via holes 142a, 142b, 142c, and 142d may be formed at the same height from the substrate 100. The first to fourth bonding pads LP1, LP2, LP3, and LP4 may be formed at the same height from the substrate 100. The first to fourth lower electrodes BE1, BE2, BE3, and BE4 may be formed at the same height from the substrate 100.

[0089] The second to fourth upper electrodes TE2, TE3, and TE4 may be formed on the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4, respectively. The second to fourth upper electrodes TE2, TE3, and TE4 may be connected to the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4, respectively. The first to fourth upper electrodes TE1, TE2, TE3, and TE4 may be formed at the same height from the substrate 100.

[0090] The second bit line BL2 may be formed on the second to fourth upper electrodes TE2, TE3, and TE4. The second bit line BL2 may be connected to the second to fourth upper electrodes TE2, TE3, and TE4. The first and second bit lines BL1 and BL2 may be formed at the same height from the substrate 100.

[0091] The second magnetic tunnel junction element MTJ2 can be electrically connected to the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41 and CT42 through the first upper wiring structure 220u, the connection wiring 110 and the first to third lower wiring structures 220l, 230l and 240l, and can be electrically connected to the second bit line BL2 through the second upper electrode TE2.

[0092] Each of the (1-1)th to (1-4)th vias 112a, 112b, 112c, and 112d, the (2-1)th via 122a, the (2-2)th via 122b, the (2-1)th wiring to the (2-4)th wiring 124a, 124b, 124c, and 124d, the (3-1)th to (3-4)th vias 132a, 132b, 132c, and 132d, the (3-1)th wiring to the (3-4)th wiring 134a, 134b, 134c, and 134d, and the (4-1)th to (4-4)th vias 142a, 142b, 142c, and 142d may include a metal (e.g., copper). Each of the first to fourth bonding pads LP1, LP2, LP3, and LP4 may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and / or tantalum), a metal-semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and / or tungsten nitride). Each of the first to fourth lower electrodes BE1, BE2, BE3, and BE4 may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). Each of the first to fourth upper electrodes TE1, TE2, TE3, and TE4 may include at least one of a metal (e.g., Ta, W, Ru, Ir, etc.) and a conductive metal nitride (e.g., TiN).

[0093] In some embodiments, the second to fourth magnetic tunnel junction elements MTJ2 , MTJ3 , and MTJ4 may have the same size as that of the first magnetic tunnel junction element MTJ1 .

[0094] Each of the first to fourth magnetic tunnel junction elements MTJ1, MTJ2, MTJ3, and MTJ4 may include a first magnetic pattern PL, a tunnel barrier pattern TL, and a second magnetic pattern FL. The tunnel barrier pattern TL may be interposed between the first magnetic pattern PL and the second magnetic pattern FL.

[0095] One of the first magnetic pattern PL and the second magnetic pattern FL may be a reference layer having a fixed magnetization direction regardless of an external magnetic field, and the other of the first magnetic pattern PL and the second magnetic pattern FL may be a free layer having a variable magnetization direction between two stable magnetization directions. For example, the first magnetic pattern PL may be a reference layer having a fixed magnetization direction, and the second magnetic pattern FL may be a free layer having a variable magnetization direction. For another example, the first magnetic pattern PL may be a free layer, and the second magnetic pattern FL may be a reference layer.

[0096] In some embodiments, each of the first and second magnetic patterns PL and FL may have perpendicular magnetic anisotropy (PMA). Each of the first and second magnetic patterns PL and FL may have an easy magnetization axis in a vertical direction (a direction perpendicular to the upper surface of the substrate 100 ).

[0097] Each of the first magnetic pattern PL and the second magnetic pattern FL may include at least one of a vertical magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy), a vertical magnetic material having an L10 structure, CoPt having a hexagonal close-packed lattice structure, and a vertical magnetic structure. The vertical magnetic material having an L10 structure may include, for example, FePt with an L10 structure, FePd with an L10 structure, CoPd with an L10 structure, or CoPt with an L10 structure. The vertical magnetic structure may include magnetic layers and non-magnetic layers that are alternately and repeatedly stacked. For example, the vertical magnetic structure may include (Co / Pt) n 、(CoFe / Pt) n 、(CoFe / Pd) n 、(Co / Pd) n 、(Co / Ni) n 、(CoNi / Pt) n 、(CoCr / Pt) n or (CoCr / Pd) n (where n is the number of stacking times).

[0098] In some embodiments, each of the first and second magnetic patterns PL and FL may have in-plane magnetic anisotropy (IMA). Each of the first and second magnetic patterns PL and FL may have an easy magnetization axis in a horizontal direction (a direction parallel to the upper surface of the substrate 100 ).

[0099] Each of the first and second magnetic patterns PL and FL having in-plane magnetic anisotropy (IMA) may include a ferromagnetic material. In some embodiments, the magnetic pattern forming a reference layer of the first and second magnetic patterns PL and FL may further include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material. For example, the ferromagnetic material of the reference layer may include CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O 12 For example, the antiferromagnetic material of the reference layer may include PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeC l2 , FeO, CoC l2 , CoO, NiCl2, NiO and Cr, or at least one selected from noble metals. The noble metal may include ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), gold (Au) or silver (Ag). For example, the ferromagnetic material of the free layer may include FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO and Y3Fe5O 12 The magnetic pattern as the free layer may be composed of a plurality of layers.

[0100] The tunnel barrier pattern TL may include, for example, at least one selected from oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), and magnesium boron (MgB), or nitrides of titanium (Ti) and vanadium (V).

[0101] The first magnetic tunnel junction element MTJ1 may store data in each memory unit cell MC by using a resistance difference according to a magnetization direction of the first magnetic pattern PL and a magnetization direction of the second magnetic pattern FL.

[0102] For example, when the magnetization direction of the first magnetic pattern PL is parallel to the magnetization direction of the second magnetic pattern FL, the first magnetic tunnel junction element MTJ1 may have a low resistance value and may store data 0. Conversely, when the magnetization direction of the first magnetic pattern PL is antiparallel to the magnetization direction of the second magnetic pattern FL, the first magnetic tunnel junction element MTJ1 may have a high resistance value and may store data 1. For another example, when the magnetization direction of the first magnetic pattern PL is parallel to the magnetization direction of the second magnetic pattern FL, the first magnetic tunnel junction element MTJ1 may store data 1, and when the magnetization direction of the first magnetic pattern PL is antiparallel to the magnetization direction of the second magnetic pattern FL, the first magnetic tunnel junction element MTJ1 may store data 0.

[0103] The second magnetic tunnel junction element MTJ2 can apply a breakdown voltage to both ends of the first magnetic pattern PL and the second magnetic pattern FL through a single programming operation to insulate the tunnel barrier pattern TL between the first magnetic pattern PL and the second magnetic pattern FL and destroy the tunnel barrier pattern TL between the first magnetic pattern PL and the second magnetic pattern FL, thereby having an irreversible resistance state. The insulated and destroyed second magnetic tunnel junction element MTJ2 can be in a short-circuit state. The insulated and destroyed second magnetic tunnel junction element MTJ2 can have a low resistance value and can store data 0. The second magnetic tunnel junction element MTJ2 that is neither insulated nor destroyed can have a high resistance value and store data 1.

[0104] when Figure 3 and Figure 4 is connected to Figure 2 When the cross-sectional view of three memory cell units (MC) and one OTP cell unit (OTPC) of the same bit line is shown, Figure 3 The first bit line BL1 can be connected with Figure 4 The second bit line BL2 is the same bit line. Figure 3 and Figure 4 is connected to Figure 2 When the cross-sectional view of three memory unit cells (MC) parts and one OTP unit cell (OTPC) part of different bit lines is shown, Figure 3 The first bit line BL1 can be connected with Figure 4 The second bit line BL2 is a different bit line.

[0105] The memory cell array 10 of the magnetic memory device according to some embodiments includes memory unit cells MC used as MRAM and OTP unit cells OTPC used as OTP. That is, since the memory unit cells MC and the OTP unit cells OTPC are implemented in one memory cell array 10 without a separate OTP memory, a highly integrated magnetic memory device can be provided.

[0106] During a write operation of the OTP unit cell OTPC, a breakdown voltage is applied to the second magnetic tunnel junction element MTJ2 to insulate and destroy the tunnel barrier pattern TL of the second magnetic tunnel junction element MTJ2. During a write operation of the memory unit cell MC, the breakdown voltage has a higher value than the write voltage applied to the first magnetic tunnel junction element MTJ1. As a result, stress may be applied to the memory unit cell MC.

[0107] On the other hand, in the magnetic memory device according to some embodiments, since the OTP unit cell OTPC includes the second to fourth cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 connected in parallel, a greater voltage can be applied to both ends of the second magnetic tunnel junction element MTJ2. Therefore, even if the write voltage applied to the OTP unit cell OTPC is not significantly increased, insulation breakdown of the tunnel barrier pattern TL of the second magnetic tunnel junction element MTJ2 can occur more easily. In addition, stress in the memory unit cell MC caused by the write voltage applied to the OTP unit cell OTPC can be improved and / or reduced.

[0108] Figure 5 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments. Figure 5 Includes connection to Figure 2 An exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG. Figure 5 Omitted Figure 2 For ease of description, the source line will be briefly described or omitted. Figures 1 to 4 The description section is repeated.

[0109] Reference Figure 5 In some embodiments, the connection wiring 110 may be formed on the Figure 3 The (3-1)th wiring 134a is at the same height from the substrate 100. That is, it is set at the same height as the Figure 3 Wirings at the same metal height as the (3-1)th wiring 134 a may be directly connected to one another below the second to fourth magnetic tunnel junction elements MTJ2 , MTJ3 , and MTJ4 .

[0110] Vias having the same metal height as the (4-2)th via 142 b may be omitted between the third magnetic tunnel junction element MTJ3 and the connection wiring 110 and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110 .

[0111] The first lower wiring structure 2201 may include a (1-2)th via 112b, a (1-2)th wiring 114b, a (2-2)th via 122b, a (2-2)th wiring 124b, and a (3-2)th via 132b sequentially stacked on the substrate 100. The second lower wiring structure 2301 may include a (1-3)th via 112c, a (1-3)th wiring 114c, a (2-3)th via 122c, a (2-3)th wiring 124c, and a (3-3)th via 132c sequentially stacked on the substrate 100. The third lower wiring structure 2401 may include a (1-4)th via 112d, a (1-4)th wiring 114d, a (2-4)th via 122d, a (2-4)th wiring 124d, and a (3-4)th via 132d sequentially stacked on the substrate 100. Each of the (2-2)th to (2-4)th vias 122b, 122c, and 122d can connect each of the (1-2)th to (1-4)th wirings 114b, 114c, and 114d to each of the (2-2)th to (2-4)th wirings 124b, 124c, and 124d. Each of the (3-2)th to (3-4)th vias 132b, 132c, and 132d can connect each of the (2-2)th to (2-4)th wirings 124b, 124c, and 124d to the connection wiring 110.

[0112] The first upper wiring structure 220u may include a (4-2)th via 142b, a second bonding pad LP2, and a second lower electrode BE2 sequentially stacked on the connection wiring 110. The (4-2)th via 142b may connect the connection wiring 110 to the second bonding pad LP2. The second upper wiring structure 230u may include a third bonding pad LP3 and a third lower electrode BE3 sequentially stacked on the connection wiring 110. The third bonding pad LP3 may be spaced apart from the connection wiring 110. The third bonding pad LP3 may not be in direct contact with the connection wiring 110. The third upper wiring structure 240u may include a fourth bonding pad LP4 and a fourth lower electrode BE4 sequentially stacked on the connection wiring 110. The fourth bonding pad LP4 may be spaced apart from the connection wiring 110. The fourth bonding pad LP4 may not be in direct contact with the connection wiring 110.

[0113] Figure 6 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments. Figure 6 Includes connection to Figure 2 An exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG. Figure 6 Omitted Figure 2 For ease of description, the source line will be briefly described or omitted. Figures 1 to 5 The description section is repeated.

[0114] Reference Figure 6 In some embodiments, the connection wiring 110 may be formed between the first bonding pad ( Figure 3 LP1) is at the same height from the substrate 100. That is, it is set at the same height as the first bonding pad ( Figure 3 Wirings at the same metal height as the metal height of LP1) may be directly connected to one another below the second to fourth magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4.

[0115] Vias having the same metal height as that of the second lower electrode BE2 may be omitted between the third magnetic tunnel junction element MTJ3 and the connection wiring 110 and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110 .

[0116] The first lower wiring structure 2201 may include a (1-2)th via 112b, a (1-2)th wiring 114b, a (2-2)th via 122b, a (2-2)th wiring 124b, a (3-2)th via 132b, a (3-2)th wiring 134b, and a (4-2)th via 142b sequentially stacked on the substrate 100. The second lower wiring structure 2301 may include a (1-3)th via 112c, a (1-3)th wiring 114c, a (2-3)th via 122c, a (2-3)th wiring 124c, a (3-3)th via 132c, a (3-3)th wiring 134c, and a (4-3)th via 142c sequentially stacked on the substrate 100. The third lower wiring structure 2401 may include a (1-4)th via 112d, a (1-4)th wiring 114d, a (2-4)th via 122d, a (2-4)th wiring 124d, a (3-4)th via 132d, a (3-4)th wiring 134d, and a (4-4)th via 142d sequentially stacked on the substrate 100. Each of the (4-2)th to (4-4)th vias 142b, 142c, and 142d may connect the (3-2)th to (3-4)th wirings 134b, 134c, and 134d to the connection wiring 110.

[0117] The first upper wiring structure 220u may include a second lower electrode BE2. The second lower electrode BE2 may connect the connection wiring 110 to the second magnetic tunnel junction element MTJ2. The second upper wiring structure ( Figure 3 and Figure 4 230u) and the third upper wiring structure ( Figure 3 and Figure 4The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be spaced apart from the connection wiring 110. The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may not be in direct contact with the connection wiring 110.

[0118] Each OTP unit cell OTPC may include second to fourth cell transistors CT21, CT22, CT31, CT32, CT41 and CT42, a connecting wiring 110, a first lower wiring structure to a third lower wiring structure 220l, 230l and 240l, a first upper wiring structure 220u, a second to fourth magnetic tunnel junction element MTJ2, MTJ3 and MTJ4, and a second to fourth upper electrode TE2, TE3 and TE4.

[0119] Figure 7 is an exemplary cross-sectional view of a magnetic memory device according to some embodiments. Figure 7 Includes connection to Figure 2 An exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG. Figure 7 Omitted Figure 2 For ease of description, the source line will be briefly described or omitted. Figures 1 to 6 The description section is repeated.

[0120] Reference Figure 7 In some embodiments, vias having the same metal height as that of vias not in direct contact with the connection wiring 110 may be omitted between the third and fourth magnetic tunnel junction elements MTJ3 and MTJ4 and the connection wiring 110. For example, vias having the same metal height as that of the (3-2)th via 132 b may be omitted between the third magnetic tunnel junction element MTJ3 and the connection wiring 110 and between the fourth magnetic tunnel junction element MTJ4 and the connection wiring 110.

[0121] The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 may be disposed between the connection wiring 110 and the third magnetic tunnel junction element MTJ3. The first sub-wiring structure 230u1 may be connected to the connection wiring 110. The second sub-wiring structure 230u2 may be connected to the third magnetic tunnel junction element MTJ3. The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 may be spaced apart from each other in the vertical direction. The first sub-wiring structure 230u1 and the second sub-wiring structure 230u2 may not directly contact each other.

[0122] The first sub-wiring structure 230u1 may include a (2-3)th via 122c and a (2-3)th wiring 124c sequentially stacked on the connection wiring 110. The second sub-wiring structure 230u2 may include a third lower electrode BE3, a third bonding pad LP3, a (4-3)th via 142c, and a (3-3)th wiring 134c sequentially stacked on a lower portion of the third magnetic tunnel junction element MTJ3. The (2-3)th wiring 124c and the (3-3)th wiring 134c may be spaced apart from each other. The (2-3)th wiring 124c and the (3-3)th wiring 134c may not directly contact each other.

[0123] The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 may be disposed between the connection wiring 110 and the fourth magnetic tunnel junction element MTJ4. The third sub-wiring structure 240u1 may be connected to the connection wiring 110. The fourth sub-wiring structure 240u2 may be connected to the fourth magnetic tunnel junction element MTJ4. The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 may be spaced apart from each other in the vertical direction. The third sub-wiring structure 240u1 and the fourth sub-wiring structure 240u2 may not be in direct contact with each other.

[0124] The third sub-wiring structure 240u1 may include a (2-4)th via 122d and a (2-4)th wiring 124d sequentially stacked on the connection wiring 110. The fourth sub-wiring structure 240u2 may include a fourth lower electrode BE4, a fourth bonding pad LP4, a (4-4)th via 142d, and a (3-4)th wiring 134d sequentially stacked on the lower portion of the fourth magnetic tunnel junction element MTJ4. The (2-4)th wiring 124d and the (3-4)th wiring 134d may be spaced apart from each other. The (2-4)th wiring 124d and the (3-4)th wiring 134d may not directly contact each other.

[0125] Figure 8 yes Figure 3 Magnified view of area S1. Figure 9 yes Figures 4 to 7 Magnified view of area S2.

[0126] Reference Figures 3 to 9 In some embodiments, resistance values ​​of the magnetic tunnel junction elements MTJ2 , MTJ3 , and MTJ4 included in the OTP unit cell OTPC may be greater than a resistance value of the magnetic tunnel junction element MTJ1 included in the memory unit cell MC.

[0127] For example, the sizes of the magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 included in the OTP unit cell OTPC can be smaller than the size of the magnetic tunnel junction element MTJ1 included in the memory unit cell MC. Therefore, the tunnel barrier pattern TL of the second magnetic tunnel junction element MTJ2 can be destroyed with a smaller current. In addition, since the resistance value of the insulated and destroyed second magnetic tunnel junction element MTJ2 becomes smaller, the lead margin of the second magnetic tunnel junction element MTJ2 can be increased.

[0128] For example, the maximum width W2 of the magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 included in the OTP unit cell OTPC may be smaller than the maximum width W1 of the magnetic tunnel junction element MTJ1 included in the memory unit cell MC. The height of the magnetic tunnel junction elements MTJ2, MTJ3, and MTJ4 included in the OTP unit cell OTPC may be smaller than the height of the magnetic tunnel junction element MTJ1 included in the memory unit cell MC. In this case, the width is defined based on the horizontal direction (the direction parallel to the upper surface of the substrate), and the height is defined based on the vertical direction (the direction perpendicular to the upper surface of the substrate).

[0129] The third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may have the same size as the second magnetic tunnel junction element MTJ2. The maximum width of the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be the same as the maximum width of the second magnetic tunnel junction element MTJ2. The maximum width W2 of the second magnetic tunnel junction element MTJ2 may be less than the maximum width W1 of the first magnetic tunnel junction element MTJ1. The height of the third magnetic tunnel junction element MTJ3 and the fourth magnetic tunnel junction element MTJ4 may be the same as the height of the second magnetic tunnel junction element MTJ2. The height of the second magnetic tunnel junction element MTJ2 may be less than the height of the first magnetic tunnel junction element MTJ1.

[0130] Figure 10 yes Figure 3 Magnified view of area S3. Figure 11 yes Figures 4 to 7 Magnified view of area S4.

[0131] Reference Figures 3 to 7 as well as Figure 10 and Figure 11In some embodiments, the threshold voltages of the cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 included in the OTP unit cell OTPC may be lower than the threshold voltages of the cell transistors CT11 and CT12 included in the memory unit cell MC. The cell transistors CT21, CT22, CT31, CT32, CT41, and CT42 included in the OTP unit cell OTPC may be high-voltage transistors operating at a high voltage, and the cell transistors CT11 and CT12 included in the memory unit cell MC may be low-voltage transistors operating at a low voltage. Therefore, a stable high voltage can be applied to the OTP unit cell OTPC.

[0132] The (1-1)th cell transistor CT11 may include a first gate dielectric film 104a, a first gate electrode 106a, and a first gate spacer 108a. The (1-2)th cell transistor CT12 may have the same structure as that of the (1-1)th cell transistor CT11. The (2-1)th cell transistor CT21 may include a second gate dielectric film 104b, a second gate electrode 106b, and a second gate spacer 108b. The (2-2)th cell transistor CT22, the (3-1)th cell transistor CT31, the (3-2)th cell transistor CT32, the (4-1)th cell transistor CT41, and the (4-2)th cell transistor CT42 may have the same structure as that of the (2-1)th cell transistor CT21.

[0133] Each of the first gate dielectric film 104a and the second gate dielectric film 104b may include, for example, at least one of silicon oxide and a high dielectric material. Each of the first gate electrode 106a and the second gate electrode 106b may include at least one of a semiconductor material doped with a dopant, a metal, a conductive metal nitride, and a metal-semiconductor compound. Each of the first gate spacer 108a and the second gate spacer 108b may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0134] In some embodiments, the width W3 of the first gate electrode 106 a may be greater than the width W4 of the second gate electrode 106 b .

[0135] In some embodiments, the thickness T1 of the first gate dielectric film 104 a may be smaller than the thickness T2 of the second gate dielectric film 104 b .

[0136] Figure 12 is an exemplary circuit diagram showing a magnetic memory device according to some embodiments. Figures 1 to 11 The description section is repeated.

[0137] Reference Figure 12 In some embodiments, the OTP unit cell OTPC may be connected to a specific bit line BL. For example, the OTP unit cell OTPC may be connected to a bit line BL disposed at an edge portion of the memory cell array 10 .

[0138] Only the memory unit cell MC may be connected to one bit line BL, or only the OTP unit cell OTPC may be connected to one bit line BL. The memory unit cell MC and the OTP unit cell OTPC may be connected to one word line WL. In some embodiments, the memory unit cell MC may be connected between one bit line BL and one source line SL in the first region R1 used as MRAM, and the OTP unit cell OTPC may be connected between another bit line BL and another source line SL in the second region R2 used as OTP.

[0139] In some embodiments, since the OTP unit cell OTPC is connected to a specific bit line BL, during a write operation of the OTP unit cell OTPC, the voltage applied to the bit line BL or the source line SL connected to the OTP unit cell OTPC can be increased, thereby increasing the magnitude of the voltage applied to both ends of the second magnetic tunnel junction element MTJ2 without increasing the stress of the memory unit cell MC.

[0140] Figure 3 This can include connecting to Figure 12 An exemplary cross-sectional view of a portion of three memory unit cells MC of one bit line in FIG. Figures 4 to 7 This can include connecting to Figure 12 FIG. 1 is an exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG.

[0141] Figure 13 is an exemplary circuit diagram showing a magnetic memory device according to some embodiments. Figures 1 to 11 The description section is repeated.

[0142] Reference Figure 13 In some embodiments, the OTP unit cell OTPC may be provided in a memory cell array (eg, the first memory cell array 10 a ) connected to a specific input / output circuit (eg, the first input / output circuit 70 a ).

[0143] Memory cell array ( Figure 1 10) may include a plurality of memory cell arrays. Each memory cell array may be connected to each of the input / output circuits and the column decoder.

[0144] For example, a memory cell array ( Figure 1The input / output circuit 10 may include a first memory cell array 10a and a second memory cell array 10b. Figure 1 The column decoder 70 may include a first input / output circuit 70a connected to the first memory cell array 10a and a second input / output circuit 70b connected to the second memory cell array 10b. Figure 1 The memory cell array 30 may include a first column decoder 30 a connected to the first memory cell array 10 a and a second column decoder 30 b connected to the second memory cell array 10 b.

[0145] The first memory cell array 10a may include OTP unit cells OTPC, and the second memory cell array 10b may include memory unit cells MC. Only the OTP unit cells OTPC may be connected to the bit lines BL of the first memory cell array 10a, and only the memory unit cells MC may be connected to the bit lines BL of the second memory cell array 10b. The memory unit cells MC and the OTP unit cells OTPC may be connected to one word line WL. The memory unit cells MC and the OTP unit cells OTPC may be connected to different input / output circuits.

[0146] For example, the OTP unit cell OTPC may be provided in the first memory cell array 10a, and the first memory cell array 10a is provided in the memory cell array ( Figure 1 10) at the edge portion.

[0147] Figure 3 This can include connecting to Figure 13 1 is an exemplary cross-sectional view of a portion of three memory unit cells MC of one bit line of the second memory cell array 10 b, and Figures 4 to 7 This can include connecting to Figure 13 FIG. 1 is an exemplary cross-sectional view of a portion of one OTP unit cell OTPC of one bit line of the first memory cell array 10 a in FIG.

[0148] Figure 14 is an exemplary circuit diagram showing a magnetic memory device according to some embodiments. Figures 1 to 11 The description section is repeated.

[0149] Reference Figure 14In some embodiments, four columns of memory unit cells MC may share a single source line SL. For example, the memory unit cells MC constituting the first column, the memory unit cells MC constituting the second column, the memory unit cells MC constituting the third column, and the memory unit cells MC constituting the fourth column may share a single source line SL. The number of columns of memory unit cells MC sharing a single source line SL is not limited thereto, and five or more columns of memory unit cells MC may share a single source line SL.

[0150] Four columns of OTP unit cells OTPC can share one source line SL. For example, the OTP unit cells OTPC constituting the first column, the OTP unit cells OTPC constituting the second column, the OTP unit cells OTPC constituting the third column, and the OTP unit cells OTPC constituting the fourth column can share one source line SL. The number of columns of OTP unit cells OTPC sharing one source line SL is not limited thereto, and five or more columns of OTP unit cells OTPC can share one source line SL.

[0151] For example, the number of columns of memory unit cells MC sharing one source line SL may be equal to the number of columns of OTP unit cells OTPC sharing one source line SL.

[0152] Figure 3 This can include connecting to Figure 14 An exemplary cross-sectional view of a portion of three memory unit cells MC of one bit line in FIG. Figures 4 to 7 This can include connecting to Figure 14 FIG. 1 is an exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG.

[0153] Figure 15 is an exemplary circuit diagram showing a magnetic memory device according to some embodiments. Figures 1 to 11 The description section is repeated.

[0154] Reference Figure 15 In some embodiments, the memory unit cell MC may have a structure in which a cell transistor CT11 is connected to a magnetic tunnel junction element MTJ1. For example, Figure 2 The (1-2)th unit transistor CT12.

[0155] The OTP unit cell OTPC may have a structure in which three cell transistors CT21, CT31, and CT41 are connected to one magnetic tunnel junction element MTJ2. The second cell transistor CT21, the third cell transistor CT31, and the fourth cell transistor CT41 may be connected in parallel. For example, the Figure 2The (2-2)th cell transistor CT22, the (3-2)th cell transistor CT32 and the (4-2)th cell transistor CT42.

[0156] The pair of the second magnetic tunnel junction element MTJ2 and the second cell transistor CT21, the pair of the third magnetic tunnel junction element MTJ3 and the third cell transistor CT31, and the pair of the fourth magnetic tunnel junction element MTJ4 and the fourth cell transistor CT41 of the OTP unit cell OTPC can be respectively arranged in the memory cell array 10 to have the same repetition periodicity as the pair of the first magnetic tunnel junction element MTJ1 and the first cell transistor CT11 of the memory unit cell MC.

[0157] exist Figure 12 、 Figure 13 and Figure 14 In the magnetic memory device of , the (1-2)th cell transistor CT12 , the (2-2)th cell transistor CT22 , the (3-2)th cell transistor CT32 , and the (4-2)th cell transistor CT42 may be omitted.

[0158] Figure 3 This can include connecting to Figure 15 An exemplary cross-sectional view of a portion of three memory unit cells MC of one bit line in FIG. Figures 4 to 7 This can include connecting to Figure 15 FIG. 1 is an exemplary cross-sectional view of a portion of an OTP unit cell OTPC of a bit line in FIG.

[0159] The above-described magnetic memory device according to an embodiment of the inventive concept may be included in various electronic products including a display device, a television, a computer (eg, a laptop computer), a phone (eg, a smartphone), a server, an infotainment system, and the like.

[0160] Although the embodiments according to the technical spirit of the present disclosure have been described with reference to the accompanying drawings, it will be clear to those skilled in the art that the present disclosure can be made in various forms without being limited to the above-described embodiments, and can be embodied in other specific forms without departing from the technical spirit and essential characteristics of the present disclosure. Therefore, the above embodiments are to be considered in all aspects as illustrative and not restrictive.

Claims

1. A magnetic memory device comprising: substrate; as well as A memory cell array including memory unit cells and one-time programmable unit cells and on a substrate, The memory unit cell includes: a first magnetic tunnel junction element on the substrate, and A wiring structure connecting the substrate to the first magnetic tunnel junction element, and One-time programmable unit cells include: Connecting wiring, on the substrate, The second magnetic tunnel junction element and the third magnetic tunnel junction element are spaced apart from each other on the connection wiring, a first lower wiring structure and a second lower wiring structure connecting the substrate and the connection wiring and spaced apart from each other, and The first upper wiring structure connects the connection wiring to the second magnetic tunnel junction element.

2. The magnetic memory device according to claim 1, wherein The first lower wiring structure includes: a first via hole connected to the substrate, The second lower wiring structure includes: a second via hole connected to the substrate, and The connection wiring is connected to the first via and the second via.

3. The magnetic memory device according to claim 1 , further comprising: The second upper wiring structure is spaced apart from the connection wiring and connected to the third magnetic tunnel junction element between the connection wiring and the third magnetic tunnel junction element.

4. The magnetic memory device according to claim 1 , further comprising: The first sub-wiring structure and the second sub-wiring structure are between the connection wiring and the third magnetic tunnel junction element. wherein the first sub-wiring structure is connected to the connection wiring, The second sub wiring structure is connected to the third magnetic tunnel junction element and is spaced apart from the first sub wiring structure.

5. The magnetic memory device according to claim 1, wherein The first upper wiring structure includes a lower electrode connecting the second magnetic tunnel junction element to the connection wiring, and The third magnetic tunnel junction element and the connection wiring are spaced apart from each other.

6. The magnetic memory device according to claim 1, wherein The one-time programmable unit cell also includes: a fourth magnetic tunnel junction element spaced apart from the second magnetic tunnel junction element and the third magnetic tunnel junction element on the connection wiring, and The third lower wiring structure connects the substrate and the connection wiring and is spaced apart from the first lower wiring structure and the second lower wiring structure.

7. The magnetic memory device according to claim 1, wherein The memory cell array includes: a first memory cell array and a second memory cell array, connected to different input / output circuits, The first memory cell array includes memory unit cells, and The second memory cell array includes one-time programmable unit cells.

8. The magnetic memory device according to claim 1, wherein A width of the first magnetic tunnel junction element is greater than a width of the second magnetic tunnel junction element.

9. The magnetic memory device according to claim 1, wherein The width of the first magnetic tunnel junction element is greater than the width of the second magnetic tunnel junction element and the width of the third magnetic tunnel junction element.

10. The magnetic memory device according to claim 1, wherein The memory unit cell includes a first cell transistor electrically connected to a wiring structure on a substrate and including a first gate electrode and a first gate dielectric film, The one-time programmable unit cell includes: a second cell transistor electrically connected to a first lower wiring structure on a substrate, the second cell transistor including a second gate electrode and a second gate dielectric film, and The width of the second gate electrode is smaller than the width of the first gate electrode.

11. The magnetic memory device according to claim 1 , further comprising: Peripheral circuits, electrically connected to the memory cell array, The memory unit cell and the one-time programmable unit cell share a peripheral circuit.

12. A magnetic memory device comprising: A memory unit cell includes: a first magnetic tunnel junction element connected to a first bit line; and a first cell transistor connecting the first magnetic tunnel junction element to a first source line; and A one-time programmable unit cell includes: second to fourth magnetic tunnel junction elements connected to a second bit line; and second to fourth cell transistors connecting a second source line to the second magnetic tunnel junction element. The third magnetic tunnel junction element and the fourth magnetic tunnel junction element are not connected to the second to fourth cell transistors.

13. The magnetic memory device according to claim 12, wherein The first bit line and the second bit line are the same bit line, and the first source line and the second source line are the same source line.

14. The magnetic memory device according to claim 12, wherein The first bit line and the second bit line are different bit lines, and the first source line and the second source line are different source lines.

15. The magnetic memory device according to claim 12, wherein Threshold voltages of the second to fourth cell transistors are lower than the threshold voltage of the first cell transistor.

16. The magnetic memory device according to claim 12, wherein A resistance of each of the second to fourth magnetic tunnel junction elements is greater than a resistance of the first magnetic tunnel junction element.

17. The magnetic memory device according to claim 12, wherein Gates of the second to fourth cell transistors are connected to different word lines, respectively.

18. The magnetic memory device according to claim 12, wherein At least one of the second to fourth cell transistors is configured to be turned on during a read operation of the one-time programmable unit cell.

19. A magnetic memory device comprising: a plurality of memory unit cells connected between a first bit line and a first source line; a plurality of one-time programmable unit cells connected between the second bit line and the second source line; as well as a peripheral circuit connected to the plurality of memory unit cells and the plurality of one-time programmable unit cells, Each of the plurality of memory unit cells includes: a first magnetic tunnel junction element connected to a first bit line; and a first cell transistor connecting the first magnetic tunnel junction element to a first source line. Each of the plurality of one-time programmable unit cells includes: second to fourth magnetic tunnel junction elements connected to a second bit line; and second to fourth cell transistors connecting a second source line to the second magnetic tunnel junction element, and The third magnetic tunnel junction element and the fourth magnetic tunnel junction element are not connected to the second to fourth cell transistors.

20. The magnetic memory device according to claim 19, wherein The gate of the first cell transistor is connected to the first word line, The gate of the second cell transistor is connected to the first word line, and A gate of the third cell transistor and a gate of the fourth cell transistor are respectively connected to a second word line and a third word line different from the first word line.

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