Operating method of ferroelectric memory cell and memory device

Abstract

The invention provides an operation method for a group of ferroelectric memory cells and a memory device. The operation method comprises the following steps: in a first cycle period, writing a first data bit into a first ferroelectric memory cell in the group of ferroelectric memory cells; in a first cycle period, writing a group of sign bits for indicating the polarity of the group of ferroelectric memory cells into at least one second ferroelectric memory cell in the group of ferroelectric memory cells, each sign bit having a first value; in a second cycle period following the first cycle period, the set of sign bits is read from the second ferroelectric memory cell. The operating method may include performing an error correction operation on the set of sign bits in the second cycle period to determine a first value of the set of sign bits written in the first cycle period.

Description

Technical Field

[0001] The present application relates to a memory and an operating method thereof, and in particular to an operating method of a ferroelectric memory cell and a memory device. Background Art

[0002] Ferroelectric memories, such as ferroelectric random access memory (FeRAM or FRAM), utilize layers of ferroelectric materials to achieve their nonvolatile storage. Ferroelectric materials exhibit a nonlinear relationship between an applied electric field and their apparent stored charge, enabling them to switch polarity in response to an applied electric field. Ferroelectric memories offer advantages such as low power consumption, fast write speeds, and excellent maximum read / write endurance. Summary of the Invention

[0003] One aspect of the present application is to provide a method for operating a group of ferroelectric memory cells, the operating method comprising:

[0004] In a first cycle, a first data bit is written into a first ferroelectric memory cell of the group of ferroelectric memory cells.

[0005] In the first cycle, a set of sign bits is written into at least one second ferroelectric memory cell in the set of ferroelectric memory cells, each sign bit has a first value, and the set of sign bits is used to indicate the polarity of at least one second ferroelectric memory cell.

[0006] In a second cycle following the first cycle, the set of sign bits is read from the second ferroelectric memory cell.

[0007] In the second cycle, an error correction operation is performed on a group of storage bits to determine the first value of the group of sign bits written in the first cycle.

[0008] In some embodiments, performing the error correction operation on the set of storage bits in the second cycle to determine the first value of the set of sign bits written in the first cycle comprises:

[0009] At most one sign bit in the set of sign bits is detected, and the at most one sign bit is inverted to a second value different from the first value.

[0010] When pre-reading or reading the set of sign bits, if most sign bits maintain the first value, the set of sign bits written in the first cycle is determined to be the first value, and the sign bits with the second value are corrected to the first value.

[0011] When pre-reading or reading the set of sign bits, if most of the sign bits maintain the first value, the sign bits are corrected and inverted to the second value.

[0012] In some embodiments, performing the error correction operation on the set of storage bits in the second cycle to determine the first value of the set of sign bits written in the first cycle includes: if it is determined that none of the sign bits are inverted, then determining that the read data has the correct polarity.

[0013] In some embodiments, the operating method further comprises: in the second cycle, inverting the sign bit of the set of sign bits from the first value to the second value.

[0014] In some embodiments, the operating method further comprises: writing a second data bit into the first ferroelectric memory cell in the second cycle, such that the polarity of the second data bit matches the polarity of the other set of written sign bits.

[0015] In some embodiments, the operating method further comprises: in the second cycle, before or after writing the second data bit into the first ferroelectric memory cell, writing the other set of sign bits into at least one of the second ferroelectric memory cells, wherein each sign bit has the second value.

[0016] In some embodiments, the error correction operation includes an error checking and correction (ECC) operation, or the error correction operation includes a majority voting operation.

[0017] In some embodiments, the operating method further comprises: writing a set of error correction bits into at least one third ferroelectric memory cell in the set of ferroelectric memory cells during the first cycle, and reading the set of error correction bits from at least one third ferroelectric memory cell during the second cycle.

[0018] In some embodiments, the error correction operation is performed based on the set of error correction bits.

[0019] In some embodiments, the error correction operation includes an error checking and correction (ECC) operation, wherein the error checking and correction (ECC) operation uses the error correction bit to determine the correct polarity of each ferroelectric memory cell in the group of ferroelectric memory cells, the ECC code, and the group of sign bits.

[0020] On the other hand, the present application aims to provide a memory device.

[0021] The memory device of the present application includes a group of ferroelectric memory cells and a peripheral circuit coupled to the group of ferroelectric memory cells. The peripheral circuit is configured to perform:

[0022] In a first cycle, a first data bit is written into a first ferroelectric memory cell of the group of ferroelectric memory cells.

[0023] In the first cycle, a set of sign bits is written into at least one second ferroelectric memory cell in the set of ferroelectric memory cells, each sign bit has a first value, and the set of sign bits is used to indicate the polarity of at least one second ferroelectric memory cell.

[0024] In a second cycle following the first cycle, the set of sign bits is read from the second ferroelectric memory cell.

[0025] In the second cycle, an error correction operation is performed on a group of storage bits to determine the first value of the group of sign bits written in the first cycle.

[0026] In some embodiments, in the second cycle, to perform the error correction operation on the group of storage bits to determine the first value of the group of sign bits in the first cycle, the peripheral circuit is configured to perform:

[0027] At most one sign bit in the set of sign bits is detected, and the at most one sign bit is inverted to a second value different from the first value. When pre-reading or reading the set of sign bits, if a majority of the sign bits maintain the first value, the set of sign bits written in the first cycle is determined to be the first value, and the sign bits having the second value are corrected to the first value. When pre-reading or reading the set of sign bits, if a majority of the sign bits maintain the first value, the sign bits inverted to the second value are corrected.

[0028] In some embodiments, in the second cycle, to perform the error correction operation on the group of storage bits to determine the first value of the group of sign bits written in the first cycle, the peripheral circuit is configured to perform:

[0029] If it is determined that the first value of the set of sign bits is not inverted to the second value, it is determined that the read data has a correct polarity.

[0030] In some embodiments, the peripheral circuit is further configured to perform:

[0031] If it is determined that none of the sign bits are inverted, it is determined that the read data has the correct polarity.

[0032] In some embodiments, the peripheral circuit is further configured to perform:

[0033] In the second cycle, a second data bit is written into the first ferroelectric memory cell, so that the polarity of the second data bit matches the polarity of another set of sign bits written in the second cycle.

[0034] In some embodiments, the peripheral circuit is further configured to perform:

[0035] In the second cycle, the other set of sign bits is written into at least one of the second ferroelectric memory cells, and each sign bit of the other set of sign bits has the second value.

[0036] In some embodiments, the error correction operation comprises an error correction code (ECC) operation, or the error correction operation comprises a majority voting operation.

[0037] In some embodiments, the peripheral circuit is further configured to perform:

[0038] In the first cycle, a set of error correction bits is written into at least one third ferroelectric memory cell of the set of ferroelectric memory cells. In the second cycle, the set of error correction bits is read from at least one third ferroelectric memory cell.

[0039] In some embodiments, the error correction operation is performed based on the set of error correction bits.

[0040] In some embodiments, the error correction operation includes an error checking and correction (ECC) operation, and the error checking and correction (ECC) operation uses the error correction bit to determine the correct polarity of each ferroelectric memory cell in the group of ferroelectric memory cells, the ECC code, and the group of sign bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings of this application constitute a part of this application, and illustrate the implementation methods of this application. Combined with the explanatory content, they further explain the principles of this application and enable people with ordinary knowledge in this technical field to implement and utilize this application.

[0042] Figure 1 1 is a schematic cross-sectional view of a ferroelectric memory cell, illustrating ferroelectric memory cells according to some exemplary embodiments of the present application.

[0043] Figure 2A Schematic diagrams of circuits illustrating ferroelectric memory cells according to some exemplary embodiments of the present application.

[0044] Figure 2B FIG2 is a timing diagram illustrating a read operation of the ferroelectric memory cell shown in FIG2A in some exemplary embodiments of the present application.

[0045] Figure 3 FIG2 is a circuit diagram illustrating a ferroelectric memory device according to some exemplary embodiments of the present application. The ferroelectric memory device is configured to implement a sign bit implementation scheme for error correction.

[0046] Figure 4 1 is a flow chart illustrating an operating method of a ferroelectric memory cell according to some exemplary embodiments of the present application. DETAILED DESCRIPTION

[0047] The technical content and effects of the present application will be clearly presented in conjunction with the drawings and detailed description of the following embodiments.

[0048] Although specific configurations and arrangements are discussed below, it should be understood that this is for illustrative purposes only. Those skilled in the art will appreciate that other configurations and arrangements may be employed without departing from the spirit and scope of the present application. Those skilled in the art will also appreciate that the present application may be applied to a variety of other applications.

[0049] It should be noted that when the specification refers to terms such as "one embodiment," "an embodiment," "exemplary embodiment," or "some embodiments," these terms indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, the terms do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, a person skilled in the art should understand that the particular feature, structure, or characteristic may be applied to other embodiments even if not explicitly described.

[0050] Generally speaking, the terms used in this application are understood, at least in part, by the context. For example, depending on the context, the term "one or more" can be used to describe a single feature, structure, or characteristic, or a combination of multiple features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can be understood as singular or plural, depending on the context.

[0051] It should be understood that the terms "on", "above", "over" and the like used in this application should be interpreted in the broadest sense, and "on" includes not only being directly on something, but also including situations where other features or layers are provided therebetween. And "above" or "on" does not only mean being above something, but also includes situations where no intervening features or layers are provided (i.e., directly above something). In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower layer", "above", "upper layer" and the like may be used in this application to illustrate the relative relationship between one element or feature and another element or feature, as shown in the figures. These spatially relative terms are intended to cover different orientations of the device during use or operation, and are not limited to the orientations shown in the figures. The device may also have other orientations (e.g., rotated 90 degrees or at other angles), and the spatially relative descriptors used in this application should be interpreted accordingly.

[0052] In this application, the term "substrate" refers to a material onto which subsequent material layers are added. The substrate itself may have a patterned structure. The material layers added to the substrate may be patterned or unpatterned. Furthermore, the substrate includes various semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0053] In this application, the term "layer" refers to a portion of a material having an area with a thickness. The layer may extend to cover the entire structure below or above, or may extend to an area smaller than the area of ​​the structure below or above. In addition, a layer may be a homogeneous or inhomogeneous area in a continuous structure, and the thickness of the area is less than the thickness of the entire continuous structure. For example, a layer may be arranged between any pair of horizontal planes, or between the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically and / or along an inclined surface. The substrate may be a layer and / or may have one or more layers arranged above, below or within it. A single layer itself may also have multiple layers. For example, an interconnect layer may include one or more conductor layers and contact layers (and in which contacts, interconnect lines and / or through-holes are formed), as well as one or more dielectric layers.

[0054] As used herein, the term "approximately" refers to a value of a given quantity that varies depending on the particular technology node to which the semiconductor device belongs. Depending on the technology node, the term "approximately" may mean that the value of the given quantity may vary within a range of 10% to 30% (e.g., ±10%, ±20%, or ±30% of its value).

[0055] As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having a vertically arranged string of memory cell transistors (hereinafter referred to as a memory string) disposed on a laterally disposed substrate, such that the memory string extends in a direction perpendicular to the laterally disposed substrate. As used herein, "vertical" refers to a direction nominally perpendicular to a lateral surface of the substrate.

[0056] Ferroelectric RAM (FeRAM) is a type of random access memory similar to dynamic random access memory (DRAM). The difference is that FeRAM utilizes a ferroelectric layer rather than a dielectric layer to achieve its non-volatility. As alternative non-volatile random access memory technologies become increasingly diverse, FeRAM is one such type, offering similar functionality to flash memory. A FeRAM chip contains a thin film of ferroelectric material (the ferroelectric layer). When an external electric field is applied, the ions in the ferroelectric layer change their relative positions, resulting in high-efficiency binary switching. When the field is removed, the positive ions in the ferroelectric layer maintain their positions, and subtle variations in their position can be detected by external circuitry. The advantageous property of the ferroelectric layer is that it is unaffected by power failures or magnetic interference, making FeRAM a reliable non-volatile memory.

[0057] Because semi-permanent electric dipoles are formed in the crystal structure of the ferroelectric material, the dielectric constant of the ferroelectric material is generally much higher than that of linear dielectric materials. When an external electric field is applied to the ferroelectric material, the electric dipoles contained in the ferroelectric material tend to align along the electric field direction of the external electric field, and this alignment is caused by a small displacement of the position of the positive ions and a change in the charge distribution of the electrons. After the electric field is removed, the electric dipoles can still maintain their polarization state. The binary "0" and "1" are stored in one of the two possible electric polarization states in each data storage cell. The data storage cell is also called a ferroelectric memory cell (FeRAM cell). For example, "1" is encoded by negative remanent polarization (-Pr), while "0" is encoded by positive remanent polarization (+Pr).

[0058] Writing to a ferroelectric memory (FeRAM) cell is accomplished by charging the electrodes on either side of the ferroelectric layer. This applies an electric field to the ferroelectric layer, forcing the positive ions within the layer to align in an upward or downward direction, depending on the polarity of the applied electric field, thereby storing a data bit of "1" or "0." During a read operation, a transistor is used to force the ferroelectric cell to a specific state, such as "0." If the ferroelectric cell originally stored a "0," the state of the ferroelectric cell remains unchanged. If the ferroelectric cell originally stored a "1," the positive ions in the ferroelectric layer rearrange, releasing additional effective charge onto the signal line of the "0" cell. The presence of this additional effective charge indicates that the ferroelectric cell is storing a "1." Because this process overwrites the ferroelectric cell, reading from it is a destructive process, requiring the data bit to be rewritten to the cell after the read.

[0059] A ferroelectric memory (FeRAM) controller performs a sensing operation to identify the contents of the ferroelectric memory cell. Because the output line carries noise, the signal must be greater than the noise in order for the ferroelectric memory controller to sense the ferroelectric memory cell. The polarization density of the ferroelectric memory cell is characterized by a 2Pr window (2Pr window) estimated by the residual polarization amount, and the 2Pr window represents the charge difference between a bit value of 0 and a bit value of 1 per unit area. Therefore, the larger the size of the ferroelectric memory capacitor, the larger the signal generated. The 2Pr window is related to the signal-to-noise ratio, and the ferroelectric memory controller performs a sensing operation based on the signal-to-noise ratio associated with the 2Pr window.

[0060] During its lifetime, ferroelectric RAM (FeRAM) can be affected by various noise sources, resulting in signal degradation and / or increased noise in the ferroelectric memory cells. This reduced signal-to-noise ratio makes writing to the ferroelectric memory cells more difficult, and it can be difficult to verify the accuracy of sensing operations.

[0061] To overcome these and other challenges, the present application provides exemplary implementations of sign bits to mitigate the negative effects of noise sources. This implementation of the sign bit includes writing a set of sign bits (e.g., one or more sign bits) simultaneously with writing data bits to a ferroelectric RAM (FeRAM) cell. The set of sign bits may indicate the polarity of the data bits written to the ferroelectric RAM. Because the set of sign bits may experience polarity variations due to process defects or noise sources, this exemplary implementation of the sign bit includes an error correction operation. The error correction operation may be used to determine the polarity of the sign bit written to the ferroelectric RAM cell. For example, the error correction operation may include an error correction code (ECC) operation or a majority vote operation. When the sign bit implementation utilizes the ECC operation, the set of sign bits may include a single sign bit. Conversely, when the sign bit implementation utilizes the majority vote operation, the set of sign bits may include an odd number of sign bits greater than 1 (e.g., 3, 5, 7, etc.). More details on an exemplary implementation of the sign bit are provided below. Figures 1 to 4 For further reference.

[0062] See Figure 1 , Figure 1 FIG1 is a schematic cross-sectional view of a ferroelectric memory cell, which is used to illustrate the cross-sectional structure of a ferroelectric memory cell 100 according to some exemplary embodiments. The ferroelectric memory cell 100 is a basic storage element of a ferroelectric memory device and can have various designs and configurations. Figure 1 As shown, the ferroelectric memory cell 100 is a 1T-1C cell. The ferroelectric memory cell 100 includes a capacitor 102 and a transistor 104 disposed on a substrate 108, and an interconnect structure 106 connecting the capacitor 102 and the transistor 104. The substrate 108 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0063] In some embodiments, the capacitor 102 includes a lower electrode 110, an upper electrode 112, and a ferroelectric layer 114 disposed vertically between the lower electrode 110 and the upper electrode 112. The lower surface of the ferroelectric layer 114 may be in contact with and electrically connected to the lower electrode 110, while the upper surface of the ferroelectric layer 114 may be in contact with and electrically connected to the upper electrode 112. The lower electrode 110 may be electrically connected to the transistor 104 via the interconnect structure 106, while the upper electrode 112 may be electrically connected to a voltage source (not shown) to apply an electric field to the ferroelectric layer 114. For ease of illustration, the present application uses a 1T-1C cell as an example in the drawings. In various embodiments, the ferroelectric layer 114 may also be implemented in any other suitable type of memory cell, each memory cell including multiple capacitors. For example, the ferroelectric layer 114 may also be implemented in a "2T-2C" cell or an "nT-mC" cell, where n and m are integers. It should be noted that the type of memory cell (eg, the number of capacitors included in a single memory cell) should not be limited to the embodiments of the present application.

[0064] The material of the lower electrode 110 and the upper electrode 112 may include, but is not limited to, at least one of the following: titanium nitride (TiN), titanium silicon nitride (TiSiNx), titanium aluminum nitride (TiAlNx), titanium carbonitride (TiCNx), tantalum nitride (TaNx), tantalum silicon nitride (TaSiNx), tantalum aluminum nitride (TaAlNx), tungsten nitride (WNx), tungsten silicide (WSix), tungsten carbonitride (WCNx), rhodium (Ru), rhodium oxide (RuOx), iridium (Ir), doped polysilicon, transparent conductive oxide (TCO), or iridium oxide (IrOx). In some embodiments, the lower electrode 110 and the upper electrode 112 include the same material. In some embodiments, the lower electrode 110 and the upper electrode 112 include different materials. The thickness of the bottom electrode 110 or the top electrode 112 may be between about 2 nm and about 50 nm, for example, between 2 nm and 20 nm, such as 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 10 nm, 15 nm, 18 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, or any range defined by any two of the foregoing values. In some embodiments, the bottom electrode 110 and the top electrode 112 have the same thickness. In some embodiments, the bottom electrode 110 and the top electrode 112 have different thicknesses.

[0065] In some embodiments, the ferroelectric layer 114 comprises a ferroelectric oxide material. The ferroelectric oxide material may comprise a ferroelectric composite oxide. For example, the ferroelectric oxide material may comprise oxygen and one or more ferroelectric metals. The ferroelectric metals may include, but are not limited to, zirconium (Zr), hafnium (Hf), and titanium (Ti). In some embodiments, the ferroelectric metal element may also comprise aluminum (Al), nickel (Ni), and / or iron (Fe). In some embodiments, the ferroelectric oxide material may comprise HfOx. In some embodiments, the ferroelectric oxide material may comprise oxygen and two or more ferroelectric metals. The molar ratio between any two ferroelectric metals may be between 0.1 and 10, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or any range with any of the above values ​​as the lower limit or bounded by any two of the above values. In some embodiments, the ferroelectric oxide material may also comprise oxygen and a non-metallic material, such as silicon.

[0066] In some embodiments, the transistor 104 may include source / drain regions 120 and a gate stack structure having a gate dielectric layer 122 and a gate conductive layer 124. The source / drain regions 120 may be formed in doped regions in the substrate 108 and have a predetermined concentration of n-type or p-type dopants. The gate dielectric layer 122 may include a dielectric material such as silicon oxide (SiOx), silicon nitride (SiNx), or a high-k dielectric material. Such high-k dielectric materials include, but are not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof. The gate conductive layer 124 may include a conductive material such as, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, silicide, or any combination thereof. The gate conductive layer 124 may serve as a word line for the ferroelectric memory cell 100. The interconnect structure (not shown) may contact one of the source / drain regions 120 that is not in contact with the interconnect structure 106 and serve as a bit line of the ferroelectric memory cell 100. Figure 1 The examples shown are limiting and may include any suitably configured planar ferroelectric memory cell or three-dimensional ferroelectric memory cell.

[0067] Figure 2A Schematic diagram of a ferroelectric memory cell according to some exemplary embodiments of the present application. The ferroelectric memory cell may be a 1T-1C ferroelectric memory cell, for example, Figure 1 The ferroelectric memory cell 100 is shown in FIG. The gate of the transistor T is electrically connected to the word line WL, one of the source and drain of the transistor T is electrically connected to the bit line BL, and the other is electrically connected to one electrode of the capacitor C. The other electrode of the capacitor C is electrically connected to the plate line PL, which can be as shown in FIG. Figure 2A As shown, a voltage VC is applied to the capacitor C. Figure 2A The shown CBL represents the total parasitic capacitance of the bit line BL.

[0068] Figure 2B In some exemplary embodiments of this application, Figure 2A The timing diagram of the read operation performed by the ferroelectric memory cell shown in FIG. Figure 2AIn the example, the read operation of a ferroelectric memory cell selected by the positive-going WL signal involves two steps. In the first step, the PL signal switches from a low potential to a high potential, and the data in the ferroelectric memory cell (e.g., the charge stored in the capacitor C) is sensed via the BL signal. Because the read operation of a ferroelectric memory is a destructive read, it changes the contents of the accessed memory location, necessitating a write back to preserve the data. In the second step, the PL signal remains positive for a fixed period of time, then switches to the low potential, writing the sensed data back to the ferroelectric memory cell.

[0069] Regarding the write operation of the ferroelectric memory cell, in one embodiment, it also includes two steps: in the first step, multiple sets of data are simultaneously sensed from multiple ferroelectric memory cells (for example, located in the same page); in the second step, the new data is written into the target ferroelectric memory cell, and the other original data is simultaneously written back to other ferroelectric memory cells in the same page.

[0070] In another example, if a larger input / output bandwidth is provided, the new data in the entire page can be directly written into the target ferroelectric memory cell without performing a sensing step (ie, the first step) first.

[0071] As mentioned above, a typical ferroelectric memory read operation requires two steps: sensing and rewriting data. In terms of performance, these two steps take comparable time because signal control requires similar time. Therefore, if a ferroelectric memory and a DRAM both have similar architectures—for example, if both utilize a 1T-1C architecture—then theoretically the performance of the ferroelectric memory should be comparable to that of the DRAM.

[0072] As mentioned above, a typical ferroelectric memory read operation requires two steps: sensing and rewriting data. In terms of performance, each step takes a similar amount of time due to similar signal control. Therefore, if a ferroelectric memory and a DRAM both have similar architectures—for example, if both utilize a 1T-1C architecture—then theoretically the performance of the ferroelectric memory should be comparable to that of the DRAM.

[0073] Various exemplary embodiments of the present application provide implementations of a sign bit. For example, implementations of the sign bit may include writing a set of sign bits (e.g., one or more sign bits) to indicate the polarity of the data bits written to the ferroelectric memory cell. For example, when the sign bit is "0," it may be written along with each data bit to indicate a "true" state, i.e., the original state stored in the ferroelectric memory cell. When the sign bit is "1," it indicates a "false" state, i.e., the data bit stored in the ferroelectric memory cell is inverted.

[0074] When reading data from the ferroelectric memory cell, the controller may first determine the polarity of the sign bit. Then, based on this, it correctly identifies whether the data bit written to the ferroelectric memory cell is in an inverted state. The sign bit implementation of the present application includes an error correction operation. The error correction operation can be used to identify the polarity of the sign bit written to the ferroelectric memory cell. For example, the error correction operation may include an error checking and correction (ECC) operation, or a majority-vote operation. When the implementation of the sign bit includes the error checking and correction (ECC) operation, the group of sign bits may include a single sign bit; conversely, when the implementation of the sign bit adopts the majority vote operation, the group of sign bits may include an odd number of sign bits greater than 1 (for example, 3, 5, 7, etc.). Other details about the implementation of the sign bit in this exemplary embodiment will be described below in conjunction with Figure 3 and Figure 4 For further explanation.

[0075] Figure 3 FIG. 3 is a circuit diagram of a ferroelectric memory device 300 according to some exemplary embodiments of the present application. Figure 3 As shown, the ferroelectric memory device 300 includes a group of ferroelectric memory cells 302, and the ferroelectric memory cell group 302 is used to store data bits and sign bits.

[0076] In some embodiments, the set of ferroelectric memory cells 302 may include an array of ferroelectric memory cells 304 arranged in columns and rows. Figure 3 As shown, each ferroelectric memory cell 304 can be a 1T-1C memory cell, including a transistor 306 and a capacitor 308. Each word line WL[0] or WL[1] is electrically connected to the gate of the transistor 306 in each ferroelectric memory cell 304 in the same row of the array; each bit line BL[0] or BL[1] is electrically connected to the source or drain of the transistor 306 in each ferroelectric memory cell 304 in the same column of the array. Each plate line PL0 or PL1 is electrically connected to one electrode of the capacitor 308 in each ferroelectric memory cell 304 in the same row of the array. In each ferroelectric memory cell 304, the source or drain of the transistor 306 is electrically connected to the other electrode of the capacitor 308.

[0077] In some embodiments, at least one ferroelectric memory cell 304 in each group of ferroelectric memory cells 302 may be configured to store a sign bit. When the sign bit implementation in these embodiments includes ECC, each group of ferroelectric memory cells 302 may include one ferroelectric memory cell 304 for storing the sign bit, two or more other ferroelectric memory cells 304 for storing the ECC bits, and at least one ferroelectric memory cell for storing data bits (e.g., user data). In some embodiments, when the sign bit implementation utilizes a majority voting operation, each group of ferroelectric memory cells 302 may include an odd number of ferroelectric memory cells 304 greater than one (e.g., 3, 5, 7, etc.).

[0078] In some embodiments, the ferroelectric memory device 300 may also include peripheral circuitry 310. The peripheral circuitry 310 is electrically connected to the set of ferroelectric memory cells 302 via bit lines, word lines, and plate lines. The peripheral circuitry 310 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage signals or current signals to the ferroelectric memory cells via the bit lines, word lines, source lines, and plate lines, and / or sensing voltage signals or current signals from the ferroelectric memory cells to facilitate operation of the ferroelectric memory cells. The peripheral circuitry 310 may include various peripheral circuit elements formed using metal oxide semiconductor (MOS) technology, such as page buffers / sense amplifiers, column decoders / bit line drivers, row decoders / word line drivers, voltage generators, control logic, registers, interfaces, and data buses.

[0079] In some embodiments, the peripheral circuit 310 may include a word line driver circuit, a plate line driver circuit, and a bit line driver circuit. The word line driver circuit may be configured to generate a plurality of word line signals and apply these word line signals to corresponding word lines to select the same word line (e.g., Figure 3 The plate line driving circuit can be configured to generate plate line signals and apply each plate line signal to the corresponding plate line (e.g., plate line code) according to the plate line timing (i.e., plate line code). Figure 3 PL0 shown). Each plate line signal can be applied to the corresponding capacitor 308 via the corresponding plate line to polarize the corresponding ferroelectric memory cell 304. The bit line driver circuit can be configured to generate a bit line signal and apply the bit line signal to the corresponding bit line (e.g., Figure 3BL[0] shown in FIG. 1 ) to write valid state data to the capacitor 308 in the corresponding ferroelectric memory cell 304 during a write operation. In some embodiments, each bit line signal is a voltage signal that pulses between 0V and the supply voltage Vdd. According to some embodiments, the bit line signal is a binary signal of 0V or Vdd. During a read operation, the bit line driver circuit can drive the corresponding bit line (e.g., Figure 3 BL[0]) reads the bit line signal and compares it to one or more reference voltages to determine the valid state of the data stored in the capacitor 308. The various operations of the sign bit embodiment will now be described.

[0080] See also Figure 3 In a first cycle, the peripheral circuit 310 may write a first data bit into a ferroelectric memory cell 304 of the group of ferroelectric memory cells 302. During the first cycle, the peripheral circuit 310 may also write a set of sign bits into at least one other ferroelectric memory cell 304 in the group of ferroelectric memory cells 302, each sign bit having a first value. Similarly, during the first cycle, the peripheral circuit 310 may also write an ECC code (ECC bits) into another ferroelectric memory cell 304. The ECC code refers to error checking and correction. The set of sign bits may be used to indicate the polarity of the group of ferroelectric memory cells 302 when written during the first cycle. In a second cycle following the first cycle, the peripheral circuit 310 may read the set of sign bits from the at least one other ferroelectric memory cell 304. During the second cycle, the peripheral circuit 310 may perform an error correction operation on the stored bits (e.g., the ECC code) to determine the first value of the set of sign bits written during the first cycle.

[0081] For example, during the second cycle, to perform error correction on the set of sign bits and determine the first value of the sign bits written during the first cycle, the peripheral circuit 310 may determine whether at most one sign bit in the set of sign bits has inverted to a second value different from the first value. If, during the second cycle, at most one sign bit in the set of sign bits does not retain the first value, the peripheral circuit 310 may determine that the sign bit written during the first cycle was the first value. For example, depending on the technical implementation and usage model, if two of the three sign bits retain the first value, the first value corresponding to the reference voltage associated with the polarity of the sign bit written during the first cycle, the peripheral circuit 310 may determine the polarity of the stored sign bit accordingly. If at most one sign bit in the set of sign bits inverts to the second value, the peripheral circuit 310 may determine that the polarity of the ferroelectric memory cell was inverted due to a defect or noise, and perform error correction. Over the lifetime of the device, the technology and usage model must ensure that at most two of the three bits may be flipped from their originally written state, otherwise the sign bit will not be able to correctly interpret the data bits.

[0082] In some embodiments, in the second cycle, in order to perform an error correction operation on the group of sign bits to determine whether the polarity of the ferroelectric memory cell is reversed, when the first value of at most only one sign bit in the group of sign bits is reversed to the second value, the peripheral circuit 310 can determine that the polarity of the ferroelectric memory cell is the polarity indicated by the group of sign bits.

[0083] In some embodiments, the peripheral circuit 310 can invert the polarity of the data bits and sign bits written to the memory during alternating cycles. Thus, during the second cycle, the peripheral circuit 310 can invert the sign bits to the second value. During the second cycle, the peripheral circuit 310 can also write the second data bits to the ferroelectric memory cells 304 and write the sign bits with the second value to at least one ferroelectric memory cell 304. The alternating frequency can vary depending on the usage scenario or be dynamically adjusted based on device characteristics.

[0084] When the error correction operation includes ECC, the peripheral circuit 310 can read the error correction bits and the sign bit from the corresponding ferroelectric memory cell 304. The peripheral circuit 310 can use the error correction bits to perform ECC to determine the correct polarity of the sign bit when it is written. ECC is also known as error checking and correction.

[0085] Figure 44 is a flow chart of an operating method 400 for a ferroelectric memory cell according to some exemplary embodiments of the present application. The operating method 400 may be performed by a device, such as the ferroelectric memory device 300, the peripheral circuit 310, or any other suitable device. The operating method 400 includes operating steps 402 to 414 described below. It should be understood that some operating steps may be selectively performed, and some operating steps may be performed simultaneously, or according to different operating steps. Figure 4 Execute in the order shown.

[0086] See Figure 4 In operation 402, the apparatus may write the first data bit into the first ferroelectric memory cell in the group of ferroelectric memory cells in the first cycle. Figure 3 In the first cycle, the peripheral circuit 310 may write the first data bit into the ferroelectric memory cell 304 in the group of ferroelectric memory cells 302. The first data bit may include either or both of data and / or error correction code (ECC code).

[0087] In operation 404, the apparatus may write a set of sign bits into at least one second ferroelectric memory cell in the set of ferroelectric memory cells in a first cycle, wherein each sign bit has a first value. Figure 3 In the first cycle, the peripheral circuit 310 may write a set of sign bits into at least another ferroelectric memory cell 304 in the set of ferroelectric memory cells 302, each sign bit having a first value. The set of sign bits may be used to indicate the polarity of the set of ferroelectric memory cells 302 during the first cycle.

[0088] In operation 406, the apparatus may read the set of sign bits from the second ferroelectric memory cell in a second cycle following the first cycle. Figure 3 In the second cycle following the first cycle, the peripheral circuit 310 may read the set of sign bits from the at least one other ferroelectric memory cell 304 .

[0089] In operation 408, the apparatus may perform an error correction operation on a set of storage bits in the second cycle to determine the first value of the set of sign bits written in the first cycle. Figure 3During the second cycle, the peripheral circuit 310 may perform the error correction operation on the set of sign bits to determine the first value of the set of sign bits written during the first cycle. For example, during the second cycle, to perform the error correction operation on the set of sign bits to determine the first value of the set of sign bits, the peripheral circuit 310 may determine whether at least one sign bit in the set of sign bits has reversed to a second value different from the first value. During the second cycle, if a majority of the sign bits in the set of sign bits maintain the first value, the peripheral circuit 310 may determine the first value of the set of sign bits written during the first cycle. For example, if at least two of the three sign bits contain the first value of the reference voltage corresponding to the polarity written during the first cycle, the peripheral circuit 310 may determine that the polarity is the first polarity corresponding to the first value. If the first value of at least one sign bit in the set of sign bits has reversed to the second value, the peripheral circuit 310 may determine that the polarity of the ferroelectric memory cell has reversed due to a defect or noise. The technical implementation and usage pattern ensure that no more than two of the three sign bits will flip to an incorrect state during the device's lifetime. For example, if two of the three sign bits contain a second value that does not correspond to the reference voltage associated with the polarity during the first write cycle, the peripheral circuit 310 may misjudge the polarity of the sign bit (e.g., a second polarity corresponding to the second value) and, further, misjudge the polarity of the data bit. In some embodiments, during the second write cycle, to perform an error correction operation on the set of sign bits to determine whether the polarity of the ferroelectric memory cell flipped due to a defect or noise, if it is determined that none of the sign bits flipped to the second value, the peripheral circuit 310 may determine that the polarity of the ferroelectric memory cell is the polarity corresponding to the write operation during the first write cycle. When the error correction operation includes ECC, the peripheral circuit 310 may read the error correction bit and the sign bit from the corresponding ferroelectric memory cell 304. The peripheral circuit 310 may perform ECC using the read error correction bit and sign bit to determine the correct polarity of the set of ferroelectric memory cells 302.

[0090] In operation 410, the apparatus may invert the sign bits of the set of sign bits to the second value in the second cycle, so that the polarity of the set of sign bits is opposite to the polarity of the sign bits in the previous cycle (i.e., the first cycle), and all sign bits have the same polarity. Figure 3 To mitigate the negative effects of device defects and / or noise sources, the peripheral circuit 310 may invert the polarity of the written data bits and sign bits in alternate cycles. Thus, in the second cycle, the peripheral circuit 310 may invert the sign bits from the first value to the second value.

[0091] In operation 412, the apparatus may write the second data bit into the first ferroelectric memory cell in the second cycle so that the polarity of the second data bit matches the polarity of another set of sign bits written in the second cycle. Figure 3 In the second cycle, the peripheral circuit 310 may write the second data bit into the ferroelectric memory cell 304, and the second data bit has the same polarity as the other set of sign bits written in the second cycle.

[0092] In operation 414, the apparatus may write the other set of sign bits each having a second value into at least one second ferroelectric memory cell before or after writing the second data bit into the first ferroelectric memory cell in the second cycle. Figure 3 In the second cycle, the peripheral circuit 310 may write the other set of sign bits into at least one second ferroelectric memory cell 304, and each sign bit has a second value.

[0093] The foregoing description of the specific embodiments will fully reveal the general concepts of the present application, so that people with skills in other technical fields can easily make various application modifications and / or adjustments to these specific embodiments based on the teachings and guidance disclosed in this application without undue experimentation, and without departing from the general concept of the present application. Therefore, based on the teachings and guidance provided in this application, such modifications and adjustments should be considered to be included in the meaning and scope of equivalents of this application. It should be understood that the words or terms used in this application are for illustrative purposes only and not for limiting purposes. The terms or terms of this application should be interpreted by people with skills in the technical field based on the teachings and guidance disclosed in this application.

[0094] The various embodiments of the present application have been described above with the aid of functional blocks to illustrate how specific functions and their interrelationships are implemented. For ease of description, the boundaries of these functional blocks have been arbitrarily defined in this application. Alternative boundaries may be defined as long as the specific functions and their interrelationships described are properly performed.

[0095] The abstract and brief description of this application may disclose one or more but not all exemplary embodiments conceived by the applicant and are not intended to limit the scope of this application and the appended patent claims in any way.

[0096] The breadth and scope of the present application should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0097] Description of Reference Numerals

[0098] 100, 304 ferroelectric memory cells

[0099] 102, 308, C capacitors

[0100] 104, 306, T transistors

[0101] 106 Interconnection Structure

[0102] 108 substrate

[0103] 110 lower electrode

[0104] 112 upper electrode

[0105] 114 Ferroelectric layer

[0106] 120 Source / drain region

[0107] 122 gate dielectric layer

[0108] 124 gate conductive layer

[0109] 300 Ferroelectric Memory Devices

[0110] 302 A set of ferroelectric memory cells

[0111] 310 Peripheral Circuit

[0112] 400 Operation Method

[0113] 402~404 Operation Steps

[0114] WL word line

[0115] BL bit line

[0116] PL, PL0, PL1 board line

[0117] VC voltage

[0118] CBL Total parasitic capacitance

Claims

1. A method for operating a group of ferroelectric memory cells, comprising: In a first cycle, writing a first data bit into a first ferroelectric memory cell in the group of ferroelectric memory cells; In the first cycle, writing a set of sign bits into at least one second ferroelectric memory cell in the set of ferroelectric memory cells, each sign bit having a first value, and the set of sign bits is used to indicate the polarity of the at least one second ferroelectric memory cell; In a second cycle following the first cycle, reading the set of sign bits from the second ferroelectric memory cell; as well as In the second cycle, an error correction operation is performed on a group of storage bits to determine the first value of the group of sign bits written in the first cycle.

2. The method for operating a ferroelectric memory cell according to claim 1, wherein: In the second cycle, performing an error correction operation on the set of stored bits to determine a first value of the set of sign bits written in the first cycle, comprising: detecting at most one sign bit in the set of sign bits, wherein the at most one sign bit is inverted to a second value different from the first value; When pre-reading or reading the set of sign bits, if a majority of the sign bits maintain the first value, determining that the set of sign bits written in the first cycle is the first value, and correcting the sign bits having the second value to the first value; and When pre-reading or reading the set of sign bits, if the majority of the sign bits maintain the first value, a correction is performed on the single sign bit that is inverted to the second value.

3. The method for operating a ferroelectric memory cell according to claim 2, wherein: In the second cycle, performing the error correction operation on the set of storage bits to determine a first value of the set of sign bits written in the first cycle comprises: If it is determined that none of the sign bits are inverted, it is determined that the read data has the correct polarity. 4 . The method for operating a ferroelectric memory cell according to claim 2 , further comprising: in the second cycle, inverting a sign bit in the set of sign bits from the first value to the second value.

5. The method for operating a ferroelectric memory cell according to claim 4, further comprising: writing a second data bit into the first ferroelectric memory cell in the second cycle, such that the polarity of the second data bit matches the polarity of another set of sign bits.

6. The method for operating a ferroelectric memory cell according to claim 5 , further comprising: in the second cycle, before or after writing the second data bit into the first ferroelectric memory cell, writing the other set of sign bits into at least one of the second ferroelectric memory cells, wherein each sign bit of the other set of sign bits has the second value.

7. The method for operating a ferroelectric memory cell according to claim 1, wherein: The error correction operation includes an error checking and correction (ECC) operation; or The error correction operation includes a majority voting operation.

8. The method for operating a ferroelectric memory cell according to claim 1 , further comprising: In the first cycle, writing a set of error correction bits into at least one third ferroelectric memory cell of the set of ferroelectric memory cells; and In the second cycle, the set of error correction bits is read from at least one of the third ferroelectric memory cells.

9. The method for operating a ferroelectric memory cell according to claim 8, wherein: The error correction operation is performed based on the set of error correction bits.

10. The method for operating a ferroelectric memory cell according to claim 9, wherein: The error correction operation includes an error checking and correction (ECC) operation, and the error checking and correction (ECC) operation uses the error correction bit to determine the correct polarity of each ferroelectric memory cell in the group of ferroelectric memory cells, the ECC code, and the group of sign bits.

11. A storage device comprising: a set of ferroelectric memory cells; and A peripheral circuit is coupled to the set of ferroelectric memory cells, the peripheral circuit being configured to perform: In a first cycle, writing a first data bit into a first ferroelectric memory cell of the group of ferroelectric memory cells; In the first cycle, writing a set of sign bits into at least one second ferroelectric memory cell in the set of ferroelectric memory cells, each sign bit having a first value, and the set of sign bits is used to indicate the polarity of the at least one second ferroelectric memory cell; In a second cycle following the first cycle, reading the set of sign bits from the second ferroelectric memory cell; as well as During the second cycle, an error correction operation is performed on a group of storage bits to determine a first value of the group of sign bits written during the first cycle.

12. The memory device according to claim 11, wherein In the second cycle, the peripheral circuit is configured to perform an error correction operation on the group of storage bits to determine the first value of the group of sign bits written in the first cycle, specifically including: detecting at most one sign bit in the set of sign bits, wherein the at most one sign bit is inverted to a second value different from the first value; When pre-reading or reading the set of sign bits, if a majority of the sign bits maintain the first value, determining that the set of sign bits written in the first cycle is the first value, and correcting the sign bits having the second value to the first value; and When pre-reading or reading the set of sign bits, if most of the sign bits maintain the first value, the sign bits that are inverted to the second value are corrected.

13. The memory device according to claim 12, wherein: In the second cycle, the peripheral circuit is configured to perform an error correction operation on the group of storage bits to determine the first value of the group of sign bits written in the first cycle, specifically including: If it is determined that the first value of the set of sign bits is not inverted to the second value, it is determined that the read data has a correct polarity.

14. The memory device according to claim 12, wherein: The peripheral circuit is further configured to perform: If it is determined that none of the sign bits are inverted, it is determined that the read data has the correct polarity.

15. The memory device according to claim 14, wherein The peripheral circuit is further configured to perform: In the second cycle, a second data bit is written into the first ferroelectric memory cell, so that the polarity of the second data bit matches the polarity of the other set of written sign bits.

16. The memory device according to claim 15, wherein The peripheral circuit is further configured to perform: In the second cycle, before or after writing the second data bit into the first ferroelectric memory cell, the other set of sign bits is written into at least one of the second ferroelectric memory cells, and each sign bit of the other set of sign bits has the second value.

17. The memory device according to claim 11, wherein The error correction operation includes an error checking and correction (ECC) operation; or The error correction operation includes a majority voting operation.

18. The memory device according to claim 11, wherein The peripheral circuit is further configured to perform: In the first cycle, writing a set of error correction bits into at least one third ferroelectric memory cell of the set of ferroelectric memory cells; and In the second cycle, the set of error correction bits is read from at least one of the third ferroelectric memory cells.

19. The memory device according to claim 18, wherein The error correction operation is performed based on the set of error correction bits.

20. The memory device according to claim 19, wherein The error correction operation includes an error checking and correction (ECC) operation, and the error checking and correction (ECC) operation uses the error correction bit to determine the correct polarity of each ferroelectric memory cell in the group of ferroelectric memory cells, the ECC code, and the group of sign bits.

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