Memory device and forming method thereof

Abstract

A memory device includes: a memory element formed of a first inverter and a second inverter cross-coupled to each other; a first transistor having a first conductivity type and connected between a first bit line of the memory element and the first memory node; a second transistor having the first conductivity type and connected between a second bit line of the memory element and a second memory node; and a third transistor having a second conductivity type opposite to the first conductivity type and connected between the first storage node and a third bit line. The embodiment of the invention also discloses a method for forming the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In most cases, this improvement in integration comes from the continuous reduction in minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a memory element formed by a first inverter and a second inverter cross-coupled with each other; a first transistor having a first conductivity type and connected between a first bit line and a first storage node of the memory element; a second transistor having a first conductivity type and connected between a second bit line and a second storage node of the memory element; and a third transistor having a second conductivity type opposite to the first conductivity type and connected between the first storage node and a third bit line.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, including: a memory cell composed of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the memory cell being configured to be read through a first bit line and a first word line, and to be programmed through a second bit line, a third bit line and a second word line; wherein the first to fourth transistors are operable to form a pair of cross-coupled inverters to store data bits using a first storage node and a second storage node; wherein the fifth transistor and the sixth transistor are commonly selected by the second word line and are respectively connected to the second bit line and the third bit line; wherein the seventh transistor is selected by the first word line and is connected to the first bit line; and wherein the fifth transistor and the sixth transistor are configured as p-type, and the seventh transistor is configured as n-type.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming a first active region extending along a first lateral direction and having a first length, the first active region having a first conductivity type; forming a second active region extending along the first lateral direction and having a second length, the second active region being spaced apart from the first active region along a second lateral direction perpendicular to the first lateral direction, the second active region having a second conductivity type, and the second length being longer than the first length; and forming a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, each gate structure extending along the second lateral direction, the first gate structure spanning the second active region, the second gate structure spanning the first active region and the second active region, the third gate structure spanning the first active region and the second active region, the fourth gate structure spanning the second active region, and the fifth gate structure spanning the first active region; wherein the first active region, the second active region, and the first to fifth gate structures are configured to collectively form a static random access memory (SRAM) cell having seven transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. Indeed, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram illustrates an example memory device including a plurality of memory cells according to some embodiments.

[0008] Figure 2 Shown according to some embodiments Figure 1 A circuit diagram of one embodiment of a memory cell.

[0009] Figure 3 It is shown that according to some embodiments, Figure 2 The layout of the memory cells is shown.

[0010] Figure 4 Shown according to some embodiments Figure 2 A cross-sectional view of an embodiment of a memory cell is shown.

[0011] Figure 5 Illustrating the operation according to some embodiments Figure 2 The signal waveform when the memory cell is

[0012] Figure 6 Shown according to some embodiments Figure 1 A circuit diagram of another embodiment of a memory cell.

[0013] Figure 7 It is shown that according to some embodiments, Figure 6 The layout of the memory cells is shown.

[0014] Figure 8 Shown according to some embodiments Figure 1 A circuit diagram of yet another embodiment of a memory cell.

[0015] Figure 9 It is shown that according to some embodiments, Figure 8 The layout of the memory cells is shown.

[0016] Figure 10 Illustrating the operation according to some embodiments Figure 8 The signal waveform when the memory cell is

[0017] Figure 11 Shown according to some embodiments Figure 1 A circuit diagram of yet another embodiment of a memory cell.

[0018] Figure 12 It is shown that according to some embodiments, Figure 11 The layout of the memory cells is shown.

[0019] Figure 13 An example flow chart illustrating a method for fabricating a memory device configured in a GAA transistor or FinFET structure according to some embodiments.

[0020] Figure 14 An example flow chart illustrating a method for fabricating a memory device configured in a CFET structure according to some embodiments is shown. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Furthermore, the present invention may refer to repeated numbers and / or letters in various examples. This repetition is for simplicity and clarity, but does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," "top," etc., may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0023] Integrated circuits often include static random access memory (SRAM) circuits to provide on-chip data storage. SRAM circuits are often configured to meet specific design requirements associated with surrounding circuitry attached to the SRAM circuits. One common type of SRAM circuit provides one port for read or write access to data stored in the SRAM circuit. The address inputs of such circuits are often shared for both read and write access. Another common type of SRAM circuit is known as a dual-port SRAM circuit, which provides two ports for accessing data stored in the SRAM circuit. A dual-port SRAM circuit often restricts all read accesses to one port and all write accesses to a second port. Each port of a dual-port SRAM circuit is often capable of asynchronous and independent access to data stored in the SRAM circuit, allowing the dual-port SRAM circuit to be incorporated into a range of different applications with different usage models.

[0024] Dual-port SRAM circuits allow designers to achieve system performance levels that are often higher than those achieved using only single-port SRAM circuits. However, dual-port SRAM circuits are often subject to the effects of SRAM circuit aging, sometimes referred to as negative bias temperature instability (NBTI). As an SRAM circuit (or its transistor components) ages, the absolute value of the p-type transistor threshold voltage increases, which causes the transistor to turn on more difficultly, resulting in lower conduction current. This can cause various problems with existing dual-port SRAM circuits. For example, existing dual-port (or multi-port) SRAM cells typically include a p-type pass gate transistor that is operably coupled between a storage node of the SRAM cell and a read port (e.g., a read bit line). Due in large part to the presence of NBTI on at least one p-type pull-up transistor of the SRAM cell, existing SRAM cells often exhibit deteriorating static noise margins as the threshold voltage shift on the p-type pull-up transistor increases. Consequently, existing dual-port SRAM circuits are not entirely satisfactory in certain respects.

[0025] The present disclosure provides various embodiments of a memory device comprising a plurality of memory cells, each memory cell being implemented as a multi-port SRAM cell that is relatively or almost immune to NBTI effects even as the disclosed memory device ages. In one aspect, the disclosed SRAM cell is comprised of seven transistors, four of which are operable as a pair of cross-coupled inverters, two of which are operable as write pass gate transistors, and one of which is operable as a read pass gate transistor. In some embodiments, each write pass gate transistor is implemented as a p-type transistor and the read pass gate transistor is implemented as an n-type transistor. In another aspect, the disclosed SRAM cell is comprised of eight transistors, four of which are operable as a pair of cross-coupled inverters, two of which are operable as write pass gate transistors, and two of which are operable as read pass gate transistors. The cross-coupled inverters (the input of the first inverter is connected to the output of the second inverter, and the output of the first inverter is connected to the input of the second inverter) can latch data bits in the storage nodes of the cross-coupled inverters. In some embodiments, write pass-gate transistors coupling a storage node to a corresponding write port (e.g., a write bit line) are each implemented as a p-type transistor, and read pass-gate transistors coupling a storage node to one or more read ports (e.g., a read bit line) are each implemented as an n-type transistor. By coupling the storage node to the read port using n-type transistors, which are relatively immune to NBTI effects compared to p-type transistors, the disclosed SRAM cell advantageously exhibits static noise margins and significantly reduces dependence on aging of the memory device (e.g., the p-type pull-up transistors forming the cross-coupled inverters).

[0026] Figure 1 1 is a block diagram of a memory system, circuit, or device 100 according to various embodiments. The memory device 100 is implemented as an integrated circuit. Figure 1 As shown in the illustrated example, memory device 100 includes a memory controller 105 and a memory array 120. Memory array 120 may include a plurality of memory circuits, memory cells, memory bits, or bit cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be accessed via a plurality of access lines.

[0027] For example, each memory cell 125 may be connected to at least one corresponding word line WL and a pair of corresponding bit lines BL. Each word line WL and bit line BL may include any conductive (e.g., metal) material. For example, each word line WL and bit line BL may be implemented as one or more metal lines. The memory controller 105 may write data into the memory array 120 or read data from the memory array based on electrical signals passing through the word lines WL and bit lines BL. In other embodiments, the memory system 100 includes a plurality of memory cells 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 20 Figure 1More, fewer, or different components than those shown in the drawings may be used and still remain within the scope of the present disclosure.

[0028] Memory array 120 is a hardware component that stores data. In various embodiments, memory array 120 is implemented as a semiconductor memory device. Memory array 120 includes a plurality of memory circuits or memory cells 125, each configured to store at least one bit of data. In some embodiments, memory array 120 includes word lines WL0, WL1, ..., WL J , each word line extends along a first direction, and bit lines BL0, BL1...BL K , each bit line extends along the second direction. The word lines WL and the bit lines BL can be conductive metal or conductive rails. Each memory cell 125 is connected to at least one corresponding word line WL and at least one corresponding bit line BL (for example, each memory cell 125 is formed at the intersection of the corresponding word line WL and the corresponding bit line BL) and can operate based on the voltage or current passing through the corresponding word line WL and the corresponding bit line BL. Each memory cell 125 can be a static random access memory (SRAM) cell. In one embodiment, the memory cell 125 can be implemented as a seven-transistor (7T) SRAM cell or other dual-port SRAM cell. In another embodiment, the memory cell 125 can be implemented as an eight-transistor (8T) SRAM cell or other three-port SRAM cell. However, it should be understood that the memory cell 125 can be implemented in any of a variety of other memory configurations while still within the scope of the present disclosure. In some embodiments, the memory array 120 includes additional lines (for example, sense lines, reference lines, reference control lines, power rails, etc.).

[0029] The memory controller 105 is a hardware component that controls the operation of the memory array 120. In some embodiments, the memory controller 105 includes a bitline controller 112, a wordline controller 114, and a timing controller 116. In various embodiments, the wordline controller 114 is a circuit capable of providing a voltage or current signal through one or more wordlines (WL) of the memory array 120. In various embodiments, the bitline controller 112 is a circuit capable of providing a voltage or current signal through one or more bitlines (BL) of the memory array 120 and sensing a voltage or current from the memory array 120 through the one or more bitlines (BL). In various embodiments, the timing controller 116 is a circuit capable of providing a clock signal for read or write access to the memory array 120. Furthermore, the timing controller 116 may provide control signals or the aforementioned clock signals to the wordline controller 114 and the bitline controller 112, respectively, to synchronize the operations of the bitline controller 112 and the wordline controller 114.

[0030] The bitline controller 112 may be connected to the bitlines BL of the memory array 120, and the wordline controller 114 may be connected to the wordlines WL of the memory array 120. Typically, to write data to the memory cell 125, the wordline controller 114 is configured to apply a voltage or current signal (sometimes referred to as a WL signal) to the memory cell 125 via one or more corresponding wordlines WL connected to the memory cell 125, while the bitline controller 112 is configured to apply a voltage or current signal corresponding to the data bit to be stored to the memory cell 125 via one or more corresponding bitlines BL connected to the memory cell 125. To read a data bit from the memory cell 125, the wordline controller 114 is configured to apply a WL signal to the memory cell 125 via the corresponding wordline WL connected to the memory cell 125, while the bitline controller 112 is configured to sense a voltage or current corresponding to the data bit stored by the memory cell 125 via the corresponding bitline BL connected to the memory cell 125. In some other embodiments, the memory controller 105 may include a memory cell 125 having a plurality of memory cells 125 and a plurality of memory cells 125 having ... Figure 1 More, fewer, or different components than those shown in the drawings may be used and still remain within the scope of the present disclosure.

[0031] Figure 2 Shown according to some embodiments Figure 1 An example circuit diagram 200 of one embodiment of a memory cell 125 is shown in FIG (hereinafter referred to as “memory cell 200”). As disclosed herein, memory cell 200 may sometimes be referred to as a 7TSRAM cell having one read port and one write port. For example, the read port (e.g., including a read bit line RBL and a read word line RWL) may operate according to a first clock signal, while the write port (e.g., including a pair of write bit lines WBL and WBLB and a write word line WWL) may operate according to a second clock signal. However, it should be understood that memory cell 200 may be implemented as any of a variety of other multi-port SRAM cells while remaining within the scope of the present disclosure.

[0032] like Figure 2As shown, the memory cell 200 includes a first pull-up (PU0) transistor, a second pull-up (PU1) transistor, a first pull-down (PD0) transistor, a second pull-down (PD1) transistor, a first write transfer gate (WPG0) transistor, a second write transfer gate (WPG1) transistor, and a read transfer gate (RPG0) transistor. In some embodiments, the PU0 transistor, the PU1 transistor, the WPG0 transistor, and the WPG1 transistor are all implemented as p-type transistors, while the PD0 transistor, the PD1 transistor, and the RPG0 transistor are all implemented as n-type transistors. In one configuration, the n-type transistors and the p-type transistors can be formed as a plurality of gate-all-around (GAA) transistors that are located on a single layer of a substrate. In another configuration, the n-type transistors and the p-type transistors can be formed as a plurality of fin-based transistors (FinFETs) that are located on a single layer of a substrate. In another configuration, the n-type transistors and the p-type transistors can be formed as a plurality of GAA transistors located in respective layers above the substrate, sometimes referred to as a complementary field effect transistor (CFET) structure.

[0033] The PU0 transistor and the PD0 transistor are operable to form a first inverter, and the PU1 transistor and the PD1 transistor are operable to form a second inverter, wherein the first inverter and the second inverter are cross-coupled to each other. For example, the first inverter has an input (node ​​Q) located at the connected gate terminals of the PU0 and PD0 transistors, connected to the output of the second inverter located at the connected drain terminals of the PU1 and PD1 transistors, and has an output (node ​​QB) located at the connected drain terminals of the PU0 and PD0 transistors, connected to the input of the second inverter located at the connected gate terminals of the PU1 and PD1 transistors. The cross-coupled inverters are coupled between power supplies (VDD and VSS) and reinforce each other to maintain one of two possible logic states, wherein a data bit is stored at one node (node ​​Q) between the inverters and the complement of the bit is stored at another node (node ​​QB) between the inverters. Node Q and node QB are sometimes referred to as the first storage node and the second storage node of the memory cell 200, respectively. The WPG0 transistor is coupled between node QB (the second storage node) and the first write bit line WBL, and the WPG1 transistor is coupled between node Q (the first storage node) and the second write bit line WBLB. The gate terminals of the WPG0 and WPG1 transistors are connected to the write word line WWL. The RPG0 transistor is coupled between node QB (the second storage node) and the read bit line RBL. The gate terminal of the RPG0 transistor is connected to the read word line RWL.

[0034] In some embodiments, during standby mode, neither the write word line WWL nor the read word line RWL is set, so the WPG0 transistor and the WPG1 transistor disconnect the memory cell 200 from the write bit line WBL and WBLB, respectively, while the RPG0 transistor disconnects the memory cell 200 from the read bit line RBL. For example, the write word line WWL is pulled up to a logic high state, while the read word line RWL is pulled down to a logic low state. For a read operation, the read bit line RBL can first be precharged to a high logic state, and the read word line RWL is set (e.g., by being pulled up). The data bit stored at node QB can be transferred to the read bit line RBL, whose logic state can be distinguished by a coupled sense amplifier (not shown). For a write operation, when the write word line WWL is set (e.g., by being pulled down), the logic state to be written is provided at the write bit line WBL, and the complement of the logic state is provided at the write bit line WBLB.

[0035] Figure 3 A method for forming a Figure 2 3. The example layout 300 of the memory cell 200 shown in FIG. For example, the layout 300 can be used to form each transistor of the memory cell 200 as a GAA transistor or a FinFET. However, it should be understood that Figure 3 The layout is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0036] like Figure 3 As shown, layout 300 includes patterns for forming active areas 310 and 320, gate structures 330, 332, 334, 336, and 338, respectively. It should be understood that layout 300 may include any number of other patterns to form corresponding active areas or gate structures while still within the scope of the present disclosure. Active areas 310 and 320 may each extend along a first lateral direction (e.g., an X direction), and gate structures 330 to 338 may each extend along a second lateral direction (e.g., a Y direction) that is perpendicular to the first lateral direction. In some embodiments, active areas 310 and 320 may each extend along the X direction and have respective lengths, wherein the length of active area 320 is greater than the length of active area 310. Gate structures 330 to 338 may each span one or more of active areas 310 and 320. For example, gate structure 330 spans only active area 320; gate structure 332 spans active areas 310 and 320; gate structure 334 spans active areas 310 and 320; gate structure 336 spans only active area 310, and gate structure 338 (spaced apart from gate structure 336 in the Y direction but aligned with gate structure 336 in the Y direction) spans only active area 320.

[0037] In a non-limiting example of forming a transistor of the memory cell 200 based on a GAA transistor structure, the active regions 310 and 320 can each be formed as a stacked structure protruding from the front side of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The corresponding portion of the semiconductor nanostructure in the stacked structure that is covered by each of the one or more gate structures 330 to 338 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structure coupled to both ends of the channel (e.g., along the X direction) can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure that covers (e.g., spans) the remaining portion of the semiconductor structure can be configured as a gate terminal of the transistor.

[0038] For example, the gate structure 332 and the active region 310 may form a PD1 transistor, wherein the source / drain terminals of the PD1 transistor are formed in the active region 310 and are located on opposite sides of the gate structure 332; the gate structure 334 and the active region 310 may form a PD0 transistor, wherein the source / drain terminals of the PD0 transistor are formed in the active region 310 and are located on opposite sides of the gate structure 334; the gate structure 336 and the active region 310 may form an RPG0 transistor, wherein the source / drain terminals of the RPG0 transistor are formed in the active region 310 and are located on opposite sides of the gate structure 336; the gate structure 330 and the active region 320 may form a WPG1 transistor, wherein the WPG1 transistor The source / drain terminals are formed in the active area 320 and are located on opposite sides of the gate structure 330; the PU1 transistor can be formed by the gate structure 332 and the active area 320, and the source / drain terminals of the PU1 transistor are formed in the active area 320 and are located on opposite sides of the gate structure 332; the PU0 transistor can be formed by the gate structure 334 and the active area 320, and the source / drain terminals of the PU0 transistor are formed in the active area 320 and are located on opposite sides of the gate structure 334; the WPG0 transistor can be formed by the gate structure 338 and the active area 320, and the source / drain terminals of the WPG0 transistor are formed in the active area 320 and are located on opposite sides of the gate structure 338.

[0039] Layout 300 also includes patterns for forming contact structures 340, 342, 344, 346, 348, 350, and 352, respectively. Contact structures 340 to 352 can each extend along the Y direction and each be interposed between adjacent gate structures. Each of contact structures 340 to 352 is in electrical and physical contact with one or more epitaxial structures formed in the active region (e.g., one or more source / drain terminals of the transistor of memory cell 200). Such contact structures are sometimes referred to as MDs.

[0040] For example, MD 340 is electrically coupled to the first source / drain terminal of the WPG1 transistor; MD 342 is electrically coupled to the second source / drain terminal of the WPG1 transistor (which is also the first source / drain terminal of the PU1 transistor) and the first source / drain terminal of the PD1 transistor; MD 344 is electrically coupled to the second source / drain terminal of the PD1 transistor and the first source / drain terminal of the PD0 transistor; MD 346 is electrically coupled to the second source / drain terminal of the PU1 transistor and the first source / drain terminal of the PU0 transistor; MD 348 is electrically coupled to the second source / drain terminal of the PD0 transistor (which is also the first source / drain terminal of the RPG0 transistor) and the second source / drain terminal of the PU0 transistor (which is also the first source / drain terminal of the WPG0 transistor); MD 350 is electrically coupled to the second source / drain terminal of the RPG0 transistor; and MD 352 is electrically coupled to the second source / drain terminal of the WPG0 transistor.

[0041] use Figure 3 In the illustrated layout 300, gate structures 330 and 338 (gate terminals of the WPG0 and WPG1 transistors, respectively) may be commonly coupled to an interconnect structure (not shown) operable to function as at least a portion of a write word line WWL; gate structure 336 (gate terminal of the RPG0 transistor) may be coupled to another interconnect structure (not shown) operable to function as at least a portion of a read word line RWL; MD 340 operable to function as at least a portion of a write bit line WBLB; MD 350 operable to function as at least a portion of a read bit line RBL; and MD 352 operable to function as at least a portion of a write bit line WBL.

[0042] Figure 4 A cross-sectional view of an example semiconductor structure 400 configured to implement a transistor of the memory cell 200 according to some embodiments is shown. The semiconductor structure 400 is formed based on a CFET structure, in which a transistor having a first conductivity type is formed in a first layer and a transistor having a second conductivity type is formed in a second layer vertically spaced apart from the first layer. As described above, the memory cell 200 can be formed in any of a variety of other transistor structures, and therefore, it should be understood that Figure 4 The semiconductor structure 400 shown in FIG. 4 is not intended to limit the scope of the present disclosure.

[0043] like Figure 4As shown, semiconductor structure 400 includes a first group of mutually vertically spaced semiconductor nanostructures 402, a second group of mutually vertically spaced semiconductor nanostructures 404, a third group of mutually vertically spaced semiconductor nanostructures 406, a fourth group of mutually vertically spaced semiconductor nanostructures 408, a fifth group of mutually vertically spaced semiconductor nanostructures 410, a sixth group of mutually vertically spaced semiconductor nanostructures 412, and a seventh group of mutually vertically spaced semiconductor nanostructures 414. In some embodiments, semiconductor nanostructures 402, 404, 408, and 412 are formed from a first active region 450 in a first layer, and semiconductor nanostructures 406, 410, and 414 are formed from a second active region 460 in a second layer located above the first layer. Each of semiconductor nanostructures 402 to 414 can be formed as a nanosheet extending along a first lateral direction (e.g., the X direction).

[0044] In some embodiments, semiconductor structures 402 to 414 may each include silicon. Alternatively, semiconductor structures 402 to 414 may each include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. Furthermore, each of semiconductor structures 402 to 414 may be undoped, i.e., semiconductor structures 402 to 414 contain no dopant (e.g., having approximately 0 cm -3 to about 1×10 17 cm -3 extrinsic dopant concentrations), where no intentional doping is performed during the growth of these semiconductor structures.

[0045] Semiconductor structure 400 further includes a first gate structure 416, a second gate structure 418, a third gate structure 420, a fourth gate structure 422, and a fifth gate structure 424. Each of gate structures 416 to 424 may extend along a second lateral direction (e.g., the Y direction). Gate structure 416 may wrap around each semiconductor nanostructure 402, gate structure 418 may wrap around each semiconductor nanostructure 404 and each semiconductor nanostructure 406, gate structure 420 may wrap around each semiconductor nanostructure 408 and each semiconductor nanostructure 410, gate structure 422 may wrap around each semiconductor nanostructure 412, and gate structure 424 may wrap around each semiconductor nanostructure 414.

[0046] In some embodiments, each of the gate structures 416 to 424 may include at least one high-k dielectric layer and at least one gate electrode layer. The high-k dielectric layer may include a dielectric material such as HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, oxynitride (SiON), or a combination thereof. The gate electrode layer may include a metal material, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof.

[0047] Semiconductor structure 400 further includes epitaxial structures 430, 432, 434, 436, 438, 440, 442, 444, and 446. Epitaxial structures 430 and 432, located on opposite sides of gate structure 416, are electrically coupled to each semiconductor nanostructure 402. Epitaxial structures 432 and 436, located on opposite sides of gate structure 418, are electrically coupled to each semiconductor nanostructure 404. Epitaxial structures 434 and 438, located on opposite sides of gate structure 418, are electrically coupled to each semiconductor nanostructure 406. Epitaxial structures 436 and 440, located on opposite sides of gate structure 420, are electrically coupled to each semiconductor nanostructure 408. Epitaxial structures 438 and 442, located on opposite sides of gate structure 420, are electrically coupled to each semiconductor nanostructure 410. Epitaxial structures 440 and 444, located on opposite sides of gate structure 422, are electrically coupled to each semiconductor nanostructure 412. Epitaxial structures 442 and 446 located on opposite sides of gate structure 424 are electrically coupled to each semiconductor nanostructure 414. In some embodiments, epitaxial structures 430, 432, 436, 440, and 444 formed in first active region 450 may have a p-type (e.g., have p-type impurities), while epitaxial structures 434, 438, 442, and 446 formed in second active region 460 may have an n-type (e.g., have n-type impurities). Figure 4 As shown, WPG1, PU1, PU0, WPG0, PD1, PD0, and RPG0 transistors can be formed.

[0048] Semiconductor structure 400 also includes contact structures 470, 472, 474, 476, 478, 480, and 482. Contact structure 470 is in electrical contact with epitaxial structure 430 (one of the source / drain terminals of the WPG1 transistor); contact structure 472 is in electrical contact with epitaxial structure 436 (one of the source / drain terminals of the PU1 transistor and one of the source / drain terminals of the PU0 transistor); contact structure 474 is in electrical contact with epitaxial structure 438 (one of the source / drain terminals of the PD1 transistor and one of the source / drain terminals of the PD0 transistor); contact structure 476 is in electrical contact with epitaxial structure 444 (one of the source / drain terminals of the WPG0 transistor); and contact structure 478 is in electrical contact with epitaxial structure 446 (one of the source / drain terminals of the RPG0 transistor). Thus, contact structure 470 can be operatively used as or coupled to a portion of write bit line WBLB, contact structure 472 can be operatively used as or coupled to a power rail carrying VDD, contact structure 474 can be operatively used as or coupled to another power rail carrying VSS, contact structure 476 can be operatively used as or coupled to a portion of write bit line WBL, and contact structure 478 can be operatively used as or coupled to a portion of read bit line RBL. Furthermore, contact structure 480 can electrically connect epitaxial structure 432 (one of the source / drain terminals of the PU1 transistor, which is also one of the source / drain terminals of the WPG1 transistor) to epitaxial structure 434 (one of the source / drain terminals of the PD1 transistor), and contact structure 482 can electrically connect epitaxial structure 440 (one of the source / drain terminals of the PU0 transistor, which is also one of the source / drain terminals of the WPG0 transistor) to epitaxial structure 442 (one of the source / drain terminals of the PD0 transistor, which is also one of the source / drain terminals of the RPG0 transistor).

[0049] Figure 5 2 and 3 show the time-varying operation of the memory cell 200 ( Figure 2 ). For example, the four phases 510, 520, 530, and 540 respectively show waveforms of a clock signal (hereinafter referred to as a “CLKR / CLKW signal”), a signal applied to the write word line WWL (hereinafter referred to as a “WWL signal”), a signal applied to the write bit line WBL (hereinafter referred to as a “WBL signal”), a signal applied to the write bit line WBLB (hereinafter referred to as a “WBLB signal”), a signal present at the node QB (hereinafter referred to as a “D signal”), a signal applied to the read word line RWL (hereinafter referred to as a “RWL signal”), and a signal present at the read bit line RBL (hereinafter referred to as a “RBL signal”).

[0050] In stage 510, a data bit is written to memory cell 200. For example, the WWL signal is pulled low, which activates the WPG0 and WPG1 transistors, and the RWL signal is pulled low or held in a logic low state, which deactivates the RPG0 transistor. Consequently, write bit line WBL (with the WBL signal provided at a logic high state) is coupled to node QB, write bit line WBLB (with the WBLB signal provided at a logic low state) is coupled to node Q, and read bit line RBL (precharged to a logic high state) is disconnected from node QB. Consequently, a logic 1 can be written to node QB (a logic 0 can be written to node Q), as indicated by the D signal.

[0051] In stage 520, the data bit written to memory cell 200 during stage 510 is read. For example, the WWL signal is pulled up or held in a logic high state, which deactivates the WPG0 and WPG1 transistors, and the RWL signal is pulled up, which activates the RPG0 transistor. Consequently, write bit line WBL is disconnected from node QB, and write bit line WBLB is disconnected from node Q. Furthermore, with the RPG0 transistor activated, read bit line RBL is coupled to node QB, allowing the D signal to be transferred to or present on read bit line RBL. Consequently, a logic 1 written to node QB (a logic 0 written to node Q) can be read via the RBL signal.

[0052] In stage 530, another data bit is written to memory cell 200. For example, the WWL signal is pulled low, which activates the WPG0 and WPG1 transistors, and the RWL signal is pulled low or held in a logic low state, which deactivates the RPG0 transistor. Consequently, the write bit line WBL (with the WBL signal provided in a logic low state) is coupled to node QB, the write bit line WBLB (with the WBLB signal provided in a logic high state) is coupled to node Q, and the read bit line RBL (precharged to or held in a logic high state) is disconnected from node QB. Consequently, a logic 0 can be written to node QB (a logic 1 can be written to node Q), as indicated by the D signal.

[0053] In stage 540, the data bit written to memory cell 200 during stage 530 is read. For example, the WWL signal is pulled up or held in a logic high state, which deactivates the WPG0 and WPG1 transistors, and the RWL signal is pulled up, which activates the RPG0 transistor. Consequently, write bit line WBL is disconnected from node QB, and write bit line WBLB is disconnected from node Q. Furthermore, with the RPG0 transistor activated, read bit line RBL is coupled to node QB, allowing the D signal to be transmitted to or present on read bit line RBL. Consequently, a logic 0 written to node QB (a logic 1 written to node Q) can be read via the RBL signal.

[0054] Figure 6 Shown according to some embodiments Figure 1 600 (hereinafter referred to as "memory cell 600") of another embodiment of the memory cell 125 shown in FIG. The memory cell 600 is similar to the memory cell 200 ( Figure 2 ) is basically similar, except that both WPG0 and WPG1 transistors are implemented as n-type transistors. Therefore, the description is not repeated.

[0055] Figure 7 A method for forming a Figure 6 6. The example layout 700 of the memory cell 600 shown in FIG. 7 can be used to form each transistor of the memory cell 600 as a GAA transistor or a FinFET, for example. However, it should be understood that Figure 7 The layout is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0056] like Figure 7 As shown, the layout 700 includes patterns for forming active areas 710, 720 and 730, and gate structures 740, 742, 744, 746 and 748, respectively. It should be understood that the layout 700 can include any number of other patterns to form corresponding active areas or gate structures while still within the scope of the present disclosure. The active areas 710 to 730 can each extend along a first lateral direction (e.g., X direction), and the gate structures 740 to 748 can each extend along a second lateral direction (e.g., Y direction) perpendicular to the first lateral direction. In some embodiments, the active area 720 is between the active areas 710 and 730. The gate structures 740 to 748 can each span one or more of the active areas 710 and 730. For example, gate structure 740 spans only active area 720; gate structure 742 spans active areas 710 and 720; gate structure 744 spans active areas 710 and 720; gate structure 748 spans only active area 720, and gate structure 746 (spaced apart from gate structure 748 in the Y direction but aligned with gate structure 748 in the Y direction) spans only active area 730.

[0057] In a non-limiting example of forming a transistor of the memory cell 600 based on a GAA transistor structure, the active regions 710 to 730 can each be formed as a stacked structure protruding from the front side of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The corresponding portion of the semiconductor nanostructure in the stacked structure that is covered by each of the one or more gate structures 740 to 748 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structure coupled to both ends of the channel (e.g., along the X direction) can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure that covers (e.g., spans) the remaining portion of the semiconductor structure can be configured as a gate terminal of the transistor.

[0058] For example, the gate structure 742 and the active region 720 may form a PD1 transistor, wherein the source / drain terminals of the PD1 transistor are formed in the active region 720 and are located on opposite sides of the gate structure 742; the gate structure 744 and the active region 720 may form a PD0 transistor, wherein the source / drain terminals of the PD0 transistor are formed in the active region 720 and are located on opposite sides of the gate structure 744; the gate structure 746 and the active region 730 may form an RPG0 transistor, wherein the source / drain terminals of the RPG0 transistor are formed in the active region 730 and are located on opposite sides of the gate structure 746; the gate structure 740 and the active region 720 may form a WPG1 transistor, wherein the WPG1 transistor The source / drain terminals are formed in the active area 720 and are located on opposite sides of the gate structure 740; the PU1 transistor can be formed by the gate structure 742 and the active area 710, and the source / drain terminals of the PU1 transistor are formed in the active area 710 and are located on opposite sides of the gate structure 742; the PU0 transistor can be formed by the gate structure 744 and the active area 710, and the source / drain terminals of the PU0 transistor are formed in the active area 710 and are located on opposite sides of the gate structure 744; the WPG0 transistor can be formed by the gate structure 748 and the active area 720, and the source / drain terminals of the WPG0 transistor are formed in the active area 720 and are located on opposite sides of the gate structure 748.

[0059] Layout 700 also includes patterns for forming contact structures 750, 752, 754, 756, 758, 760, and 762, respectively. Contact structures 750 to 762 can each extend along the Y direction and each be interposed between adjacent gate structures. Each of contact structures 750 to 762 is in electrical and physical contact with one or more epitaxial structures formed in the active region (e.g., one or more source / drain terminals of the transistor of memory cell 600). Such contact structures are sometimes referred to as MDs.

[0060] For example, MD 750 is electrically coupled to the first source / drain terminal of the WPG1 transistor; MD 752 is electrically coupled to the second source / drain terminal of the WPG1 transistor (which is also the first source / drain terminal of the PD1 transistor) and the first source / drain terminal of the PU1 transistor; MD 754 is electrically coupled to the second source / drain terminal of the PU1 transistor and the first source / drain terminal of the PU0 transistor; MD 756 is electrically coupled to the second source / drain terminal of the PD1 transistor and the first source / drain terminal of the PD0 transistor; MD 758 is electrically coupled to the second source / drain terminal of the PU0 transistor, the second source / drain terminal of the PD0 transistor (which is also the first source / drain terminal of the WPG0 transistor), and the first source / drain terminal of the RPG0 transistor; MD760 is electrically coupled to the second source / drain terminal of the WPG0 transistor; and MD 784 is electrically coupled to the second source / drain terminal of the RPG0 transistor.

[0061] use Figure 7 In the illustrated layout 700, gate structures 740 and 748 (gate terminals of the WPG0 and WPG1 transistors, respectively) can be commonly coupled to an interconnect structure (not shown) that is operable to serve as at least a portion of a write word line WWL; gate structure 746 (gate terminal of the RPG0 transistor) can be coupled to another interconnect structure (not shown) that is operable to serve as at least a portion of a read word line RWL; MD 750 is operable to serve as at least a portion of a write bit line WBLB; MD 762 is operable to serve as at least a portion of a read bit line RBL; and MD 760 is operable to serve as at least a portion of a write bit line WBL.

[0062] Figure 8 Shown according to some embodiments Figure 1 800 (hereinafter referred to as "memory cell 800") of yet another embodiment of the memory cell 125 shown in FIG. 800 (hereinafter referred to as "memory cell 800"). As disclosed herein, the memory cell 800 may sometimes be referred to as an 8TSRAM cell having two read ports and one write port. For example, a first of the read ports (e.g., including a first read bit line ARBL and a first read word line ARWL) and a second of the read ports (e.g., including a second read bit line BRBL and a second read word line BRWL) may operate according to a first clock signal, and the write port (e.g., including a pair of write bit lines WBL and WBLB and a write word line WWL) may operate according to a second clock signal. However, it should be understood that the memory cell 800 may be implemented as any of a variety of other multi-port SRAM cells while remaining within the scope of the present disclosure.

[0063] like Figure 8As shown, the memory cell 800 includes a first pull-up (PU0) transistor, a second pull-up (PU1) transistor, a first pull-down (PD0) transistor, a second pull-down (PD1) transistor, a first write transfer gate (WPG0) transistor, a second write transfer gate (WPG1) transistor, a first read transfer gate (RPG0) transistor, and a second read transfer gate (RPG1) transistor. In some embodiments, the PU0 transistor, the PU1 transistor, the WPG0 transistor, and the WPG1 transistor are all implemented as p-type transistors, while the PD0 transistor, the PD1 transistor, the RPG0 transistor, and the RPG1 transistor are all implemented as n-type transistors. In one configuration, the n-type transistors and the p-type transistors can be formed as a plurality of all-around gate (GAA) transistors, which are located on a single layer of the substrate. In another configuration, the n-type transistors and the p-type transistors can be formed as a plurality of fin-based transistors (FinFETs), which are located on a single layer of the substrate. In yet another configuration, the n-type transistor and the p-type transistor can be formed as multiple GAA transistors located in corresponding layers above the substrate, sometimes also referred to as a complementary field effect transistor (CFET) structure.

[0064] The PU0 transistor and the PD0 transistor are operable to form a first inverter, and the PU1 transistor and the PD1 transistor are operable to form a second inverter, wherein the first inverter and the second inverter are cross-coupled to each other. For example, the first inverter has an input (node ​​Q) located at the connected gate terminals of the PU0 and PD0 transistors, connected to the output of the second inverter located at the connected drain terminals of the PU1 and PD1 transistors, and has an output (node ​​QB) located at the connected drain terminals of the PU0 and PD0 transistors, connected to the input of the second inverter located at the connected gate terminals of the PU1 and PD1 transistors. The cross-coupled inverters are coupled between power supplies (VDD and VSS) and reinforce each other to maintain one of two possible logic states, wherein a data bit is stored at one node (node ​​Q) between the inverters and the complement of the bit is stored at another node (node ​​QB) between the inverters. Node Q and node QB are sometimes referred to as the first storage node and the second storage node of the memory cell 800, respectively. The WPG0 transistor is coupled between node QB (the second storage node) and the first write bit line WBL, and the WPG1 transistor is coupled between node Q (the first storage node) and the second write bit line WBLB. The gate terminals of the WPG0 and WPG1 transistors are connected to the write word line WWL. The RPG0 transistor is coupled between node QB (the second storage node) and the first read bit line ARBL, and the RPG1 transistor is coupled between node Q (the first storage node) and the second read bit line BRBL. The gate terminal of the RPG0 transistor is connected to the first read word line ARWL, and the gate terminal of the RPG1 transistor is connected to the second read word line BRWL.

[0065] Figure 9 A method for forming a Figure 8 800 is shown in FIG. 800. For example, the layout 900 can be used to form each transistor of the memory cell 800 as a GAA transistor or a FinFET. However, it should be understood that Figure 9 The layout is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0066] like Figure 9 As shown, layout 900 includes patterns for forming active areas 910 and 920, gate structures 930, 932, 934, 936, 938, and 940, respectively. It should be understood that layout 900 can include any number of other patterns to form corresponding active areas or gate structures while still within the scope of the present disclosure. Active areas 910 and 920 can each extend along a first lateral direction (e.g., an X direction), and gate structures 930 to 940 can each extend along a second lateral direction (e.g., a Y direction) that is perpendicular to the first lateral direction. In some embodiments, active areas 910 and 920 can each extend along the X direction and have respective lengths, wherein the length of active area 920 is equal to the length of active area 910. Gate structures 930 to 940 can each span one or more of active areas 910 and 920. For example, gate structure 930 spans only active region 910; gate structure 932 spans only active region 920; gate structure 934 spans both active regions 910 and 920; gate structure 936 spans both active regions 910 and 920; gate structure 938 spans only active region 910; and gate structure 940 spans only active region 920. Furthermore, gate structure 930 is spaced apart from gate structure 932 in the Y direction but aligned with gate structure 932 in the Y direction, and gate structure 938 is spaced apart from gate structure 940 in the Y direction but aligned with gate structure 940 in the Y direction.

[0067] In a non-limiting example of forming a transistor of the memory cell 800 based on a GAA transistor structure, the active regions 910 and 920 can each be formed as a stacked structure protruding from the front side of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The corresponding portion of the semiconductor nanostructure in the stacked structure that is covered by each of the one or more gate structures 930 to 940 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structure coupled to both ends of the channel (e.g., along the X direction) can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure that covers (e.g., spans) the remaining portion of the semiconductor structure can be configured as a gate terminal of the transistor.

[0068] For example, gate structure 934 and active region 910 may form a PD1 transistor, with source / drain terminals of the PD1 transistor formed in active region 910 and located on opposite sides of gate structure 934; gate structure 936 and active region 910 may form a PD0 transistor, with source / drain terminals of the PD0 transistor formed in active region 910 and located on opposite sides of gate structure 936; gate structure 938 and active region 910 may form an RPG0 transistor, with source / drain terminals of the RPG0 transistor formed in active region 910 and located on opposite sides of gate structure 938; gate structure 930 and active region 910 may form an RPG1 transistor, with source / drain terminals of the RPG1 transistor formed in active region 910 and located on opposite sides of gate structure 930; The WPG1 transistor may be formed by a gate structure 932 and an active region 920, with the source / drain terminals of the WPG1 transistor formed in the active region 920 and located on opposite sides of the gate structure 932; the PU1 transistor may be formed by a gate structure 934 and an active region 920, with the source / drain terminals of the PU1 transistor formed in the active region 920 and located on opposite sides of the gate structure 934; the PU0 transistor may be formed by a gate structure 936 and an active region 920, with the source / drain terminals of the PU0 transistor formed in the active region 920 and located on opposite sides of the gate structure 936; the WPG0 transistor may be formed by a gate structure 940 and an active region 920, with the source / drain terminals of the WPG0 transistor formed in the active region 920 and located on opposite sides of the gate structure 940.

[0069] Layout 900 also includes patterns for forming contact structures 950, 952, 954, 956, 958, 960, 962, and 964, respectively. Contact structures 950 to 964 can each extend along the Y direction and each be interposed between adjacent gate structures. Each of contact structures 950 to 964 is in electrical and physical contact with one or more epitaxial structures formed in the active region (e.g., one or more source / drain terminals of the transistor of memory cell 800). Such contact structures are sometimes referred to as MDs.

[0070] For example, MD 950 is electrically coupled to the first source / drain terminal of the RPG1 transistor; MD 952 is electrically coupled to the first source / drain terminal of the WPG1 transistor; MD 954 is electrically coupled to the second source / drain terminal of the RPG1 transistor (which is also the first source / drain terminal of the PD1 transistor) and the second source / drain terminal of the WPG1 transistor (which is also the first source / drain terminal of the PU1 transistor); MD 956 is electrically coupled to the second source / drain terminal of the PD1 transistor and the first source / drain terminal of the PD0 transistor; MD 958 is electrically coupled to the second source / drain terminal of the PU1 transistor and the first source / drain terminal of the PU0 transistor; MD 960 is electrically coupled to the second source / drain terminal of the PD0 transistor (which is also the first source / drain terminal of the RPG0 transistor) and the second source / drain terminal of the PU0 transistor (which is also the first source / drain terminal of the WPG0 transistor); MD 962 is electrically coupled to the second source / drain terminal of the RPG0 transistor; and MD 964 is electrically coupled to the second source / drain terminal of the WPG0 transistor.

[0071] use Figure 9 In the illustrated layout 900, gate structures 932 and 940 (gate terminals of the WPG0 and WPG1 transistors, respectively) can be commonly coupled to an interconnect structure (not shown) that can be operable to serve as at least a portion of a write word line WWL; gate structure 938 (gate terminal of the RPG0 transistor) can be coupled to another interconnect structure (not shown) that can be operable to serve as at least a portion of a read word line ARWL; gate structure 930 (gate terminal of the RPG1 transistor) can be coupled to yet another interconnect structure (not shown) that can be operable to serve as at least a portion of a read word line BRWL; MD952 can be operable to serve as at least a portion of a write bit line WBLB; MD 950 can be operable to serve as at least a portion of a read bit line BRBL; MD 962 can be operable to serve as at least a portion of a read bit line ARBL; and MD 964 can be operable to serve as at least a portion of a write bit line WBL.

[0072] Figure 10 800 ( Figure 8). For example, the four phases 1010, 1020, 1030, and 1040 respectively show the waveforms of the clock signal (hereinafter referred to as the “CLKR / CLKW signal”), the signal applied to the write word line WWL (hereinafter referred to as the “WWL signal”), the signal applied to the write bit line WBL (hereinafter referred to as the “WBL signal”), the signal applied to the write bit line WBLB (hereinafter referred to as the “WBLB signal”), the signal present at the node QB (hereinafter referred to as the “D signal”), the signal applied to the read word line ARWL (hereinafter referred to as the “ARWL signal”), the signal applied to the read word line BRWL (hereinafter referred to as the “BRWL signal”), the signal present at the read bit line ARBL (hereinafter referred to as the “ARBL signal”), and the signal present at the read bit line BRBL (hereinafter referred to as the “BRBL signal”).

[0073] In stage 1010, a data bit is written to memory cell 800. For example, the WWL signal is pulled low, which activates the WPG0 and WPG1 transistors, and the ARWL and BRWL signals are both pulled low or held in a logic low state, which deactivates the RPG0 and RPG1 transistors, respectively. Consequently, write bit line WBL (with the WBL signal provided at a logic high state) is coupled to node QB, write bit line WBLB (with the WBLB signal provided at a logic low state) is coupled to node Q, and read bit lines ARBL and BRBL (each precharged to a logic high state) are disconnected from node QB and node Q, respectively. Consequently, a logic 1 can be written to node QB (and a logic 0 can be written to node Q), as indicated by the D signal.

[0074] In stage 1020, the data bit written to memory cell 800 during stage 1010 is read. For example, the WWL signal is pulled up or maintained in a logic high state, which deactivates the WPG0 and WPG1 transistors, and both the ARWL and BRWL signals are pulled up, which activates the RPG0 and RPG1 transistors, respectively. As a result, write bit line WBL is disconnected from node QB, and write bit line WBLB is disconnected from node Q. Additionally, with the RPG0 transistor activated, read bit line ARBL is coupled to node QB, which allows the D signal to be transmitted to or present on read bit line ARBL. Simultaneously or subsequently, with the RPG1 transistor activated, read bit line BRBL is coupled to node Q, which allows the complement of the D signal to be transmitted to or present on read bit line BRBL. In this way, a logic 1 written to node QB (a logic 0 written to node Q) can be read via the ARBL signal or the BRBL signal.

[0075] In stage 1030, another data bit is written to memory cell 800. For example, the WWL signal is pulled low, which activates the WPG0 and WPG1 transistors. The ARWL and BRWL signals are both pulled low or held in a logic low state, which deactivates the RPG0 and RPG1 transistors, respectively. Consequently, the write bit line WBL (with the WBL signal provided at a logic low state) is coupled to node QB, the write bit line WBLB (with the WBLB signal provided at a logic high state) is coupled to node Q, and the read bit line RBL (precharged to or held in a logic high state) is disconnected from node QB. Consequently, a logic 0 can be written to node QB (a logic 1 can be written to node Q), as indicated by the D signal.

[0076] In stage 1040, the data bit written to memory cell 800 during stage 1030 is read. For example, the WWL signal is pulled up or maintained in a logic high state, which deactivates the WPG0 and WPG1 transistors, and both the ARWL and BRWL signals are pulled up, which activates the RPG0 and RPG1 transistors, respectively. As a result, write bit line WBL is disconnected from node QB, and write bit line WBLB is disconnected from node Q. Additionally, with the RPG0 transistor activated, read bit line ARBL is coupled to node QB, which allows the D signal to be transmitted to or present on read bit line ARBL. Simultaneously or subsequently, with the RPG1 transistor activated, read bit line BRBL is coupled to node Q, which allows the complement of the D signal to be transmitted to or present on read bit line BRBL. In this way, a logic 0 written to node QB (a logic 1 written to node Q) can be read via the ARBL signal or the BRBL signal.

[0077] Figure 11 Shown according to some embodiments Figure 1 1 and 2. The memory cell 125 of FIG. 1 is an exemplary circuit diagram 1100 (hereinafter referred to as “memory cell 1100”) of another embodiment of the memory cell 125 shown in FIG. The memory cell 1100 is similar to the memory cell 8200 ( Figure 8 ) is basically similar, except that both WPG0 and WPG1 transistors are implemented as n-type transistors. Therefore, the description is not repeated.

[0078] Figure 12 A method for forming a Figure 11 1. The example layout 1200 of the memory cell 1100 shown in FIG. 1. For example, the layout 1200 can be used to form each transistor of the memory cell 1100 as a GAA transistor or a FinFET. However, it should be understood that Figure 12 The layout is for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0079] like Figure 12As shown, layout 1200 includes patterns for forming active areas 1210, 1220, 1230, and 1240, and gate structures 1250, 1252, 1254, 1256, 1258, and 1260, respectively. It should be understood that layout 1200 can include any number of other patterns to form corresponding active areas or gate structures while still within the scope of the present disclosure. Active areas 1210 to 1240 can each extend along a first lateral direction (e.g., an X direction), and gate structures 1250 to 1260 can each extend along a second lateral direction (e.g., a Y direction) perpendicular to the first lateral direction. Gate structures 1250 to 1260 can each span one or more of active areas 1210 and 1240. For example, gate structure 1250 spans only active area 1220; gate structure 1252 spans only active area 1230; gate structure 1254 spans active areas 1210 and 1220; gate structure 1256 spans active areas 1210 and 1220; gate structure 1258 spans only active area 1220; and gate structure 1260 spans only active area 1220. Furthermore, gate structure 1250 is spaced apart from gate structure 1252 in the Y direction but aligned with gate structure 1252 in the Y direction, and gate structure 1258 is spaced apart from gate structure 1260 in the Y direction but aligned with gate structure 1260 in the Y direction.

[0080] In a non-limiting example of forming a transistor of the memory cell 1100 based on a GAA transistor structure, the active regions 1210 to 1240 can each be formed as a stacked structure protruding from the front side of the substrate. The stacked structure includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The corresponding portion of the semiconductor nanostructure in the stacked structure that is covered by each of the one or more gate structures 1252 to 1260 is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor structure can be configured as a channel of the corresponding transistor, and the epitaxial structure coupled to both ends of the channel (e.g., along the X direction) can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure that covers (e.g., spans) the remaining portion of the semiconductor structure can be configured as a gate terminal of the transistor.

[0081] For example, gate structure 1254 and active region 1220 may form a PD1 transistor, with source / drain terminals of the PD1 transistor formed in active region 1220 and located on opposite sides of gate structure 1254; gate structure 1256 and active region 1220 may form a PD0 transistor, with source / drain terminals of the PD0 transistor formed in active region 1220 and located on opposite sides of gate structure 1256; gate structure 1260 and active region 1240 may form an RPG0 transistor, with source / drain terminals of the RPG0 transistor formed in active region 1240 and located on opposite sides of gate structure 1260; and an RPG1 transistor may be formed by gate structure 1252 and active region 1230, with source / drain terminals of the RPG1 transistor formed in active region 1230 and located on opposite sides of gate structure 1252. ; The WPG1 transistor can be formed by the gate structure 1250 and the active area 1220, and the source / drain terminals of the WPG1 transistor are formed in the active area 1220 and are located on opposite sides of the gate structure 1250; the PU1 transistor can be formed by the gate structure 1254 and the active area 1210, and the source / drain terminals of the PU1 transistor are formed in the active area 1210 and are located on opposite sides of the gate structure 1254; the PU0 transistor can be formed by the gate structure 1256 and the active area 1210, and the source / drain terminals of the PU0 transistor are formed in the active area 1210 and are located on opposite sides of the gate structure 1256; the WPG0 transistor can be formed by the gate structure 1258 and the active area 1220, and the source / drain terminals of the WPG0 transistor are formed in the active area 1220 and are located on opposite sides of the gate structure 1258.

[0082] Layout 1200 also includes patterns for forming contact structures 1270, 1272, 1274, 1276, 1278, 1280, 1282, and 1284, respectively. Contact structures 1270 to 1284 can each extend along the Y direction and each be interposed between adjacent gate structures. Each of contact structures 1270 to 1284 is in electrical and physical contact with one or more epitaxial structures formed in the active region (e.g., one or more source / drain terminals of the transistor of memory cell 1100). Such contact structures are sometimes referred to as MDs.

[0083] use Figure 12In the illustrated layout 1200, gate structures 1250 and 1258 (gate terminals of the WPG0 and WPG1 transistors, respectively) can be commonly coupled to an interconnect structure (not shown) that can be operable to serve as at least a portion of a write word line WWL; gate structure 1260 (gate terminal of the RPG0 transistor) can be coupled to another interconnect structure (not shown) that can be operable to serve as at least a portion of a read word line ARWL; gate structure 1252 (gate terminal of the RPG1 transistor) can be coupled to yet another interconnect structure (not shown) that can be operable to serve as at least a portion of a read word line BRWL; MD 1270 can be operable to serve as at least a portion of a write bit line WBLB; MD 1272 can be operable to serve as at least a portion of a read bit line BRBL; MD 1284 can be operable to serve as at least a portion of a read bit line ARBL; and MD 1282 can be operable to serve as at least a portion of a write bit line WBL.

[0084] Figure 13 A flowchart illustrating an example method 1300 for forming a memory device (e.g., a memory cell) according to various embodiments of the present invention is shown. For example, the operations of method 1300 may be configured to fabricate a transistor (e.g., a transistor) of a memory cell in a GAA transistor or FinFET structure. Figure 2 200, Figure 6 600, Figure 8 800, Figure 11 1100). Therefore, the following discussion of method 1300 may sometimes refer to the above-mentioned figures. It should be noted that Figure 13 The method 1300 shown is merely an example and is not intended to limit the present disclosure. Figure 13 The order of the operations of method 1300 may be changed, for example, additional operations may be provided before, during, and after method 1300, and some operations may be only briefly described herein.

[0085] Method 1300 begins at operation 1310 by forming a plurality of active regions in a single layer (or level) above a semiconductor substrate, each active region extending along a first lateral direction. Figure 2 ) layout 300( Figure 3) As a representative example, active regions 310 and 320 extending in the X direction can be formed above the semiconductor substrate. The active regions 310 and 320 can be formed as a first stack and a second stack, respectively. In some embodiments, a first and a second stack can be formed on the semiconductor substrate, which are horizontally aligned but spaced apart from each other. In other words, the first and second stacks are formed in a single layer (or level) above the substrate. Each of the first and second stacks includes a first semiconductor layer (e.g., SiGe) and a second semiconductor layer (e.g., Si) alternately stacked on top of each other. The first semiconductor layer can later be replaced with one or more gate structures, and the second semiconductor layer can be configured as a channel of one or more transistors.

[0086] In some embodiments, a blanket stack of first and second semiconductor layers is epitaxially grown on a semiconductor substrate. Each of the first semiconductor layers of the first composition is between a pair of second semiconductor layers of the second composition. The first and second compositions may be different. In one embodiment, the second semiconductor layer is composed of silicon germanium and the first semiconductor layer is composed of silicon. However, other embodiments are possible, including those that provide first and second compositions with different oxidation rates and / or etching selectivities. For example, the epitaxial growth of the stack can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. After the blanket stack is formed, the stack may be arranged based on the corresponding pattern shown in the layout (e.g., Figure 3 310-320, Figure 7 710-730, Figure 9 910-920, Figure 12 1210-1240) form an active area by patterning a blanket stack of first and second semiconductor layers.

[0087] Method 1300 continues with operation 1320 where a plurality of gate structures extending along the second lateral direction are formed. Continuing with layout 300 ( Figure 3 ), gate structures 330 to 338 extending along the Y direction can be formed to span one or more active regions 310-320. In an example, the gate structures 330 to 338 can each be formed as a dummy gate structure that is subsequently removed. After forming dummy gate structures (e.g., 330 to 338) that each cover a corresponding portion of each active region 310-320, the uncovered portion of each active region 310-320 is removed to expose the sidewalls of the second semiconductor layer that are still covered by the dummy gate structure. Next, epitaxial structures serving as source / drain terminals for each transistor can be grown. Next, the dummy gate structures can be replaced with metal gate structures, respectively.

[0088] To form one of the disclosed memory cells, e.g. Figure 2 200 in, layout 300 ( Figure 3 ) can be used to define the active area and the footprint of the gate structure. For example, after forming the active area 310 and the active area 320 that extends further than the active area 310 in the X direction, five gate structures 330, 332, 334, 336 and 338 are formed. The gate structures 330 to 338 each extend in the Y direction and are arranged as follows: Figure 3 The arrangement shown is formed. Furthermore, gate structure 330 is formed across only active region 320 to form the WPG1 transistor; gate structure 332 is formed across both active regions 310 and 320 to form the PD1 and PU1 transistors; gate structure 334 is formed across active regions 310 and 320 to form the PD0 and PU0 transistors; gate structure 336 is formed across only active region 310 to form the RPG0 transistor; and gate structure 338 is formed across only active region 320 to form the WPG0 transistor. Gate structures 336 and 338 are aligned with each other along the Y direction but are spaced apart from each other along the Y direction.

[0089] As another non-limiting example, in forming Figure 8 When the memory cell 800 is used, the layout 900 ( Figure 9 For example, after forming the active region 910 and the active region 920 having substantially the same length in the X direction, six gate structures 930, 932, 934, 936, 938, and 940 are formed. The gate structures 930 to 940 each extend in the Y direction and are arranged as follows. Figure 9 The arrangement shown is formed. In addition, gate structure 930 is formed to span only active region 910 to form the RPG1 transistor; gate structure 932 is formed to span only active region 920 to form the WPG1 transistor; gate structure 934 is formed to span both active regions 910 and 920 to form the PD1 and PU1 transistors; gate structure 936 is formed to span active regions 910 and 920 to form the PD0 and PU0 transistors; gate structure 938 is formed to span only active region 910 to form the RPG0 transistor; and gate structure 940 is formed to span only active region 920 to form the WPG0 transistor. Gate structures 930 and 932 are aligned with each other in the Y direction but spaced apart from each other in the Y direction, and gate structures 938 and 940 are aligned with each other in the Y direction but spaced apart from each other in the Y direction.

[0090] Method 1300 continues with operation 1330 where a plurality of contact structures extending along the second lateral direction are formed. Continuing with the example of layout 300 ( Figure 3), contact structures 340 to 352 extending along the Y direction may be formed above one or more epitaxial structures formed along active regions 310-320. In an example, contact structures 340 to 352 may each be formed as a metal structure to electrically and physically contact one or more corresponding epitaxial structures. Furthermore, according to some embodiments of the present invention, each of contact structures 340 to 352 may be configured to electrically connect the respective source / drain terminals of two transistors or electrically couple the source / drain terminals of a transistor to an access line, such as a read bit line RBL, a write bit line WBL, etc.

[0091] In order to form Figure 2 The memory cell 200 in the embodiment can be realized by using the layout 300 ( Figure 3 ) to define the footprint of the contact structures 340 to 352. For example, before replacing the dummy gate structure with a metal gate structure, an interlayer dielectric (ILD) layer is formed at least above the epitaxial structure. The ILD layer includes a dielectric material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials.

[0092] After forming a metal gate structure having an epitaxial structure (source / drain terminals of the transistor) covered by an ILD layer, a contact structure 340 is formed to contact one of the source / drain terminals of the WPG1 transistor which is part of the write bit line WBLB; a contact structure 342 is formed to connect the respective source / drain terminals of the WPG1 transistor, the PD1 transistor, and the PU1 transistor; a contact structure 344 is formed to connect the respective source / drain terminals of the PD0 transistor and the PD1 transistor to VSS; a contact structure 346 is formed to connect the respective source / drain terminals of the PU0 transistor and the PU1 transistor to VDD; a contact structure 348 is formed to connect the respective source / drain terminals of the WPG0 transistor, the RPG0 transistor, the PD0 transistor, and the PU0 transistor; a contact structure 350 is formed to contact one of the source / drain terminals of the RPG0 transistor which is part of the read bit line RBL; and a contact structure 352 is formed to contact one of the source / drain terminals of the WPG0 transistor which is part of the write bit line WBL.

[0093] Figure 14 A flowchart illustrating an example method 1400 for forming a memory device (e.g., a memory cell) according to various embodiments of the present invention is shown. For example, the operations of method 1400 may be configured to fabricate a transistor (e.g., Figure 2 200, Figure 6 600, Figure 8800, Figure 11 1100). Therefore, the following discussion of method 1400 may sometimes refer to Figure 2 、 Figure 6 、 Figure 8 and Figure 11 It should be noted that Figure 14 The method 1400 shown is merely an example and is not intended to limit the present disclosure. Figure 14 The order of the operations of method 1400 may be changed, for example, additional operations may be provided before, during, and after method 1400, and only certain operations may be briefly described herein.

[0094] The method 1400 begins at operation 1410 by forming a first active region in a first layer (or level) above a semiconductor substrate and forming a second active region in a second layer (or level) above the first layer, each of the first and second active regions extending along a first lateral direction. Figure 4 As a representative example, a first active region 450 including semiconductor structures 402, 404, 408, and 412 formed later is first formed over a semiconductor substrate, and then a second active region 460 including semiconductor structures 406, 410, and 414 formed later is formed. Each of the first and second active regions 450 and 460 may extend along the X-direction. In some embodiments, the first active region 450 and the second active region 460 may be vertically aligned with (or overlap) each other.

[0095] The first active region 450 and the second active region 460 may be formed as a first stack and a second stack, respectively. In some embodiments, the first stack may be formed on a semiconductor substrate at a first level, and the second stack may be formed on a second level above the first level. The first stack and the second stack may be vertically aligned with each other. Each of the first and second stacks includes a first semiconductor layer (e.g., SiGe) and a second semiconductor layer (e.g., Si) alternately stacked on top of each other. The first semiconductor layer may later be replaced with one or more gate structures, and the second semiconductor layer may be configured as a channel for one or more transistors.

[0096] In some embodiments, a blanket stack of first and second semiconductor layers is epitaxially grown on a semiconductor substrate. Furthermore, the blanket stack may include a first set of first and second semiconductor layers and a second set of first and second semiconductor layers, wherein the first and second sets are vertically separated from each other by at least one dielectric layer. The first set may be configured to form a first active region 450, and the second set may be configured to form a second active region 460. Each of the first semiconductor layers of a first composition is interposed between a pair of second semiconductor layers of a second composition. The first and second compositions may be different. In one embodiment, the second semiconductor layer is composed of silicon germanium, while the first semiconductor layer is composed of silicon. However, other embodiments are possible, including those providing first and second compositions with different oxidation rates and / or etch selectivities. For example, the epitaxial growth of the stacked layers may be performed using a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. After forming the blanket stack, the first and second active regions 450 and 460 may be formed by patterning the blanket stack of first and second semiconductor layers based on corresponding patterns specified in the layout. For example, a single pattern may be used to define the first and second active regions 450 and 460 .

[0097] The method 1400 continues with operation 1420 where a plurality of gate structures extending along the second lateral direction are formed. Figure 4 ), gate structures 416 to 422 extending in the Y direction can be formed to span one or more of the first and second active regions 450 and 460. In an example, the gate structures 416 to 422 can each be formed as a dummy gate structure that is subsequently removed. After forming dummy gate structures (e.g., 416 to 422) that each cover a corresponding portion of each active region 450 and 460, the uncovered portion of each active region 450 and 460 is removed to expose the sidewalls of the second semiconductor layer that are still covered by the dummy gate structure. Next, epitaxial structures serving as source / drain terminals for the respective transistors can be grown. Next, the dummy gate structures can be replaced with metal gate structures, respectively.

[0098] For example, after forming the first active region 450 and the second active region 460 extending in the X direction, five gate structures 416, 418, 420, 422, and 424 are formed. The gate structures 416 to 422 each extend in the Y direction and are arranged as follows: Figure 4The arrangement shown is formed. Furthermore, gate structure 416 is formed across active region 450 only to form the WPG1 transistor; gate structure 418 is formed across both active regions 450 and 460 to form the PD1 and PU1 transistors; gate structure 420 is formed across active regions 450 and 460 to form the PD0 and PU0 transistors; gate structure 422 is formed across active region 450 only to form the WPG0 transistor; and gate structure 424 is formed across active region 460 only to form the RPG0 transistor. Gate structures 422 and 424 are aligned with each other in the Z direction but spaced apart from each other in the Z direction.

[0099] The method 1400 continues with operation 1430 where a plurality of contact structures extending along the second lateral direction are formed. Figure 4 ), contact structures 470 to 482 extending along the Y direction may be formed to contact one or more epitaxial structures. In an example, each of contact structures 470 to 482 may be formed as a metal structure to electrically and physically contact one or more corresponding epitaxial structures. Furthermore, according to some embodiments of the present invention, each contact structure 470 to 482 may be configured to electrically connect the respective source / drain terminals of two transistors or electrically couple the source / drain terminals of a transistor to an access line, such as a read bit line RBL, a write bit line WBL, etc.

[0100] After forming the metal gate structure, a contact structure 470 is formed to contact one of the source / drain terminals of the WPG1 transistor which is part of the write bit line WBLB; a contact structure 480 is formed to connect the respective source / drain terminals of the WPG1 transistor, the PD1 transistor, and the PU1 transistor; a contact structure 474 is formed to connect the respective source / drain terminals of the PD0 transistor and the PD1 transistor to VSS; a contact structure 472 is formed to connect the respective source / drain terminals of the PU0 transistor and the PU1 transistor to VDD; a contact structure 482 is formed to connect the respective source / drain terminals of the WPG0 transistor, the RPG0 transistor, the PD0 transistor, and the PU0 transistor; a contact structure 478 is formed to contact one of the source / drain terminals of the RPG0 transistor which is part of the read bit line RBL; and a contact structure 476 is formed to contact one of the source / drain terminals of the WPG0 transistor which is part of the write bit line WBL.

[0101] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes: a memory element formed by a first inverter and a second inverter that are cross-coupled with each other; a first transistor having a first conductivity type and connected between a first bit line of the memory element and a first storage node; a second transistor having the first conductivity type and connected between a second bit line of the memory element and a second storage node; and a third transistor having a second conductivity type opposite to the first conductivity type and connected between the first storage node and a third bit line.

[0102] In some embodiments, the first conductivity type is p-type, and the second conductivity type is n-type.

[0103] In some embodiments, the first transistor has a first gate terminal, the second transistor has a second gate terminal, and the first gate terminal and the second gate terminal are connected to a first word line.

[0104] In some embodiments, the third transistor has a third gate terminal connected to the second word line.

[0105] In some embodiments, when programming the storage element, the first word line is configured to be in a logic low state and the second word line is configured to be in a logic low state.

[0106] In some embodiments, when reading the storage element, the first word line is configured to be at a logic high state and the second word line is configured to be at a logic high state.

[0107] In some embodiments, the first bit line and the second bit line are configured to program the storage element.

[0108] In some embodiments, the third bit line is configured to read the storage element.

[0109] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell consisting of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the memory cell being configured to be read via a first bit line and a first word line and programmed via a second bit line, a third bit line, and a second word line. The first to fourth transistors are operable to form a pair of cross-coupled inverters to store data bits using a first storage node and a second storage node. The fifth and sixth transistors are commonly selected by the second word line and are connected to the second bit line and the third bit line, respectively. The seventh transistor is selected by the first word line and is connected to the first bit line. The fifth and sixth transistors are configured as p-type, and the seventh transistor is configured as n-type.

[0110] In some embodiments, the fifth transistor is connected between the second bit line and the first storage node, and the sixth transistor is connected between the third bit line and the second storage node.

[0111] In some embodiments, the seventh transistor is connected between the first storage node and the first bit line.

[0112] In some embodiments, the first transistor and the second transistor are operable to form a first inverter of a pair of inverters, with respective gate terminals connected to the second storage node.

[0113] In some embodiments, the third transistor and the fourth transistor are operable to form a second inverter of a pair of inverters, with respective gate terminals connected to the first storage node.

[0114] In some embodiments, when programming the memory cell with the data bit, the second word line is configured to be in a logic low state and the first word line is configured to be in a logic low state.

[0115] In some embodiments, when reading a data bit from a memory cell, the second word line is configured to be in a logic high state and the first word line is configured to be in a logic high state.

[0116] In some embodiments, the memory cells are static random access memory cells.

[0117] In another aspect of the present disclosure, a method for forming a memory device is disclosed. The method includes forming a first active region extending along a first lateral direction and having a first length, the first active region having a first conductivity type. The method includes forming a second active region extending along the first lateral direction and having a second length, the second active region being spaced apart from the first active region along a second lateral direction perpendicular to the first lateral direction, the second active region having a second conductivity type, and the second length being longer than the first length. The method includes forming a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, each gate structure extending along the second lateral direction, the first gate structure spanning the second active region, the second gate structure spanning the first and second active regions, the third gate structure spanning the first and second active regions, the fourth gate structure spanning the second active region, and the fifth gate structure spanning the first active region. The first active region, the second active region, and the first to fifth gate structures are configured to collectively form a static random access memory (SRAM) cell having seven transistors.

[0118] In some embodiments, the first conductivity type is n-type, and the second conductivity type is p-type.

[0119] In some embodiments, the first active region includes a plurality of first nanostructures vertically spaced apart from one another, and the second active region includes a plurality of second nanostructures vertically spaced apart from one another.

[0120] In some embodiments, the first active region is formed in a first level, and the second active region is formed in a second level vertically spaced apart from the first level.

[0121] As used herein, the words "about" and "approximately" generally refer to a value of a given quantity that may vary based on the particular technology node associated with the subject semiconductor device. Based on the particular technology node, the word "about" may refer to a value of a given quantity that varies within, for example, 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0122] The components of several embodiments have been discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device comprising: a storage element formed by a first inverter and a second inverter cross-coupled with each other; a first transistor having a first conductivity type and connected between the first bit line and a first storage node of the storage element; a second transistor having the first conductivity type and connected between a second bit line and a second storage node of the storage element; as well as The third transistor has a second conductivity type opposite to the first conductivity type and is connected between the first storage node and a third bit line.

2. The memory device according to claim 1, wherein The first transistor has a first gate terminal, the second transistor has a second gate terminal, and the first gate terminal and the second gate terminal are connected to a first word line.

3. The memory device according to claim 2, wherein: The third transistor has a third gate terminal connected to the second word line.

4. The memory device according to claim 3, wherein: When programming the storage element, the first word line is configured to be in a logic low state, and the second word line is configured to be in the logic low state.

5. The memory device according to claim 3, wherein: When reading the storage element, the first word line is configured to be in a logic high state, and the second word line is configured to be in the logic high state.

6. A storage device comprising: a memory cell composed of a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, the memory cell being configured to be read via a first bit line and a first word line and to be programmed via a second bit line, a third bit line, and a second word line; wherein the first to fourth transistors are operable to form a pair of cross-coupled inverters to store data bits using a first storage node and a second storage node; wherein the fifth transistor and the sixth transistor are both selected by the second word line and are connected to the second bit line and the third bit line respectively; wherein the seventh transistor is selected by the first word line and connected to the first bit line; and The fifth transistor and the sixth transistor are configured as p-type, and the seventh transistor is configured as n-type.

7. The memory device according to claim 6, wherein: The fifth transistor is connected between the second bit line and the first storage node, and the sixth transistor is connected between the third bit line and the second storage node.

8. The memory device according to claim 6, wherein: The first transistor and the second transistor are operable to form a first inverter of the pair of inverters, with respective gate terminals connected to the second storage node.

9. A method of forming a memory device, comprising: forming a first active region extending along a first lateral direction and having a first length, the first active region having a first conductivity type; forming a second active region extending along the first lateral direction and having a second length, the second active region being spaced apart from the first active region along a second lateral direction perpendicular to the first lateral direction, the second active region having a second conductivity type, and the second length being longer than the first length; as well as forming a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure, each gate structure extending along the second lateral direction, the first gate structure spanning the second active area, the second gate structure spanning the first active area and the second active area, the third gate structure spanning the first active area and the second active area, the fourth gate structure spanning the second active area, and the fifth gate structure spanning the first active area; The first active region, the second active region, and the first to fifth gate structures are configured to jointly form a static random access memory cell having seven transistors.

10. The method according to claim 9, wherein: The first active region includes a plurality of first nanostructures vertically spaced apart from one another, and the second active region includes a plurality of second nanostructures vertically spaced apart from one another.

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