Memory system, control method thereof, and readable storage medium

Abstract

The embodiment of the invention discloses a memory system and a control method thereof. The memory system comprises a memory device; and a memory controller coupled thereto; the memory device includes a plurality of memory cells, each of the plurality of memory cells configured to store one of a plurality of data states; the memory controller is configured to: perform a read operation using a trial read voltage corresponding to a selected data state of the plurality of data states; obtaining the number of the storage units of which the threshold voltages meet a preset condition; wherein the preset condition comprises that the threshold voltage is smaller than or equal to the trial reading voltage; or the threshold voltage is greater than or equal to the trial reading voltage; determining a difference between the number and an expected number; obtaining at least one rereading voltage according to the difference value, the mapping relation and a rereading meter; the mapping relation comprises a corresponding relation between the expected voltage deviation value and the difference value.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly, to a memory system and a control method thereof, and a readable storage medium. Background Art

[0002] Memory is a storage device used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has become a mainstream product in the memory market due to its high storage density, manageable production costs, suitable programming and erasing speeds, and retention characteristics.

[0003] However, as people's requirements for memory continue to increase, there are still many problems when the memory and its system perform read and write operations. Summary of the Invention

[0004] According to some aspects of the embodiments of the present disclosure, a memory system is provided, comprising: a memory device; and a memory controller coupled thereto; the memory device comprising a plurality of memory cells, each of the plurality of memory cells being configured to store one of a plurality of data states; the memory controller being configured to: perform a read operation using a trial read voltage corresponding to a selected data state from the plurality of data states; obtain the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition comprises: a threshold voltage less than or equal to the trial read voltage; or a threshold voltage greater than or equal to the trial read voltage; determine a difference between the number and an expected number; and obtain at least one reread voltage based on the difference, a mapping relationship, and a reread table; the mapping relationship comprises a correspondence between an expected voltage offset value and the difference.

[0005] In some embodiments, the quantity includes a first quantity in which the threshold voltage of the multiple storage cells is less than or equal to the trial read voltage; the expected quantity includes a first expected quantity, which is a set quantity when the threshold voltage of the multiple storage cells is less than or equal to the default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected quantity; the memory controller is also configured to: obtain a first expected voltage offset value based on a first difference between the first quantity and the first expected quantity, the first mapping relationship, and the voltage difference between the trial read voltage and the default read voltage; and obtain at least one first voltage offset value from the reread table based on the first expected voltage offset value.

[0006] In some embodiments, the at least one first voltage offset value is stored in the reread table in order of size.

[0007] In some embodiments, among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

[0008] In some embodiments, the memory controller is further configured to: generate an offset value interval based on the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value interval; and obtain at least one of the first voltage offset values ​​within the offset value interval from the reread table.

[0009] In some embodiments, the maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

[0010] In some embodiments, the memory controller is further configured to: obtain a plurality of adjacent first voltage offset values ​​from the reread table.

[0011] In some embodiments, the storage cell is a multi-bit storage cell, and each of the multiple data states is distinguished by multi-level read voltages; the reread table stores the second voltage offset value corresponding to at least one level of read voltage; wherein the second voltage offset value corresponding to the highest level read voltage is stored in order of size; and the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest level read voltage.

[0012] In some embodiments, the multi-level read voltages are divided into multiple groups; the reread table includes multiple reread sub-tables, and one of the reread sub-tables stores the second voltage offset value corresponding to at least one first-level read voltage in the group; the second voltage offset value corresponding to the highest-level read voltage is stored in the reread sub-table in order of size; wherein, the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-level read voltage in the storage sub-table.

[0013] In some embodiments, a first number of the plurality of memory cells having a threshold voltage lower than the test read voltage is greater than a second number of the plurality of memory cells having a threshold voltage higher than the test read voltage.

[0014] In some embodiments, the memory controller is configured to: sum the default read voltage with each of the first voltage offset values ​​to obtain the corresponding re-read voltage.

[0015] According to some aspects of the embodiments of the present disclosure, a method for controlling a memory system is provided, comprising: performing a read operation on a plurality of memory cells using a trial read voltage corresponding to a selected data state from a plurality of data states; each of the plurality of memory cells being configured to store one of the plurality of data states; obtaining the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition comprises: a threshold voltage less than or equal to the trial read voltage; or a threshold voltage greater than or equal to the trial read voltage; determining a difference between the number and an expected number; obtaining at least one reread voltage based on the difference, a mapping relationship, and a reread table; the mapping relationship comprising a correspondence between an expected voltage offset value and the difference.

[0016] In some embodiments, the number includes a first number of the plurality of memory cells whose threshold voltage is less than or equal to the test read voltage; the expected number includes a first expected number, which is a set number of the plurality of memory cells when the threshold voltage is less than or equal to a default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected number; and the control method further includes:

[0017] Obtaining a first expected voltage offset value according to a first difference between the first quantity and the first expected quantity, the first mapping relationship, and a voltage difference between the trial read voltage and the default read voltage;

[0018] At least one first voltage offset value is obtained from the rereading table according to the first expected voltage offset value.

[0019] In some embodiments, the at least one first voltage offset value is stored in the reread table in order of size.

[0020] In some embodiments, among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

[0021] In some embodiments, the control method further includes: generating an offset value interval based on the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value interval; and obtaining at least one first voltage offset value within the offset value interval from the rereading table.

[0022] In some embodiments, the maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

[0023] In some embodiments, the control method further includes: acquiring a plurality of adjacent first voltage offset values ​​from the rereading table.

[0024] In some embodiments, the storage cell is a multi-bit storage cell, and each of the multiple data states is distinguished by multi-level read voltages; the reread table stores the second voltage offset value corresponding to at least one level of read voltage; wherein the second voltage offset value corresponding to the highest level read voltage is stored in order of size; and the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest level read voltage.

[0025] In some embodiments, the multi-level read voltages are divided into multiple groups; the reread table includes multiple reread sub-tables, and one of the reread sub-tables stores the second voltage offset value corresponding to at least one first-level read voltage in the group; the second voltage offset value corresponding to the highest-level read voltage is stored in the reread sub-table in order of size; wherein, the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-level read voltage in the storage sub-table.

[0026] In some embodiments, a first number of the plurality of memory cells having a threshold voltage lower than the test read voltage is greater than a second number of the plurality of memory cells having a threshold voltage higher than the test read voltage.

[0027] In some embodiments, the control method further includes: summing the default read voltage with each of the first voltage offset values ​​to obtain the corresponding re-read voltage.

[0028] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and the computer program implements the control method when executed.

[0029] An embodiment of the present disclosure provides a memory system, wherein a storage unit in a memory device is configured to store one of a plurality of data states, and a memory controller is configured to perform a read operation using a trial read voltage corresponding to a selected data state from the plurality of data states; obtain a number whose threshold voltage is less than or equal to the trial read voltage, or obtain a number whose threshold voltage is greater than or equal to the trial read voltage; determine a difference between the number and an expected number, and obtain a voltage offset value from a reread table based on a mapping relationship between the difference, an expected voltage offset value, and the difference, and obtain a reread voltage based on the voltage offset value; compared with a solution of directly accessing the reread table, the embodiment of the present disclosure can reduce the number of accesses to the reread table, improve the utilization efficiency of the reread table, and thus improve the operating speed of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of an exemplary system according to an embodiment of the present disclosure;

[0031] Figure 2a is a schematic diagram of an exemplary memory card according to an embodiment of the present disclosure;

[0032] Figure 2b is a schematic diagram of an exemplary solid-state drive according to an embodiment of the present disclosure;

[0033] Figure 3 is a schematic diagram of an exemplary memory device according to an embodiment of the present disclosure;

[0034] Figure 4 is an exemplary cross-sectional schematic diagram showing a memory cell array according to an embodiment of the present disclosure;

[0035] Figure 5 is a schematic diagram of another exemplary memory device according to an embodiment of the present disclosure;

[0036] Figure 6 is a schematic diagram of a reading operation flow according to an embodiment of the present disclosure;

[0037] Figure 7 is a schematic diagram of an exemplary memory system according to an embodiment of the present disclosure;

[0038] Figure 8 is an exemplary rereading representation diagram according to an embodiment of the present disclosure;

[0039] Figure 9 is a schematic diagram of an exemplary threshold voltage according to an embodiment of the present disclosure;

[0040] Figure 10 is another exemplary threshold voltage diagram according to an embodiment of the present disclosure;

[0041] Figure 11 is a schematic diagram showing a bit quantity distribution according to an embodiment of the present disclosure;

[0042] Figure 12 is a schematic diagram showing a voltage offset value reading according to an embodiment of the present disclosure;

[0043] Figure 13 is a schematic diagram of an exemplary trial reading voltage according to an embodiment of the present disclosure;

[0044] Figure 14 is a schematic diagram showing an exemplary distribution of the number of storage units according to an embodiment of the present disclosure;

[0045] Figure 15 is a schematic diagram showing an exemplary mapping relationship according to an embodiment of the present disclosure;

[0046] Figure 16is another exemplary rereading representation diagram according to an embodiment of the present disclosure;

[0047] Figure 17 is a schematic diagram showing an exemplary correspondence relationship of a rereading table according to an embodiment of the present disclosure;

[0048] Figure 18 is a schematic diagram showing a correspondence relationship between voltage offset values ​​of multiple data states according to an embodiment of the present disclosure;

[0049] Figure 19 The figure is a flow chart of a memory system control method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0051] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0052] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. When used herein, the singular forms "a," "an," and "said / the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising," when used in this specification, determine the presence of the features, integers, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] It should be understood that “some embodiments” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, “in some embodiments” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments if there is no conflict.

[0054] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0055] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0056] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0057] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction code (ECC) on data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Mini Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0058] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown in FIG, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0059] Figure 3 FIG. 1 is a schematic circuit diagram illustrating an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 3. An example of a memory device 104 in FIG. Memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to memory cell array 301. Memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0060] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, while a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0061] like Figure 3 As shown in FIG, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0062] like Figure 3As shown in FIG, a NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304a, the source lines 314 coupled to the selected memory block 304a and the unselected memory blocks 304b in the same plane as the selected memory block 304a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-memory block level, at the quarter-memory block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. Figure 4 1 shows a cross-sectional schematic diagram of an exemplary memory cell array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 alternately stacked in sequence, and a memory string 308 vertically extending through the gate layers 411 and insulating layers 412. Gate layers 411 and insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in stacked structure 410 may determine the number of memory cells included in memory cell array 301.

[0063] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0064] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0065] In some embodiments, NAND memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel comprises silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer comprising a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0066] Return Reference Figure 3 , the peripheral circuit 302 may be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 5 Additional peripheral circuits not shown.

[0067] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one memory page of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0068] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0069] In some specific embodiments, the programming operation may include multiple phases. For example, the programming operation may include a channel precharge phase, a channel boost phase, a programming pulse phase, and a recovery phase. During the channel precharge phase, a voltage generator may generate voltages required for the subsequent phase, such as voltages applied to each gate and a channel boost voltage. During the channel boost phase, a channel boost voltage may be applied to the selected word line. During the programming pulse phase, a target voltage for each programming operation may be applied to the selected word line. During the recovery phase, the voltage of both the unselected and selected word lines may be reduced to a corresponding lower voltage, such as Vcc or Vdd. During the recovery phase, the voltage may be reduced to the corresponding voltage in one or more steps, such as by first reducing the voltage to an intermediate voltage and maintaining it at the intermediate voltage for a period of time before finally reducing the voltage to the corresponding voltage.

[0070] The control logic 512 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0071] In some embodiments, the memory cells of the NAND memory can be divided into single-layer memory cells (one-bit memory cells), double-layer memory cells (two-bit memory cells), triple-layer memory cells (three-bit memory cells), quad-layer memory cells (four-bit memory cells), and five-layer memory cells (five-bit memory cells) according to the storage density. However, regardless of whether it is a single-layer memory cell or a multi-layer memory cell, its read operation can be performed in units of pages. Specifically, when performing a read operation, a read voltage is applied to the word line coupled to the selected page in the memory device 104 (i.e., the selected word line). When the read voltage reaches the threshold voltage of multiple memory cells coupled to the selected word line, or the number of memory cells that have not reached the threshold voltage is within the allowable range, the read operation of the entire page is terminated. The memory cell can be an M-bit memory cell, and the memory cell has 2 states including an erased state. M data states, through 2 MA -1-level read voltage is used to read M bits of stored data. For example, the first-level read voltage is between the threshold voltages of the erased state and the first data state. When the first-level read voltage is applied to the word line, memory cells in the erased state are turned on, while memory cells in the first data state are not turned on. The erased state and the first data state are distinguished and read out.

[0072] It should be noted that during the read operation, storage cells that have not reached the target threshold voltage are marked as error bits. In order to prevent read errors, an error correction code (ECC) is introduced. When the number of error bits is less than or equal to the maximum number of failed bits that the error correction code can correct, the error bits in the read operation can be corrected, so that the data can be read correctly.

[0073] In some embodiments, the host 108 sends a read command (or read instruction, or read request) to the memory controller 106 based on the current user command request. The memory controller 106 transmits the read control command, including information such as a logical address-physical address mapping table, to the memory device 104 via the interface 516, controlling the memory device 104 to perform a read operation on the memory cell corresponding to the corresponding physical address. The memory device 104 then sends the read data to the memory controller 106 via the interface 516, and the memory controller 106 feeds the data back to the host 108 via an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device via the interface 516. The control logic applies the corresponding operating voltage to the selected word line or bit line based on the corresponding physical address, thereby performing a read operation on the corresponding memory cell. The control logic can generate the corresponding operating voltage by controlling a voltage generator based on the corresponding read voltage mapping table, which is then decoded by a row decoder and applied to the word line corresponding to the address, or applied to the bit line corresponding to the address by a column decoder.

[0074] In some other embodiments, when the memory device 104 reads the corresponding storage unit under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 (or the error correction module in the memory controller 106) controls the memory device 104 to perform error correction in response to the failure of the read operation. The error correction mode may include ECC error correction. According to some aspects of the embodiments of the present disclosure, Figure 6 FIG. 1 is a schematic diagram showing an exemplary read operation flow of the memory system 102. Figure 6As shown, when the memory controller 106 controls the memory device 104 to perform a read operation, a default read operation (default read) is first performed on the memory cell of the corresponding physical address. If the default read fails, the reread table (RRT) is accessed to obtain a voltage offset value and the voltage offset value is added to the default read voltage to obtain a reread voltage for performing a reread operation (Readretry). Hard bit decoding (HB decoding) can be applied to the reread operation and the default read operation. If the reread operation fails, an optimal reread operation (Find optimal read level) is entered, which can also be called a valley voltage search operation. A positive or negative offset is performed based on the default read voltage or the read voltage of the current read failure. The optimal read voltage is obtained by increasing or decreasing the voltage value to perform a read operation on the memory cell. When performing a read operation with the re-determined optimal read voltage, hard decoding or soft bit decoding (SB decoding) can be applied, or soft decoding can be applied if hard decoding fails. If the optimal read voltage fails to be read, a soft decoding operation (Soft decoding flow) or a soft decision operation is performed. The soft decoding operation may include a hard read (HB The hard-read data is hard-decoded or the LLR (Log Likelihood Rate) table is not updated according to the LDPC algorithm. The soft decoding operation may also include a soft bit read (SB read), and the soft-read data is soft-decoded. If the soft decoding operation fails, a redundant array of independent disks (RAID) operation or a redundant array of independent NAND (RAIN) operation is performed. If the RAID or RAIN operation fails, the ECC error correction operation stops and the read fails due to the inability to correct the error. The memory controller 106 sends a read failure (Readfail) or UECC signal to the host 108.

[0075] Exemplarily, RAID can be disk-level data recovery. One memory device 104 can serve as a disk, and multiple disks form a disk array. When data in one or more disks is read incorrectly, the erroneous data can be recovered using checksum data and data in disks that have not experienced errors. Checksum data can be generated based on write data during the disk write phase. RAIN can be called NAND-level RAID. For memory devices 104, including NAND storage arrays, checksum data can be generated based on programming data of multiple data blocks during the programming phase. The checksum data can be stored in the OP (Over-provisioning) area of ​​the memory device 104. A data block can include data from one storage unit or multiple storage units on a word line. When data in a data block or multiple data blocks is read incorrectly, the erroneous data can be recovered based on the checksum data and the data that has not experienced errors.

[0076] Error correction operations such as reread operations, searching for optimal read voltages, soft decoding operations, and RAID operations can be controlled by the error correction module 1064 (e.g., an ECC module) in the memory controller 106 to perform the memory device 104. The memory controller 106 sends control commands to the memory device 104 via the interface 516, and the memory device 104 feeds back read information to the memory controller 106 via the interface 516. It should be noted that after any of the reread operations, soft decoding operations, and RAID operations are successfully completed, subsequent operations may be stopped.

[0077] In some specific embodiments, a soft decoding operation can be understood as re-decoding data by a decoding unit 1066 (e.g., a soft decoder) in the memory controller 106, and then performing a read operation based on the re-decoded data. A RAID operation can be understood as mirroring data through secondary encoding to reconstruct stored data and parity data. The redundant array re-encoding of the stored data is typically performed in the data buffer 1067 of the memory controller 106.

[0078] According to some aspects of the embodiments of the present disclosure, Figure 7 A block diagram of a memory system 102 including a memory controller 106 and an error correction module 1064 is provided. Figure 7As shown, the memory system 102 includes a memory controller 106 and a memory. The memory controller 106 and the memory device 104 can be coupled in any suitable manner. In the embodiment of the present disclosure, the memory controller 106 includes a host I / F 1061, a memory I / F 1062, a control unit 1063, an error correction (ECC) module 1064, a data buffer 1067, and an internal bus 1060. The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The host I / F 1061 outputs commands and user data (write data) received from the host 108 to the internal bus 1060, and sends user data (read data) read from the memory device 104 and responses from the control unit 1063 to the host 108.

[0079] The memory I / F controls the writing of user data and the like to and from the memory device 104 based on instructions from the control unit 1063. The control unit 1063, such as a central processing unit (CPU) or a microprocessor (MPU), controls the entire memory system 102. Upon receiving commands from the host 108 via the host I / F 1061, the control unit 1063 performs control based on these commands. For example, the control unit 1063 instructs the memory I / F to write user data and parity to the memory device 104 based on a command from the host 108. Furthermore, the control unit 1063 instructs the memory I / F to read user data and parity from the memory device 104 based on a command from the host 108.

[0080] The error correction module 1064 includes an encoding unit 1065 and a decoding unit 1066. The encoding unit 1065 encodes user data of a predetermined size written in the same page to generate parity data. The parity data is written to the page where the user data serving as the basis for the encoding has been written, and the decoding unit 1066 decodes the data using this parity data. The data buffer 1067 temporarily stores user data received from the host 108 before storing it in the memory device 104, and temporarily stores data read from the memory device 104 before sending it to the host 108.

[0081] In some embodiments, Figure 6 The process for determining the reread voltage during a reread operation may include: the error correction module 1064 in the memory controller 106 queries a corresponding reread table to obtain a corresponding voltage offset value, which may be a positive offset value or a negative offset value, and sums the voltage offset value with the default read voltage to obtain the reread voltage. The memory controller 106 controls the memory device 104 to perform a reread operation on the memory cell at the corresponding physical address using the reread voltage. Figure 8The exemplary form of a reread table is shown for illustration only, and the embodiments of the present disclosure do not limit the form of the reread table. The reread table can store or record multiple levels of read voltages to distinguish multiple data states of a memory cell, such as Figure 8 The voltage offset values ​​corresponding to the read voltages Rd1 to Rd7 are stored in , and the RR-m entries store the read voltage offset values. Rd1 to Rd7 are used to read the data of the TLC memory cell. The seven-level read voltage is used to distinguish the eight data states including the erased state. For memory cells with a higher storage bit count, such as QLC memory cells, which have 16 data states, the 16 data states are distinguished using the Rd1 to Rd15-level read voltages. The correspondence between the read voltages Rd1 to Rd15 and the data states L0 to L15 can be shown as follows: Figure 10 As shown, the reread table at this time can record the voltage offset value corresponding to the voltage read by Rd1~Rd15. Figure 10 In the process, a read operation is performed on the memory cell. The memory cell with a threshold voltage less than Rd1 is in the erase state L0, the memory cell with a threshold voltage between Rd1 and Rd2 is in the L1 state, the memory cell with a threshold voltage between Rd2 and Rd3 is in the L2 state, and the memory cell with a threshold voltage greater than Rd15 is in the L15 state.

[0082] It should be noted that the memory controller 106 may adopt a polling method when querying the reread table. A reread table may include multiple sub-tables, such as m sub-tables, or Figure 8 The memory device 104 includes multiple rows of setting items RR-1 to RR-m, where m is a natural number greater than 1. Each sub-table may include a voltage offset value for the corresponding data state of the corresponding memory cell. Sub-tables are queried sequentially from the first sub-table to the mth sub-table. Each query obtains a voltage offset value, which is then summed with the default read voltage to obtain a reread voltage. The memory device 104 uses this reread voltage for reading. A reread operation can have up to m sub-read operations, which is not limited in the embodiments of the present disclosure. For example, V1 in the reread table is a voltage offset value for the read voltage Rd1. When polling the reread table, queries can be made from RR-1 of the first index to RR-m in sequence, obtaining the reread voltages in sequence and performing a reread operation until the read is successful.

[0083] In some embodiments, a reread table may correspond to a default read voltage for each data state, and a reread voltage is obtained by summing the default read voltage with a voltage offset value recorded in the reread table. The default read voltage is a calibration value for the memory device during factory testing and is stored in the memory device for use by a memory controller or peripheral circuitry of the memory device. The reference value for summing the read voltage at each stage and the voltage offset value in the reread table may be different, meaning that the default read voltage corresponding to each data state may be different. In other embodiments, after a memory cell fails to read, the reread table is queried to obtain a voltage offset value based on the read voltage at the time of the current read failure, and the voltage is summed with the current read voltage to obtain the reread voltage. The current read voltage at the time of the read failure may be a real-time value and may not be equal to the default read voltage.

[0084] In some embodiments, when a re-read operation fails, an optimal read voltage may be sought. Figure 9 As shown, taking the threshold voltage distribution peaks of any two adjacent data states Li and Lj as an example, the optimal read voltage between the two data states is the valley voltage of line B. When the threshold voltage shifts, it will cause the original read voltage to shift to line A or line C relative to the current threshold voltage. When the read voltage shifts to line A, the read voltage needs to be positively shifted close to the valley voltage of line B; when the read voltage shifts to line C, the read voltage needs to be negatively shifted close to the valley voltage of line B; thereby finding the optimal read voltage to correctly read the storage cell.

[0085] In some embodiments, combined Figure 9 and Figure 10 As shown, when programming memory cells, writing can be performed based on data randomization. When programming memory cells of the minimum programming unit (or, minimum programming area) in the memory device, the memory cells of the minimum programming unit are all memory cells on a word line or memory cells in a portion of a word line that can be independently read and written. The number of each data state is equal or approximately equal within a certain error range. Memory cells whose target data state is the erased state are not programmed. The threshold voltage distribution of each data state is a normal distribution, and the area of ​​the threshold voltage distribution peak of each data state is equal or approximately equal within a certain error range. Figure 10In the figure, the threshold voltage distribution of QLC is shown, where the threshold voltage horizontal axis is voltage, and the corresponding value on the normal distribution curve is the number of memory cells (bit count). The total number of memory cells in the minimum programming unit is Z. QLC has a total of 16 data states, and the number of memory cells corresponding to each data state can be configured as Z / 16. However, during the subsequent read process, due to the offset of the threshold voltage, if the read voltage determined by the randomly distributed threshold voltage distribution is still used, the number of memory cells corresponding to some data states will differ significantly from Z / 16. This may cause some memory cells programmed to the Li state to be read as the Lj state during the read process, and vice versa.

[0086] In some embodiments, as Figure 11 In the example, based on the random distribution programming logic, when the threshold voltage of the memory cell does not shift or the threshold voltage shift is not considered, the bit count of each data state read is the expected count, which can be the expected count set during the programming operation. The bit count of each data state actually read is the actual count. Due to the shift in the threshold voltage, the actual count of some data states may be greater than or less than the expected count, and the difference between the two may be greater than the predetermined deviation range, resulting in a read error. For example, the actual count corresponding to the L14 data state is greater than the expected count, and the difference exceeds the predetermined deviation range. In other embodiments, the expected count may be a set value calibrated during the factory test phase of the memory device 104 or the memory system 102. The set value may be set according to the Gray code encoding rules of the memory cell. The expected count, as the set value, may be stored in a storage area of ​​the memory device 104 for access by the memory controller 106.

[0087] In some embodiments, the memory cell of the present disclosure may be configured to store M-bit data, with 2 M data states, M data states are read by N-level read voltages, and N=2 M-1. The N-level read voltages can be divided into M groups, each group including at least one level of read voltage. The grouping of the read voltages can be determined according to an encoding rule, which may include but is not limited to a Gray code encoding rule. It should be noted that a typical binary Gray code is often referred to as a Gray code. In the encoding of a set of numbers, if any two adjacent codes differ by only one binary digit, this encoding is called a Gray code. Furthermore, because the maximum and minimum numbers also differ by only one digit, i.e., they are "connected end to end," it is also called a cyclic code or a reflection code. Gray codes also have various other encoding forms, such as decimal encoding and four-bit natural binary encoding. Gray codes are generated by recursively generating a code table, such as a two-bit Gray code, a three-bit Gray code, or a four-bit Gray code. In some embodiments, the M groups of multi-level read voltages can correspond to M types of pages (or, M pages). The corresponding level of read voltage corresponding to each type of page, distinguishing the corresponding bit of stored data, is determined according to the encoding rule.

[0088] For example, when M=2, the storage data in the memory cell includes two bits. In this case, the memory may include two types of pages, namely, upper page and lower page. The two-bit memory cell needs to pass through three stages (3=2 2 -1) Read voltage reads the two-bit stored data; illustratively, the two-bit data stored in the memory cell corresponds to four states (one erased state and three programmed states), that is, four voltage ranges are assigned to four data values. During reading, the two-bit data stored in the memory cell is read by applying three levels of read voltages to distinguish the four voltage ranges. The upper page corresponds to the first level of read voltage, and the lower page corresponds to the second level of read voltage.

[0089] When M=3, the storage data in the memory cell includes three bits. At this time, the memory can include three types of pages, namely, upper page (UP), middle page (MP) and lower page (LP). The three-bit memory cell needs to pass through seven levels (7=2 3 -1) Read voltage reads its three-bit stored data; illustratively, the three-bit data stored in the memory cell corresponds to eight states L0 to L7 (one erased state and seven programmed states), that is, eight voltage ranges are assigned to eight data values. During reading, the three-bit data stored in the memory cell is read by applying seven levels of read voltages used to distinguish the eight voltage ranges. The upper page can correspond to two levels of read voltages, Rd3 and Rd7; the middle page can correspond to three levels of read voltages, Rd2, Rd4, and Rd6; and the lower page can correspond to two levels of read voltages, Rd1 and Rd5. L0 to L7 are encoded using a three-bit Gray code, which can be 111, 110, 100, 000, 101, 011, 001, and 101, respectively.

[0090] When M=4, the storage data in the storage unit includes four bits, such as Figure 10As shown, the memory includes four types of pages, namely upper page (UP), middle page (MP), lower page (LP), and extra page (XP), and the four-bit storage unit corresponds to the fifteenth level (15=2 4 -1) read voltage to read its four bits of data; illustratively, the four bits of data stored in the memory cell correspond to sixteen data states (one erased state and fifteen programmed states), that is, sixteen voltage ranges are assigned to sixteen data values. During reading, fifteen levels of read voltages are applied to distinguish the sixteen voltage ranges to read the three bits of data stored in the memory cell. Among them, the lower page LP corresponds to three levels of read voltages, Rd2, Rd8, and Rd14; the middle page MP corresponds to four levels of read voltages, Rd3, Rd7, Rd9, and Rd13; the upper page UP corresponds to four levels of read voltages, Rd5, Rd10, Rd12, and Rd15; and the extra page XP corresponds to four levels of read voltages, Rd1, Rd4, Rd6, and Rd11. The optimal read voltage can be located at two adjacent peaks and valleys of the threshold voltage distribution, such as Rd1 located between the L0 and L1 threshold voltages and at the valley. L0 to L15 are encoded using a 4-bit Gray code, which can be 1111, 1110, 0110, 0010, 0011, 0001, 0000, 0100, 1100, 1000, 1010, 1011, 1001, 1101, 0101, and 0111. During a read operation, read voltages Rd1 to Rd15 are applied to distinguish the data states of L0 to L15. For example, a threshold voltage less than Rd1 is in the L0 state, a threshold voltage between Rd1 and Rd2 is in the L1 state, and a threshold voltage greater than Rd15 is in the L15 state. When applying the read voltage for the read operation, it can be applied according to the page. For example, Rd2, Rd8 and Rd14 corresponding to the LP page can be applied to read the LP page. The threshold voltage less than Rd2 is read as 1, the threshold voltage between Rd2 and Rd8 is read as 0, the threshold voltage between Rd8 and Rd14 is read as 0, and the threshold voltage greater than Rd14 is read as 0; Rd3, Rd7, Rd9 and Rd13 corresponding to the MP page can be applied. The threshold voltage less than Rd3 is read as 1, the threshold voltage between Rd3 and Rd7 is read as 0, the threshold voltage between Rd7 and Rd9 is read as 1, the threshold voltage between Rd9 and Rd13 is read as 0, and the threshold voltage greater than Rd13 is read as 1; similarly, after applying the read voltages corresponding to UP and XP, the read data is summarized for decoding, that is, the bit values ​​of each data state are read out, such as 1111 for L0.

[0091] In some embodiments, according to the read logic of the read operation, combined with Figure 11The difference between the actual number of each data state and the expected number is used to establish a mapping relationship between the voltage offset value and the difference, and the mapping relationship is mapped with the voltage offset value in the reread table to facilitate querying the reread table. For example, after applying Rd1 to Rd15 to the memory cell, for example, Figure 11 The bit count statistics corresponding to each data state shown are shown. Taking the L14 state as an example, a mapping relationship may exist between the difference value corresponding to the L14 state and the optimal voltage offset value of Rd14. The mapping relationship may be a linear relationship or a fitted linear relationship. The mapping relationship may be test calibration data during the factory test phase of the memory device, stored in the memory device for access by the memory controller or peripheral circuits. The optimal voltage offset value of Rd14 is such that when a difference occurs between the actual number of reads in the L14 state and the expected number, the reread voltage obtained by adding Rd14 to the optimal voltage offset value can correct the read error. In other words, the optimal voltage offset value can make the actual number of reads corresponding to the subsequent L14 state close to the expected number and within a preset error range to correctly read the data. The difference values ​​read in other data states and the optimal voltage offset values ​​refer to the L14 state. For example, a mapping relationship is established between the read difference value of the L13 state and the optimal voltage offset value of Rd13. Other data states are not described in detail here.

[0092] Reference Figure 12 As shown, the voltage offset values ​​corresponding to Rd14 in the reread table are sorted from negative to positive, and a mapping is established between the voltage offset value and the Index value. One Index value corresponds to one voltage offset value Rd14_offset. A linear fitting is performed on Rd14_offset to obtain a linear relationship between Rd14_offset and the Index value. According to the difference between the actual number of reads and the expected number of L14 states, the optimal voltage offset value is obtained through the mapping relationship between the optimal voltage offset value of Rd14 and the difference. According to the optimal voltage offset value, the optimal voltage offset value is obtained. Figure 11 The linear relationship between Rd14_offset and the index value shown is used to calculate the index value. Using the calculated index value as a reference, the voltage offset value of at least one index is retrieved from the rearranged reread table and the reread voltage is calculated. The calculated index value may be an integer or non-integer. The index retrieved from the reread table may be equal to the calculated value, or multiple index values ​​may be retrieved, where the numerical range formed by the retrieved index values ​​includes the calculated index value. The calculated index value may be rounded. Figure 12In this embodiment, other read voltage offset values ​​for the same type of LP page can also be arranged in order of voltage magnitude, such as the mapping relationship between Rd8_offset and Index, and the mapping relationship between Rd2_offset and Index. In this embodiment, a portion of the reread table indexes can be polled based on the calculated index value, without having to poll the reread table starting from the first index. Only a portion of the reread table indexes can be matched for reread operations, which is more efficient.

[0093] In some other embodiments, a memory system is provided, whose memory controller can also poll a portion of the reread table to improve the access efficiency of the reread table, and adopt a single-level read (SLR) method, after reading with only a first-level read voltage, determine the size relationship between the threshold voltage and the read voltage of that level, calculate the index value according to the number of threshold voltages greater than the read voltage and the number of threshold voltages less than the read voltage, and match the index interval of the reread table, without having to apply all the read voltages before obtaining the read difference of each data state, thereby reducing the time of the reread operation and improving the operating rate of the memory system. In some specific embodiments, taking a memory system of a QLC type storage cell as an example, compared with a multi-state read solution, the single-level read of the embodiment of the present disclosure can reduce the time of a reread operation by 73% or more. The details are described below.

[0094] According to some aspects of the embodiments of the present disclosure, a memory system 102 is provided, comprising: a memory device 104; and a memory controller 106 coupled thereto; the memory device 104 comprises a plurality of memory cells, each of the plurality of memory cells being configured to store one of a plurality of data states; the memory controller 106 being configured to: perform a read operation using a trial read voltage corresponding to a selected data state from the plurality of data states; obtain the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition comprises: the threshold voltage being less than or equal to the trial read voltage; or the threshold voltage being greater than or equal to the trial read voltage; determine a difference between the number and the expected number; and obtain at least one reread voltage based on the difference, a mapping relationship, and a reread table; the mapping relationship comprises a correspondence between an expected voltage offset value and the difference.

[0095] Memory controller 106 controls memory device 104 to perform a read operation using a test read voltage. Memory controller 106 sends an operation instruction and corresponding address information to memory device 104, controlling memory device 104 to activate a single-level read mode. In response to the operation instruction, memory controller 106 performs a single-level read operation on the memory cell at the corresponding address using the test read voltage. The single-level read mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage. The memory cell is configured as an SLC and read using a single test read voltage RL. The read bits are counted. Memory cells with a threshold voltage lower than or equal to the test read voltage are read as 1, while memory cells with a threshold voltage higher than the test read voltage are read as 0. Bit count is not performed after applying multiple test read voltages. The test read voltages correspond to read voltages such as Rd1 and Rd2. For example, test read voltage RL1 can be equal to a default Rd1, or RL1 can be a voltage value obtained by offsetting, error correction, or other operations on Rd1. RL1 can be offset within a certain range based on the default Rd1. Statistics of the number of threshold voltages less than or equal to the test-read voltage, or statistics of the number of threshold voltages less than or greater than the test-read voltage, may be performed by peripheral circuits of the memory device 104 and sent to the memory controller 106, or the memory controller 106 may autonomously obtain statistical information; the memory controller 106 compares the number with the expected number to obtain a difference and performs a subsequent access reread table operation; the relevant number may also be statistics of the memory controller 106 based on read information.

[0096] Reference Figure 13 As shown, taking a QLC memory cell as an example, it is configured into 16 data states L0 to L15, including an erased state, with L0 being the erased state; taking the L14 state as the selected data state, and performing a reread operation when the read voltage Rd14 corresponding to the L14 state fails to read as an example, the operation of determining the reread voltage by the trial read voltage corresponding to other selected data states can refer to the operation of determining the reread voltage by Rd14 in this example. It should be noted that based on the read logic of the multi-bit memory cell, after the multi-level read voltage is read, all data states are distinguished. The read voltage can be located between the threshold voltage peaks of two data states, such as at the valley. The read voltages corresponding to the multiple data states of this embodiment are only used to distinguish a certain level of read voltage. The first level read voltage can correspond to any one or two of the adjacent data states it distinguishes. For example, the read voltage Rd14 can correspond to the L14 state, or can correspond to the L13 state, or can be a read voltage between the L13 state and the L14 state. In the disclosed embodiment, Rd14 corresponds to the L14 state, and Rd7 corresponds to the L7 state. These will not be described in detail below.

[0097] Combine Figure 6The read operation process shown is schematic. Before the reread operation, a read operation is performed to confirm whether the data is read correctly. When an error occurs, a reread operation is performed and the reread table is accessed. The read operation can be performed using the default read voltage stored in the memory device 104. The default read voltage can be a reference voltage value corresponding to the reread table, which is used to be added to the voltage offset value obtained from the reread table to obtain the reread voltage; or, the read operation before the reread operation can also be a real-time read operation. The read voltage value can be different from the default read voltage and can be any read voltage obtained after offset, error correction or other operations, which can be recorded as a trial read voltage to distinguish it from the default read voltage.

[0098] by Figure 13 Take the trial read voltage RL14 corresponding to the L14 state as an example. RL14 is no longer the optimal read voltage because of the offset of the threshold voltage. Its optimal read position may be in the valley between L13 and L14. It needs to be offset negatively to obtain the optimal read voltage for re-reading. For other threshold voltage offset situations, or the RL voltage corresponding to other states may need to be offset positively to obtain the optimal read voltage. The trial read voltage RL14 fails after the default read operation and enters the re-read operation. The single-level read mode of the memory device 104 is turned on. The memory cell is read in a single level with RL14. The memory cell with a threshold voltage less than or equal to the trial read voltage RL14 is read as 1, and the number is recorded as the first number. The set number of L14 state threshold voltages less than or equal to Rd14 (the number set to be programmed to the L14 state) is the first expected number. The memory cell with a threshold voltage greater than the trial read voltage RL14 is read as 0, and the number is recorded as the second number. The set number of L14 state threshold voltages greater than Rd14 is the second expected number. For example, Figure 13 As shown, when a single-stage read is performed using a test read voltage, the memory cells located to the left of RL14 whose threshold voltage is less than or equal to the test read voltage RL14 are turned on and the reading is successful. At this time, the number of memory cells that are successfully read is recorded as the first number; the read cells whose threshold voltage is greater than the test read voltage RL14 are not successfully read, and their number is the second number.

[0099] like Figure 14As shown, RL14_left_"1" indicates that the threshold voltage is less than or equal to the test read voltage RL14, and RL14_right_"0" indicates that the threshold voltage is greater than the test read voltage RL14. The first and second test read counts are the actual read counts, which are real-time read values. The first expected count and the second expected count are preset calibration counts, which are known set values. Based on the random distribution programming logic, the first expected count can be 14 / 15 of the total number of memory cells edited in a single run, and the second expected count can be 1 / 15 of the total number of memory cells edited in a single run. A first difference exists between the first count and the first expected count, and a second difference exists between the second count and the second expected count. The first and second differences are mapped to an optimal offset value (or expected voltage offset value) for adjusting the current test read voltage RL14 to the optimal read voltage. This mapping relationship can be a linear relationship or a fitted linear relationship. The expected voltage offset value can reduce the difference after the current test read voltage offset to within the allowable read error range or eliminate the difference. The mapping relationship is obtained by testing and calibration of the memory system 102 or the memory device 104 during the factory test phase, and is stored in the memory device 104 for use by the memory device 104 or the memory controller 106 .

[0100] In some specific embodiments, the memory controller 106 may retrieve the corresponding mapping relationship between the expected voltage offset value and the difference based on the real-time first difference or second difference, calculate or obtain the expected voltage offset value based on the difference and the mapping relationship, and use the calculated expected voltage offset value as a reference to match the reread table to obtain one or more voltage offset values. The voltage offset values ​​in the reread table can be arranged according to the size of the voltage offset value. The voltage offset value of the reread table is set based on its default read voltage or reference voltage. The trial read voltage may have a voltage difference with the default read voltage. Before matching the reread table, the expected voltage value calculated according to the mapping relationship needs to be summed with the voltage difference to obtain a first expected voltage value. When the voltage difference is 0, the trial read voltage is equal to the default read voltage. The expected voltage value obtained from the mapping relationship is the first expected voltage value. Taking the first expected voltage value as a reference, one or more voltage offset values ​​are obtained from the reread table, which are equal to or close to the first expected voltage offset value, or the interval composed of multiple voltage offset values ​​includes the first expected voltage offset value, and the voltage offset values ​​obtained from the reread table are sequentially summed with the default read voltage to obtain the reread voltage for rereading, thereby reducing the number of polling times of the reread table and reducing the time to obtain the first quantity or the second quantity in a single-stage read mode, thereby improving the operation rate.

[0101] The disclosed embodiment performs a single-stage reading to obtain the first quantity or the second quantity and then accesses the reread table to perform a reread operation. Compared with the reread operation of accessing the reread table after all read voltages are read, the time of a single reread operation can be reduced by 73% or more.

[0102] In some embodiments, reference Figure 14 As shown, a first number of the plurality of memory cells whose threshold voltage is lower than the test read voltage is greater than a second number of the plurality of memory cells whose threshold voltage is higher than the test read voltage.

[0103] Whether to select the first number or the second number as the statistical object can be selected according to the data state corresponding to the trial read voltage to be corrected. If the trial read voltage corresponds to a low data state, such as RL1 in the L1 state, the first number of threshold voltages less than the trial read voltage RL1 is less than the second number of threshold voltages greater than the trial read voltage RL1. In this case, the second number and the second expected number can be selected to construct a mapping relationship to obtain a larger statistical base and reduce errors. If the trial read voltage corresponds to a high data state, such as Figure 14 In the L14 state of RL14, the first number is greater than the second number, and the first number and the first expected number are selected to establish a mapping relationship.

[0104] In some embodiments, the quantity includes a first quantity in which the threshold voltage of a plurality of memory cells is less than or equal to the test read voltage; the expected quantity includes a first expected quantity, which is a set quantity when the threshold voltage of a plurality of memory cells is less than or equal to the default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected quantity; the memory controller 106 is further configured to: obtain a first expected voltage offset value based on a first difference between the first quantity and the first expected quantity, the first mapping relationship, and a voltage difference between the test read voltage and the default read voltage; and obtain at least one first voltage offset value from the reread table based on the first expected voltage offset value.

[0105] Take the test read voltage RL14 corresponding to the L14 state as an example, select Figure 14A first mapping relationship is established by using a first quantity and a first expected quantity in the L14 state. A default read voltage corresponding to the L14 state is correlated with the calibration quantity. The default read voltage may be located at a valley between the peaks of the threshold voltage distributions of the L14 state and the L15 state. The first expected quantity is the calibration quantity programmed into L14. A mapping relationship is formed between a first difference between the first quantity and the first expected quantity and an expected voltage offset value. The first mapping relationship is known calibration data and stored in the memory device for access by the memory controller. The first quantity and the first difference obtained in a subsequent trial read are the current real-time values. A voltage difference between a trial read voltage and the default read voltage is determined. A single-level read operation is performed on the memory cell using the trial read voltage to obtain the real-time first quantity. A first difference between the first quantity and the first expected quantity is determined. An expected offset value for the trial read voltage is obtained or calculated based on the first difference and the first mapping relationship. The expected offset value is added to the voltage difference to obtain a first expected voltage offset value. Based on the first expected voltage offset value, at least one first voltage offset value is obtained from a reread table. The first voltage offset value is added to the default read voltage corresponding to the reread table to obtain a reread voltage.

[0106] In some embodiments, reference Figure 15 As shown, a first mapping relationship between a first quantity of read voltage offset values ​​Rd7 (corresponding to a trial read voltage RL7) corresponding to the L7 state of a TLC memory cell, an expected voltage offset value (best_offset) established by a first expected quantity, and a first difference (Diff) is illustrated. The first mapping relationship may be a linear relationship or a fitted linear relationship. Here, the first expected voltage offset value is the sum of the expected voltage offset value best_offset obtained from the mapping relationship, the voltage difference between the trial read voltage and the default read voltage, and the first voltage offset value is a voltage offset value recorded in the reread table and obtained for the reread operation, as shown in FIG. Figure 16 The recorded Rd7 corresponds to at least one of the numerical values.

[0107] In some embodiments, the at least one first voltage offset value is stored in the reread table in order of size.

[0108] Reference Figure 16 As shown, the reread table is stored in the order of the voltage offset value corresponding to Rd7. The reread table before sorting is arranged according to the original index RR-24 to RR-33. The reread table after sorting is arranged according to the voltage offset value of Rd7 and new indexes 3 to 9 are set. The voltage offset values ​​of different indexes can be the same or different. The embodiment of the present disclosure does not limit the number of indexes in the reread table and the specific values ​​of the voltage offset value. Figure 16This is for illustrative purposes only. The reread table can be sorted by memory controller 106 before accessing it, or the reread table can be sorted during factory testing and stored in memory device 104, with no further sorting required when accessed by memory controller 106. If rereading Rd3 for error correction, the voltage offset values ​​of Rd3 can be sorted in order of magnitude. Another mapping relationship can be established using the same mapping method as that used to establish a mapping between the expected voltage offset value of Rd7 and the first difference. Based on the difference and the established mapping relationship, one or more voltage offset values ​​for Rd3 can be retrieved from the reread table and applied to the reread operation.

[0109] In some embodiments, among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

[0110] For example, refer to Figure 15 As shown in the first mapping relationship, if the trial read voltage RL7 at this time is equal to the default read voltage corresponding to the L7 state, when the single-level reading is performed on the memory cell, the first difference between the first quantity and the first expected quantity is calculated through the first mapping relationship to obtain a first expected offset value of -250 (mV). Based on the first expected offset value, Figure 16 The first voltage offset value corresponding to Rd7 is obtained from the reread table shown. -250 is recorded in the reread table. A single first voltage offset value, -250, can be directly selected to calculate the reread voltage, or multiple first voltage offset values, including -250, can be obtained and summed with the default read voltage to obtain multiple reread voltages. For example, 1 to 7 or more first voltage offset values, including -250, can be obtained. In some embodiments, when the first expected offset value calculated based on the first mapping relationship may not be recorded in the reread table, such as -248.5, multiple first expected offset values ​​can also be obtained based on -250.

[0111] In some embodiments, when obtaining multiple first voltage offset values, the first voltage offset value that is equal to or closest to the first expected voltage offset value can be located in the rereading table based on the calculated first expected voltage offset value. For example, when the first expected voltage offset value is -250 or -248.5, it is located at the new Index 6, -250 in the rereading table, and multiple indexes are obtained before and after the located Index, such as 3, that is, Index 3 to 9 are obtained, or more indexes are obtained before and after.

[0112] In some embodiments, reference Figure 17 As shown, Figure 16 After rereading the table, Rd7 is sorted by the offset voltage value, and a new Index is set to generate a mapping relationship with the voltage offset value Rd7_offset. Figure 15The calculated first expected voltage offset value is combined with Figure 17 The mapping relationship between the voltage offset value Rd_offset and the Index is used to calculate or obtain the required target Index and query based on the target Index. Figure 16 The mapping relationship between the voltage offset value and the index can be linearly fitted to facilitate calculation or search. After the memory controller 106 calculates the first expected voltage offset value, it can directly use the first expected voltage offset value as a reference to query Figure 16 The table is reread to obtain one or more first voltage offset values, where the first voltage offset value includes a first region voltage offset value, or an offset value interval formed by multiple first voltage offset values ​​includes a first expected voltage offset value.

[0113] In some embodiments, the memory controller 106 is further configured to: generate an offset value interval according to the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value interval; and obtain at least one first voltage offset value within the offset value interval from the reread table.

[0114] In some embodiments, the maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

[0115] Taking the first expected offset value of -250 as an example, the first and second step sizes are both set to 50, generating an offset value range of -300 to -200. The first voltage offset values ​​in the reread table within the range of -300 to -200, inclusive, are retrieved. For some first voltage offset values ​​recorded in the reread table that are equal, either only one value or all values ​​may be retrieved. If the first expected offset value is not recorded in the reread table, the first voltage offset value closest to the first expected offset value may be first searched for, and the offset range generated based on the closest first voltage offset value. Alternatively, the offset range may be generated directly based on the first expected offset value.

[0116] In some embodiments, the memory controller 106 is further configured to obtain a plurality of adjacent first voltage offset values ​​from the reread table.

[0117] When there are multiple equal voltage values ​​among the multiple first voltage offset values ​​obtained from the reread table, only one equal voltage value is obtained, or all of them are obtained. Figure 16The reread table shown records the voltage offset values ​​of Rd3 and Rd7 corresponding to the TLC upper page (UP). Only Rd7 is sorted. Rd3 and Rd7 may have a corresponding relationship, that is, after obtaining multiple indexes according to the voltage offset value of Rd7, the voltage offset values ​​corresponding to Rd3 under the multiple indexes are applied to the reread operation error correction of Rd3. At this time, for the first voltage offset values ​​of multiple indexes, whether they are equal or not, they need to be obtained and applied to the reread operation to avoid missing the voltage offset value of Rd3. Rd7 is the highest-order read voltage of the UP page. When sorting it, it is applied Figure 15 The mapping relationship established based on the first quantity and the first expected quantity shown above obtains a larger statistical cardinality with a smaller error. If Rd3 is sorted, a mapping relationship based on the second quantity and the second expected quantity needs to be established, where the second quantity is greater than the first quantity.

[0118] In some embodiments, the memory cell is a multi-bit memory cell, and each of the multiple data states is distinguished by a multi-level read voltage; the reread table stores the second voltage offset value corresponding to at least one level of read voltage; wherein the second voltage offset value corresponding to the highest level read voltage is stored in order of magnitude; and at least one first voltage offset value is included in the second voltage offset value corresponding to the highest level read voltage. Here, the second voltage offset value is the voltage offset value recorded in the reread table, and the first voltage offset value is the voltage offset value recorded in the reread table and obtained and applied to the reread operation. Figure 16 The reread table is taken as an example, which records some voltage offset values ​​corresponding to Rd3 and Rd7 of the UP page of TLC. There are more voltage offset values ​​of the Index that are not shown. The voltage offset values ​​recorded in the reread table are recorded as second voltage offset values, such as -50, -100 corresponding to Rd3, -300, -270 corresponding to Rd7, etc. The voltage offset values ​​corresponding to the highest-order read voltage are arranged in order of size. One or more voltage offset values ​​obtained from the reread table according to the first difference and the first mapping relationship are applied to the reread operation and recorded as the first voltage offset value, such as -270, -250, -250 or more corresponding to Rd7.

[0119] In some embodiments, combined Figure 8As shown, the voltage offset values ​​of all reread voltages Rd1 to Rd7 can be recorded in a reread table, and the voltage offset values ​​can be correlated with each other. The highest-order voltage offset values ​​can be arranged in order of voltage magnitude, and a single-stage read operation is performed with the trial read voltage RL7 corresponding to Rd7, and the first quantity and the first difference are determined. Combined with the first mapping relationship, multiple indexes of the reread table are obtained, and the voltage offset values ​​other than Rd7 corresponding to the multiple indexes are directly applied to the reread operation. In other embodiments, there may be no corresponding relationship between the voltage offset values ​​corresponding to the various data states in the reread table, and the voltage offset values ​​of each data state can be obtained separately when accessing the reread table to obtain the voltage offset value. Figure 8 As shown, when rereading and correcting the Rd7 reading voltage, the voltage offset value of RR-1 of Rd7 is obtained and added to the corresponding default reading voltage to obtain the reread voltage for rereading; while when rereading and correcting Rd1, RR-2 or RR-3 may be obtained, which does not necessarily correspond to RR-1; even if Figure 16 Rd3 is on the same UP page as Rd7, and obtaining RR-27 of Rd7 does not necessarily mean obtaining RR-27 of Rd3.

[0120] In some embodiments, multi-level read voltages are divided into multiple groups; the reread table includes multiple reread sub-tables, and one of the reread sub-tables stores the second voltage offset value corresponding to at least one first-level read voltage in a group; the second voltage offset value corresponding to the highest-level read voltage is stored in the reread sub-table in order of size; wherein, at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-level read voltage in the storage sub-table.

[0121] Taking the TLC read voltages for Rd1-Rd7 as an example, these voltages correspond to three pages, or groups. The upper page (UP) corresponds to a two-level read voltage, Rd3 and Rd7; the middle page (MP) corresponds to a three-level read voltage, Rd2, Rd4, and Rd6; and the lower page (LP) corresponds to a two-level read voltage, Rd1 and Rd5. L0-L7 are encoded using a three-bit Gray code: 111, 110, 100, 000, 101, 011, 001, and 101, respectively. A reread subtable stores the voltage offset for each page's read voltage, facilitating fast access to the reread table. Figure 16 In the example of the voltage offset value of the upper page UP, the voltage offset values ​​of the highest-order read voltage Rd7 of the page are arranged in order of voltage magnitude, while the voltage offset values ​​of the lower-order read voltage Rd3 may not be arranged in order of magnitude, such as Figure 17 The Rd3_offset in the table does not increase strictly in accordance with the increase of the Index. The voltage offset values ​​of the highest-order read voltage Rd6 of the reread sub-table of the record page MP are arranged in order of size.

[0122] In some embodiments, in a reread table that records the voltage offset values ​​of all reread voltages, or in a reread sub-table that records only one page of voltage offset values, only the voltage offset values ​​of the highest-order reread voltages in the table may be arranged in order of magnitude, and the voltage offset values ​​of other lower-order read voltages may use other voltage offset values ​​under the index of the offset value of the highest-order read voltage. For example, Figure 16 In the example, the voltage offset value of Rd7 obtains Index 5, 6, and 7, and the voltage offset value of Rd3 also uses -50, -50, and -80 of Index 5, 6, and 7. There is no need to access the reread table again, rearrange Rd3, and re-establish the mapping relationship between the expected voltage offset value and the corresponding difference value.

[0123] In some other embodiments, there is a correlation between the voltage offset values ​​of each level of read voltage, and knowing the voltage offset value of a certain level of read voltage, the offset values ​​of other read voltages can be obtained based on the correlation. Figure 18 As shown, taking the read voltages Rd1 to Rd7 of the TLC memory cell as an example, and taking the voltage offset value Rd7_offset of the highest-order read voltage as a reference, Rd1_offset, Rd2_offset, Rd3_offset, Rd4_offset, Rd5_offset, and Rd6_offset can have a linear relationship or a fitted linear relationship with Rd7_offset, and can be calculated by Rd7_offset. In the reread table, the voltage offset values ​​of the highest-order read voltage are sorted by size to establish Figure 15 The first mapping relationship between the highest-order read voltage offset value (best_offset) and the first difference (Diff) is shown. The first difference is the first difference between the first quantity and the first expected quantity. The first quantity is the number of memory cells whose threshold voltage is less than or equal to the trial read voltage corresponding to the highest-order read voltage. The first expected quantity is the calibration quantity reached when programming the highest data state. The memory cell is read at a single level using the trial read voltage corresponding to the highest-order reread voltage to obtain the first quantity currently read and calculate the current first difference. The expected voltage offset value corresponding to the current trial read voltage is obtained or calculated according to the first mapping relationship. The first expected voltage offset value is obtained by adding the calculated expected voltage offset value, the trial read voltage, and the default read voltage. The first expected voltage offset value is obtained from the reread table with reference to the first expected voltage offset value. The first voltage offset value is added to the default read voltage to obtain the reread voltage. The expected voltage offset values ​​(best_offset) of other low-order read voltages can be obtained according to Figure 18 The linear relationship is calculated and can be established only once Figure 15The first mapping relationship shown in FIG. 1 is used, and only the voltage offset values ​​of the highest-order read voltages in the reread table are sorted by size, thereby improving the execution rate of the reoperation.

[0124] In some embodiments, the memory controller 106 is configured to: sum the default read voltage with each of the first voltage offset values ​​to obtain the corresponding re-read voltage. The default read voltage is a reference voltage obtained by summing the voltage offset values ​​of each data state in the re-read table. The default read voltages for different data states may be different. When there is a voltage difference between the test read voltage and the default read voltage, the voltage difference needs to be compared with the reference voltage. Figure 15 The obtained expected voltage offset values ​​are summed to obtain a first expected voltage offset value, and the first voltage offset value obtained from the reread table according to the first voltage offset value is summed with the default read voltage to obtain a reread voltage.

[0125] According to some aspects of the embodiments of the present disclosure, Figure 19 A control method for a memory system 102 is provided, comprising: performing a read operation on a plurality of memory cells using a trial read voltage corresponding to a selected data state from a plurality of data states; each of the plurality of memory cells being configured to store one of the plurality of data states; obtaining the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition comprises: a threshold voltage less than or equal to the trial read voltage; or a threshold voltage greater than or equal to the trial read voltage; determining a difference between the number and an expected number; obtaining at least one reread voltage based on the difference, a mapping relationship, and a reread table; the mapping relationship comprising a correspondence between an expected voltage offset value and the difference.

[0126] In the disclosed embodiment, a single-level read mode is enabled, and the memory controller 106 performs a single-level read operation on the memory cell at the response address using a test read voltage in response to the operation instruction. The single-level read mode includes reading at least one bit of storage data stored in the memory cell using a first-level read voltage, configuring the memory cell as an SLC, reading using a test read voltage RL, and counting the bit information read. Memory cells with a threshold voltage lower than the test read voltage are read as 1, and memory cells with a threshold voltage higher than the test read voltage are read as 0. Multiple test read voltages are not applied before counting the bit information.

[0127] In some embodiments, the number includes a first number of the plurality of memory cells whose threshold voltage is less than or equal to the test read voltage; the expected number includes a first expected number, which is a set number of the plurality of memory cells when the threshold voltage is less than or equal to a default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected number; and the control method further includes:

[0128] Obtaining a first expected voltage offset value according to a first difference between the first quantity and the first expected quantity, the first mapping relationship, and a voltage difference between the trial read voltage and the default read voltage;

[0129] At least one first voltage offset value is obtained from the rereading table according to the first expected voltage offset value.

[0130] In some embodiments, the at least one first voltage offset value is stored in the reread table in order of size.

[0131] In some embodiments, among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

[0132] In some embodiments, the control method further includes: generating an offset value interval based on the first expected voltage offset value, wherein the first expected voltage offset value is within the offset value interval; and obtaining at least one first voltage offset value within the offset value interval from the rereading table.

[0133] In some embodiments, the maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

[0134] In some embodiments, the control method further includes: acquiring a plurality of adjacent first voltage offset values ​​from the rereading table.

[0135] In some embodiments, the storage cell is a multi-bit storage cell, and each of the multiple data states is distinguished by multi-level read voltages; the reread table stores the second voltage offset value corresponding to at least one level of read voltage; wherein the second voltage offset value corresponding to the highest level read voltage is stored in order of size; and the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest level read voltage.

[0136] In some embodiments, the multi-level read voltages are divided into multiple groups; the reread table includes multiple reread sub-tables, and one of the reread sub-tables stores the second voltage offset value corresponding to at least one first-level read voltage in the group; the second voltage offset value corresponding to the highest-level read voltage is stored in the reread sub-table in order of size; wherein, the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-level read voltage in the storage sub-table.

[0137] In some embodiments, a first number of the plurality of memory cells having a threshold voltage lower than the test read voltage is greater than a second number of the plurality of memory cells having a threshold voltage higher than the test read voltage.

[0138] In some embodiments, the control method further includes: summing the default read voltage with each of the first voltage offset values ​​to obtain the corresponding re-read voltage.

[0139] According to some aspects of the embodiments of the present disclosure, a readable storage medium is provided, wherein the readable storage medium stores a computer program, and the computer program implements the control method when executed.

[0140] The memory device 104 may include a NAND memory, and a memory cell of the NAND memory may include a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0141] The storage medium may be a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage device, an optical disc, or a compact disc read-only memory (CD-ROM); or various devices including one or any combination of the above-mentioned memory devices 104.

[0142] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0143] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as, for example, one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0144] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0145] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory system, characterized in that: include: memory device; and a memory controller coupled thereto; The memory device includes a plurality of memory cells, each of the plurality of memory cells being configured to store one of a plurality of data states; and the memory controller is configured to: performing a read operation using a test read voltage corresponding to a selected data state among the plurality of data states; Obtaining the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition includes: the threshold voltage is less than or equal to the trial read voltage; or the threshold voltage is greater than or equal to the trial read voltage; determining the difference between the amount and the expected amount; and At least one reread voltage is acquired according to the difference, a mapping relationship, and a reread table; the mapping relationship includes a corresponding relationship between an expected voltage offset value and the difference.

2. The memory system according to claim 1, wherein: The number includes a first number of the plurality of memory cells whose threshold voltage is less than or equal to the test read voltage; the expected number includes a first expected number, which is a set number of the plurality of memory cells when the threshold voltage is less than or equal to the default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected number; and the memory controller is further configured to: Obtaining a first expected voltage offset value according to a first difference between the first quantity and the first expected quantity, the first mapping relationship, and a voltage difference between the trial read voltage and the default read voltage; and obtaining at least one first voltage offset value from the rereading table according to the first expected voltage offset value.

3. The memory system according to claim 2, wherein: The at least one first voltage offset value is stored in the reread table in order of size.

4. The memory system according to claim 3, wherein: Among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

5. The memory system according to claim 3, wherein: The memory controller is further configured to: An offset value interval is generated according to the first expected voltage offset value, where the first expected voltage offset value is within the offset value interval; and at least one first voltage offset value within the offset value interval is acquired from the reread table.

6. The memory system according to claim 5, wherein: The maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

7. The memory system according to claim 5, wherein: The memory controller is further configured to obtain a plurality of adjacent first voltage offset values ​​from the reread table.

8. The memory system according to claim 3, wherein: The memory cell is a multi-bit memory cell, and each of the plurality of data states is distinguished by a multi-level read voltage; The reread table stores second voltage offset values ​​corresponding to at least one first-order read voltage; wherein the second voltage offset values ​​corresponding to the highest-order read voltage are stored in order of size; and the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-order read voltage.

9. The memory system according to claim 8, wherein: The multi-level read voltages are divided into a plurality of groups; the reread table comprises a plurality of reread sub-tables, each of the reread sub-tables storing the second voltage offset value corresponding to at least one level of read voltage in the group; The second voltage offset values ​​corresponding to the highest-order read voltage are stored in the reread sub-table in order of size; wherein the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-order read voltage in the storage sub-table.

10. The memory system according to claim 2, wherein: A first number of the plurality of memory cells having a threshold voltage lower than the test read voltage is greater than a second number of the plurality of memory cells having a threshold voltage higher than the test read voltage.

11. The memory system according to claim 2, wherein: The memory controller is configured to: The default read voltage is summed with each of the first voltage offset values ​​to obtain the corresponding re-read voltage.

12. A method for controlling a memory system, characterized in that: include: performing a read operation on the plurality of memory cells using a test read voltage corresponding to a selected data state from the plurality of data states; Each memory cell of the plurality of memory cells is configured to store one of the plurality of data states; Obtaining the number of memory cells whose threshold voltages satisfy a preset condition; wherein the preset condition includes: the threshold voltage is less than or equal to the trial read voltage; or the threshold voltage is greater than or equal to the trial read voltage; determining the difference between the stated amount and the expected amount; At least one reread voltage is acquired according to the difference, a mapping relationship, and a reread table; the mapping relationship includes a corresponding relationship between an expected voltage offset value and the difference.

13. The control method according to claim 12, characterized in that: The number includes a first number of the plurality of memory cells whose threshold voltage is less than or equal to the test read voltage; the expected number includes a first expected number, which is a set number of the plurality of memory cells when the threshold voltage is less than or equal to the default read voltage; the mapping relationship includes a first mapping relationship, which is obtained based on the first expected number; and the control method further includes: Obtaining a first expected voltage offset value according to a first difference between the first quantity and the first expected quantity, the first mapping relationship, and a voltage difference between the trial read voltage and the default read voltage; At least one first voltage offset value is obtained from the rereading table according to the first expected voltage offset value.

14. The control method according to claim 13, characterized in that: The at least one first voltage offset value is stored in the reread table in order of size.

15. The control method according to claim 14, characterized in that: Among the at least one first voltage offset value, the number of first voltage offset values ​​equal to the first expected voltage offset value includes one or more.

16. The control method according to claim 14, characterized in that: The control method further includes: An offset value interval is generated according to the first expected voltage offset value, where the first expected voltage offset value is within the offset value interval; and at least one first voltage offset value within the offset value interval is acquired from the reread table.

17. The control method according to claim 16, characterized in that: The maximum value of the offset value interval is the first expected voltage offset value plus the first step length, and the minimum value of the offset interval is the first expected voltage offset value minus the second step length.

18. The control method according to claim 16, characterized in that: The control method further includes: A plurality of adjacent first voltage offset values ​​are obtained from the rereading table.

19. The control method according to claim 14, characterized in that: The storage cell is a multi-bit storage cell, and each of the multiple data states is distinguished by multi-level read voltages; the reread table stores the second voltage offset value corresponding to at least one level of read voltage; wherein the second voltage offset value corresponding to the highest level of read voltage is stored in order of size; and the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest level of read voltage.

20. The control method according to claim 19, characterized in that: The multi-level read voltages are divided into a plurality of groups; the reread table comprises a plurality of reread sub-tables, each of the reread sub-tables storing the second voltage offset value corresponding to at least one level of read voltage in the group; The second voltage offset values ​​corresponding to the highest-order read voltage are stored in the reread sub-table in order of size; wherein the at least one first voltage offset value is included in the second voltage offset value corresponding to the highest-order read voltage in the storage sub-table.

21. The control method according to claim 13, characterized in that: A first number of the plurality of memory cells having a threshold voltage lower than the test read voltage is greater than a second number of the plurality of memory cells having a threshold voltage higher than the test read voltage.

22. The control method according to claim 13, characterized in that: The control method further includes: The default read voltage is summed with each of the first voltage offset values ​​to obtain the corresponding re-read voltage.

23. A readable storage medium, characterized in that The readable storage medium stores a computer program, and when the computer program is executed, the control method according to any one of claims 12 to 22 is implemented.

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