Multilayer ceramic capacitor

Abstract

The present invention provides a laminated ceramic capacitor capable of suppressing the occurrence of interlayer peeling in a laminated body in a laminated ceramic capacitor of a high withstand voltage specification. The first to fourth main surface-side external electrodes (411A, 412A, 411B, 540B) have first to fourth recesses (510A, 520A, 530B, 540B), which are recessed toward the laminate (10) side, respectively, and the first to fourth main surface-side external electrodes (411A, 412A, 411B, 540B) are provided with first to fourth recesses (510A, 520A, 530B, 540B). In a cross-sectional view along the longitudinal direction (L) and the lamination direction (T), an intersection point (300) between a first imaginary line (100) connecting the first recess (510A) and the fourth recess (540B) and a second imaginary line (200) connecting the second recess (520A) and the third recess (530B) is located between the first capacitor part (CAP1) and the second capacitor part (CAP2) in the longitudinal direction (L), and the external electrode (40) has tensile stress as residual stress.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, as a multilayer ceramic capacitor having a high withstand voltage, a multilayer ceramic capacitor having a structure in which a plurality of capacitor portions are connected in series (so-called series structure) is known (see Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 10-261546

[0006] In a series-structured multilayer ceramic capacitor, significant electrostriction also occurs between the series-connected capacitor sections, generating a force (tensile stress) within the stack that extends from the center of the stack toward the main surfaces. Furthermore, if the external electrodes have residual tensile stress, a residual force (tensile stress) extends from the center of the stack toward the ends of the external electrodes. These forces, acting in the stack from the center of the stack toward the main surfaces, are combined. If this combined force increases, delamination of the stack can occur. Summary of the Invention

[0007] Problems to be solved by the invention

[0008] An object of the present invention is to provide a multilayer ceramic capacitor having a high withstand voltage specification, in which interlayer delamination in a multilayer body can be suppressed.

[0009] Technical solutions to solve problems

[0010] The multilayer ceramic capacitor of the present invention comprises: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and including a first main surface and a second main surface opposing each other in the height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and a pair of external electrodes spaced apart from each other and arranged at opposite ends of the laminate in the length direction, the internal electrode layers including a first internal electrode layer extending to the first end surface, a second internal electrode layer extending to the second end surface, and an intermediate electrode layer not extending to either the first end surface or the second end surface, the laminate including a first capacitor portion formed by the first internal electrode layer and the intermediate electrode layer facing each other, and a second capacitor portion formed by the second internal electrode layer and the intermediate electrode layer facing each other, the external electrodes including a first external electrode arranged on the first end surface side; and a second external electrode, arranged on the second end surface side, the first external electrode comprising: a first main surface side external electrode, arranged on the first main surface side; and a second main surface side external electrode, arranged on the second main surface side, the second external electrode comprising: a third main surface side external electrode, arranged on the first main surface side; and a fourth main surface side external electrode, arranged on the second main surface side, the first main surface side external electrode comprising a first recessed portion recessed toward the stack side, the second main surface side external electrode comprising a The second recess, the third main surface side external electrode has a third recess recessed toward the stack side, the fourth main surface side external electrode has a fourth recess recessed toward the stack side, and in a cross-sectional view along the length direction and the height direction, an intersection of a first imaginary line connecting the first recess and the fourth recess and a second imaginary line connecting the second recess and the third recess is located between the first capacitor portion and the second capacitor portion in the length direction, and the external electrode has tensile stress as residual stress.

[0011] Effects of the Invention

[0012] According to the present invention, it is possible to provide a multilayer ceramic capacitor having a high withstand voltage specification, in which occurrence of interlayer delamination in a multilayer body can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a perspective view of the appearance of a double-structured multilayer ceramic capacitor according to the embodiment.

[0014] Figure 2 yes Figure 1The II-II cross-sectional view is a diagram for explaining the schematic structure of the double-structured stacked body according to the embodiment.

[0015] Figure 3 yes Figure 2 Sectional view III-III.

[0016] Figure 4A yes Figure 2 The IVA-IVA cross-sectional view is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer.

[0017] Figure 4B yes Figure 2 The IVB-IVB cross-sectional view is a cross-sectional view along the middle electrode layer.

[0018] Figure 5A It is a diagram showing a part of the method for manufacturing a multilayer ceramic capacitor according to the embodiment, and is a diagram showing a first step of forming external electrodes on a multilayer body.

[0019] Figure 5B A diagram showing a portion of the method for manufacturing a multilayer ceramic capacitor according to the embodiment, and showing a second step of forming external electrodes on a multilayer body.

[0020] Figure 5C A diagram showing a portion of the method for manufacturing a multilayer ceramic capacitor according to the embodiment, showing a third step of forming external electrodes on a multilayer body.

[0021] Figure 6 LT is a cross-sectional view schematically showing a double-structured multilayer ceramic capacitor according to the embodiment, and is a diagram for explaining forces acting on the inside.

[0022] Figure 7 LT is a cross-sectional view schematically showing a triple-structured multilayer ceramic capacitor according to a first modification.

[0023] Figure 8 LT is a cross-sectional view schematically showing a quadruple-structured multilayer ceramic capacitor according to a second modification.

[0024] Description of Reference Numerals

[0025] 1: Multilayer ceramic capacitor;

[0026] 10: laminate;

[0027] 20: dielectric layer;

[0028] 30: internal electrode layer;

[0029] 31: first internal electrode layer;

[0030] 32: second internal electrode layer;

[0031] 33: middle electrode layer;

[0032] 40: external electrode;

[0033] 40A: 1st external electrode;

[0034] 40B: second external electrode;

[0035] 100: 1st imaginary line;

[0036] 200: 2nd imaginary line;

[0037] 300: intersection;

[0038] 331: first intermediate electrode layer;

[0039] 332: second intermediate electrode layer;

[0040] 333: third intermediate electrode layer;

[0041] 411A: first main surface side external electrode;

[0042] 412A: Second main surface side external electrode;

[0043] 411B: third main surface side external electrode;

[0044] 412B: fourth main surface side external electrode;

[0045] 510A: 1st recess;

[0046] 520A: 2nd recess;

[0047] 530B: 3rd concave part;

[0048] 540B: ​​4th recess;

[0049] CAP1: Capacitor part 1;

[0050] CAP2: capacitor part 2;

[0051] 1a: a portion of the first capacitor portion on the second end surface side;

[0052] 2a: a portion of the second capacitor portion on the first end surface side;

[0053] ECA, EC1A: first electrode layer side opposing portion;

[0054] ECB, EC2A: second electrode layer side opposing portion;

[0055] EC1B: first intermediate electrode layer opposing portion;

[0056] EC2B: second intermediate electrode layer opposing portion;

[0057] EC3A: third intermediate electrode layer opposing portion;

[0058] EC3B: 4th intermediate electrode layer opposing portion;

[0059] L: length direction;

[0060] T: stacking direction (height direction);

[0061] W: width direction;

[0062] LS1: 1st end face;

[0063] LS2: 2nd end face;

[0064] TS1: 1st main surface;

[0065] TS2: 2nd main surface;

[0066] WS1: side 1;

[0067] WS2: Side 2. DETAILED DESCRIPTION

[0068] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto.

[0069] A dual-structured multilayer ceramic capacitor 1 according to an embodiment will be described with reference to the accompanying drawings. Multilayer ceramic capacitor 1 in this embodiment is a temperature-compensating capacitor with a low rate of change in capacitance due to temperature changes, and is used for applications such as filters and matching high-frequency circuits. However, multilayer ceramic capacitor 1 disclosed herein is not limited to this configuration. Figure 1 1 is a perspective view of the external appearance of a double-structured multilayer ceramic capacitor 1 according to the embodiment. Figure 2 yes Figure 1 The II-II cross-sectional view is a diagram for explaining the schematic structure of the double-structured stacked body according to the embodiment. Figure 3 yes Figure 2 Sectional view III-III. Figure 4A yes Figure 2 The IVA-IVA cross-sectional view is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer. Figure 4B yes Figure 2 The IVB-IVB cross-sectional view is a cross-sectional view along the middle electrode layer.

[0070] In addition, in order to illustrate the content of the invention, the drawings are sometimes simplified and drawn schematically, and sometimes the ratios of the dimensions of the drawn components or the dimensions between the components are inconsistent with the ratios of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings, or the number of components is omitted in the drawings. For example, for the convenience of explanation, Figure 2 、 Figure 3 The number of internal electrode layers described in FIG is 7, but this does not indicate the actual number of internal electrode layers 30. Figures 6 to 8 Furthermore, the shapes, geometric conditions, terms that define their degree (e.g., terms such as “parallel,” “orthogonal,” and “same”), lengths, angle values, etc. used in the present invention are not to be construed in a strict sense, but are to be interpreted within a range that encompasses the degree to which the same function can be expected.

[0071] like Figure 1 As shown, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape and includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 so as to be spaced apart from each other.

[0072] exist Figure 1 In FIG. 1 , arrow T indicates the stacking direction as the height direction of the multilayer ceramic capacitor 1 and the multilayer body 10. The stacking direction T is also the thickness direction of the multilayer ceramic capacitor 1 and the multilayer body 10. Figure 1 In FIG. 1 , arrow L indicates the longitudinal direction of the multilayer ceramic capacitor 1 and the multilayer body 10 perpendicular to the stacking direction T. Figure 1 In FIG, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10 , which is perpendicular to the lamination direction T and the longitudinal direction L. The pair of external electrodes 40 are respectively arranged at one end and the other end of the laminate 10 in the longitudinal direction L.

[0073] exist Figures 1 to 4B In FIG, an XYZ orthogonal coordinate system is shown. The length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Z direction. Here, Figure 2 The section shown is also referred to as the LT section. Figure 3 The cross section shown is also referred to as the WT cross section. Figure 4A as well as Figure 4B The cross section shown is also referred to as the LW cross section.

[0074] like Figures 1 to 4BAs shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W perpendicular to the stacking direction T and the length direction L.

[0075] like Figure 1 As shown, the laminate 10 has a generally rectangular parallelepiped shape. Furthermore, the dimension of the laminate 10 in the longitudinal direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is where three surfaces of the laminate intersect, and a ridge is where two surfaces of the laminate intersect. Furthermore, concavities and convexities may be formed on part or all of the surface constituting the laminate 10.

[0076] The dimensions of the laminate 10 are not particularly limited. However, if the dimension in the longitudinal direction L of the laminate 10 is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the dimension in the stacking direction T of the laminate 10 is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the dimension in the width direction W of the laminate 10 is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0077] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the lamination direction T so as to sandwich the inner layer portion 11 .

[0078] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in a stacking direction T. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 and the internal electrode layer 30 located closest to the second main surface TS2 in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0079] The plurality of dielectric layers 20 are composed of a dielectric material. As described above, the multilayer ceramic capacitor 1 according to this embodiment is a temperature-compensating capacitor, and the dielectric material is a CaZrO3-based (hereinafter sometimes referred to as CZ-based) or Ca(Sr, Zr)O3-based (hereinafter sometimes referred to as CSZ-based) dielectric material. CZ-based and CSZ-based dielectric materials contain perovskite-type compounds containing at least Ca and Zr. CZ-based dielectric materials contain not only CaZrO3 but also a CaZrO3 solid solution in which a portion of Ca, a portion of Zr, or a portion of Ca and Zr are replaced with appropriate elements. The dielectric material contains at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). As an example, the dielectric layer 20 contains a perovskite-type compound containing Ca, Zr, and optionally Sr and Ti. Specifically, dielectric layer 20 contains CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), and other materials. While multilayer ceramic capacitors 1 typically generate oxygen vacancies due to firing in a reducing atmosphere, CaZrO3, in particular, suppresses the generation of oxygen vacancies due to its high band gap. This results in high reliability. Alternatively, the dielectric material may be a material containing additives such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0080] The dielectric layer 20 of this embodiment uses a material containing at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). This results in a relative dielectric constant of approximately 20 to 300, resulting in lower capacitance than high-dielectric-constant materials. Furthermore, the dielectric layer 20 of this embodiment exhibits a characteristic in which the relative dielectric constant changes approximately linearly with temperature, resulting in excellent heat resistance and high-frequency characteristics. Furthermore, the capacitance value of the dielectric layer 20 of this embodiment exhibits negligible temporal variation, resulting in minimal capacitor loss even at high temperatures, high power, and high frequencies, resulting in excellent stability. Furthermore, the dielectric constant of the dielectric layer 20 exhibits minimal temporal variation and variation due to applied voltage. Furthermore, the dielectric material is not limited to this; for example, high-dielectric-constant ceramics such as BaTiO3 (BT) can also be used.

[0081] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. The thickness of the dielectric layer 20 is particularly preferably 3 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers 20 in the inner layer portion 11 and the number of dielectric layers 20 in each of the first main surface-side outer layer portion 12 and the second main surface-side outer layer portion 13.

[0082] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31, a plurality of second internal electrode layers 32, and an intermediate electrode layer 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other in a spaced-apart manner in the longitudinal direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are alternately arranged in the stacking direction T with the dielectric layer 20 interposed therebetween.

[0083] The first internal electrode layer 31 extends to the first end surface LS1 and is connected to the first external electrode 40A, described later. The second internal electrode layer 32 extends to the second end surface LS2 and is connected to the second external electrode 40B, described later. The intermediate electrode layer 33 extends neither to the first end surface LS1 nor to the second end surface LS2, and is neither connected to the first external electrode 40A nor to the second external electrode 40B, described later. The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 included in the plurality of internal electrode layers 30 form a capacitor element connected in series. In the following description, when it is unnecessary to distinguish between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0084] like Figure 2 、 Figure 4A As shown, the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region that faces the intermediate electrode layer 33 adjacently arranged in the stacking direction T, sandwiching the dielectric layer 20 therebetween. It is located within the stacked body 10. The first internal electrode layer 31 has a first opposing portion EA that is connected to the first lead portion D1 and faces the internal electrode layer 30 adjacently arranged in the stacking direction T. The first lead portion D1 is a portion that extends from the first opposing portion EA toward the first end surface LS1 and is exposed at the first end surface LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is extended to the first end surface LS1 and connected to the first external electrode 40A.

[0085] like Figure 2 、 Figure 4AAs shown, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region that faces the intermediate electrode layer 33 disposed adjacent in the stacking direction T, sandwiching the dielectric layer 20 therebetween. It is located within the stacked body 10. The second internal electrode layer 32 has a second opposing portion EB that is connected to the second lead portion D2 and faces the internal electrode layer 30 disposed adjacent in the stacking direction T. The second lead portion D2 extends from the second opposing portion EB toward the second end surface LS2 and is exposed at the second end surface LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is extended to the second end surface LS2 and connected to the second external electrode 40B.

[0086] like Figure 2 、 Figure 4B As shown, the intermediate electrode layer 33 includes a first electrode layer side opposing portion ECA, a second electrode layer side opposing portion ECB, and a connecting portion E0. The first electrode layer side opposing portion ECA is a region that faces the first internal electrode layer 31, which is adjacently arranged in the stacking direction T, with the dielectric layer 20 interposed therebetween, and is located within the laminate 10. The second electrode layer side opposing portion ECB is a region that faces the second internal electrode layer 32, which is adjacently arranged in the stacking direction T, with the dielectric layer 20 interposed therebetween, and is located within the laminate 10. The connecting portion E0 connects the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and is located between the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB.

[0087] In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the first end face LS1 side is disposed apart from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the first end face LS1 side is disposed closer to the first end face LS1 than the end portion 40AE of the first external electrode 40A. However, this is not limiting; the end portion of the intermediate electrode layer 33 on the first end face LS1 side may also be disposed closer to the second end face LS2 than the end portion 40AE of the first external electrode 40A.

[0088] The end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed apart from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed closer to the second end face LS2 than the end portion 40BE of the second external electrode 40B. However, this is not limiting; the end portion of the intermediate electrode layer 33 on the second end face LS2 side may also be disposed closer to the first end face LS1 than the end portion 40BE of the second external electrode 40B.

[0089] like Figure 2As shown, in the multilayer ceramic capacitor 1 according to the embodiment, the first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the embodiment, the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are stacked so as to overlap alternately with the dielectric layers 20 interposed therebetween.

[0090] In the multilayer ceramic capacitor 1 of this embodiment, the first opposing portion EA and the first electrode layer-side opposing portion ECA of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a portion generating capacitance CAP1. Hereinafter, the portion generating capacitance CAP1 will be referred to as the first capacitor portion CAP1.

[0091] In the multilayer ceramic capacitor 1 of this embodiment, the second opposing portion EB and the second electrode layer-side opposing portion ECB of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a portion generating capacitance CAP2. Hereinafter, the portion generating capacitance CAP2 will be referred to as the second capacitor portion CAP2.

[0092] That is, the laminate 10 includes: a first capacitor portion CAP1 formed by the first internal electrode layer 31 and the intermediate electrode layer 33 facing each other; and a second capacitor portion CAP2 formed by the second internal electrode layer 32 and the intermediate electrode layer 33 facing each other. Figure 2 In the figure, the rectangular regions of the first capacitor portion CAP1 and the second capacitor portion CAP2, respectively, are indicated by two-dot chain lines in the LT cross-sectional view. The connecting portion E0 connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment has a so-called two-connected serial structure, in which two capacitor portions (the first capacitor portion CAP1 and the second capacitor portion CAP2) are connected in series.

[0093] The first capacitor portion CAP1 includes a portion 1a on the second end surface LS2 side. The portion 1a on the second end surface LS2 side refers to a portion of the first capacitor portion CAP1 corresponding to the end surface facing the second end surface LS2 and the vicinity of the portion corresponding to the end surface.

[0094] The second capacitor portion CAP2 has a portion 2a on the first end surface LS1 side. The portion 2a on the first end surface LS1 side refers to a portion of the second capacitor portion CAP2 corresponding to the end surface facing the first end surface LS1 and the vicinity of the portion corresponding to the end surface.

[0095] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion D1 and the second lead portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0096] The dimension in the width direction W of the first opposing portion EA and the dimension in the width direction W of the first lead portion D1 can be the same, or either dimension can be smaller. The dimension in the width direction W of the second opposing portion EB and the dimension in the width direction W of the second lead portion D2 can be the same, or either dimension can be narrower. The dimension in the width direction W of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the dimension in the width direction W of the connecting portion E0 can be the same, or either dimension can be smaller.

[0097] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are formed of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be formed of, for example, an Ag-Pd alloy.

[0098] The thickness of each of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably 0.2 μm to 2.0 μm, for example. The total number of the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 is preferably 10 to 1000.

[0099] like Figure 2 as well as Figure 3 As shown, the first principal surface-side outer layer portion 12 is located on the first principal surface TS1 side of the laminate 10. The first principal surface-side outer layer portion 12 is a collection of multiple dielectric layers 20 located between the first principal surface TS1 and the internal electrode layer 30 closest to the first principal surface TS1. On the other hand, the second principal surface-side outer layer portion 13 is located on the second principal surface TS2 side of the laminate 10. The second principal surface-side outer layer portion 13 is a collection of multiple dielectric layers 20 located between the second principal surface TS2 and the internal electrode layer 30 closest to the second principal surface TS2. The dielectric layers 20 used in the first principal surface-side outer layer portion 12 and the second principal surface-side outer layer portion 13 may be the same as the dielectric layers 20 used in the internal layer portion 11.

[0100] In addition, the laminate 10 has a series capacitor forming portion 11E. The series capacitor forming portion 11E includes the first capacitor portion CAP1, the second capacitor portion CAP2, and a connecting portion E0 of the intermediate electrode layer 33 that connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series. The series capacitor forming portion 11E is configured as a part of the inner layer portion 11. Figure 4A as well as Figure 4B , the ranges of the series capacitor forming portion 11E in the width direction W and the length direction L are shown. Note that the first capacitor portion CAP1 and the second capacitor portion CAP2 in the series capacitor forming portion 11E are also referred to as capacitor effective portions.

[0101] In addition, the stacked body 10 has a side outer layer portion. The side outer layer portion includes a first side outer layer portion WG1 and a second side outer layer portion WG2. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the first side WS1. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor forming portion 11E and the second side WS2. Figure 3 、 Figure 4A as well as Figure 4B , the range of the first side outer layer portion WG1 and the second side outer layer portion WG2 in the width direction W is shown. In addition, the side outer layer portion is also called a W interval or a side interval.

[0102] In addition, the stacked body 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 and a second end face side outer layer portion LG2. The first end face side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion D1. That is, the first end face side outer layer portion LG1 is a collection of portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions D1. The second end face side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion D2. That is, the second end face side outer layer portion LG2 is a collection of portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions D2. In Figure 2 、 Figure 4A as well as Figure 4B , the ranges of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the longitudinal direction L are shown. In addition, the end surface side outer layer portion is also referred to as an L interval or an end interval.

[0103] The series capacitor-forming portion 11E of the laminate 10 also includes a series connection region. This region encompasses the dielectric layer 20 and the connecting portion E0 located between the first capacitor portion CAP1 and the second capacitor portion CAP2. Specifically, the series connection region is the aggregate of the central portions of the multiple dielectric layers 20 in the longitudinal direction L and the multiple connecting portions E0. The series connection region is also referred to as the intermediate space.

[0104] like Figure 1 as well as Figure 2 As shown, the external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B arranged on the second end surface LS2 side of the stacked body 10 .

[0105] The first external electrode 40A and the second external electrode 40B have the same basic structure. Furthermore, the first external electrode 40A and the second external electrode 40B have shapes that are substantially plane-symmetrical with respect to a WT cross-section taken at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following description, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40.

[0106] The first external electrode 40A is arranged on the first end surface LS1. The first external electrode 40A contacts the first lead portion D1 of each of the plurality of first internal electrode layers 31 exposed on the first end surface LS1. Thus, the first external electrode 40A is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 40A may also be arranged on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0107] The second external electrode 40B is disposed on the second end surface LS2. The second external electrode 40B contacts the second lead portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. Thus, the second external electrode 40B is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0108] As described above, within the laminate 10, the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 oppose each other via the dielectric layer 20, thereby forming the first capacitor portion CAP1. The second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 oppose each other via the dielectric layer 20, thereby forming the second capacitor portion CAP2.

[0109] The connecting portion E0 connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series. Therefore, a capacitor characteristic formed by series-connected capacitance is exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0110] like Figure 2 As shown, the first external electrode 40A includes a first foundation electrode layer 50A and a first plating layer 60A disposed on the first foundation electrode layer 50A. The second external electrode 40B includes a second foundation electrode layer 50B and a second plating layer 60B disposed on the second foundation electrode layer 50B.

[0111] The first foundation electrode layer 50A is disposed on the first end surface LS1. The first foundation electrode layer 50A is connected to the first lead portion D1 of each of the plurality of first internal electrode layers 31 exposed on the first end surface LS1. In the present embodiment, the first foundation electrode layer 50A is formed so as to extend from the first end surface LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0112] The second foundation electrode layer 50B is disposed on the second end surface LS2. The second foundation electrode layer 50B contacts the second lead portion D2 of each of the plurality of second internal electrode layers 32 exposed on the second end surface LS2. In the present embodiment, the second foundation electrode layer 50B is formed so as to extend from the second end surface LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0113] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0114] The first and second base electrode layers 50A and 50B of this embodiment are sintered layers. The sintered layers preferably contain either a metal component, a glass component, or a ceramic component, or both. The metal component, for example, includes at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like. The glass component, for example, includes at least one selected from B, Si, Ba, Mg, Al, Li, and the like. The ceramic component may be the same or a different type of ceramic material as the dielectric layer 20. For example, the ceramic component may include at least one selected from CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), and the like.

[0115] The sintered layer is, for example, a sintered layer obtained by applying a conductive paste containing glass and metal to the laminate 10 and sintering it. The sintered layer can be formed by simultaneously sintering a pre-sintered laminate chip (chip) having multiple internal electrode layers and a dielectric layer, which is the raw material of the laminate 10, and the conductive paste applied to the laminate chip. Alternatively, it can be formed by applying a conductive paste to the laminate 10 and sintering it after the laminate 10 is obtained by sintering the laminate chip. In addition, in the case of the above-mentioned structure, the sintered layer is preferably formed by sintering a paste to which a ceramic material is added instead of a glass component. In this case, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20 as the added ceramic material. In addition, the sintered layer can also be a plurality of layers.

[0116] The thickness of the first foundation electrode layer 50A located on the first end surface LS1 in the longitudinal direction L is preferably about 2 μm or more and 220 μm or less in the central portion in the stacking direction T and the width direction W of the first foundation electrode layer 50A.

[0117] The thickness of the second foundation electrode layer 50B located on the second end surface LS2 in the longitudinal direction L is preferably about 2 μm or more and 220 μm or less in the central portion in the stacking direction T and the width direction W of the second foundation electrode layer 50B.

[0118] In the case where the first base electrode layer 50A is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on the portion corresponding to the stacking direction T is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the first base electrode layer 50A provided on the portion.

[0119] In the case where the first base electrode layer 50A is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on the portion corresponding to the width direction W is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the stacking direction T of the first base electrode layer 50A provided on the portion.

[0120] In the case where a second base electrode layer 50B is also provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on the portion corresponding to the stacking direction T is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the length direction L and the width direction W of the second base electrode layer 50B provided on the portion.

[0121] In the case where the second base electrode layer 50B is also provided on a portion of at least one surface of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided on the portion corresponding to the width direction W is preferably, for example, greater than 3 μm and less than 40 μm in the central portion in the longitudinal direction L and the stacking direction T of the second base electrode layer 50B provided on the portion.

[0122] The first plating layer 60A is arranged to cover the first foundation electrode layer 50A.

[0123] The second plating layer 60B is arranged to cover the second foundation electrode layer 50B.

[0124] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, and the like. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0125] In the present embodiment, the first plating layer 60A includes a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0126] In the present embodiment, the second plating layer 60B includes a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0127] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being corroded by solder when mounting the multilayer ceramic capacitor 1. Furthermore, the Sn plating layer improves solder wettability when mounting the multilayer ceramic capacitor 1. This facilitates mounting the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0128] Alternatively, the external electrode 40 of this embodiment may include, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may also be disposed so as to cover the sintered layer. When the conductive resin layer is disposed so as to cover the sintered layer, the conductive resin layer is disposed between the sintered layer and the plating layers (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the sintered layer or partially cover the sintered layer.

[0129] The conductive resin layer composed of a thermosetting resin is more flexible than conductive layers composed of, for example, a plated film or a fired product of a conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Consequently, the conductive resin layer prevents cracks from forming in the multilayer ceramic capacitor 1.

[0130] The metal constituting the conductive particles may also be Ag, Cu, Ni, Sn, Bi, or alloys thereof. The conductive particles preferably contain Ag. An example of the conductive particles is Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, making it resistant to oxidation and highly weatherable. Therefore, Ag metal powder is suitable as the conductive particles.

[0131] Alternatively, the conductive particles may be metal powder coated with Ag. When using Ag-coated metal powder, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy thereof. To maintain the properties of Ag while using an inexpensive base metal, Ag-coated metal powder is preferred.

[0132] Furthermore, the conductive particles may be Cu or Ni treated to prevent oxidation. Furthermore, the conductive particles may be metal powder coated with Sn, Ni, or Cu. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy thereof.

[0133] The shape of the conductive particles is not particularly limited. Spherical, flat, or other shapes can be used as the conductive particles, but a mixture of spherical metal powder and flat metal powder is preferably used.

[0134] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the conductivity of the conductive resin layer. Specifically, the conductive particles are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0135] The resin constituting the conductive resin layer may also include at least one selected from various well-known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is particularly suitable due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin of the conductive resin layer preferably includes a curing agent along with the thermosetting resin. When an epoxy resin is used as the base resin, the epoxy resin curing agent may also be various well-known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides.

[0136] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0137] The above is the basic structure of the multilayer ceramic capacitor 1 according to the embodiment. Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the multilayer body 10 and the external electrodes 40, is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the multilayer body 10 and the external electrodes 40, is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1, is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0138] The multilayer ceramic capacitor 1 of the present embodiment having the above-described basic structure has the following features in the external electrodes 40 (ie, the first external electrode 40A and the second external electrode 40B).

[0139] The first external electrode 40A of this embodiment is as follows Figure 2 As shown, the first end surface side external electrode 400A is arranged on the first end surface LS1, the first main surface side external electrode 411A is arranged on the first main surface TS1, and the second main surface side external electrode 412A is arranged on the second main surface TS2, and Figure 4A as well as Figure 4B As shown, the first side surface side external electrode 421A is arranged on the first side surface WS1 and the second side surface side external electrode 422A is arranged on the second side surface WS2 .

[0140] like Figure 2 As shown, the first end surface-side external electrode 40A includes a first end surface-side base electrode layer 500A disposed on the first end surface LS1 and a first end surface-side plating layer 600A formed above the first end surface-side base electrode layer 500A. The first end surface-side base electrode layer 500A is a portion of the first base electrode layer 50A. The first end surface-side plating layer 600A is a portion of the first plating layer 60A and includes a first Ni plating layer 61A and a first Sn plating layer 62A formed on the first Ni plating layer 61A.

[0141] like Figure 2 As shown, the first main surface-side external electrode 411A of the first external electrode 40A includes a first main surface-side base electrode layer 511A disposed on the first main surface TS1 and a first main surface-side plating layer 611A formed above the first main surface-side base electrode layer 511A. The first main surface-side base electrode layer 511A is a portion of the first base electrode layer 50A. The first main surface-side plating layer 611A is a portion of the first plating layer 60A and includes a first Ni plating layer 61A and a first Sn plating layer 62A formed on the first Ni plating layer 61A.

[0142] like Figure 2 As shown, the second main surface-side external electrode 412A of the first external electrode 40A includes a second main surface-side base electrode layer 512A disposed on the second main surface TS2 and a second main surface-side plating layer 612A formed above the second main surface-side base electrode layer 512A. The second main surface-side base electrode layer 512A is a portion of the first base electrode layer 50A. The second main surface-side plating layer 612A is a portion of the first plating layer 60A and includes a first Ni plating layer 61A and a first Sn plating layer 62A formed on the first Ni plating layer 61A.

[0143] like Figure 4A as well as Figure 4B As shown, the first side surface external electrode 421A of the first external electrode 40A includes a first side surface base electrode layer 521A disposed on the first side surface WS1 and a first side surface plating layer 621A formed above the first side surface base electrode layer 521A. The first side surface base electrode layer 521A is a portion of the first base electrode layer 50A. The first side surface plating layer 621A is a portion of the first plating layer 60A and includes a first Ni plating layer 61A and a first Sn plating layer 62A formed on the first Ni plating layer 61A.

[0144] like Figure 4A as well as Figure 4BAs shown, the second-side-side external electrode 422A of the first external electrode 40A includes a second-side-side base electrode layer 522A disposed on the second side surface WS2 and a second-side-side plating layer 622A formed above the second-side-side base electrode layer 522A. The second-side-side base electrode layer 522A is a portion of the first base electrode layer 50A. The second-side-side plating layer 622A is a portion of the first plating layer 60A and includes a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0145] The second external electrode 40B of this embodiment is as follows Figure 2 As shown, the second end surface side external electrode 400B is arranged on the second end surface LS2, the third main surface side external electrode 411B is arranged on the first main surface TS1, and the fourth main surface side external electrode 412B is arranged on the second main surface TS2, and Figure 4A as well as Figure 4B As shown, the third side surface external electrode 421B is arranged on the first side surface WS1 and the fourth side surface external electrode 422B is arranged on the second side surface WS2 .

[0146] like Figure 2 As shown, the second end surface-side external electrode 40B includes a second end surface-side base electrode layer 500B disposed on the second end surface LS2 and a second end surface-side plating layer 600B formed above the second end surface-side base electrode layer 500B. The second end surface-side base electrode layer 500B is a portion of the second base electrode layer 50B. The second end surface-side plating layer 600B is a portion of the second plating layer 60B and includes a second Ni plating layer 61B and a second Sn plating layer 62B formed on the second Ni plating layer 61B.

[0147] like Figure 2 As shown, the third main surface-side external electrode 411B of the second external electrode 40B includes a third main surface-side base electrode layer 511B disposed on the first main surface TS1 and a third main surface-side plating layer 611B formed above the third main surface-side base electrode layer 511B. The third main surface-side base electrode layer 511B is a portion of the second base electrode layer 50B. The third main surface-side plating layer 611B is a portion of the second plating layer 60B and includes a second Ni plating layer 61B and a second Sn plating layer 62B formed on the second Ni plating layer 61B.

[0148] like Figure 2As shown, the fourth main surface-side external electrode 412B of the second external electrode 40B includes a fourth main surface-side base electrode layer 512B disposed on the second main surface TS2 and a fourth main surface-side plating layer 612B formed above the fourth main surface-side base electrode layer 512B. The fourth main surface-side base electrode layer 512B is a portion of the second base electrode layer 50B. The fourth main surface-side plating layer 612B is a portion of the second plating layer 60B and includes a second Ni plating layer 61B and a second Sn plating layer 62B formed on the second Ni plating layer 61B.

[0149] like Figure 4A as well as Figure 4B As shown, the third-side external electrode 421B of the second external electrode 40B includes a third-side base electrode layer 521B disposed on the first side surface WS1 and a third-side plated layer 621B formed above the third-side base electrode layer 521B. The third-side base electrode layer 521B is a portion of the second base electrode layer 50B. The third-side plated layer 621B is a portion of the second plated layer 60B and includes a second Ni plated layer 61B and a second Sn plated layer 62B formed on the second Ni plated layer 61B.

[0150] like Figure 4A as well as Figure 4B As shown, the fourth side surface external electrode 422B of the second external electrode 40B includes a fourth side surface base electrode layer 522B arranged on the second side surface WS2 and a fourth side surface plating layer 622B formed above the fourth side surface base electrode layer 522B. The fourth side surface base electrode layer 522B is a portion of the second base electrode layer 50B. The fourth side surface plating layer 622B is a portion of the second plating layer 60B and includes a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B. The maximum thickness of each of the first principal surface base electrode layer 511A, the second principal surface base electrode layer 512A, the third principal surface base electrode layer 511B, and the fourth principal surface base electrode layer 512B is not limited, but is preferably, for example, not less than 15 μm and not more than 40 μm.

[0151] like Figure 2 As shown, the first main surface side external electrode 411A of the first external electrode 40A has a first recess 510A that is recessed toward the laminate 10 side. The first recess 510A is formed on the surface of the first main surface side external electrode 411A. The first recess 510A has a width direction W (i.e., perpendicular to the LT cross section) perpendicular to the LT cross section. Figure 2The first recess 510A preferably extends in the width direction W of the first main-surface-side external electrode 411A. The first recess 510A may be located approximately near the center of the first main-surface-side external electrode 411A in the longitudinal direction L, or may be located on the inner or outer sides in the longitudinal direction L.

[0152] The first recess 510A in this embodiment is formed by recessing the first principal surface-side base electrode layer 511A and the first principal surface-side plating layer 611A toward the first principal surface TS1 of the laminate 10. Preferably, the bottom of the first recess 510A is recessed in an R-shape when viewed in cross-section (LT), and the edges at both ends in the longitudinal direction (L) where the surface of the first principal surface-side external electrode 411A transitions are also gently R-shaped. The depth of the first recess 510A is not limited, but is preferably, for example, 3 μm to 35 μm. The depth referred to herein refers to the shortest distance between a line connecting the surfaces of the first principal surface-side external electrodes 411A on both sides of the first recess 510A in the longitudinal direction (L) and the deepest portion of the first recess 510A. The width of the first recess 510A (the dimension corresponding to the longitudinal direction (L)) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0153] like Figure 2 As shown, the second main surface side external electrode 412A of the first external electrode 40A has a second recess 520A that is recessed toward the laminate 10 side. The second recess 520A is formed on the surface of the second main surface side external electrode 412A. The second recess 520A has a width direction W (i.e., perpendicular to the LT cross section) perpendicular to the LT cross section. Figure 2 The second recess 520A preferably extends in the width direction W of the second main-surface-side external electrode 412A. The second recess 520A may be located approximately near the center of the second main-surface-side external electrode 412A in the longitudinal direction L, or may be located on the inner or outer sides in the longitudinal direction L.

[0154] The second recess 520A in this embodiment is formed by recessing the second principal surface-side base electrode layer 512A and the second principal surface-side plating layer 612A toward the second principal surface TS2 of the laminate 10. Preferably, the bottom of the second recess 520A is recessed in an R-shape when viewed in cross-section (LT), and the edges at both ends in the longitudinal direction (L) where the surface of the second principal surface-side external electrode 412A transitions are also gently R-shaped. The depth of the second recess 520A is not limited, but is preferably, for example, 3 μm to 35 μm. The depth referred to herein refers to the shortest distance between a line connecting the surfaces of the second principal surface-side external electrode 412A on both sides of the second recess 520A in the longitudinal direction (L) and the deepest portion of the second recess 520A. The width of the second recess 520A (the dimension corresponding to the longitudinal direction (L)) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0155] like Figure 2 As shown, the third main surface side external electrode 411B of the second external electrode 40B has a third recess 530B that is recessed toward the laminate 10 side. The third recess 530B is formed on the surface of the third main surface side external electrode 411B. The third recess 530B has a width direction W (i.e., perpendicular to the LT cross section) that is perpendicular to the LT cross section. Figure 2 The third recess 530B preferably extends in the width direction W of the third principal-surface-side external electrode 411B. The third recess 530B may be disposed approximately near the center of the third principal-surface-side external electrode 411B in the longitudinal direction L, or may be disposed on the inner or outer sides in the longitudinal direction L.

[0156] The third recess 530B in this embodiment is formed by recessing the third principal surface-side base electrode layer 511B and the third principal surface-side plating layer 611B toward the first principal surface TS1 of the laminate 10. Preferably, the bottom of the third recess 530B is recessed in an R-shape when viewed in cross-section along the LT direction, and the edges at both ends in the longitudinal direction L, where the surface of the third principal surface-side external electrode 411B transitions, are also gently R-shaped. The depth of the third recess 530B is not limited, but is preferably, for example, 3 μm to 35 μm. The depth referred to herein refers to the shortest distance between a line connecting the surfaces of the third principal surface-side external electrodes 411B on both sides of the third recess 530B in the longitudinal direction L and the deepest portion of the third recess 530B. The width of the third recess 530B (the dimension along the longitudinal direction L) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0157] like Figure 2As shown, the fourth main surface side external electrode 412B of the second external electrode 40B has a fourth recess 540B that is recessed toward the laminate 10 side. The fourth recess 540B is formed on the surface of the fourth main surface side external electrode 412B. The fourth recess 540B has a width direction W (i.e., perpendicular to the LT cross section) that is perpendicular to the LT cross section. Figure 2 The fourth recess 540B preferably extends in the longitudinal direction W of the fourth principal-surface-side external electrode 412B. The fourth recess 540B may be disposed approximately near the center of the fourth principal-surface-side external electrode 412B in the longitudinal direction L, or may be disposed on the inner side or the outer side in the longitudinal direction L.

[0158] The fourth recess 540B in this embodiment is formed by recessing the fourth principal surface-side base electrode layer 512B and the fourth principal surface-side plating layer 612B toward the second principal surface TS2 of the laminate 10. Preferably, the bottom of the fourth recess 540B is recessed in an R-shape when viewed in cross-section (LT), and the edges at both ends in the longitudinal direction (L) where the surface of the fourth principal surface-side external electrode 412B transitions are also gently R-shaped. The depth of the fourth recess 540B is not limited, but is preferably, for example, 3 μm or more and 35 μm or less. The depth referred to herein refers to the shortest distance between a line connecting the surfaces of the fourth principal surface-side external electrode 412B on both sides of the fourth recess 540B in the longitudinal direction (L) and the deepest portion of the fourth recess 540B. The width of the fourth recess 540B (the dimension corresponding to the longitudinal direction (L)) is not limited, but is preferably, for example, 50 μm or more and 400 μm or less.

[0159] The depth of the first recess 510A is not limited, but is preferably 10% to 80% of the maximum thickness of the first principal-surface-side external electrode 411A in the stacking direction T. For example, it can be 40% to 80% or 60% to 80%. The depth of the second recess 520A is not limited, but is preferably 10% to 80% of the maximum thickness of the second principal-surface-side external electrode 412A in the stacking direction T. For example, it can be 40% to 80% or 60% to 80%. The depth of the third recess 530B is not limited, but is preferably 10% to 80% of the maximum thickness of the third principal-surface-side external electrode 411B in the stacking direction T. For example, it can be 40% to 80% or 60% to 80%. The depth of the fourth recess 540B is not limited, but is preferably greater than 10% and less than 80% of the maximum thickness of the fourth main surface side external electrode 412B corresponding to the stacking direction T. For example, it can be greater than 40% and less than 80%, or greater than 60% and less than 80%.

[0160] Here, in the LT cross section of the multilayer ceramic capacitor 1, Figure 2 , a first imaginary line 100 and a second imaginary line 200 are shown. The first imaginary line 100 is an imaginary line connecting the first recess 510A and the fourth recess 540B in the LT cross-section of the multilayer ceramic capacitor 1. The first imaginary line 100 connects the deepest part of the first recess 510A and the deepest part of the fourth recess 540B. The second imaginary line 200 is an imaginary line connecting the second recess 520A and the third recess 530B in the LT cross-section of the multilayer ceramic capacitor 1. The second imaginary line 200 connects the deepest part of the second recess 520A and the deepest part of the third recess 530B. Furthermore, in Figure 2 , an intersection 300 of the first imaginary line 100 and the second imaginary line 200 is shown.

[0161] In this embodiment, the intersection 300 of the first imaginary line 100 and the second imaginary line 200 is located between the first capacitor unit CAP1 and the second capacitor unit CAP2 in the longitudinal direction L. The intersection 300 of the first imaginary line 100 and the second imaginary line 200 is located in the aforementioned series connection region (intermediate gap).

[0162] In the present embodiment, the first imaginary line 100 intersects a portion 1 a on the second end face LS2 side of the first capacitor portion CAP1 and intersects a portion 2 a on the first end face LS1 side of the second capacitor portion CAP2.

[0163] In the present embodiment, the second imaginary line 200 intersects a portion 1 a on the second end face LS2 side of the first capacitor portion CAP1 and intersects a portion 2 a on the first end face LS1 side of the second capacitor portion CAP2.

[0164] In the multilayer ceramic capacitor 1 of this embodiment, the external electrodes 40 (i.e., the first external electrode 40A and the second external electrode 40B) each have tensile stress as residual stress. This tensile stress is generated by contraction of the sintered layers (the first base electrode layer 50A and the second base electrode layer 50B) of the external electrodes 40 formed on the surface of the laminate 10 during cooling. For example, the tensile stress acts from the main surface-side external electrode toward the center of the end surface-side external electrode.

[0165] The tensile stress as the residual stress of the first external electrode 40A and the second external electrode 40B is, for example, 10 MPa or more or 50 MPa or more.

[0166] Regarding the method for measuring the depth and width of each of the aforementioned recesses, for example, the following method can be used. The multilayer ceramic capacitor 1 is ground from the first side surface WS1 or the second side surface WS2 to a position approximately halfway along the width direction W. This exposes the LT cross-section of the multilayer ceramic capacitor 1 at the exact center along the width direction W. Next, the depth and width of the recesses in the LT cross-section exposed by grinding are measured using a digital microscope. This allows the depth and width of each recess to be confirmed.

[0167] As described above, in the multilayer ceramic capacitor 1 of the present embodiment, the first external electrode 40A and the second external electrode 40B have tensile stress. This tensile stress can be measured by the following method.

[0168] First, the multilayer ceramic capacitor 1 is immersed in a liquid for a predetermined time using a metal stripping agent for Sn stripping, and then rinsed with water to strip the Sn plating layer. Next, the multilayer ceramic capacitor 1 is immersed in a liquid for a predetermined time using a metal stripping agent for Ni stripping, and then rinsed with water to strip the Ni plating layer. Then, near the end portions of the base electrode layers on the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 ( Figure 2 The stress was measured using X-ray diffraction (μ-XRD (X-ray Diffraction)) on the surface of the end portion 40AE and the vicinity of the end portion 40BE.

[0169] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as the aforementioned requirements are met. However, a preferred manufacturing method includes the following steps. Each step is described in detail below.

[0170] A dielectric sheet for dielectric layer 20 and a conductive paste for internal electrode layer 30 are prepared. The conductive paste for dielectric sheet and internal electrode layer contains a binder and a solvent. The binder and solvent may be known binders and solvents.

[0171] For example, a conductive paste for the internal electrode layer 30 is printed in a predetermined pattern on the dielectric sheet by screen printing, gravure printing, or the like. Thus, a dielectric sheet having patterns for the first internal electrode layer 31 and the second internal electrode layer 32 formed thereon, and a dielectric sheet having a pattern for the intermediate electrode layer 33 formed thereon are prepared.

[0172] A predetermined number of dielectric sheets without the internal electrode layer 30 pattern printed thereon are stacked to form the portion that will become the first principal surface outer layer portion 12 on the first principal surface TS1 side. Dielectric sheets with the first internal electrode layer 31 pattern and the second internal electrode layer 32 pattern, and dielectric sheets with the intermediate electrode layer 33 pattern, are stacked alternately thereon. This forms the portion that will become the inner layer portion 11. A predetermined number of dielectric sheets without the internal electrode layer 30 pattern printed thereon are stacked to form the portion that will become the second principal surface outer layer portion 13 on the second principal surface TS2 side. This completes the production of a laminated sheet.

[0173] The laminated sheets are pressed in the height direction by isostatic pressing or the like to produce a laminated block.

[0174] The laminated block is cut into a given size, thereby cutting out a plurality of laminated pieces.

[0175] At this time, the corners and ridges of the stacked small pieces may be rounded by barrel polishing or the like.

[0176] The stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0177] A conductive paste serving as a base electrode layer is applied to both end surfaces of the laminate 10 .

[0178] In this embodiment, the base electrode layer is a sintered layer. For example, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A sintering process is then performed to form the base electrode layer. The sintering process temperature is preferably between 700°C and 900°C.

[0179] Furthermore, when the pre-fired laminated pieces and the conductive paste applied to the laminated pieces are fired simultaneously, the sintered layer is preferably formed by sintering a paste to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is particularly preferably the same type of ceramic material as that used in dielectric layer 20. In this case, the conductive paste is applied to the pre-fired laminated pieces, and the laminated pieces and the conductive paste applied to the laminated pieces are sintered simultaneously to form laminate 10, which has the sintered layer formed thereon.

[0180] Next, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. The plating process can be performed using either electrolytic plating or electroless plating.

[0181] However, electroless plating requires pretreatment with a catalyst or the like to increase the deposition rate of the coating, which has the disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. The Ni plating layer and the Sn plating layer are sequentially formed, for example, by barrel plating.

[0182] Furthermore, when a conductive resin layer is provided as the base electrode layer, the conductive resin layer can also be arranged to cover the sintered layer. When providing a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer and then heat-treated at a temperature of 250 to 550°C or higher. This heat cures the thermosetting resin, forming the conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent scattering of the resin and oxidation of the various metal components, the oxygen concentration is preferably 100 ppm or less.

[0183] Here, when obtaining the above-mentioned groove-shaped recessed portion on each main surface side external electrode of the external electrode 40 as in the embodiment, for example, the following method can be mentioned.

[0184] Figures 5A to 5C The step of forming the foundation electrode layer (the first foundation electrode layer 50A and the second foundation electrode layer 50B) in this method is schematically shown. Figure 5A As shown, the base electrode paste 50P that becomes the base electrode layer is applied by dipping the end portion of the laminate 10 in the longitudinal direction L. Figure 5B As shown in FIG. 1 , the stacked body 10 is passed between a pair of rod-shaped clamps 90 disposed facing each other. The passing direction is Figure 5B The middle is the inside and outside direction of the paper. Figure 5C As shown, groove-shaped recesses G are formed on both sides of the base electrode paste 50P by the tips of a pair of rod-shaped jigs 90. These recesses G become the first recess 510A, second recess 520A, third recess 530B, and fourth recess 540B described above. Then, Ni and Sn plating layers are formed on the base electrode layer.

[0185] Alternatively, the recessed portion can be formed by appropriately adjusting the viscosity of the base electrode paste 50P or designing a dipping method.

[0186] Through the above-described manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0187] The multilayer ceramic capacitor 1 according to the embodiment has a so-called serial structure, a two-ply structure. In this multilayer ceramic capacitor 1, significant electrostriction may occur between the series-connected capacitor sections, generating a force (tensile stress) within the stack 10 in the stacking direction T, extending from the center of the stack 10 toward the first and second main surfaces TS1 and TS2. Furthermore, due to shrinkage of the sintered layer, the external electrodes 40 may have residual tensile stress. This tensile stress on the external electrodes 40 generates a force (tensile stress) within the stack 10, extending from the center of the stack 10 toward the ends of the external electrodes 40.

[0188] Figure 6 LT is a schematic sectional view of the multilayer ceramic capacitor 1 for illustrating the above-mentioned forces. Figure 6 In FIG, the component force in the stacking direction T caused by the electrostriction generated between the first capacitor portion CAP1 and the second capacitor portion CAP2 is shown by arrow K1. The component force K1 in the stacking direction is a tensile stress from the center of the stacked body 10 toward the first main surface TS1 and the second main surface TS2. Figure 6 In the figure, arrows K2 indicate the force acting from the center of the stack 10 toward the ends of the first and second external electrodes 40A, 40B, respectively, due to the residual stress in the external electrodes 40. The residual stress in the external electrodes 40 is indicated by arrows K3 within each of the first and second external electrodes 40A, 40B. As described above, the residual stress K3 within the external electrodes 40 is a tensile stress generated by, for example, contraction of the sintered layers (first and second base electrode layers 50A, 50B) of the external electrodes 40 formed on the surface of the stack 10 during cooling. The residual stress within the external electrodes 40 acts on the first external electrode 40A from the first principal surface-side external electrode 411A and the second principal surface-side external electrode 412A toward the center of the first end surface-side external electrode 400A. The residual stress in the external electrode 40 acts on the second external electrode 40B from the third main surface side external electrode 411B and the fourth main surface side external electrode 412B toward the center of the second end surface side external electrode 400B. Figure 6 In FIG. 1 , a component in the stacking direction of a force K2 directed from the center of the stacked body 10 toward the end of the external electrode 40 due to the residual stress of the external electrode 40 is shown by a dotted arrow K4 .

[0189] Here, the stacking direction force K4 of the force K1 due to electrostriction and the force K2 extending from the center of the stack 10 toward the end of the external electrode 40 due to the residual stress in the external electrode 40 is synthesized. If this synthesized stacking direction force increases, interlayer delamination may occur in the stack 10. However, by providing each main surface-side external electrode with a recessed portion as in the multilayer ceramic capacitor 1 of this embodiment, the residual stress in the external electrode 40 extending from the main surface-side external electrode toward the end surface-side external electrode is partially blocked by the recessed portion, thereby weakening this force.

[0190] Specifically, the residual stress K3 in the first external electrode 40A extending from the first principal-surface-side external electrode 411A toward the first end-surface-side external electrode 400A is partially interrupted by the first recess 510A, thereby reducing the force. The residual stress K3 in the first external electrode 40A extending from the second principal-surface-side external electrode 412A toward the first end-surface-side external electrode 400A is partially interrupted by the second recess 520A, thereby reducing the force. The residual stress K3 in the second external electrode 40B extending from the third principal-surface-side external electrode 411B toward the second end-surface-side external electrode 400B is partially interrupted by the third recess 530B, thereby reducing the force. The residual stress K3 in the second external electrode 40B extending from the fourth principal-surface-side external electrode 412B toward the second end-surface-side external electrode 400B is partially interrupted by the fourth recess 540B, thereby reducing the force.

[0191] Therefore, the force K2 directed from the center of the stack 10 toward the ends of the external electrodes 40 is weakened due to the residual stress in the external electrodes 40, and the force that tends to cause interlayer delamination (i.e., the component force K4 in the stacking direction described above) is weakened. As a result, the occurrence of interlayer delamination is suppressed.

[0192] According to the multilayer ceramic capacitor 1 according to the above-described embodiment, the following effects are achieved.

[0193] (1) A multilayer ceramic capacitor 1 according to an embodiment comprises: a laminate 10 including a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately laminated in a lamination direction T, and including a first main surface TS1 and a second main surface TS2 opposing each other in the lamination direction T, a first side surface WS1 and a second side surface WS2 opposing each other in a width direction W perpendicular to the lamination direction T, and a first end surface LS1 and a second end surface LS2 opposing each other in a length direction L perpendicular to the lamination direction T and the width direction W; and a pair of external electrodes 40 disposed at two ends of the laminate 10 in the length direction L, spaced apart from each other. The internal electrode layer 30 includes: a first internal electrode layer 31, which is led to the first end face LS1; a second internal electrode layer 32, which is led to the second end face LS2; and an intermediate electrode layer 33, which is not led to either the first end face LS1 or the second end face LS2. The laminate 10 includes: a first capacitor portion CAP1, which is formed by the first internal electrode layer 31 and the intermediate electrode layer 33 being opposed to each other; and a second capacitor portion CAP2, which is formed by the second internal electrode layer 32 and the intermediate electrode layer 33 being opposed to each other. The external electrode 40 includes: a first external electrode 40A, which is arranged on the first end face LS1 side; and a second external electrode 40B. 40B, arranged on the second end surface LS2 side, the first external electrode 40A has: a first main surface side external electrode 411A, arranged on the first main surface TS1 side; and a second main surface side external electrode 412A, arranged on the second main surface TS2 side, the second external electrode 40B has: a third main surface side external electrode 411B, arranged on the first main surface TS1 side; and a fourth main surface side external electrode 412B, arranged on the second main surface TS2 side, the first main surface side external electrode 411A has a first recessed portion 510A recessed toward the stack 10 side, and the second main surface side external electrode 412A has a second recessed portion recessed toward the stack 10 side. 520A, the third main surface side external electrode 411B has a third recess 530B recessed toward the side of the stack 10, and the fourth main surface side external electrode 412B has a fourth recess 540B recessed toward the side of the stack 10. In a cross-sectional view along the length direction L and the stacking direction T, an intersection 300 of a first imaginary line 100 connecting the first recess 510A and the fourth recess 540B and a second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the length direction L, and the external electrode 40 has a tensile stress as a residual stress.

[0194] Thus, in the multilayer ceramic capacitor 1 of high withstand voltage specification, it is possible to suppress the occurrence of interlayer delamination in the laminate 10 .

[0195] (2) Preferably, in the multilayer ceramic capacitor 1 according to the embodiment, the first imaginary line 100 intersects with the portion 1a on the second end face LS2 side of the first capacitor portion CAP1 and intersects with the portion 2a on the first end face LS1 side of the second capacitor portion CAP2, and the second imaginary line 200 intersects with the portion 1a on the second end face LS2 side of the first capacitor portion CAP1 and intersects with the portion 2a on the first end face LS1 side of the second capacitor portion CAP2.

[0196] Thus, in the multilayer ceramic capacitor 1 of high withstand voltage specification, it is possible to suppress the occurrence of interlayer delamination in the laminate 10 .

[0197] The present invention is not limited to the dual-structured multilayer ceramic capacitor 1 according to the above embodiment, but can be widely applied to multilayer ceramic capacitors having a serial structure. A first modification having a triple structure and a second modification having a quadruple structure are described below.

[0198] (First Modification)

[0199] The multilayer ceramic capacitor 1 according to the first modification is a triple-structured multilayer ceramic capacitor. Figure 7 A multilayer ceramic capacitor 1 according to a first modification will be described. In the following description, detailed descriptions of the same configurations as those in the above-described embodiment may be omitted. Figure 7 LT is a cross-sectional view schematically showing a multilayer ceramic capacitor 1 according to a first modification. The manufacturing method of the first modification is the same as that of the above-described embodiment, and a description thereof will be omitted.

[0200] In the multilayer ceramic capacitor 1 of the first modification, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 , a plurality of second internal electrode layers 32 , and an intermediate electrode layer 33 .

[0201] like Figure 7 As shown, the intermediate electrode layer 33 according to the first modification includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332 .

[0202] The first intermediate electrode layer 331 includes a first electrode layer side opposing portion EC1A, a first intermediate electrode layer opposing portion EC1B, and a first connecting portion E10. The first electrode layer side opposing portion EC1A is a region opposing the first internal electrode layer 31 arranged adjacent to the stacking direction T and is located within the stack 10. The first intermediate electrode layer opposing portion EC1B is a region opposing the second intermediate electrode layer 332 arranged adjacent to the stacking direction T and is located within the stack 10. The first connecting portion E10 connects the first electrode layer side opposing portion EC1A and the first intermediate electrode layer opposing portion EC1B and is located between the first electrode layer side opposing portion EC1A and the first intermediate electrode layer opposing portion EC1B.

[0203] The second intermediate electrode layer 332 includes a second electrode layer side opposing portion EC2A, a second intermediate electrode layer opposing portion EC2B, and a second connecting portion E20. The second electrode layer side opposing portion EC2A opposes the second internal electrode layer 32, which is arranged adjacent to the stacking direction T. The second intermediate electrode layer opposing portion EC2B opposes the first intermediate electrode layer 331, which is arranged adjacent to the stacking direction T. The second connecting portion E20 connects the second electrode layer side opposing portion EC2A and the second intermediate electrode layer opposing portion EC2B and is arranged between the second electrode layer side opposing portion EC2A and the second intermediate electrode layer opposing portion EC2B.

[0204] like Figure 7 As shown, in the multilayer ceramic capacitor 1 according to the first modification, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the first modification, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the longitudinal direction L.

[0205] In the multilayer ceramic capacitor 1 according to the first modification, the first internal electrode layers 31 and the second intermediate electrode layers 332 and the second internal electrode layers 32 and the first intermediate electrode layers 331 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0206] In the first variant, the first opposing portion EA and the first electrode layer-side opposing portion EC1A oppose each other via the dielectric layer 20, thereby forming the first capacitor portion CAP1, which generates capacitance CAP1. The second opposing portion EB and the second electrode layer-side opposing portion EC2A oppose each other via the dielectric layer, thereby forming the second capacitor portion CAP2, which generates capacitance CAP2. The first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B oppose each other via the dielectric layer 20, thereby forming the third capacitor portion CAP3, which generates capacitance CAP3. The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the third capacitor portion CAP3 in series. The multilayer ceramic capacitor 1 of the first variant is a multilayer ceramic capacitor having a so-called triple structure, a serial structure, with three capacitor portions (the first capacitor portion CAP1, the second capacitor portion CAP2, and the third capacitor portion CAP3) connected in series.

[0207] The laminate 10 also includes a series capacitor forming portion 11E. This portion includes a first capacitor portion CAP1, a second capacitor portion CAP2, a third capacitor portion CAP3, a portion connecting the first and third capacitor portions CAP1 and CAP3 in series, and a portion connecting the second and third capacitor portions CAP2 and CAP3 in series. The series capacitor forming portion 11E forms part of the inner portion 11. The first, second, and third capacitor portions CAP1 and CAP2 in the series capacitor forming portion 11E are also referred to as a capacitor effective portion.

[0208] Furthermore, the series capacitor forming portion 11E of the stacked body 10 includes a first series connection region and a second series connection region. The first series connection region is a portion located between the first capacitor portion CAP1 and the third capacitor portion CAP3, comprising the dielectric layer 20 and the first connecting portion E10. The second series connection region is a portion located between the second capacitor portion CAP2 and the third capacitor portion CAP3, comprising the dielectric layer 20 and the second connecting portion E20. Specifically, the first series connection region is a collection of portions of the plurality of dielectric layers 20 that overlap with the first connecting portion E10 when viewed in the stacking direction T, and the plurality of first connecting portions E10. The second series connection region is a collection of portions of the plurality of dielectric layers 20 that overlap with the second connecting portion E20 when viewed in the stacking direction T, and the plurality of second connecting portions E20.

[0209] like Figure 7 As shown, the external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B arranged on the second end surface LS2 side of the stacked body 10 .

[0210] The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the third capacitor portion CAP3 in series. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics based on series-connected capacitance.

[0211] In the multilayer ceramic capacitor 1 according to the first modification, similarly to the above-described embodiment, each main surface side external electrode has a groove-shaped recessed portion that is recessed toward the side of the multilayer body 10. That is, the first main surface side external electrode 411A of the first external electrode 40A has a first recessed portion 510A, and the second main surface side external electrode 412A has a second recessed portion 520A. The third main surface side external electrode 411B of the second external electrode 40B has a third recessed portion 530B, and the fourth main surface side external electrode 412B has a fourth recessed portion 540B. Furthermore, as Figure 7 As shown, in the LT cross-sectional view, the intersection 300 of the first imaginary line 100 connecting the first recess 510A and the fourth recess 540B and the second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the longitudinal direction L. Furthermore, in the multilayer ceramic capacitor 1 of the first modified example, similarly to the above-described embodiment, both of the external electrodes 40 (i.e., the first external electrode 40A and the second external electrode 40B) have tensile stress as residual stress.

[0212] (3) In the multilayer ceramic capacitor 1 according to the first variant, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332, the first intermediate electrode layer 331 having a first electrode layer side opposing portion EC1A opposing to the first internal electrode layer 31 arranged adjacent to the stacking direction T and a first intermediate electrode layer opposing portion EC1B opposing to the second intermediate electrode layer 332 arranged adjacent to the stacking direction T, and the second intermediate electrode layer 332 having a second electrode layer side opposing portion EC2A opposing to the second internal electrode layer 32 arranged adjacent to the stacking direction T and a second intermediate electrode layer opposing portion EC2B opposing to the first intermediate electrode layer 331 arranged adjacent to the stacking direction T.

[0213] Even in such a high-voltage-resistant triple-structured multilayer ceramic capacitor 1 , the occurrence of interlayer delamination in the laminate 10 can be suppressed.

[0214] (Second Modification)

[0215] The multilayer ceramic capacitor 1 according to the second modification is a quadruple structure multilayer ceramic capacitor. Figure 8A multilayer ceramic capacitor 1 according to a second modification will be described. In the following description, detailed descriptions of the same structures as those in the above-described embodiment and the first modification will be omitted. Figure 8 LT is a cross-sectional view schematically showing a multilayer ceramic capacitor 1 according to a second modification. The manufacturing method of the second modification is the same as that of the above-described embodiment, and a description thereof will be omitted.

[0216] In the multilayer ceramic capacitor 1 of the second modification, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 , a plurality of second internal electrode layers 32 , and an intermediate electrode layer 33 .

[0217] like Figure 8 As shown, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 , a second intermediate electrode layer 332 , and a third intermediate electrode layer 333 .

[0218] The first intermediate electrode layer 331 includes a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent in the stacking direction T, a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacent in the stacking direction T, and a first connecting portion E10.

[0219] The second intermediate electrode layer 332 includes a second electrode layer side opposing portion EC2A opposing the second internal electrode layer 32 arranged adjacent in the stacking direction T, a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacent in the stacking direction T, and a second connecting portion E20.

[0220] The third intermediate electrode layer 333 includes a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 adjacent to the stacking direction T, a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 adjacent to the stacking direction T, and a third connecting portion E30.

[0221] like Figure 8 As shown, in the multilayer ceramic capacitor 1 according to the second modification, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the longitudinal direction L. In the multilayer ceramic capacitor 1 according to the second modification, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the longitudinal direction L.

[0222] In the multilayer ceramic capacitor 1 according to the second modification, the first internal electrode layers 31 , the third intermediate electrode layers 333 , and the second internal electrode layers 32 are stacked alternately with the first intermediate electrode layers 331 and the second intermediate electrode layers 332 interposed therebetween via the dielectric layers 20 .

[0223] In the second variant, the first opposing portion EA and the first electrode layer-side opposing portion EC1A oppose each other via the dielectric layer 20, thereby forming the first capacitor portion CAP1 that generates electrostatic capacitance CAP1. The second opposing portion EB and the second electrode layer-side opposing portion EC2A oppose each other via the dielectric layer 20, thereby forming the second capacitor portion CAP2 that generates electrostatic capacitance CAP2. The first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A oppose each other via the dielectric layer 20, thereby forming the third capacitor portion CAP3 that generates electrostatic capacitance CAP3. The second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B oppose each other via the dielectric layer 20, thereby forming the fourth capacitor portion CAP4 that generates electrostatic capacitance CAP4. The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the fourth capacitor portion CAP4 in series. The third connecting portion E30 connects the third capacitor portion CAP3 and the fourth capacitor portion CAP4 in series. The multilayer ceramic capacitor 1 of the second modified example is a multilayer ceramic capacitor having a so-called quadruple series structure, in which four capacitor portions (the first capacitor portion CAP1, the second capacitor portion CAP2, the third capacitor portion CAP3, and the fourth capacitor portion CAP4) are connected in series.

[0224] The laminate 10 also includes a series capacitor forming portion 11E. This portion 11E includes a first capacitor portion CAP1, a second capacitor portion CAP2, a third capacitor portion CAP3, a fourth capacitor portion CAP4, a portion connecting the first and third capacitor portions CAP1 and CAP3 in series, a portion connecting the second and fourth capacitor portions CAP2 and CAP4 in series, and a portion connecting the third and fourth capacitor portions CAP3 and CAP4 in series. The series capacitor forming portion 11E forms part of the inner portion 11. The first, second, third, and fourth capacitor portions CAP3 and CAP4 in the series capacitor forming portion 11E are also referred to as a capacitor effective portion.

[0225] Furthermore, the series capacitor-forming portion 11E of the laminate 10 includes a first series-connected region, a second series-connected region, and a third series-connected region. The first series-connected region is the portion located between the first capacitor portion CAP1 and the third capacitor portion CAP3, comprising the dielectric layer 20 and the first connecting portion E10. The second series-connected region is the portion located between the second capacitor portion CAP2 and the fourth capacitor portion CAP4, comprising the dielectric layer 20 and the second connecting portion E20. The third series-connected region is the portion located between the third capacitor portion CAP3 and the fourth capacitor portion CAP4, comprising the dielectric layer 20 and the third connecting portion E30. Specifically, the first series-connected region is the aggregate of the portions of the multiple dielectric layers 20 that overlap with the first connecting portion E10 when viewed in the stacking direction T, and the multiple first connecting portions E10. The second series-connected region is the aggregate of the portions of the multiple dielectric layers 20 that overlap with the second connecting portion E20 when viewed in the stacking direction T, and the multiple second connecting portions E20. The third series connection region is an aggregate of portions of the plurality of dielectric layers 20 that overlap with the third connecting portion E30 when viewed in the stacking direction T, and the plurality of third connecting portions E30 .

[0226] like Figure 8 As shown, the external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side of the stacked body 10 and a second external electrode 40B arranged on the second end surface LS2 side of the stacked body 10 .

[0227] The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the fourth capacitor portion CAP4 in series. The third connecting portion E30 connects the third capacitor portion CAP3 and the fourth capacitor portion CAP4 in series. Therefore, the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32 exhibit capacitor characteristics based on series-connected capacitance.

[0228] In the multilayer ceramic capacitor 1 according to the second modification, as in the above-described embodiment and the first modification, each main surface side external electrode has a groove-shaped recessed portion that is recessed toward the side of the stacked body 10. That is, the first main surface side external electrode 411A of the first external electrode 40A has a first recessed portion 510A, and the second main surface side external electrode 412A has a second recessed portion 520A. The third main surface side external electrode 411B of the second external electrode 40B has a third recessed portion 530B, and the fourth main surface side external electrode 412B has a fourth recessed portion 540B. Furthermore, as Figure 8As shown, in the LT cross-sectional view, the intersection 300 of the first imaginary line 100 connecting the first recess 510A and the fourth recess 540B and the second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the longitudinal direction L. Furthermore, in the multilayer ceramic capacitor 1 of the second modification, similar to the above-described embodiment and the first modification, both of the external electrodes 40 (i.e., the first external electrode 40A and the second external electrode 40B) have tensile stress as residual stress.

[0229] (4) In the multilayer ceramic capacitor 1 according to the second modification, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333. The first intermediate electrode layer 331 has: a first electrode layer side opposing portion EC1A, which is opposed to the first internal electrode layer 31 arranged adjacent to the stacking direction T; and a first intermediate electrode layer opposing portion EC1B, which is opposed to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The second intermediate electrode layer 332 has: a second electrode side opposing portion EC1A, which is opposed to the first internal electrode layer 31 arranged adjacent to the stacking direction T; and a first intermediate electrode layer opposing portion EC1B, which is opposed to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The layer-side opposing portion EC2A is opposite to the second internal electrode layer 32 arranged adjacent to the stacking direction T; and the second intermediate electrode layer opposing portion EC2B is opposite to the third intermediate electrode layer 333 arranged adjacent to the stacking direction T. The third intermediate electrode layer 333 has: the third intermediate electrode layer opposing portion EC3A, opposite to the first intermediate electrode layer 331 arranged adjacent to the stacking direction T; and the fourth intermediate electrode layer opposing portion EC3B, opposite to the second intermediate electrode layer 332 arranged adjacent to the stacking direction T.

[0230] Even in such a quadruple-structured multilayer ceramic capacitor 1 with a high withstand voltage specification, it is possible to suppress the occurrence of interlayer delamination in the multilayer body 10 .

[0231] The present invention is not limited to the configuration of the above embodiment, and can be applied with appropriate modifications within the scope of the present invention. In addition, a combination of two or more configurations of the preferred configurations described in the above embodiment also constitutes the present invention.

[0232] For example, the multilayer ceramic capacitor 1 may be a two-terminal multilayer ceramic capacitor including two external electrodes, or may be a multi-terminal multilayer ceramic capacitor including a plurality of external electrodes.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and comprising a first main surface and a second main surface opposing each other in the height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and A pair of external electrodes are disposed at two ends of the stack in the longitudinal direction thereof, separated from each other. The internal electrode layer comprises: a first internal electrode layer extending to the first end surface; a second internal electrode layer extending to the second end surface; and The intermediate electrode layer is not extended to either the first end surface or the second end surface. The laminate comprises: a first capacitor portion formed by the first internal electrode layer and the intermediate electrode layer facing each other; and The second capacitor portion is formed by the second internal electrode layer and the intermediate electrode layer facing each other. The external electrode comprises: a first external electrode disposed on the first end surface side; and The second external electrode is arranged on the second end surface side, The first external electrode has: a first main surface side external electrode disposed on the first main surface side; and The second main surface side external electrode is arranged on the second main surface side, The second external electrode has: a third main surface side external electrode, arranged on the first main surface side; and The fourth main surface side external electrode is arranged on the second main surface side, The first main surface side external electrode has a first recessed portion recessed toward the stacked body side. The second main surface side external electrode has a second recessed portion recessed toward the stacked body side. The third main surface side external electrode has a third recessed portion recessed toward the stacked body side. The fourth main surface side external electrode has a fourth recessed portion recessed toward the stacked body side. In a cross-sectional view along the longitudinal direction and the height direction, an intersection of a first imaginary line connecting the first recess and the fourth recess and a second imaginary line connecting the second recess and the third recess is located between the first capacitor portion and the second capacitor portion in the longitudinal direction. The external electrode has tensile stress as residual stress.

2. The multilayer ceramic capacitor according to claim 1, wherein The first imaginary line intersects a portion of the first capacitor portion on the second end surface side and intersects a portion of the second capacitor portion on the first end surface side. The second imaginary line intersects a portion of the first capacitor portion on the second end surface side, and intersects a portion of the second capacitor portion on the first end surface side.

3. The multilayer ceramic capacitor according to claim 1, wherein The intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer, The first intermediate electrode layer has: a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the height direction; and The first intermediate electrode layer facing portion faces the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the height direction. The second intermediate electrode layer has: a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the height direction; and The second intermediate electrode layer opposing portion faces the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the height direction.

4. The multilayer ceramic capacitor according to claim 1, wherein The intermediate electrode layer includes a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer. The first intermediate electrode layer has: a first electrode layer-side opposing portion facing the first internal electrode layer disposed adjacent to the first internal electrode layer in the height direction; and The first intermediate electrode layer facing portion faces the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the height direction. The second intermediate electrode layer has: a second electrode layer-side opposing portion facing the second internal electrode layer disposed adjacent to the second internal electrode layer in the height direction; and The second intermediate electrode layer facing portion faces the third intermediate electrode layer disposed adjacent to the third intermediate electrode layer in the height direction. The third intermediate electrode layer has: a third intermediate electrode layer opposing portion facing the first intermediate electrode layer disposed adjacent to the first intermediate electrode layer in the height direction; and The fourth intermediate electrode layer opposing portion faces the second intermediate electrode layer disposed adjacent to the second intermediate electrode layer in the height direction.

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