Etching method of inner side wall, semiconductor device manufacturing method, and semiconductor device

Abstract

The application provides an inner sidewall etching method, a semiconductor device manufacturing method and a semiconductor device. In the inner sidewall etching method, a deposition process stage, a trimming process stage and an etching process stage are included. The deposition process stage uses a first process gas to form a polymer on exposed surfaces of a fin structure. The exposed surfaces include a top, a sidewall and a groove bottom of the fin structure. The trimming process stage uses a second process gas to remove the polymer on the sidewall. The etching process stage uses a third process gas to remove an inner sidewall material on the sidewall to form the inner sidewall. The etching method has low requirements for etching selectivity of the fin structure material and a longitudinal / lateral etching ratio, thereby facilitating expansion of a process window and improvement of a process yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an etching method of inner sidewall, a preparation method of semiconductor device and the semiconductor device. BACKGROUND

[0002] In the manufacturing process of GAAFET (Gate All Around Field Effect Transistor), the inner sidewall is a very important process module, which has the functions of physical isolation and electrical isolation, and is of great significance to improve the performance of the device. In the related technical solution, the inner sidewall is mainly formed by anisotropic etching process. Since the longitudinal etching amount of the inner sidewall dielectric is often greater than 150 nm, and the total lateral deposition amount of the inner sidewall dielectric is only about 5 nm, it puts forward very high requirements for the anisotropic inner sidewall dielectric etching process: ① The etching process should have very high etching selectivity for hard mask material and Si material; ② The etching process should have very high anisotropic etching characteristics, that is, very high longitudinal / lateral etching ratio. However, the strict process requirements are easy to cause small process window, which leads to poor process repeatability, low production yield and cannot meet the actual process requirements. SUMMARY

[0003] Therefore, the purpose of the present application is to provide an etching method of inner sidewall, a preparation method of semiconductor device and the semiconductor device, so as to solve the problem of low production yield caused by small process window in the related technical solution.

[0004] In a first aspect, an etching method of inner sidewall is provided by embodiments of the present application, which is applied to a semiconductor device, the semiconductor device comprising a substrate and a fin structure formed on the substrate, and an inner sidewall material deposited on the exposed surface of the fin structure; the method comprises:

[0005] A deposition process stage: using a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface comprises the top, sidewall and groove bottom of the fin structure;

[0006] A trimming process stage: using a second process gas to remove the polymer on the sidewall;

[0007] An etching process stage: using a third process gas to remove the inner sidewall material on the sidewall to form an inner sidewall.

[0008] Optionally, the first process gas comprises a gas containing carbon element and hydrogen element.

[0009] Optionally, the second process gas is a gas containing oxygen element.

[0010] Optionally, the third process gas comprises a halogen etching gas.

[0011] Optionally, the halogen etching gas comprises at least one of nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, and fluoromethane.

[0012] Optionally, a polymer thickness of a top of the fin structure and a bottom of the trench is greater than a polymer thickness on the sidewall.

[0013] Optionally, a power of a lower radio frequency power source is 0 W in the trimming process stage and the etching process stage.

[0014] In a second aspect, an embodiment of the present application further provides a preparation method of a semiconductor device, the method comprising:

[0015] epitaxially growing a fin structure on a substrate; wherein the fin structure comprises a sacrificial layer;

[0016] laterally etching the sacrificial layer to form a filling cavity with a preset length;

[0017] depositing an inner sidewall material on the filling cavity and exposed surfaces of the fin structure;

[0018] adopting the etching method of the inner sidewall of the first aspect to remove the inner sidewall material outside the filling cavity to form the inner sidewall.

[0019] Optionally, the step of epitaxially growing a fin structure on a substrate comprises: forming a stack and a dummy gate on the substrate; wherein the stack is located on a surface of the substrate and is alternately provided with the sacrificial layer and a channel layer in a direction away from the substrate, and the dummy gate is located on a surface of the stack away from the substrate; depositing a hard mask on an outer surface of the dummy gate, and taking the stack, the dummy gate, and the hard mask as the fin structure.

[0020] In a third aspect, an embodiment of the present application further provides a semiconductor device, which is prepared by the preparation method of the semiconductor device of the second aspect.

[0021] The embodiment of the present application has the following beneficial effects:

[0022] The embodiment of the present application provides an inner sidewall etching method, a semiconductor device preparation method and a semiconductor device; in the inner sidewall etching method, a deposition process stage, a trimming process stage and an etching process stage are included, the first process gas is used in the deposition process stage to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, the sidewall and the groove bottom of the fin structure; the second process gas is used in the trimming process stage to remove the polymer on the sidewall, and the third process gas is used in the etching process stage to remove the inner sidewall material on the sidewall to form the inner sidewall, the etching method is low in requirements for the etching selectivity of the material of the fin structure and the longitudinal / lateral etching ratio, so that the process window is widened, and the process yield is improved.

[0023] Other features and advantages of the present application will be set forth in the descriptions below, and in part will become apparent to those skilled in the art from the descriptions below, or can be learned by practice of the present application. The purposes and other advantages of the present application can be realized and obtained by the structure particularly pointed out in the descriptions and the drawings.

[0024] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the related technical description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative labor.

[0026] Figure 1 The TEM and EDS schematic diagram in the related technical solutions;

[0027] Figure 2 The flowchart of the inner sidewall etching method provided by the embodiment of the present application;

[0028] Figure 3 The semiconductor device schematic diagram after the deposition process stage is completed, which is provided by the embodiment of the present application;

[0029] Figure 4 The semiconductor device schematic diagram after the trimming process stage is completed, which is provided by the embodiment of the present application;

[0030] Figure 5 The semiconductor device schematic diagram after the etching process stage is completed, which is provided by the embodiment of the present application;

[0031] Figure 6A semiconductor device after polymer is completely removed according to an embodiment of the present application;

[0032] Figure 7 A semiconductor device after inner side wall is formed according to an embodiment of the present application;

[0033] Figure 8 A flow chart of a preparation method of a semiconductor device according to an embodiment of the present application;

[0034] Figure 9 A schematic diagram of forming a filling cavity in a semiconductor device according to an embodiment of the present application;

[0035] Figure 10 A schematic diagram of semiconductor device after inner side wall material deposition is completed according to an embodiment of the present application.

[0036] Icon:

[0037] 31 - substrate; 32 - channel layer; 33 - sacrificial layer; 34 - spacer layer; 35 - dummy gate; 36 - hard mask; 37 - inner side wall material; 381 - polymer on sidewall; 382 - polymer at bottom of trench; 383 - polymer at top; 39 - inner side wall; 40 - filling cavity. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0039] With the continuous development of Moore's Law, the semiconductor process develops to 3nm and below technology node, and GAAFET is considered as an effective substitute for FinFET (Fin Field Effect Transistor). In the manufacturing process of GAAFET, the inner spacer is a very important process module, which can be divided into physical isolation and electrical isolation. On the one hand, according to the manufacturing process of GAAFET, the channel release process is located after the inner spacer and the selective epitaxy to form the source / drain. In the channel release process, the inner spacer has physically isolated the source / drain and the gate region of the sacrificial layer, avoiding the uncontrollable extension etching of the source / drain in the channel release process. Therefore, the inner spacer is particularly important for the device with the same material of source / drain and sacrificial layer. On the other hand, if there is no inner spacer structure, there will only be a very thin gate oxide layer between the gate metal and the source / drain of the nanosheet, which will greatly increase the parasitic capacitance and leakage current of the device. Therefore, the inner spacer between the source / drain and the gate can play an electrical isolation role, thereby greatly reducing the parasitic capacitance and leakage current between the source / drain and the gate, and improving the dynamic performance of the device.

[0040] For the formation process of the inner spacer, the related technical solution takes silicon nitride (SiN) material as an example to illustrate the inner spacer dielectric. Anisotropic etching process is adopted, according to the etching gas combination (difluoromethane (CH2F2) / methane (CH4) / oxygen (O2) / argon (Ar)), and by optimizing the ratio of each gas in the mixed gas and the process pressure, an inner spacer structure with ultra-high etching selectivity (SiN:Si>1:100, SiN:SiO2>1:30) and ultra-high longitudinal / lateral etching ratio (longitudinal:lateral>80:1) is obtained, as shown in the TEM (Transmission Electron Microscope) and EDS (Energy Dispersive Spectrometer) schematic diagram shown in Figure 1 (b) in the left side of (a) is a TEM diagram after SiN etching back, and the right side is an EDS diagram, and the distribution of carbon (C), germanium (Ge), nitrogen (N), oxygen (O) and silicon (Si) in each EDS diagram is shown.

[0041] In practical applications, the longitudinal etching depth of the inner sidewall dielectric often exceeds 150 nm, while the total lateral deposition depth of the inner sidewall dielectric is only about 5 nm. This places extremely high demands on the anisotropic inner sidewall dielectric etching process: ① The etching process must have extremely high etching selectivity for both the hard mask material and the Si material; ② The etching process must have extremely high anisotropic etching characteristics, i.e., an extremely high longitudinal / lateral etching ratio. However, these stringent process requirements can easily result in a small process window, leading to poor process repeatability, decreased production yield, and failure to meet actual process needs.

[0042] Based on this, embodiments of the present invention provide an etching method for inner sidewalls, a method for fabricating semiconductor devices, and a semiconductor device. The etching method for inner sidewalls includes a deposition process stage, a trimming process stage, and an etching process stage. In the deposition process stage, a first process gas is used to form a polymer on the exposed surface of the fin structure. The exposed surface includes the top, sidewalls, and bottom of the trenches of the fin structure. In the trimming process stage, a second process gas is used to remove the polymer from the sidewalls. In the etching process stage, a third process gas is used to remove the inner sidewall material from the sidewalls, forming the inner sidewall. This etching method has lower requirements for the etching selectivity of the fin structure material and the longitudinal / transverse etching ratio, thereby helping to widen the process window and improve process yield.

[0043] To facilitate understanding of this embodiment, the embodiments of the present invention will be described in detail below.

[0044] Example 1

[0045] This invention provides an inner sidewall etching method for semiconductor devices, including but not limited to GAAFETs and FinFETs. In practical applications, the semiconductor device includes a substrate and a fin structure formed on the substrate. The fin structure includes a sacrificial layer, a channel layer, a dummy gate, and a hard mask, etc., and the exposed surface of the fin structure is deposited with inner sidewall material. The specific fin structure can be referred to in the prior art, and will not be described in detail here.

[0046] Based on the above semiconductor devices, such as Figure 2 As shown, the etching method for the inner wall provided in this embodiment of the invention includes the following steps:

[0047] Step S202, Deposition process stage: Using the first process gas, a polymer is formed on the exposed surface of the fin structure.

[0048] Specifically, in the deposition process phase, a polymer is formed on the exposed surface of the fin structure by using a first process gas; wherein the exposed surface includes the top of the fin structure, the sidewall and the trench bottom; the first process gas includes a gas containing carbon (C) element and hydrogen (H) element, i.e. the first process gas is a hydrocarbon gas, including but not limited to CH4, ethane (C2H6), propane (C3H8), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), fluoromethane (CH3F) and trifluoromethane (CHF3) and the like.

[0049] In addition, the first process gas can also be a combination of a hydrocarbon gas and an inert gas, where the inert gas includes but is not limited to Ar and helium (He) and the like, and in some scenarios, the first process gas can also be a combination of multiple hydrocarbon gases and inert gases, such as CH4 or CH4 / Ar gas combination or CH4 / CHF3 / Ar gas combination, and thus, the polymer, which can also be referred to as a hydrocarbon polymer, is formed on the exposed surface of the fin structure by using the first process gas, so as to protect the top of the fin structure and the trench bottom by the polymer in the subsequent etching process, further ensuring the process effect of the inner sidewall.

[0050] Step S204, trim process phase: using a second process gas to remove the polymer on the sidewall.

[0051] After the above deposition process is completed, the trim process phase is entered, and in the trim process phase, the polymer on the sidewall is removed by using a second process gas. Wherein the second process gas is a gas containing oxygen element, such as O2, which can be adjusted adaptively according to actual conditions.

[0052] Step S206, etching process phase: using a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall.

[0053] After the trimming is completed, the etching process phase is entered, and in the etching process phase, the inner sidewall material on the sidewall is removed by using a third process gas to form the inner sidewall. Wherein the third process gas includes a halogen etching gas, which includes at least one of the following: nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), CHF3 and CH3F and the like, in addition, the third process gas can also be a combination of a halogen etching gas and an inert gas, or a combination of multiple halogen etching gases and inert gases, such as CF4 or CF4 / Ar gas combination or CF4 / CHF3 / Ar gas combination, which can be set according to actual conditions.

[0054] Therefore, the etching method of the inner sidewall provided by the embodiment of the present application includes a deposition process stage, a trimming process stage and an etching process stage. The deposition process stage uses a first process gas to form a polymer on exposed surfaces of the fin structure. The exposed surfaces include a top of the fin structure, a sidewall and a groove bottom. The trimming process stage uses a second process gas to remove the polymer on the sidewall. The etching process stage uses a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall. The etching method has low requirements for the etching selectivity of the material of the fin structure and the longitudinal / lateral etching ratio, thereby facilitating the expansion of the process window and improving the process yield.

[0055] In an embodiment, the polymer thickness of the top of the fin structure and the groove bottom is greater than the polymer thickness on the sidewall.

[0056] Specifically, in the deposition process stage, the polymer deposition is completed by one or more different polymer deposition steps. The final deposition result is that the polymer thickness of the top of the fin structure and the groove bottom is greater than the polymer thickness on the sidewall. Therefore, when the polymer on the sidewall is removed in the trimming process stage, not only is it convenient to remove the polymer on the sidewall, but also the top of the fin structure and the groove bottom are protected by the thicker polymer during the removal process, thereby ensuring the process effect of the inner sidewall.

[0057] In an embodiment, in the trimming process stage and the etching process stage, the power of the lower radio frequency power supply is 0 W.

[0058] In actual application, an inductively coupled plasma (ICP) etching machine is one of the most common etching equipment, which usually has two sets of radio frequency systems. The upper radio frequency power supply is used to generate and maintain plasma, which can also be called a source radio frequency (SRF). The lower radio frequency power supply is used to control the ion bombardment energy and directionality, which can also be called a bias radio frequency (BRF). Since the bias voltage applied by the lower radio frequency power supply on the process table can accelerate ions and vertically bombard the wafer surface, the etching process based on the ICP etching equipment more exhibits anisotropic etching characteristics.

[0059] In order to weaken the anisotropic etching characteristics and enhance the isotropic etching, the ICP etching equipment can reduce the power of the lower radio frequency power supply. In the trimming process stage and the etching process stage, the power of the lower radio frequency power supply is set to 0 W, and the ICP cavity is used to realize the lateral etching of the inner sidewall material film. Compared with the isotropic etching of the inner sidewall material by using a free radical etching equipment, there is a clear cost advantage.

[0060] Further, in order to ensure the process effect of each process stage, each process stage is also provided with a process parameter. Among them, in the deposition process stage, in order to ensure the deposition effect of the polymer, the process parameters include but are not limited to: the chamber pressure is 5mT~100mT, the total gas flow of the first process gas is 50sccm~500sccm, the process time is 5s~60s, the power of the upper radio frequency power supply is 500W~3000W, the power of the lower radio frequency power supply is 0W~1000W, and the specific values of each process parameter can be set according to the actual situation.

[0061] Similarly, in the trimming process stage, in order to ensure the removal effect and removal efficiency of the polymer on the side wall, the process parameters include but are not limited to: the chamber pressure is 5mT~100mT, the total gas flow of the second process gas is 50sccm~500sccm, the process time is 5s~30s, the power of the upper radio frequency power supply is 500W~3000W, and the power of the lower radio frequency power supply is 0W. The specific values of each process parameter can be set according to the actual situation.

[0062] In the etching process stage, in order to ensure the removal effect and removal efficiency of the inner side wall material on the side wall, the process parameters include but are not limited to: the chamber pressure is 5mT~100mT, the total gas flow of the third process gas is 50sccm~500sccm, the process time is 5s~60s, the power of the upper radio frequency power supply is 500W~3000W, and the power of the lower radio frequency power supply is 0W. The specific values of each process parameter can be set according to the actual situation.

[0063] Further, by setting the power of the lower radio frequency power supply to 0W, although the isotropic characteristics of the etching process can be greatly enhanced, but in the actual application, self-bias voltage will inevitably occur in the process cavity, thereby causing the longitudinal etching rate to be greater than the lateral etching rate. In order to solve the problem that the longitudinal etching rate is greater than the lateral etching rate in the etching process, the etching method of the inner side wall provided by the embodiment of the present application mainly includes a multi-step etching process of a deposition process stage, a trimming process stage and an etching process stage. Among them, the functions of each process stage are as follows:

[0064] (1) The deposition process stage utilizes the first process gas to form a polymer on the exposed surface of the fin structure.

[0065] In actual application, for example, Figure 3As shown, the semiconductor device comprises a substrate 31 and a fin structure formed on the substrate; wherein the fin structure comprises a plurality of channel layers 32, a plurality of sacrificial layers 33, a dummy gate 35, a spacer layer 34 and a hard mask 36, and the plurality of channel layers 32 and the plurality of sacrificial layers 33 are arranged alternately, the dummy gate 35 spans the plurality of channel layers 32 and the plurality of sacrificial layers 33 which are stacked alternately, the spacer layer 34 is on both sides of the dummy gate 35 and spans the plurality of channel layers 32 and the plurality of sacrificial layers 33 which are stacked alternately. In addition, an inner sidewall material 37 is deposited on the exposed surface of the fin structure, and the inner sidewall material 37 is also deposited in the filling cavity 40. The inner sidewall material 37 can also be referred to as an inner sidewall dielectric material. It should be noted that the spacer layer 34 can also be referred to as an outer sidewall, the material of the sacrificial layer 33 is silicon germanium (SiGe), and the material of the channel layer 32 is Si, which can be adjusted adaptively according to actual conditions.

[0066] In the deposition process stage, a polymer is formed on the exposed surface of the fin structure by using a first process gas; wherein the polymer comprises a polymer 381 on the sidewall, a polymer 382 at the bottom of the trench and a polymer 383 at the top. In practical applications, the polymer can be obtained by single or multiple deposition, and the final effect is that the thickness of the polymer at the top and the bottom of the trench is larger, and the thickness of the polymer on the sidewall is smaller, that is, the thickness of the polymer 382 at the bottom of the trench and the polymer 383 at the top is larger than the thickness of the polymer 381 on the sidewall; the purpose is to strengthen the protection of the top and the bottom of the trench by the thicker polymer 382 at the bottom of the trench and the polymer 383 at the top, and the thinner polymer 381 on the sidewall is convenient for subsequent removal.

[0067] (2) trimming process stage; the polymer on the sidewall is removed by using a second process gas.

[0068] In the etching process stage, since the third process gas used for etching the inner sidewall material 37 is mainly a halogen etching gas, the etching rate of the halogen radical to the polymer is slow. If the etching process step of the inner sidewall material 37 is directly performed after the polymer deposition process stage is completed, the active halogen radical needs to spend a lot of time to remove the polymer 381 on the sidewall before etching the inner sidewall material 37 in the lateral direction, thereby causing the process efficiency to be reduced and the repeatability to be poor.

[0069] Therefore, the embodiment of the present application adds a trimming process stage between the deposition process stage and the etching process stage, and the polymer 381 on the sidewall is removed by oxidation in the trimming process stage, so as to realize the subsequent lateral etching of the inner sidewall material 37. In practical applications, the process time of the trimming process stage should be appropriate, which can not only ensure that the polymer 381 on the sidewall is completely removed, but also ensure that the polymer 382 at the bottom of the trench and the polymer 383 at the top still remain part of the unremoved, so as to protect the bottom and the top of the trench in the subsequent etching process stage. For example,Figure 4 As shown, after the trimming process phase is completed, the polymer 381 on the sidewall is completely removed, and the polymer 382 at the bottom of the trench and the polymer 383 at the top are still partially removed.

[0070] (3) Etching process phase; the inner spacer material on the sidewall is removed by using a third process gas to form an inner spacer.

[0071] After the above-mentioned trimming process phase is completed, the etching process phase is entered, and the excess inner spacer material 37 on the sidewall is removed by using a third process gas through lateral etching, as shown in Figure 5 As shown, the inner spacer 39, i.e., the filling cavity 40 filled with the inner spacer material 37, is formed. At this time, the polymer 382 at the bottom of the trench and the polymer 383 at the top will be consumed in most of the etching process of the inner spacer material 37 on the sidewall, and the remaining polymer 382 at the bottom of the trench and the polymer 383 at the top are removed by dry or wet cleaning, and after the removal, as shown in Figure 6 In addition, after the polymer removal is completed, the inner spacer material 37 is still left on the top of the fin structure and the bottom of the trench, at which time the remaining inner spacer material 37 can be removed by dry etching, as shown in Figure 7 As shown, the inner spacer 39 of the semiconductor device is finally generated.

[0072] In summary, the etching method of the inner spacer provided by the embodiment of the present application includes a deposition process phase, a trimming process phase, and an etching process phase. When the inner spacer material is back-etched, the etching selectivity requirement for Si and SiGe materials is low, and the etching selectivity and longitudinal / lateral etching ratio requirements for the hard mask and other materials are also low, which relaxes the requirements of the inner spacer material back-etching process for the etching equipment and process engineers, thereby facilitating the expansion of the process window and the improvement of the process yield. In addition, compared with the isotropic etching of the inner spacer material by using a radical etching device, there is also a significant cost advantage.

[0073] Embodiment two

[0074] On the basis of the above-mentioned etching method of the inner spacer, the embodiment of the present application further provides a preparation method of a semiconductor device, as shown in Figure 8 The method includes the following steps:

[0075] Step S802, epitaxially forming a fin structure on a substrate; wherein the fin structure includes a sacrificial layer.

[0076] Step S804, laterally etching the sacrificial layer to form a filling cavity with a preset length.

[0077] Step S806, depositing an inner spacer material in the filling cavity and on the exposed surface of the fin structure.

[0078] Step S808, the inner side wall is removed by etching method of inner side wall to form inner side wall.

[0079] In an embodiment, the step of epitaxially forming the fin structure on the substrate comprises: forming a stack and a dummy gate on the substrate; wherein the stack is located on the surface of the substrate, and is alternately provided with a sacrificial layer and a channel layer in a direction away from the substrate, and the dummy gate is located on the surface of the stack away from the substrate; depositing a hard mask on the outer surface of the dummy gate, and taking the stack, the dummy gate and the hard mask as the fin structure. The specific fin structure can refer to the foregoing embodiments, and will not be described in detail herein.

[0080] In actual application, the inner side wall is one of the most important and most challenging process modules in the GAAFET manufacturing process; wherein the inner side wall mainly comprises the following three process steps:

[0081] (A1) cavity etching process step; that is, partially removing the sacrificial layer 33 in the stack structure by using selective etching process, as shown in FIG. 4, to form a filling cavity 40 for filling the inner side wall material. Figure 9

[0082] In order to better realize the current balance of N / P devices, under ideal conditions, the channel layer 32 material of the NMOS (N-Metal-Oxide-Semiconductor) transistor should be Si, and the sacrificial layer 33 material should be SiGe; the channel layer 32 material of the PMOS (Positivechannel Metal Oxide Semiconductor) transistor should be SiGe, and the sacrificial layer 33 material should be Si. Therefore, the sacrificial layer 33 in the Si / SiGe stack structure is removed by using selective etching process to form a filling cavity 40 for filling the inner side wall material, and the preset length of the filling cavity 40 can be set according to actual conditions. Here, the selective etching process can be a wet process or a dry process, and the wet process and the dry process can refer to the prior art, and will not be described in detail herein.

[0083] (A2) inner side wall material deposition; as shown in FIG. 5, the inner side wall material 37 is deposited in the filling cavity 40 and on the exposed surface of the fin structure by deposition process. Figure 10

[0084] ​​The inner sidewall material deposition step requires that the thin film deposition process has good filling performance, and can achieve hole-free and gap-free filling of the cavity 40. Therefore, this step often uses an atomic layer deposition process with excellent step coverage and conformal filling capability. In order to reduce the parasitic capacitance between the source / drain and the gate to the greatest extent, a dielectric with a lower dielectric constant should be used as the material of the inner sidewall as much as possible. In practical applications, the dielectric material of the inner sidewall includes but is not limited to silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and silicon oxycarbonitride (SiOCN), etc. The specific setting can be made according to the actual situation. It should be noted that the deposition process of the inner sidewall material can refer to the prior art, and the embodiments of the present application will not be described in detail here.

[0085] (A3) inner sidewall material etching back; that is, using the above-mentioned inner sidewall etching method to remove the inner sidewall material outside the cavity to form an inner sidewall, as shown in Figure 7 It should be noted that the deposition process of the inner sidewall material can refer to the prior art, and the embodiments of the present application will not be described in detail here.

[0086] In summary, the preparation method of the semiconductor device provided by the embodiments of the present application includes a deposition process stage, a trimming process stage and an etching process stage in the inner sidewall etching process. The deposition process stage uses a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, sidewall and groove bottom of the fin structure; the trimming process stage uses a second process gas to remove the polymer on the sidewall, and the etching process stage uses a third process gas to remove the inner sidewall material on the sidewall to form an inner sidewall. This etching method has low requirements for the etching selectivity and longitudinal / lateral etching ratio of the material of the fin structure, thereby facilitating the widening of the process window and improving the process yield of the semiconductor device.

[0087] Further, the embodiments of the present application also provide a semiconductor device prepared by the above-mentioned preparation method of the semiconductor device.

[0088] The semiconductor device provided by the embodiments of the present application has the same technical features as the preparation method of the semiconductor device provided by the above-mentioned embodiments, so it can also solve the same technical problems and achieve the same technical effects.

[0089] The embodiments of the present application also provide an electronic device including a processor and a memory. The memory stores machine executable instructions executable by the processor. The processor executes the machine executable instructions to implement the above-mentioned inner sidewall etching method and the preparation method of the semiconductor device.

[0090] The embodiment also provides a machine readable storage medium, which stores machine executable instructions, and the machine executable instructions, when invoked and executed by a processor, cause the processor to implement the etching method of the inner sidewall and the preparation method of the semiconductor device.

[0091] The etching method of the inner sidewall, the preparation method of the semiconductor device and the computer program product of the semiconductor device provided by the embodiment of the present application include a computer readable storage medium storing program codes, the program codes include instructions for executing the method described in the foregoing method embodiment, and the specific implementation can be referred to the method embodiment, which will not be described here.

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the foregoing method embodiment, which will not be described here.

[0093] In addition, in the description of the embodiment of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection" and "connection" should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0094] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the present application which essentially contributes to the prior art or the part of the technical solutions can be embodied in the form of software products, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and various program code storage media.

[0095] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0096] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, and are not limiting. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can make modifications or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical range disclosed by the present application, or make equivalent replacements to some technical features; and these modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for etching inner sidewalls, applied to a semiconductor device, the semiconductor device comprising a substrate and a fin structure formed on the substrate, wherein an inner sidewall material is deposited on the exposed surface of the fin structure; characterized in that, The method includes: epitaxially forming a fin structure on a substrate; wherein the fin structure includes a sacrificial layer; laterally etching the sacrificial layer to form a filled cavity of a predetermined length; and depositing an inner sidewall material in the filled cavity and on the exposed surface of the fin structure. Deposition process stage: Using a first process gas, a polymer is formed on the exposed surface of the fin structure; wherein, the exposed surface includes the top, sidewalls and bottom of the trench of the fin structure, and the polymer thickness at the top and bottom of the trench is greater than the polymer thickness on the sidewalls; Trimming process stage: Using a second process gas, the polymer on the sidewall is removed until the polymer on the sidewall is completely removed, and some polymer remains on the top of the fin structure and the bottom of the groove. Etching process stage: Using a third process gas, the inner sidewall material outside the cavity on the sidewall is removed to form the inner sidewall.

2. The method according to claim 1, characterized in that, The first process gas includes a gas containing carbon and hydrogen.

3. The method according to claim 1, characterized in that, The second process gas is an oxygen-containing gas.

4. The method according to claim 1, characterized in that, The third process gas includes halogen etching gas.

5. The method according to claim 4, characterized in that, The halogen etching gas includes at least one of the following: nitrogen trifluoride, carbon tetrafluoride, trifluoromethane, and fluoromethane.

6. The method according to claim 1, characterized in that, During the trimming process and the etching process, the power of the lower RF power supply is 0W.

7. A method for fabricating a semiconductor device, characterized in that, The method includes: The inner wall is formed by removing the inner wall material outside the filling cavity using the etching method of any one of claims 1-6.

8. The method according to claim 7, characterized in that, The steps of epitaxially constructing fin structures on a substrate include: A stacked portion and a dummy gate are formed on the substrate; wherein the stacked portion is located on the surface of the substrate, and the sacrificial layer and the channel layer are alternately disposed along a direction away from the substrate, and the dummy gate is located on the surface of the stacked portion away from the substrate; A hard mask is deposited on the outer surface of the dummy gate, and the stacked portion, the dummy gate, and the hard mask are used as the fin structure.

9. A semiconductor device, characterized in that, The semiconductor device is prepared by the semiconductor device preparation method according to any one of claims 7-8.

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