Fabrication method of package substrate

Abstract

A manufacturing method of a package substrate includes laminating two substrates on a carrier, forming a circuit structure on the substrates, combining a support and a reinforcing member on the circuit structure, and removing the carrier, so that the manufacturing method of the present disclosure can be used for any ultra-thin substrate by means of the configuration of the reinforcing member. And the performance of the existing processing equipment is enough to meet the process requirement, so that the capability of manufacturing the minimum plate thickness can be achieved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor packaging process, and more particularly to a method for manufacturing a packaging substrate capable of improving reliability. Background Art

[0002] With the rapid development of the electronics industry, electronic products are becoming thinner, lighter, and smaller, while their functionality is being developed towards higher performance, greater functionality, and higher speed. Therefore, to meet the demands for high integration and miniaturization of semiconductor devices, packaging substrates with thinner, low-warpage, and high-density wiring designs are often used in the packaging process.

[0003] like Figure 1 As shown, the conventional packaging substrate 1 includes a dielectric structure 10, a first circuit layer 11 and a second circuit layer 12 arranged on the dielectric structure 10, and the dielectric structure 10 has a core layer 100, a plurality of first insulating layers 101 and a plurality of second insulating layers 102 respectively arranged on opposite sides of the core layer 100, and the core layer 100 has a plurality of conductive through-holes 120 to electrically connect the first and second circuit layers 11, 12.

[0004] However, the existing package substrate 1 is extremely thin due to miniaturization requirements, and thus a temporary carrier must be configured during the process. Therefore, after the temporary carrier is removed, the thickness of the package substrate 1 often exceeds the process capability of the production equipment, resulting in easy board jams.

[0005] Furthermore, the package substrate 1 is prone to warpage during temperature cycling. Figure 1 The dotted outline shown results in poor package planarity.

[0006] Therefore, how to overcome the various problems of the above-mentioned prior art has become a difficult problem that needs to be overcome urgently in the industry. Summary of the Invention

[0007] An object of the present invention is to provide a method for manufacturing a package substrate to solve at least one of the above problems.

[0008] In view of the above-mentioned defects of the prior art, the present disclosure provides a method for manufacturing a packaging substrate, comprising: respectively arranging a substrate on opposite sides of a carrier; forming a circuit structure on the substrate; combining a support member on the circuit structure, and combining a reinforcement member on the support member; removing the carrier to expose the substrate; forming a wiring layer electrically connected to the circuit structure on the surface of the substrate after the carrier is removed; and removing the support member and the reinforcement member.

[0009] In the aforementioned manufacturing method, the substrate includes a core layer and first and second metal layers formed on opposite surfaces of the core layer. For example, the circuit structure includes a circuit layer formed using the second metal layer and at least one conductive post disposed in the core layer and electrically connecting the circuit layer to the wiring layer.

[0010] In the aforementioned manufacturing method, the wiring layer is made of the first metal layer. Furthermore, the circuit structure further comprises an insulating layer formed on the core layer to cover the wiring layer.

[0011] The aforementioned manufacturing method further includes forming a solder mask layer on the surface of the substrate on which the wiring layer is formed, so that a portion of the wiring layer is exposed on the surface of the solder mask layer.

[0012] In the aforementioned manufacturing method, the hardness (pencil hardness) and modulus (Young's modulus) of the core layer are both greater than the hardness and modulus of the solder mask layer.

[0013] In the aforementioned manufacturing method, the support member is made of a thermally dissociated film.

[0014] In the aforementioned manufacturing method, the reinforcing member is formed by coating an ink layer on the supporting member and then baking and curing the ink layer. In addition, the viscosity of the ink layer before baking and curing is 35-50 Pa·s.

[0015] In the aforementioned manufacturing method, the reinforcement member is mainly composed of epoxy resin material.

[0016] In the aforementioned manufacturing method, the hardness (pencil hardness) of the reinforcement is greater than or equal to 8H, and the hardness (pencil hardness) of the core layer is greater than or equal to 6H.

[0017] Furthermore, in one embodiment, the hardness (pencil hardness) of the reinforcement is greater than the hardness (pencil hardness) of the core layer.

[0018] In one embodiment, the modulus (Young's modulus) of the reinforcement is greater than 40 GPa, and the modulus (Young's modulus) of the core layer is 10 to 20 GPa.

[0019] From the above, it can be seen that the method of manufacturing the packaging substrate disclosed in the present invention mainly relies on the configuration of the reinforcement component to enable existing processing equipment to continue to carry out subsequent processes (such as making the wiring layer) after removing the carrier without any structural thickness restrictions. Therefore, compared with the existing technology, the method disclosed in the present invention can be used for any ultra-thin substrate, and the performance of existing processing equipment is sufficient to meet the process requirements without the problem of board jamming, thereby achieving the ability to produce the minimum board thickness to improve reliability.

[0020] Furthermore, in order to ensure that the flatness of the thinned substrate structure meets the requirements and avoid the problem of warping of the packaging substrate, compared with the existing technology, the manufacturing method disclosed in the present invention uses the configuration of the reinforcement to prevent the packaging substrate from warping during temperature cycling (such as thermally curing the solder mask layer), thereby ensuring that the packaging flatness meets the requirements, thereby improving reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a cross-sectional schematic diagram of an existing packaging substrate.

[0022] Figures 2A to 2H Schematic cross-sectional view of the method for manufacturing the package substrate disclosed herein.

[0023] The reference numerals are as follows:

[0024] 1,2 Package substrate

[0025] 10 Dielectric structure

[0026] 100,80 core layer

[0027] 101 First Insulation Layer

[0028] 102 second insulation layer

[0029] 11 First circuit layer

[0030] 12 Second circuit layer

[0031] 120 conductive vias

[0032] 20 Line Structure

[0033] 201 circuit layer

[0034] 202 conductive pillars

[0035] 203 electrical contact pads

[0036] 21 wiring layer

[0037] 210 electrical contacts

[0038] 22 solder mask

[0039] 220 opening

[0040] 23 Surface treatment layer

[0041] 24 Insulation layer

[0042] 240 Opening

[0043] 6 reinforcements

[0044] 7 Support

[0045] 8. Substrate

[0046] 81 First Metal Layer

[0047] 82 Second Metal Layer

[0048] 83 Third Metal Layer

[0049] 9 bearing parts

[0050] D, D0, D1, D2, D3, D4, D5, t1, t2 thickness

[0051] H0, H1, H2, H3 structure thickness. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present disclosure with reference to specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification.

[0053] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed in the present disclosure without affecting the efficacy and purpose that can be achieved by the present disclosure. At the same time, the terms such as "upper", "first", "second", "third", "one" and so on quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present disclosure. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical content.

[0054] Figures 2A to 2H Schematic cross-sectional view of the manufacturing method of the package substrate 2 disclosed in the present invention.

[0055] like Figure 2A As shown, a plurality of substrates 8 are provided, and the substrates 8 are symmetrically combined on opposite sides of a carrier 9 to form a symmetrical structure.

[0056] In this embodiment, the substrate 8 is a core material having metal layers on opposite sides, such as a copper foil substrate. The core layer 80 includes a first metal layer 81 and a second metal layer 82, such as copper layers, on opposite surfaces. A third metal layer 83, such as copper, is formed on the first metal layer 81 and the second metal layer 82, so that the third metal layer 83 on the first metal layer 81 is laminated to the carrier 9. For example, the core layer 80 is an insulating material, such as bismaleimide triazine (BT) or other dielectric materials.

[0057] Furthermore, the thickness D0 of the core layer 80 is 40 microns (μm), and the thickness D1 of the first metal layer 81 and the thickness D2 of the second metal layer 82 are less than the thickness D3 of the third metal layer 83. For example, the thickness D1 of the first metal layer 81 and the thickness D2 of the second metal layer 82 are both 3 μm, and the thickness D3 of the third metal layer 83 is 18 μm, so that the thickness D of the substrate 8 is 82 μm.

[0058] In addition, the carrier 9 is a temporary carrier. For example, the thickness t1 of the carrier 9 is 133 microns, so that the structure thickness H0 is 297 microns. Figure 2A shown.

[0059] like Figure 2B As shown, the third metal layer 83 on the second metal layer 82 is removed to expose the second metal layer 82 , so that the structure thickness H1 becomes 261 μm.

[0060] like Figure 2C As shown, a patterning process is performed on the second metal layer 82 to form a circuit layer 201 on each of the core layers 80 .

[0061] In this embodiment, a plurality of conductive pillars 202 electrically connected to the circuit layer 201 may be formed in the core layer 80. For example, the thickness D4 of the circuit layer 201 is 15 microns, so that the structure thickness H2 becomes 291 microns.

[0062] Furthermore, the circuit layer 201 and the conductive pillars 202 are fabricated using a build-up process by electroplating metal (e.g., copper) or other methods. For example, a plurality of through-holes are first formed on the core layer 80 using a laser, and then copper is electroplated on the core layer 80 and in the through-holes to integrally form the circuit layer 201 and the conductive pillars 202.

[0063] Furthermore, there are many ways to make the through-holes, and there is no particular limitation. For example, the copper material may not completely fill the through-holes; or a plurality of interconnected bi-conical through-holes may be formed.

[0064] like Figure 2D As shown, an insulating layer 24 is formed on the core layer 80 to cover the circuit layer 201 , so as to form a circuit structure 20 .

[0065] In this embodiment, the thickness D5 of the insulating layer 24 is 20 micrometers, so that the structure thickness H3 becomes 331 micrometers.

[0066] Furthermore, the insulating layer 24 mainly comprises acrylic resin as a solder mask and has an opening 240, exposing the circuit layer 201 to the opening 240 for use as an electrical contact pad 203. For example, a surface treatment layer 23 such as nickel, gold, or other metal materials can be formed on the electrical contact pad 203.

[0067] like Figure 2E As shown, a support member 7 is combined on each of the circuit structures 20 (or the insulating layer 24 ), and a reinforcement member 6 is combined on the support member 7 .

[0068] In this embodiment, the support member 7 can be made of any material having a toughness and a glass transition temperature (Tg) higher than that of the substrate 8 and / or the core layer 80, such as glass fiber-containing prepreg (PP), FR4, or a thermal decomposition film. For example, the support member 7 is made of a thermal decomposition film made of polyethylene terephthalate (PET) with a thickness t2 greater than or equal to 140 microns (μm), and is adhered to the circuit structure 20 (or the insulation layer 24) using vacuum lamination.

[0069] Furthermore, the reinforcing member 6 is primarily composed of an epoxy resin material. For example, ink is first applied to the support member 7 to form an ink layer with a viscosity of 35-50 Pa·s. After application, the ink is baked and cured. In addition to a solvent, the ink's main ingredients include epoxy resin and / or pigment. Other ingredients may include a dispersant, leveling agent, or anti-settling agent.

[0070] like Figure 2F As shown, the carrier 9 is removed, and then the third metal layer 83 is removed to expose the first metal layer 81 .

[0071] In this embodiment, the carrier 9 is first removed by scribing to expose the third metal layer 83 , and then the third metal layer 83 is etched or stripped off.

[0072] Furthermore, in the present disclosure, the hardness (pencil hardness) of the reinforcement is greater than or equal to 8H, and the hardness (pencil hardness) of the core layer is greater than or equal to 6H. In one embodiment, the hardness of the reinforcement is greater than the hardness of the core layer.

[0073] In one embodiment, the modulus (Young's modulus) of the reinforcement is greater than 40 GPa, and the modulus (Young's modulus) of the core layer is 10 to 20 GPa. Preferably, the modulus of the reinforcement is greater than the modulus of the core layer.

[0074] like Figure 2GAs shown, a patterning and wiring process is performed on the first metal layer 81 to form a wiring layer 21 electrically connected to the conductive pillars 202 on each of the core layers 80 .

[0075] In this embodiment, the wiring layer 21 is made of copper, such as a redistribution layer (RDL) specification.

[0076] Furthermore, a solder mask layer 22 may be formed on each of the core layers 80 on which the wiring layer 21 is formed, so that a portion of the wiring layer 21 is exposed on the surface of the solder mask layer 22 to serve as the electrical contacts 210. For example, the solder mask layer 22 may be formed with a plurality of openings 220 that expose the electrical contacts 210. In one embodiment, the pencil hardness and Young's modulus of the core layer are both greater than those of the solder mask layer.

[0077] Therefore, the present disclosure uses the support member 7 as the first support body, the purpose of which is to avoid the appearance of depression on the surface of the substrate 8 due to the opening 240 of the insulating layer 24 after removing the carrier 9. Since the rigidity of the thermal decomposition film (support member 7) is relatively low, the present disclosure forms an ink (reinforcement member 6) with better hardness and rigidity thereon as the second support body to facilitate the production of the wiring layer 21 and the solder mask layer 22.

[0078] like Figure 2H As shown, the reinforcing member 6 and the supporting member 7 are removed, and the solder mask 22 is thermally cured to obtain the package substrate 2 .

[0079] In this embodiment, when the support member 7 is made of a thermally dissociable film, the temperature at which it decomposes and leaves the circuit structure 20 (or the insulating layer 24) (i.e., the dissociation temperature) can be higher or lower than the post-cure temperature or curing temperature of the solder mask 22 as required. Therefore, when the dissociation temperature of the support member 7 (e.g., 120°C) is lower than the curing temperature of the solder mask 22 (e.g., 160°C), the support member 7 is first heated (e.g., 120°C) to remove the support member 7, and then heated (e.g., 160°C) to cure the solder mask 22. In other embodiments, when the dissociation temperature of the support member 7 (e.g., 190°C) is higher than the curing temperature of the solder mask 22 (e.g., 160°C), the solder mask 22 is first heated to cure, and then the support member 7 is heated to remove the support member 7.

[0080] It should be understood that since the reinforcement member 6 is combined with the support member 7 , when the support member 7 is removed, the reinforcement member 6 will also be removed.

[0081] In summary, the manufacturing method of the packaging substrate 2 disclosed in the present invention mainly relies on the configuration of the reinforcement member 6 so that after removing the carrier 9, the existing processing equipment can continue to perform subsequent processes, such as making the wiring layer 21 and the solder mask layer 22, without any structural thickness restrictions. Therefore, compared with the existing technology, the manufacturing method disclosed in the present invention can be used for any ultra-thin substrate 8, and the performance of the existing processing equipment is sufficient to meet the process requirements without the problem of board jamming, thereby achieving the ability to produce the minimum board thickness to improve reliability.

[0082] Furthermore, by using the reinforcing member 6 and the supporting member 7 , any ultra-thin core substrate-type substrate 8 can be fabricated into the packaging substrate 2 .

[0083] In addition, in order to ensure that the flatness of the thinned substrate structure meets the requirements and avoid the problem of warping of the packaging substrate 2, compared with the existing technology, the manufacturing method disclosed in the present invention uses the configuration of the reinforcement 6 to prevent the packaging substrate 2 from warping during temperature cycling (such as thermally curing the solder mask 22), thereby ensuring that the packaging flatness meets the requirements, thereby improving reliability.

[0084] The above embodiments are intended to illustrate the principles and effects of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art may modify the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be as set forth in the claims.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: Disposing substrates on opposite sides of the carrier respectively; forming a circuit structure on the substrate; A support member is combined on the circuit structure, and a reinforcement member is combined on the support member; removing the carrier to expose the substrate; forming a wiring layer electrically connected to the circuit structure on the surface of the substrate from which the carrier is removed; as well as Remove the support member and the reinforcement member.

2. The method for manufacturing a package substrate according to claim 1, wherein: The substrate includes a core layer and a first metal layer and a second metal layer respectively formed on two opposite surfaces of the core layer.

3. The method for manufacturing a package substrate according to claim 2, wherein: The circuit structure includes a circuit layer made of the second metal layer and at least one conductive column arranged in the core layer and electrically connecting the circuit layer and the wiring layer.

4. The method for manufacturing a package substrate according to claim 2, wherein: The wiring layer is made of the first metal layer.

5. The method for manufacturing a package substrate according to claim 2, wherein: The circuit structure further includes an insulating layer formed on the core layer to cover the circuit layer.

6. The method for manufacturing a package substrate according to claim 2, wherein: The manufacturing method further comprises forming a solder resist layer on the surface of the substrate on which the wiring layer is formed, so that a portion of the wiring layer is exposed on the surface of the solder resist layer.

7. The method for manufacturing a package substrate according to claim 6, wherein: The pencil hardness and Young's modulus of the core layer are both greater than those of the solder mask layer.

8. The method for manufacturing a package substrate according to claim 1, wherein: The support member is made of a thermally dissociative film.

9. The method for manufacturing a package substrate according to claim 1, wherein: The reinforcing member is formed by coating an ink layer on the supporting member and then baking and curing the ink layer.

10. The method for manufacturing a package substrate according to claim 1, wherein: The reinforcement member is mainly composed of epoxy resin material.

11. The method for manufacturing a package substrate according to claim 9, wherein: The viscosity of the ink layer before baking and curing is 35-50 Pa·s.

12. The method for manufacturing a package substrate according to claim 2, wherein: The pencil hardness of the reinforcement is greater than or equal to 8H, and the pencil hardness of the core layer is greater than or equal to 6H.

13. The method for manufacturing a package substrate according to claim 12, wherein: The pencil hardness of the reinforcement is greater than the pencil hardness of the core layer.

14. The method for manufacturing a package substrate according to claim 2, wherein: The Young's modulus of the reinforcement is greater than 40 GPa, and the Young's modulus of the core layer is 10 to 20 GPa.

15. The method for manufacturing a package substrate according to claim 14, wherein: The Young's modulus of the reinforcement is greater than the Young's modulus of the core layer.

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