Multi-DBC packaging structure and packaging method of WLCSP chip

Abstract

The invention discloses a multi-DBC packaging structure and packaging method of a WLCSP chip, belongs to the technical field of chip packaging, and solves the problems that the heat conduction path of a chip of an existing heat dissipation packaging structure is lengthy, the overall heat resistance is large, and the overall heat dissipation capacity of the chip is limited. Mounting metal bumps on a bonding pad on the surface of the wafer in an array manner, and manufacturing a DBC (Direct Bonding Copper) packaging framework with a low thermal resistance path; the WLCSP chip and the DBC packaging framework are connected in a flip-chip mode through the DBC flip-chip technology; placing the packaged single WLCSP chip in a mold of a molding machine, and cutting off redundant structural copper by using an edge trimmer to form a finished product WLCSP chip; in the invention, the WLCSP chip and the DBC packaging framework are inversely connected based on a DBC inversion process, so that the heat generated by the chip is more effectively conducted to the outside, high-reliability chip packaging is realized by utilizing the characteristics of high heat conduction and high insulation of the DBC packaging framework, and the stability of the chip is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a multi-DBC packaging structure and a packaging method for a WLCSP chip. Background Art

[0002] With the rapid development of microelectronics technology, chip integration and power density continue to increase, placing higher demands on the heat dissipation performance, reliability, and flexibility of chip packaging. However, traditional chip packaging structures are gradually exposing limitations in terms of heat dissipation efficiency and adaptability to application scenarios, making it difficult to meet the needs of modern high-power, high-frequency, and high-voltage systems.

[0003] Traditional chip packaging structures mainly use single-layer DBC (direct bonded copper) substrates, which achieve heat dissipation and electrical connection by mounting the chip on a single-layer DBC substrate. However, this single-layer structure has the following problems: limited heat dissipation efficiency, difficulty in withstanding large currents and heat, and easy to cause package failure.

[0004] Chinese patent CN119008553B discloses a chip heat dissipation package structure and a method for preparing the same. The chip heat dissipation package structure comprises a substrate, a packaged chip, a thermally conductive material layer, and a first heat dissipation cover. The packaged chip is mounted on the substrate; the thermally conductive material layer is disposed on a side of the packaged chip facing away from the substrate; the first heat dissipation cover is disposed on the substrate and covers the packaged chip, with the first heat dissipation cover at least partially located on the side of the thermally conductive material layer facing away from the substrate. The first heat dissipation cover has a plurality of first heat dissipation bumps disposed on a side of the first heat dissipation cover proximal to the substrate. The first heat dissipation bumps are connected to a surface of the packaged chip facing away from the substrate, and the thermally conductive material layer is connected to the first heat dissipation cover. However, existing heat dissipation package structures form a heat conduction path through the thermally conductive material layer and the heat dissipation cover bumps. This lengthy heat conduction path results in high overall thermal resistance, further limiting the chip's overall heat dissipation capability. To address these issues, we propose a multi-DBC package structure and packaging method for WLCSP (Wafer-Level Chip Scale Package) chips. Summary of the Invention

[0005] The present invention aims to address the shortcomings of the prior art and provide a multi-DBC packaging structure and packaging method for a WLCSP chip. This solves the problem that the existing heat dissipation packaging structure forms a heat conduction path through the cooperation of a thermally conductive material layer and a heat dissipation cover bump, resulting in a long heat conduction path for the chip and a large overall thermal resistance, further limiting the overall heat dissipation capacity of the chip.

[0006] The present invention is implemented as follows: a multi-DBC packaging method for a WLCSP chip, the method comprising: The wafer tray is cleaned with deionized water and ultrasonic waves to remove particle contaminants from the wafer tray surface. The dielectric layer is deposited on each wafer in the wafer tray, followed by the UBM layer (bottom metallization layer). Metal bumps are installed in an array of pads on the wafer surface to obtain pre-processed WLCSP chips. Based on the WLCSP chip type, the thickness ratio of the thermal conductive ceramic layer and the thermal conductive copper layer is preset. The thermal conductive ceramic layer and the thermal conductive copper layer are alternately deposited on the package substrate. Vertical through holes are made in the DBC package architecture using laser drilling technology to produce a DBC package architecture with a low thermal resistance path. The pre-processed WLCSP chip is turned upside down, and the DBC flip-chip process is used to flip-chip interconnect the WLCSP chip and the DBC package structure. Solder paste is printed on the surface of the package substrate, and the heat dissipation frame is fastened to the outside of the package substrate. The multi-DBC package of the WLCSP chip is completed by welding in a vacuum eutectic furnace. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting. The packaged single WLCSP chip is placed in the mold of the molding machine, and high-temperature resistant thermal conductive material is injected into the mold. After the mold is opened, it is cooled and the excess structural copper is removed using a trimming machine to form a finished WLCSP chip. The finished WLCSP chip is then electrically tested to screen qualified finished WLCSP chips.

[0007] Preferably, the method for mounting metal bumps in an array of wafer surface pads comprises: Determine the type of metal bumps based on the wafer type. Metal bumps include tin-lead bumps, lead-free bumps, and copper pillar bumps. Use a laser thickness gauge to detect the size deviation of the metal bumps, and analyze the surface defect rate of the metal bumps using a scanning electron microscope. Oxygen plasma is used to plasma clean the pads on the wafer surface. A robotic arm grabs the metal bumps from the bump conveyor belt and aligns the metal bumps with the pads using a CCD camera (a digital imaging device based on a charge-coupled device image sensor). The laser bonding machine bonds the metal bumps to the pads according to the material type of the metal bumps, evaluates the reliability of the metal bump interconnection based on the modal synthesis method, and adjusts the thickness of the metal bump nano-silver paste based on the reliability evaluation results.

[0008] Preferably, the method for evaluating the reliability of metal bump interconnection based on modal synthesis method comprises: Obtaining wafer surface pad size parameters and bump distribution coordinate parameters, and using a three-dimensional visualization tool to construct a bump three-dimensional model based on the wafer surface pad size parameters and bump distribution coordinate parameters, wherein the bump three-dimensional model includes a wafer, pads, and metal bumps; Simulate accelerated thermal cycle testing of wafers to accelerate fatigue failure of metal bumps, calculate fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of metal bumps, and obtain indicator failure curves based on the bump fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness. Normalize the indicators to obtain a normalized failure curve. Based on the modal synthesis method, modal analysis is performed on the normalized failure curve, and modal analysis is performed on the substructures associated with the metal bump to obtain the substructure modal failure probability. The substructure modal failure probabilities are linearly weighted and combined to obtain the comprehensive failure probability of the metal bump. Determine whether the comprehensive failure probability of the metal bump exceeds a preset probability threshold, and if the comprehensive failure probability of the metal bump exceeds the preset probability threshold, locate the metal bump as a failed bump; Obtaining the failed bumps in the three-dimensional bump model and marking the failed bumps, adjusting the thickness of the metal bump nano-silver paste based on the comprehensive failure probability corresponding to the failed bumps, and feeding back the marked failed bumps and the metal bump nano-silver paste thickness; The thickness of the adjusted metal bump nano silver paste is calculated using the following formula: in, Indicates the thickness of the nano silver paste for metal bumps after adjustment. is the initial bump nano silver paste thickness, are the comprehensive failure probability and the preset probability threshold, respectively. Sub-mode The substructure weight coefficient and substructure modal failure probability, Represents sub-modes The fatigue life and shape parameters of the shape parameter are key parameters that describe the morphological characteristics of the probability distribution. For submodal the number of Represents the sensitivity coefficient.

[0009] Preferably, the method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type includes: Identify the WLCSP chip type, determine the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculate the chip's maximum thermal resistance based on the chip junction temperature requirement, chip power consumption, and maximum ambient temperature. Using ANSYS Icepak (high-precision professional simulation software for electronic thermal management analysis) as a constraint, simulate at least one set of thickness ratio combinations of thermally conductive ceramic layers and thermally conductive copper layers. Loading at least one set of thickness ratio combinations, presetting a maximum skin depth, determining a thickness range of the thermal conductive copper layer based on the maximum skin depth, and screening a thickness ratio combination that meets the maximum skin depth based on the thickness range of the thermal conductive copper layer; A DBC thermal resistance model is established based on the maximum thermal resistance, thermal expansion coefficient, and maximum carrying current. The thickness ratio combination that meets the maximum skin depth is used as a variable to calculate the overall thermal resistance of the DBC thermal resistance model. The thickness ratio combination with the minimum overall thermal resistance is regarded as the optimal thickness ratio combination.

[0010] Preferably, the method for manufacturing a DBC packaging architecture with a low thermal resistance path includes: Obtain the thickness ratio of the thermal conductive ceramic layer and the thermal conductive copper layer, cut the package substrate into the target size, and polish the surface of the package substrate; A thermally conductive copper layer and a thermally conductive ceramic layer are deposited on a substrate by magnetron sputtering, and the thermally conductive copper layer and the thermally conductive ceramic layer are alternately bonded by high temperature and high pressure to produce a target circuit pattern on the thermally conductive copper layer; Vertical through holes are made in the DBC package architecture using laser drilling technology, and temperature sensors are embedded in the vertical through holes to obtain a DBC package architecture with a low thermal resistance path.

[0011] Preferably, the method for flip-chip interconnecting a WLCSP chip and a DBC package architecture using a DBC flip-chip process comprises: A robotic arm is used to grip the DBC package frame, the WLCSP chip is turned upside down, and a CCD camera is used to align the WLCSP chip and the DBC package structure; Micro-etching the thermal conductive copper layer on the top of the DBC package frame, and printing nano silver paste on the micro-etched thermal conductive copper layer on the top of the DBC package frame; The aligned WLCSP chip and DBC package structure are aligned and flipped, and thermocompression bonded at 280-340°C and 3.5MPa pressure. The thermocompression bonded WLCSP chip and DBC package structure are then reflow soldered to complete the flip-chip interconnection between the WLCSP chip and DBC package structure.

[0012] Preferably, when printing nano-silver paste on the thermally conductive copper layer on the top of the micro-etched DBC package frame, the copper layer interconnection points corresponding to the failed bumps in the thermally conductive copper layer on the top of the DBC package frame are identified, the marked failed bumps and the thickness of the nano-silver paste on the metal bumps are obtained, and the thickness of the nano-silver paste on the metal bumps of the copper layer interconnection points is adjusted based on the marked failed bumps.

[0013] Preferably, when performing electrical testing on the finished WLCSP chip, the test items include insulation test, electrostatic discharge test, leakage current test under drain-source voltage, switching test, reverse recovery time test, resistance over-limit test, and DC parameter test.

[0014] On the other hand, the present invention also provides a multi-DBC packaging structure for a WLCSP chip, wherein the multi-DBC packaging structure for a WLCSP chip comprises: The packaging substrate, DBC packaging structure, and heat dissipation frame are welded with large pads. The DBC packaging structure is bonded to the packaging substrate. The WLCSP chip is bonded to the top of the DBC packaging structure, and the chip electrodes are electrically connected to the bottom layer of the DBC packaging structure through conductive through-holes.

[0015] Preferably, the DBC packaging architecture includes a thermally conductive copper layer and a thermally conductive ceramic layer, and at least one thermally conductive copper layer and thermally conductive ceramic layer are respectively provided, and the thermally conductive copper layer and thermally conductive ceramic layer are alternately arranged. The DBC packaging architecture also includes at least one group of vertical through holes passing through the thermally conductive copper layer and the thermally conductive ceramic layer, and bonding wires are arranged in the vertical through holes.

[0016] Compared with the prior art, the embodiments of the present application have the following beneficial effects: In an embodiment of the present invention, a DBC packaging architecture with a low thermal resistance path is fabricated, and the WLCSP chip and the DBC packaging architecture are flip-chip interconnected based on the DBC flip-chip process, thereby ensuring that the heat generated by the chip is more effectively conducted to the outside. By utilizing the high thermal conductivity and high insulation properties of the DBC packaging frame, high-reliability chip packaging is achieved, the operating temperature of the chip is reduced, and the stability and reliability of the chip are improved.

[0017] In an embodiment of the present invention, considering that long-term thermal cycling can cause creep strain inside the solder joint, when the strain exceeds the fatigue limit of the bonding alloy of the interconnection point, microcracks will appear in the metal bump and gradually expand, eventually causing failure. In order to avoid the problem of chip damage caused by metal bump failure during flip-chip interconnection of WLCSP chips and DBC packaging architectures, an embodiment of the present invention provides a reliability assessment method for metal bump interconnection based on a modal synthesis method. Through high-temperature-low-temperature rapid cycling, fatigue failure of metal bumps can be accelerated, thereby obtaining failure data in long-term use in a short period of time. By performing modal analysis on the normalized failure curve, the modal failure probability of the substructure associated with the metal bump can be obtained, thereby accurately reflecting the failure risk of the bump under different working conditions. By identifying high-risk bumps at an early stage and adjusting the thickness of the metal bump nanosilver paste, failure can be effectively avoided while improving the reliability consistency of batch products. Ultimately, the failure rate of chip packaging is effectively reduced.

[0018] In an embodiment of the present invention, a method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type is provided. By identifying the WLCSP chip type and determining its junction temperature requirements, power consumption, and maximum ambient temperature, the maximum thermal resistance requirement of the chip can be accurately calculated. This ensures that the thickness ratio design meets the heat dissipation requirements of the specific chip, avoiding performance degradation or damage due to insufficient heat dissipation. At the same time, by establishing a DBC thermal resistance model and using the thickness ratio combination that meets the maximum skin depth as a variable, the overall thermal resistance can be accurately calculated. This helps to find the optimal thickness ratio combination. By optimizing the thickness ratio, the heat dissipation performance of the package can be improved, thereby improving the reliability and performance of the chip and extending its service life.

[0019] In an embodiment of the present invention, a method for fabricating a DBC packaging architecture with a low thermal resistance path is provided. The DBC packaging architecture adopts a low thermal resistance design and, through the alternating stacking structure of copper and ceramic layers and optimized thickness ratio, effectively solves the problems of interface delamination and solder joint fatigue caused by CTE mismatch (thermal expansion mismatch) in traditional packaging. In addition, the DBC packaging architecture can be flexibly adapted to different types of WLCSP chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention provides a schematic diagram of the implementation process of the multi-DBC packaging method for the WLCSP chip.

[0021] Figure 2 A schematic diagram of the structure of a finished WLCSP chip in an embodiment of the present invention is shown.

[0022] Figure 3 It is a three-dimensional structural schematic diagram of the multi-DBC packaging structure of the WLCSP chip provided by the present invention.

[0023] Figure 4 It is a top view of the multi-DBC packaging structure of the WLCSP chip provided by the present invention.

[0024] Figure 5 The module circuit diagram of the DBC packaging architecture is shown.

[0025] Figure 6 A schematic diagram of the arrangement of the thermally conductive copper layer and the thermally conductive ceramic layer in the DBC packaging architecture is shown.

[0026] In the figure: 1-plastic package shell, 2-package substrate, 3-heat dissipation frame, 4-DBC package structure, 41-thermal conductive copper layer, 42-thermal conductive ceramic layer, 43-vertical through hole. DETAILED DESCRIPTION

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application. The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0028] The existing heat dissipation packaging structure forms a heat conduction path by combining a thermally conductive material layer and a heat dissipation cover bump. The heat conduction path of the chip is long and the overall thermal resistance is large, which further limits the overall heat dissipation capacity of the chip. To address the above problems, we propose a multi-DBC packaging structure and packaging method for WLCSP chips. The method includes depositing a dielectric layer on each wafer in a wafer tray, then depositing a UBM layer, and mounting metal bumps in an array of pads on the wafer surface to obtain a pre-processed WLCSP chip. The thickness of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 are preset based on the type of WLCSP chip. The invention relates to a method for fabricating a DBC package structure 4 with a low thermal resistance path by alternately depositing thermally conductive ceramic layers 42 and thermally conductive copper layers 41 on a package substrate 2. The DBC flip-chip process is used to flip-chip interconnect the WLCSP chip and the DBC package structure 4. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting. The packaged individual WLCSP chips are placed in a mold of a molding machine, and excess structural copper is removed using a trimming machine to form finished WLCSP chips. The finished WLCSP chips are then electrically tested to screen qualified finished WLCSP chips. In an embodiment of the present invention, by fabricating a DBC package structure 4 with a low thermal resistance path and flip-chip interconnecting the WLCSP chip and the DBC package structure 4 based on the DBC flip-chip process, heat generated by the chip is more effectively conducted to the outside. The high thermal conductivity and high insulation properties of the DBC package frame are utilized to achieve high-reliability chip packaging, reduce the operating temperature of the chip, and thereby improve the stability and reliability of the chip.

[0029] The embodiment of the present invention provides a multi-DBC packaging method for a WLCSP chip. Figure 1 A schematic diagram of a multi-DBC packaging method for a WLCSP chip is shown. The multi-DBC packaging method for a WLCSP chip specifically includes: S10, using deionized water combined with ultrasonic cleaning to treat the wafer disc to remove particle contaminants on the wafer disc surface, performing dielectric layer deposition on each wafer in the wafer disc, and then performing UBM layer deposition, and mounting metal bumps in an array of pads on the wafer surface to obtain a pre-processed WLCSP chip; It should be noted that when using deionized water combined with ultrasonic cleaning on the wafer tray, a plasma machine can also be used to activate and clean the wafers within the wafer tray. The plasma machine's cleaning power can be 100-250W, the processing temperature is 20-40°C, and the processing time is 20-60s. The WLCSP chip also has a metal redistribution layer.

[0030] S20, preset the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 based on the WLCSP chip type, alternately deposit the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 on the package substrate 2, and form vertical through holes 43 in the DBC package structure 4 using laser drilling technology to produce a DBC package structure 4 with a low thermal resistance path; S30, inverting the pre-treated WLCSP chip, using the DBC flip-chip process to flip-chip interconnect the WLCSP chip and the DBC package structure 4, printing solder paste on the surface of the package substrate 2, and fastening the heat dissipation frame 3 to the outside of the package substrate 2, and soldering in a vacuum eutectic furnace to complete the multi-DBC package of the WLCSP chip, and using laser cutting to cut the wafer-level WLCSP chip into individual WLCSP chips; S40, placing the packaged single WLCSP chip in a mold of a molding machine, injecting high-temperature resistant thermal conductive material into the mold, cooling the mold after opening, so that the plastic package shell 1 covers the WLCSP chip and the DBC package structure 4, and using a trimming machine to remove excess structural copper to form a finished WLCSP chip. The finished WLCSP chip is electrically tested to screen qualified finished WLCSP chips. Figure 2 A schematic diagram of the structure of a finished WLCSP chip in an embodiment of the present invention is shown. The finished WLCSP chip is electrically tested at least three times, with a single batch size of 600-900 test chips. The electrical tests on the finished WLCSP chips show a test pass rate exceeding 98% for WLCSP chips packaged using the multi-DBC packaging method for WLCSP chips provided in an embodiment of the present invention.

[0031] In this embodiment, when the finished WLCSP chip is electrically tested, the test equipment includes a probe station, a flying probe tester, and a vector network analyzer. The test items include but are not limited to insulation test, electrostatic discharge test (EAS), leakage current test under drain-source voltage (DVDS), switching test (SW), reverse recovery time test (TRR), resistance overrun test (RG), and DC parameter test (DC).

[0032] An embodiment of the present invention provides a method for mounting metal bumps in an array of wafer surface pads. The method for mounting metal bumps in an array of wafer surface pads specifically includes: S101, determining the type of metal bumps based on the wafer type, where the metal bumps include but are not limited to tin-lead bumps, lead-free bumps, and copper pillar bumps, using a laser thickness gauge to detect the size deviation of the metal bumps, where the size deviation is less than 3 μm, and analyzing the surface defect rate of the metal bumps using a scanning electron microscope, where the surface defect rate is ≤5%, thereby avoiding short circuits during bonding or welding; S102, using oxygen plasma to perform plasma cleaning on the pads on the wafer surface, using a robotic arm to grab metal bumps from a bump conveyor belt, and using a CCD camera to align the metal bumps with the pads; S103: A laser bonder bonds the metal bump to the pad based on the material type of the metal bump. The bonding pressure may be 3-5 MPa. The reliability of the metal bump interconnect is evaluated using a modal synthesis method, and the thickness of the metal bump nanosilver paste is adjusted based on the reliability evaluation results.

[0033] In this embodiment, the reliability of metal bump interconnects is evaluated based on the modal synthesis method. Its goal is to identify the potential failure risks of the bumps under stresses such as thermal cycling, mechanical vibration, and temperature shock, thereby ensuring the stability and service life of the WLCSP chip after packaging. It should be noted that Nano Silver Paste is a conductive paste formed by dispersing nanoscale silver particles in an organic or inorganic solvent. Due to its unique nano effect, it has high conductivity, low resistivity, good adhesion, and high temperature and chemical corrosion resistance. In this embodiment, Nano Silver Paste is used to replace conventional solder or metal plating, which can reduce the circuit resistance of the WLCSP chip, achieve high-resolution printing and high thermal conductivity, and improve the overall heat dissipation performance of the WLCSP chip.

[0034] Considering that long-term thermal cycling can cause creep strain inside the solder joint, when the strain exceeds the fatigue limit of the bonding alloy of the interconnection point, microcracks will appear in the metal bump and gradually expand, eventually causing failure. In order to avoid the problem of chip damage caused by metal bump failure during flip-chip interconnection between WLCSP chips and DBC packaging architecture 4, an embodiment of the present invention provides a method for evaluating the reliability of metal bump interconnection based on the modal synthesis method. The method for evaluating the reliability of metal bump interconnection based on the modal synthesis method specifically includes: S1031, obtaining the wafer surface pad size parameters and bump distribution coordinate parameters, and the three-dimensional visualization tool constructs a bump three-dimensional model based on the wafer surface pad size parameters and bump distribution coordinate parameters, wherein the bump three-dimensional model includes the wafer, pads and metal bumps; wherein, by constructing the bump three-dimensional model, the geometric relationship between the wafer, pads and bumps can be truly restored, providing accurate geometric input for subsequent simulation analysis, and avoiding the "idealization" error of traditional two-dimensional analysis.

[0035] S1032, simulates accelerated thermal cycle testing of wafers, wherein the number of accelerated thermal cycle tests can be 1000-1500 times, the temperature cycle is -40℃-150℃, accelerates fatigue failure of metal bumps, and statistics fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of metal bumps, respectively, and obtains indicator failure curves based on bump fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness mapping, and normalizes the indicators to obtain normalized failure curves. It should be noted that the fatigue failure time of metal bumps reflects the ability to resist thermal cycling, the cumulative creep strain reflects the degree of plastic deformation, and the fracture toughness reflects the interconnection is the ability of metal bumps to resist crack propagation; normalizing the indicators eliminates the influence of test equipment and environmental differences, making the data universal.

[0036] S1033, performing modal analysis on the normalized failure curve based on a modal synthesis method, performing modal analysis on substructures associated with the metal bump to obtain modal failure probabilities of the substructures, and performing linear weighted combination of the modal failure probabilities of the substructures to obtain a comprehensive failure probability of the metal bump; In the embodiment of the present invention, the substructures include but are not limited to the printed silver paste layer, the chip, the thermal conductive copper layer 41 and other substructures, and their failure probabilities are evaluated separately, avoiding the ambiguity of "overall evaluation".

[0037] S1034, determining whether the comprehensive failure probability of the metal bump exceeds a preset probability threshold, wherein the preset probability threshold can be set to 50-60%; S1035, if the comprehensive failure probability of the metal bump exceeds a preset probability threshold, the metal bump is identified as a failed bump; If the comprehensive failure probability of the metal bump does not exceed the preset probability threshold, the current metal bump is determined to be a normal bump.

[0038] S1036, obtaining the failed bumps in the three-dimensional bump model and marking the failed bumps, adjusting the thickness of the metal bump nano-silver paste based on the comprehensive failure probability corresponding to the failed bumps, and feeding back the marked failed bumps and the metal bump nano-silver paste thickness.

[0039] In this embodiment, the thickness of the adjusted metal bump nano silver paste is calculated using the following formula: in, Indicates the thickness of the nano silver paste for metal bumps after adjustment. is the initial bump nano silver paste thickness, are the comprehensive failure probability and the preset probability threshold, respectively. Sub-mode The substructure weight coefficient and substructure modal failure probability, Represents sub-modes The fatigue life and shape parameters of the shape parameter are key parameters that describe the morphological characteristics of the probability distribution. For submodal the number of Represents the sensitivity coefficient.

[0040] In an embodiment of the present invention, considering that long-term thermal cycling can cause creep strain inside the solder joint, when the strain exceeds the fatigue limit of the bonding alloy of the interconnection point, microcracks will appear in the metal bump and gradually expand, eventually causing failure. In order to avoid the problem of chip damage caused by metal bump failure during flip-chip interconnection of WLCSP chips and DBC packaging architecture 4, an embodiment of the present invention provides a reliability assessment method for metal bump interconnection based on a modal synthesis method. Through high-temperature-low-temperature rapid cycling, fatigue failure of metal bumps can be accelerated, thereby obtaining failure data in long-term use in a short period of time. By performing modal analysis on the normalized failure curve, the modal failure probability of the substructure associated with the metal bump can be obtained, thereby accurately reflecting the failure risk of the bump under different working conditions. By early identifying high-risk bumps and adjusting the thickness of the metal bump nanosilver paste, failure can be effectively avoided while improving the reliability consistency of batch products. Ultimately, the failure rate of chip packaging is effectively reduced.

[0041] In WLCSP (wafer-level chip scale packaging) chip packaging, the thickness ratio of the thermally conductive ceramic layer 42 to the thermally conductive copper layer 41 directly affects the package's thermal resistance, heat dissipation efficiency, and long-term reliability. In traditional package designs, however, the thicknesses of the ceramic and copper layers are often selected empirically, which can lead to excessive thermal resistance, insufficient heat dissipation efficiency, or CTE mismatch, resulting in excessive chip junction temperature and affecting chip operational stability. Therefore, an embodiment of the present invention provides a method for presetting the thickness ratio of the thermally conductive ceramic layer 42 to the thermally conductive copper layer 41 based on the WLCSP chip type. This method specifically includes: S201, identifying the WLCSP chip type, determining the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculating the chip maximum thermal resistance based on the chip junction temperature requirement, chip power consumption, and maximum ambient temperature. WLCSP chip types include high power, high frequency, and low power consumption, and the maximum thermal resistance calculation formula is expressed as: in, Indicates the maximum thermal resistance of the chip, is the chip power consumption, is the chip operating temperature difference, In this embodiment, the upper limit of thermal resistance is inferred from the junction temperature requirement, thereby avoiding the risk of excessive junction temperature due to excessive thermal resistance in advance.

[0042] S202, using the maximum thermal resistance of the chip as a constraint, simulate at least one set of thickness ratio combinations of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 based on ANSYS Icepak. In this embodiment, using the maximum thermal resistance of the chip as a constraint, the simulation based on ANSYS Icepak simultaneously simulates and evaluates multiple dimensional indicators, including thermal resistance, skin effect, and CTE mismatch. This allows for the initial screening of candidate combinations with superior overall performance based on the maximum thermal resistance of the chip as a constraint.

[0043] S203, loading at least one set of thickness ratio combinations, presetting a maximum skin depth, determining a thickness range of the thermally conductive copper layer 41 based on the maximum skin depth, and screening a thickness ratio combination that meets the maximum skin depth based on the thickness range of the thermally conductive copper layer 41; S204: Establish a DBC thermal resistance model based on the maximum thermal resistance, thermal expansion coefficient, and maximum carrying current, and calculate the overall thermal resistance of the DBC thermal resistance model using the thickness ratio combination that meets the maximum skin depth as a variable. The thickness ratio combination with the minimum overall thermal resistance is determined as the optimal thickness ratio combination.

[0044] In this embodiment, the DBC thermal resistance model incorporates CTE mismatch stress and maximum load-carrying current constraints, which can effectively ensure that the optimal combination has no risk of interlayer delamination or overheating during long-term use, and the optimized thickness ratio can be directly input into process equipment such as electroplating and sputtering, thereby reducing manual adjustment errors.

[0045] In an embodiment of the present invention, a method for presetting the thickness ratio of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 based on the WLCSP chip type is provided. By identifying the WLCSP chip type and determining its junction temperature requirements, power consumption, and maximum ambient temperature, the maximum thermal resistance requirement of the chip can be accurately calculated. This ensures that the thickness ratio design meets the heat dissipation requirements of the specific chip, avoiding performance degradation or damage due to insufficient heat dissipation. At the same time, by establishing a DBC thermal resistance model and using the thickness ratio combination that meets the maximum skin depth as a variable, the overall thermal resistance can be accurately calculated. This helps to find the optimal thickness ratio combination. By optimizing the thickness ratio, the heat dissipation performance of the package can be improved, thereby improving the reliability and performance of the chip and extending its service life.

[0046] An embodiment of the present invention provides a method for fabricating a DBC package architecture 4 with a low thermal resistance path. The method for fabricating a DBC package architecture 4 with a low thermal resistance path specifically includes: S301, obtaining a thickness ratio of the thermally conductive ceramic layer 42 to the thermally conductive copper layer 41, cutting the package substrate 2 into a target size, and polishing the surface of the package substrate 2. In the embodiment of the present invention, the ratio of the thermally conductive ceramic layer 42 to the thermally conductive copper layer 41 can be 1-1.4:0.4-1.2, and the number of layers of the thermally conductive ceramic layer 42 and the thermally conductive copper layer 41 can be 2-4. S302, depositing a thermally conductive copper layer 41 and a thermally conductive ceramic layer 42 on the substrate by magnetron sputtering, and alternately bonding the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 by high temperature and high pressure, thereby forming a target circuit pattern on the thermally conductive copper layer 41; S303, a vertical through hole 43 is made in the DBC package architecture 4 through laser drilling technology, and a temperature sensor is embedded in the vertical through hole 43 to obtain a DBC package architecture 4 with a low thermal resistance path. Among them, the DBC package architecture 4 integrates more functions in a limited space through laser drilling technology and vertical through hole 43 design, thereby improving the packaging density.

[0047] In an embodiment of the present invention, a method for manufacturing a DBC packaging architecture 4 with a low thermal resistance path is provided. The DBC packaging architecture 4 adopts a low thermal resistance design, and through the alternating stacking structure and thickness ratio optimization of copper layers and ceramic layers, it effectively solves the problems of interface delamination and solder joint fatigue caused by CTE mismatch in traditional packaging. In addition, the DBC packaging architecture 4 can be flexibly adapted to different types of WLCSP chips.

[0048] An embodiment of the present invention provides a method for flip-chip interconnecting a WLCSP chip and a DBC package architecture 4 using a DBC flip-chip process. The method for flip-chip interconnecting a WLCSP chip and a DBC package architecture 4 using a DBC flip-chip process specifically includes: S401, using a robot to clamp the DBC package frame, turning the WLCSP chip upside down, and using a CCD camera to align the WLCSP chip and the DBC package frame 4; S402: Micro-etching the thermally conductive copper layer 41 on the top of the DBC package. Micro-etching the DBC copper layer increases surface roughness, thereby improving the mechanical bonding ability of the nanosilver paste. It also removes the surface oxide layer, ensuring the chemical bonding quality between the silver paste and the copper layer. Nanosilver paste is then printed on the micro-etched thermally conductive copper layer 41 on the top of the DBC package. In semiconductor packaging (WLCSP, BGA, Flip Chip), nanosilver paste printing can be used to interconnect chips and substrates / PCBs (printed circuit boards), replacing traditional solder or conductive adhesives. Nanosilver paste has a much higher thermal conductivity than organic conductive adhesives and provides better thermal compatibility with ceramic and metal substrates. In chip packaging, the nanosilver paste-printed interconnect layer can reduce thermal resistance and chip junction temperature, thereby extending chip life.

[0049] S403, the aligned WLCSP chip and DBC package structure 4 are aligned and flipped, and thermocompression bonded at 280-340°C and 3.5 MPa. The thermocompression bonded WLCSP chip and DBC package structure 4 are then reflow soldered to complete the flip-chip interconnection between the WLCSP chip and the DBC package structure 4.

[0050] In this embodiment, when printing nano-silver paste on the thermally conductive copper layer 41 on the top of the micro-etched DBC package frame, the copper layer interconnection points corresponding to the failed bumps in the thermally conductive copper layer 41 on the top of the DBC package frame are identified, the marked failed bumps and the thickness of the nano-silver paste on the metal bumps are obtained, and the thickness of the nano-silver paste on the metal bumps of the copper layer interconnection points is adjusted based on the marked failed bumps.

[0051] On the other hand, the embodiment of the present invention also provides a multi-DBC packaging structure of a WLCSP chip, such as Figure 3-Figure 4 As shown, the multi-DBC packaging structure of the WLCSP chip specifically includes: The packaging substrate 2, the DBC packaging structure 4, and the heat dissipation frame 3 are welded with large pads. The DBC packaging structure 4 is bonded to the packaging substrate 2. The WLCSP chip and the DBC packaging structure 4 are covered by the plastic package shell 1. The WLCSP chip is bonded to the top of the DBC packaging structure 4, and the chip electrodes are electrically connected to the bottom layer of the DBC packaging structure 4, and the DBC packaging structure 4 and the WLCSP chip are electrically connected through conductive through-holes.

[0052] In this embodiment, Figure 6 A schematic diagram of the arrangement of the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 in the DBC packaging architecture 4 is shown. The DBC packaging architecture 4 includes a thermally conductive copper layer 41 and a thermally conductive ceramic layer 42. At least one layer of the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 are provided respectively, and the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42 are alternately arranged. The DBC packaging architecture 4 also includes at least one set of vertical through holes 43 passing through the thermally conductive copper layer 41 and the thermally conductive ceramic layer 42, and bonding wires are provided in the vertical through holes 43.

[0053] It should be noted that the DBC package architecture 4 also integrates a module circuit. Figure 5The module circuit schematic diagram of the DBC package architecture 4 is shown. The module circuit is provided with a first thermistor (NTC1) and a second thermistor (NTC2). The first thermistor and the second thermistor serve as temperature sensors. Accurate temperature measurement is achieved through the characteristic that the resistance changes with temperature, and a wide temperature range of -40°C to 150°C is supported. The resistance of the first thermistor and the second thermistor in the module circuit are both R=10KΩ (25°C), and the B value is 3435. The module circuit also includes a first diode (D1) and a second diode (D2). The first anode (D1+) is connected to the common node of the module circuit, and the second cathode (D2-) is also connected to the common node of the module circuit. The module circuit is also provided with a first gate (G1) and a second gate (G2). The first gate A switch (S) is provided between the first gate (G1) and the second gate (G2), and a group of field effect transistors (MOSFET) are respectively provided between the first gate (G1) and the switch (S) and between the second gate (G2) and the switch (S). The field effect transistor (MOSFET) includes a drain (Drain), a gate (Gate), and a source (Source). The field effect transistor (MOSFET) is connected to the switch through the source (Source), the field effect transistor (MOSFET) is electrically connected to the first gate (G1) or the second gate (G2) through the gate (Gate), and the field effect transistor (MOSFET) is electrically connected to the first diode (D1) or the second diode (D2) through the drain (Drain). In the embodiment of the present invention, the DBC packaging architecture 4 integrates the NTC sensor and signal processing chip through the DBC substrate, taking into account temperature measurement accuracy, heat dissipation performance and reliability, and providing a standardized temperature monitoring module for high-temperature and high-reliability scenarios. It simplifies the peripheral circuit design while improving system stability. The WLCSP chip provides three power levels of 6kW, 9kW, and 12kW, covering low and medium power to medium and high power requirements, and adapting to different system scales.

[0054] In summary, the present invention provides a multi-DBC packaging structure and packaging method for a WLCSP chip. In an embodiment of the present invention, a DBC packaging architecture 4 with a low thermal resistance path is manufactured, and the WLCSP chip and the DBC packaging architecture 4 are flip-chip interconnected based on the DBC flip-chip process, thereby ensuring that the heat generated by the chip is more effectively conducted to the outside. The high thermal conductivity and high insulation properties of the DBC packaging frame are utilized to achieve high-reliability chip packaging, reduce the operating temperature of the chip, and thus improve the stability and reliability of the chip.

[0055] It should be noted that for the aforementioned embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the scope of protection of the invention. Obviously, the embodiments described are only some embodiments of the present invention, rather than all embodiments. Based on these embodiments, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in this field can still combine, add, delete or make other adjustments to the features in the various embodiments of the present invention according to the circumstances without conflict, without making creative work, so as to obtain different other technical solutions that do not deviate from the concept of the present invention in essence, and these technical solutions also fall within the scope of protection of the present invention.

Claims

1. A multi-DBC packaging method for a WLCSP chip, characterized in that: The packaging method comprises: The wafer is cleaned with deionized water and ultrasonic waves to remove particle contaminants from the wafer surface. Dielectric layers are deposited on each wafer in the wafer, followed by UBM deposition. Metal bumps are then installed in an array on the wafer surface to obtain pre-processed WLCSP chips. Based on the WLCSP chip type, the thickness ratio of the thermal conductive ceramic layer and the thermal conductive copper layer is preset. The thermal conductive ceramic layer and the thermal conductive copper layer are alternately deposited on the package substrate. Vertical through holes are made in the DBC package architecture using laser drilling technology to produce a DBC package architecture with a low thermal resistance path. The pre-processed WLCSP chip is turned upside down, and the DBC flip-chip process is used to flip-chip interconnect the WLCSP chip and the DBC package structure. Solder paste is printed on the surface of the package substrate, and the heat dissipation frame is fastened to the outside of the package substrate. The multi-DBC package of the WLCSP chip is completed by welding in a vacuum eutectic furnace. The wafer-level WLCSP chip is cut into individual WLCSP chips using laser cutting. The packaged single WLCSP chip is placed in the mold of the molding machine, and high-temperature resistant thermal conductive material is injected into the mold. After the mold is opened, it is cooled and the excess structural copper is removed using a trimming machine to form a finished WLCSP chip. The finished WLCSP chip is then electrically tested to screen qualified finished WLCSP chips.

2. The multi-DBC packaging method for a WLCSP chip according to claim 1, wherein: The method for mounting metal bumps in an array of wafer surface pads comprises: Determine the type of metal bumps based on the wafer type. Metal bumps include tin-lead bumps, lead-free bumps, and copper pillar bumps. Use a laser thickness gauge to detect the size deviation of the metal bumps, and analyze the surface defect rate of the metal bumps using a scanning electron microscope. Oxygen plasma is used to plasma clean the pads on the wafer surface. A robotic arm grabs the metal bumps from the bump conveyor belt and aligns the metal bumps with the pads using a CCD camera. The laser bonding machine bonds the metal bumps to the pads according to the material type of the metal bumps, evaluates the reliability of the metal bump interconnection based on the modal synthesis method, and adjusts the thickness of the metal bump nano-silver paste based on the reliability evaluation results.

3. The multi-DBC packaging method for a WLCSP chip according to claim 2, wherein: The method for evaluating the reliability of metal bump interconnection based on the modal synthesis method includes: Obtaining wafer surface pad size parameters and bump distribution coordinate parameters, and using a three-dimensional visualization tool to construct a bump three-dimensional model based on the wafer surface pad size parameters and bump distribution coordinate parameters, wherein the bump three-dimensional model includes a wafer, pads, and metal bumps; Simulate accelerated thermal cycle testing of wafers to accelerate fatigue failure of metal bumps, calculate fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness of metal bumps, and obtain indicator failure curves based on the bump fatigue failure time, fatigue life, cumulative creep strain, and fracture toughness. Normalize the indicators to obtain a normalized failure curve. Based on the modal synthesis method, modal analysis is performed on the normalized failure curve, and modal analysis is performed on the substructures associated with the metal bump to obtain the substructure modal failure probability. The substructure modal failure probabilities are linearly weighted and combined to obtain the comprehensive failure probability of the metal bump. Determine whether the comprehensive failure probability of the metal bump exceeds a preset probability threshold, and if the comprehensive failure probability of the metal bump exceeds the preset probability threshold, locate the metal bump as a failed bump; The failed bumps in the three-dimensional bump model are obtained and marked, the thickness of the metal bump nano-silver paste is adjusted based on the comprehensive failure probability corresponding to the failed bumps, and the marked failed bumps and the thickness of the metal bump nano-silver paste are fed back.

4. The multi-DBC packaging method for a WLCSP chip according to claim 1, wherein: The method for presetting the thickness ratio of the thermally conductive ceramic layer and the thermally conductive copper layer based on the WLCSP chip type includes: Identify the WLCSP chip type, determine the chip junction temperature requirement, chip power consumption, and maximum ambient temperature based on the WLCSP chip type, and calculate the chip's maximum thermal resistance based on the chip junction temperature requirement, chip power consumption, and maximum ambient temperature. Using the maximum thermal resistance of the chip as a constraint, simulate at least one set of thickness ratio combinations of thermally conductive ceramic layers and thermally conductive copper layers using ANSYS Icepak. Loading at least one set of thickness ratio combinations, presetting a maximum skin depth, determining a thickness range of the thermal conductive copper layer based on the maximum skin depth, and screening a thickness ratio combination that meets the maximum skin depth based on the thickness range of the thermal conductive copper layer; A DBC thermal resistance model is established based on the maximum thermal resistance, thermal expansion coefficient, and maximum carrying current. The thickness ratio combination that meets the maximum skin depth is used as a variable to calculate the overall thermal resistance of the DBC thermal resistance model. The thickness ratio combination with the minimum overall thermal resistance is regarded as the optimal thickness ratio combination.

5. The multi-DBC packaging method for a WLCSP chip according to claim 4, wherein: The method for manufacturing a DBC packaging architecture with a low thermal resistance path includes: Obtain the thickness ratio of the thermal conductive ceramic layer and the thermal conductive copper layer, cut the package substrate into the target size, and polish the surface of the package substrate; A thermally conductive copper layer and a thermally conductive ceramic layer are deposited on a substrate by magnetron sputtering, and the thermally conductive copper layer and the thermally conductive ceramic layer are alternately bonded by high temperature and high pressure to produce a target circuit pattern on the thermally conductive copper layer; Vertical through holes are made in the DBC package architecture using laser drilling technology, and temperature sensors are embedded in the vertical through holes to obtain a DBC package architecture with a low thermal resistance path.

6. The multi-DBC packaging method for a WLCSP chip according to claim 1, wherein: The method for flip-chip interconnecting a WLCSP chip and a DBC package architecture using a DBC flip-chip process includes: A robotic arm is used to grip the DBC package frame, the WLCSP chip is turned upside down, and a CCD camera is used to align the WLCSP chip and the DBC package structure; Micro-etching the thermal conductive copper layer on the top of the DBC package frame, and printing nano silver paste on the micro-etched thermal conductive copper layer on the top of the DBC package frame; The aligned WLCSP chip and DBC package structure are aligned and flipped, and thermocompression bonded at 280-340°C and 3.5MPa pressure. The thermocompression bonded WLCSP chip and DBC package structure are then reflow soldered to complete the flip-chip interconnection between the WLCSP chip and DBC package structure.

7. The multi-DBC packaging method for a WLCSP chip according to claim 6, wherein: When printing nano-silver paste on the thermally conductive copper layer on the top of the micro-etched DBC package frame, the copper layer interconnection points corresponding to the failed bumps in the thermally conductive copper layer on the top of the DBC package frame are identified, the marked failed bumps and the thickness of the nano-silver paste on the metal bumps are obtained, and the thickness of the nano-silver paste on the metal bumps at the copper layer interconnection points is adjusted based on the marked failed bumps.

8. The multi-DBC packaging method for a WLCSP chip according to claim 1, wherein: When conducting electrical tests on finished WLCSP chips, the test items include insulation test, electrostatic discharge test, leakage current test under drain-source voltage, switching test, reverse recovery time test, resistance over-limit test, and DC parameter test.

9. A multi-DBC packaging structure for a WLCSP chip, used to implement the multi-DBC packaging method for a WLCSP chip according to any one of claims 1 to 8, characterized in that: The multi-DBC packaging structure of the WLCSP chip includes: The packaging substrate, DBC packaging structure, and heat dissipation frame are welded with large pads. The DBC packaging structure is bonded to the packaging substrate. The WLCSP chip is bonded to the top of the DBC packaging structure, and the chip electrodes are electrically connected to the bottom layer of the DBC packaging structure through conductive through-holes.

10. The multi-DBC package structure of the WLCSP chip according to claim 9, wherein: The DBC packaging architecture includes a thermally conductive copper layer and a thermally conductive ceramic layer. The thermally conductive copper layer and the thermally conductive ceramic layer are each provided with at least one layer, and the thermally conductive copper layer and the thermally conductive ceramic layer are alternately arranged. The DBC packaging architecture also includes at least one group of vertical through holes penetrating the thermally conductive copper layer and the thermally conductive ceramic layer, and bonding wires are arranged in the vertical through holes.

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