Semiconductor device and method for forming a semiconductor device

Abstract

The invention provides a semiconductor device and a method for forming the semiconductor device. The method comprises the following steps: providing a packaging substrate; mounting at least one preformed conductive block and at least one electronic component on a top surface of the package substrate, wherein the preformed conductive block comprises an insulating substrate and at least one conductive post extending through the insulating substrate; forming an encapsulant on a top surface of the package substrate, wherein the encapsulant exposes a top surface of a conductive pillar of the conductive block and a top surface of the electronic component; and forming a heat sink cap over the encapsulant to electrically couple the heat sink cap to the conductive posts of the conductive block and thermally couple the heat sink cap to the electronic component.

Description

Technical Field

[0001] The present application relates generally to semiconductor technology and, more particularly, to semiconductor devices and methods for forming semiconductor devices. Background Art

[0002] As consumers want their electronic devices to be smaller, faster, and higher performing, and to pack more and more functions into a single device, the semiconductor industry has been facing complex integration challenges. In order to meet consumer demand, more and more electronic components are being tightly integrated into a single device or package. However, due to the tight integration, electromagnetic interference (EMI) may easily occur between electronic components, and the heat generated by one electronic component may be blocked by another electronic component and cannot be dissipated. Typically, an EMI shield can be formed over the device to cover electronic components that are susceptible to EMI or generate EMI, and a heat sink can be attached to the device to dissipate the heat generated by the electronic components. However, conventional methods for forming EMI shields and heat sinks are complex, resulting in high costs and low reliability.

[0003] Therefore, there is a need for a semiconductor device with reduced cost. Summary of the Invention

[0004] An object of the present application is to provide a semiconductor device with low cost.

[0005] According to one aspect of the present application, a method for forming a semiconductor device is provided. The method may include: providing a packaging substrate; mounting at least one preformed conductive block and at least one electronic component on a top surface of the packaging substrate, wherein the preformed conductive block includes an insulating substrate and at least one conductive pillar extending through the insulating substrate; forming an encapsulant on the top surface of the packaging substrate, wherein the encapsulant exposes the top surface of the conductive pillar of the conductive block and the top surface of the electronic component; and forming a heat dissipation cap on the encapsulant to electrically couple the heat dissipation cap to the conductive pillar of the conductive block and thermally couple the heat dissipation cap to the electronic component.

[0006] According to another aspect of the present application, a method for forming a semiconductor device is provided. The method may include: providing a packaging substrate; mounting at least one preformed conductive block and at least one electronic component on a top surface of the packaging substrate; forming an encapsulant on the top surface of the packaging substrate, wherein the encapsulant exposes the top surface of the conductive block; and forming a heat dissipation cover on the encapsulant to connect with the conductive block, such that the conductive block and the heat dissipation cover form an enclosed structure to accommodate the electronic component.

[0007] According to another aspect of the present application, a semiconductor device is provided. The semiconductor device may include: a package substrate; at least one preformed conductive block and at least one electronic component, the preformed conductive block and the electronic component being mounted on a top surface of the package substrate, wherein the preformed conductive block includes an insulating base and at least one conductive post extending through the insulating base; an encapsulant formed on the top surface of the package substrate, wherein the encapsulant exposes the top surface of the conductive post of the conductive block and the top surface of the electronic component; and a heat dissipation top cover formed on the encapsulant, wherein the heat dissipation top cover is electrically coupled to the conductive post of the conductive block and thermally coupled to the electronic component.

[0008] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. In addition, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings cited herein form part of this specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless the specific implementation method clearly indicates otherwise, and the reader of this specification should not make any contrary implications.

[0010] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present application is shown.

[0011] Figure 2 A cross-sectional view of a semiconductor device according to another embodiment of the present application is shown.

[0012] Figure 3 A cross-sectional view of a semiconductor device according to another embodiment of the present application is shown.

[0013] Figure 4 A cross-sectional view of a semiconductor device according to another embodiment of the present application is shown.

[0014] Figure 5 A cross-sectional view of a semiconductor device according to another embodiment of the present application is shown.

[0015] Figures 6A to 6H Cross-sectional views illustrating various steps of a method for forming a semiconductor device according to an embodiment of the present application are shown.

[0016] Figures 7A to 7H Cross-sectional views illustrating various steps of a method for forming a semiconductor device according to another embodiment of the present application are shown.

[0017] Figures 8A to 8DCross-sectional views illustrating various steps of a method for forming a semiconductor device according to another embodiment of the present application are shown.

[0018] The same reference numbers will be used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0019] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of this specification. The accompanying drawings illustrate specific exemplary embodiments in which the present application can be practiced. The detailed description, including the accompanying drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical and other changes without departing from the spirit or scope of the present application. Therefore, readers of the following detailed description should not interpret the description in a restrictive sense, and only the appended claims define the scope of the embodiments of the present application.

[0020] In this application, unless otherwise specifically stated, the use of the singular includes the plural. In this application, unless otherwise stated, the use of "or" means "and / or". In addition, the use of the term "include" and other forms such as "include" and "comprising" are not limiting. In addition, unless otherwise specifically stated, terms such as "element" or "component" encompass elements and components comprising one unit, as well as elements and components comprising more than one subunit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0021] Spatially relative terms such as "below," "below," "above," "on," "up," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc., as used herein, may be used herein for ease of description to describe the relationship of one element or feature to another or more elements or features as shown in the drawings. In addition to the orientations depicted in the drawings, spatially relative terms are also intended to cover different orientations of the device when in use or in operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can also be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to or coupled to the other element, or there can be intermediate elements.

[0022] Figure 1FIG2 shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present application. The semiconductor device 100 may include a package substrate 110, a plurality of electronic components 121, 122, 123, and 124, and at least one pre-molded conductive block 130 mounted on the top surface of the package substrate 110. An encapsulant 140 may be formed on the top surface of the package substrate 110 to seal the various components thereon, and a heat dissipation cap 150 may be further formed on the encapsulant 140.

[0023] The package substrate 110 can provide support and connectivity for the electronic components and devices mounted thereon. For example, the package substrate 110 can include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnects, a ceramic substrate, a stacked interposer, a strip interposer, a lead frame, or other suitable substrate. The package substrate 110 can include any structure on which or in which an integrated circuit system can be manufactured. In some examples, the package substrate 110 can include a redistribution structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layers can define pads, traces, and plugs through which electrical signals or voltages can be distributed horizontally and vertically across the redistribution structure.

[0024] Electronic components 121 to 124 may include any of various semiconductor dies, semiconductor packages, or discrete devices. For example, electronic components 121 to 124 may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, a radio frequency (RF) circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, a memory controller, a memory device, an application-specific integrated circuit, etc. In some other instances, electronic components 121 to 124 may be passive components, such as resistors, capacitors, inductors, switches, or any other suitable electronic devices. As an example, electronic components 121 and 122 are discrete devices, and electronic components 123 and 124 are semiconductor dies.

[0025] The conductive block 130 is preformed and includes an insulating base 134 and a conductive pillar 132 extending through the insulating base 134. The conductive block 130 can surround the electronic components 121 to 124. In some examples, the conductive block 130 can be formed as a whole and can have a square, rectangular, or circular shape to surround the electronic components 121 to 124. In some examples, a plurality of conductive blocks 130 can be provided on the package substrate 110 to form a wall surrounding the electronic components 121 to 124. In some examples, the conductive blocks 130 can be distributed at four sides of the electronic components 121 to 124. In this case, the conductive blocks 130 may not completely surround the electronic components 121 to 124 at their lateral sides, and the sealing material of the sealant 140 fills the gaps between adjacent conductive blocks 130.

[0026] In some embodiments, the preformed conductive block 130 may include an electrical functional column (e-bar) module. The electrical functional column module may include at least one conductive column (e.g., a copper column) surrounded by a dielectric layer (e.g., an insulating polymer material or a composite). More specifically, the bottom surface of the conductive column may be exposed or protruded from the bottom surface of the dielectric layer to be electrically connected to the contact pad of the substrate 110. Similarly, the top surface of the conductive column may be exposed or protruded from the top surface of the dielectric layer for electrical contact purposes, such as connection to the heat dissipation top cover 150. The number of conductive columns included in the conductive block 130 may vary according to the actual needs of the semiconductor device 100.

[0027] In some embodiments, the preformed conductive block 130 may include a molded interconnect substrate (MIS). Generally speaking, MIS is an effective semiconductor substrate technology for thin semiconductor packages by routing pre-molded copper traces (or interconnects) into the substrate. Examples for preforming MIS may include providing a carrier (e.g., cold rolled steel sheet (SPCC)) and then plating one or more metal (e.g., copper) layers on the carrier. The one or more metal layers are configured to form horizontal or vertical interconnects. The one or more metal layers may then be sealed by performing an over-mold procedure if an epoxy molding compound (EMC) material is used, or if an Ajinomoto TM The film material of the built-up film (ABF) can be used to seal the one or more metal layers by performing a lamination process. In addition, a surface grinding process can be performed to expose a portion of the metal layer, and an etching process can be performed to remove at least a portion of the carrier.

[0028] In some embodiments, for example Figure 1In the illustrated embodiment, a plurality of solder bumps may be formed on contact pads on the top surface of the package substrate 110. The electronic components 121 to 124 and the conductive blocks 130 may be placed on the top surface of the package substrate 110 and contacted with the solder bumps, and the solder bumps may then be reflowed to mount the electronic components 121 to 124 and the conductive blocks 130 to the top surface of the package substrate 110 via the solder bumps, thereby forming electrical connections between the conductive layers in the package substrate 110 and the electronic components 121 to 124 and the conductive blocks 130. For example, the conductive pillars 132 of the conductive blocks 130 may be electrically connected to a reference node or potential, such as a ground layer in the package substrate 110.

[0029] refer to Figure 1 , the sealant 140 is formed on the top surface of the package substrate 110. The sealant 140 may be made of a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with appropriate filler, but the scope of the present application is not limited thereto. Figure 1 In the example shown in FIG, the top surface of the conductive block 123 or the top surface of the conductive pillar 132 protruding from the insulating base 134 is substantially flush with the top surface of the electronic component 123, but higher than the top surface of each of the electronic components 121, 122, and 124. Therefore, the sealant 140 exposes the top surface of the conductive pillar 132 of the conductive block 130 and the top surface of the electronic component 123, but seals and covers the electronic components 121, 122, and 124. Therefore, the heat dissipation cover 150 formed on the sealant 140 can be electrically coupled to the conductive pillar 132 of the conductive block 130 and thermally coupled to the top surface of the electronic component 123.

[0030] exist Figure 1 In the example shown in , the heat dissipation top cover 150 may include an electromagnetic interference (EMI) shield 152, a thermal interface material (TIM) layer 156, and a heat sink 154, wherein the EMI shield 152 is formed on the sealant 140 and electrically coupled to the conductive pillars 132 of the conductive block 130; the TIM layer 156 is formed on the EMI shield 152; and the heat sink 154 is attached to the TIM layer 156 and thermally coupled to the top surface of the electronic component 123 via the TIM layer 156 and the EMI shield 152.

[0031] The EMI shield 152 may include copper, aluminum, iron, or any other suitable material for EMI shielding. In some embodiments, the EMI shield 152 may be formed by spraying, plating, sputtering, or any other suitable metal deposition process. The EMI shield 152 may be formed on the top surface of the sealant 140 and cover the top surface of the electronic component 123 and the top surface of the conductive pillars 132 of the conductive block 130 to surround the electronic components 121 to 124 of the semiconductor device 100. The EMI shield 152 may form a closed loop circuit with the conductive pillars 132 of the conductive block 130 and the ground layer in the package substrate 110 to guide the induced EMI current to the ground layer in the package substrate 110.

[0032] TIM layer 156 may include solder, indium, silver, an indium / silver alloy, or other suitable materials. In some embodiments, TIM layer 156 may be formed by spraying, plating, sputtering, or any other suitable metal deposition process. TIM layer 156 may be used to solder EMI shield 152 to heat sink 154 to enhance adhesion between EMI shield 152 and heat sink 154.

[0033] Heat sink 154 may include a metal cap made of copper, aluminum, nickel-plated copper, nickel-plated aluminum, or other materials with high thermal conductivity. Heat sink 154 may be attached to TIM layer 156 and thermally coupled to electronic component 123 through TIM layer 156 and EMI shield 152 to dissipate heat generated by electronic component 123 and other electronic components to the external environment.

[0034] Continue to refer Figure 1 , the semiconductor device 100 may further include a plurality of conductive bumps 160 formed on the bottom surface of the package substrate 110. Figure 1 In the example shown in FIG, the conductive bumps 160 are shown as solder bumps, but the scope of the present application is not limited thereto. In some other embodiments, the conductive bumps 160 may include conductive pillars, copper balls, etc. When the semiconductor device 100 is mounted on an external device or a substrate such as a printed circuit board (PCB), the conductive bumps 160 may be used to electrically connect the semiconductor device 100 to the external device or substrate.

[0035] exist Figure 1In the semiconductor device 100 shown in FIG, a preformed conductive block 130 (e.g., an electrical functional column module or a molded interconnect substrate) is connected to a heat dissipation top cover 150 to form a closed structure, and electronic components 121 to 124 are housed within the closed structure. The closed structure can not only serve as an EMI shielding structure for the electronic components 121 to 124, but also dissipate heat generated by the electronic components 121 to 124. The manufacturing cost of the preformed conductive block 130 is generally lower than that of a traditional metal strip and can be easily attached to the package substrate 110 by surface mounting technology (SMT). Therefore, the cost for forming the semiconductor device 100 can be reduced compared to traditional processes. In addition, the preformed conductive block 130 can serve as a leg to support the heat dissipation top cover 150 on the package substrate 110, thereby eliminating the need for an additional support structure and enhancing the rigidity of the semiconductor device 100.

[0036] In addition, the preformed conductive block 130 can be used not only to form Figure 1 The full shielding structure of the semiconductor device 100 shown in FIG. 1 can also be used to form Figure 2 The compartment shielding structure of the semiconductor device 200 is shown in FIG.

[0037] refer to Figure 2 , which shows a cross-sectional view of a semiconductor device 200 having a compartment shielding structure according to an embodiment of the present application. The semiconductor device 200 may have Figure 1 The similar or identical parts between the semiconductor device 200 and the semiconductor device 100 will not be repeated here.

[0038] Specifically, if Figure 2 As shown in FIG, the semiconductor device 200 may include: a package substrate 210; a plurality of electronic components 222, 223, and 224 and at least one pre-formed conductive block 230 mounted on the top surface of the package substrate 210; a sealant 240 formed on the top surface of the package substrate 210; and a heat dissipation top cover 250 formed on the sealant 240. The heat dissipation top cover 250 has a multi-layer stacked structure, which includes an EMI shield 252, a TIM layer 256, and a heat sink 254. Different from Figure 1In the semiconductor device 100 shown in FIG, the preformed conductive block 230 of the semiconductor device 200 forms two distinct compartments, namely a first compartment I for accommodating the electronic component 223 and a second compartment II for accommodating the electronic components 222 and 224. This is beneficial when electromagnetic interference exists between the electronic component 223 and the electronic components 222 and 224. In some preferred embodiments, the preformed conductive block 230 can extend substantially across the package substrate 210 to provide better EMI shielding performance. In addition, the preformed conductive block 230 also provides a heat dissipation path from the interior of the semiconductor device 200 to the heat dissipation top cover 250, which improves the heat dissipation performance of the entire semiconductor device 200.

[0039] Figure 3 FIG. 3 shows a cross-sectional view of a semiconductor device 300 according to another embodiment of the present application. The semiconductor device 300 may have Figure 1 The similar or identical parts between the semiconductor device 300 and the semiconductor device 100 will not be repeated here.

[0040] Specifically, if Figure 3 As shown in FIG, the semiconductor device 300 may include: a package substrate 310; a plurality of electronic components 321, 322, 323, and 324 and at least one pre-molded conductive block 330 mounted on the top surface of the package substrate 310; a sealant 340 formed on the top surface of the package substrate 310; and a heat dissipation top cover 350 formed on the sealant 340. The heat dissipation top cover 350 has a multi-layer stacked structure including an EMI shield 352, a TIM layer 356, and a heat sink 354. Unlike Figure 1 In the semiconductor device 100 shown in FIG, the EMI shield 352 of the semiconductor device 300 may be a conformal shield that follows the shape and / or contour of the encapsulant 340 and the substrate 310. Specifically, the EMI shield 352 covers the top surface of the electronic component 323, the top surface of the conductive pillar of the conductive block 330, the top surface and side surfaces of the encapsulant 340, and the side surface of the package substrate 310. The conformal EMI shield 352 may provide better EMI shielding performance and better heat dissipation performance for the entire semiconductor device 300.

[0041] Figure 4 FIG. 4 shows a cross-sectional view of a semiconductor device 400 according to another embodiment of the present application. The semiconductor device 400 may have Figure 1 The similar or identical parts between the semiconductor device 400 and the semiconductor device 100 will not be repeated here.

[0042] Specifically, if Figure 4As shown in FIG, the semiconductor device 400 may include: a package substrate 410; a plurality of electronic components 421, 422, 423, and 424 and at least one pre-formed conductive block 430 mounted on the top surface of the package substrate 410; a sealant 440 formed on the top surface of the package substrate 410; and a heat dissipation top cover 450 formed on the sealant 440. Figure 1 In the semiconductor device 100 shown in FIG, the heat dissipation cap 450 of the semiconductor device 400 may include an interconnect layer 458 formed on the top surface of the conductive pillars of the conductive block 430, a TIM layer 456 formed on the top surface of the electronic component 423, and a heat sink 454 attached to the interconnect layer 458 and the TIM layer 456. The interconnect layer 458 may be made of a conductive material such as solder, conductive ink, or conductive epoxy. Therefore, the heat sink 454 may be electrically coupled to the conductive pillars of the conductive block 430 through the interconnect layer 458 and thermally coupled to the electronic component 423 through the TIM layer 456.

[0043] In some examples, the TIM layer 456 may include a material having a melting point close to room temperature, such as gallium, gallium-indium alloy (InGa), gallium-indium-tin alloy (InGaSn), etc. That is, the TIM layer 456 may be liquid at room temperature. The interconnect layer 458, together with the heat sink 454, may surround the liquid TIM layer 456 and prevent it from leaking to the outside. The liquid TIM layer 456 can provide several advantages due to its inherent high thermal conductivity, flexibility, and low melting point. For example, the liquid TIM layer 456 can fully cover rough surfaces and fill air voids, thereby further reducing interface resistance. However, the present application is not limited thereto. In some other examples, the TIM layer 456 may include solder, silver, indium / silver alloy, or other suitable materials.

[0044] exist Figure 4 In the semiconductor device 400 shown in FIG, the heat spreader 454, together with the interconnect layer 458 and the conductive block 430, acts as an EMI shield. In some embodiments, the interconnect layer 458 may surround the TIM layer 456, without filling other TIM material between the heat spreader 454 and the sealant layer 440. However, in some alternative embodiments, additional TIM material may be formed outside the interconnect layer 458 to further improve heat transfer between the heat spreader 454 and the sealant layer 440.

[0045] Figure 5 FIG. 5 shows a cross-sectional view of a semiconductor device 500 according to another embodiment of the present application. The semiconductor device 500 may have Figure 4 The similar or identical parts between the semiconductor device 500 and the semiconductor device 400 will not be repeated here.

[0046] Specifically, if Figure 5 As shown in , the semiconductor device 500 may include: a package substrate 510; a plurality of electronic components 522, 523, and 524 and at least one pre-formed conductive block 530 mounted on the top surface of the package substrate 510; a sealant 540 formed on the top surface of the package substrate 510; and a heat dissipation top cover 550 formed on the sealant 540. The heat dissipation top cover 550 may include an interconnection layer 558 formed on the top surface of the conductive pillar of the conductive block 530, a TIM layer 556 formed on the top surface of the electronic component 523, and a heat sink 554 attached to the interconnection layer 558 and the TIM layer 556. In some examples, the TIM layer 556 may include a material having a melting point close to room temperature, such as gallium, a gallium-indium alloy, a gallium-indium-tin alloy, etc. The interconnection layer 558 may surround the liquid TIM layer 551 and prevent it from leaking to the outside. In some examples, the TIM layer 556 may include solder, silver, an indium / silver alloy, or other suitable materials. Different from Figure 4 In the semiconductor device 400 shown in FIG, the preformed conductive block 530 of the semiconductor device 500 forms two different compartments, namely a first compartment I for accommodating the electronic component 523 and a second compartment II for accommodating the electronic components 522 and 524. This is beneficial when there is electromagnetic interference between the electronic component 523 and the electronic components 522 and 524.

[0047] refer to Figures 6A to 6H , according to an embodiment of the present application, various steps of a method for forming a semiconductor device are shown. For example, the method can be used to form Figure 1 The semiconductor device 100 shown in FIG. Figures 6A to 6H The method is described in more detail.

[0048] refer to Figure 6A , providing a package substrate 610. The package substrate 610 can provide support and connectivity for the electronic components and devices mounted thereon. For example, the package substrate 610 may include a printed circuit board (PCB), a carrier substrate, a semiconductor substrate with electrical interconnection, a ceramic substrate, a stacked interposer, a strip interposer, a lead frame, or other suitable substrate. In some instances, the package substrate 610 may include a redistribution structure having one or more dielectric layers and one or more conductive layers between and through the dielectric layers. The conductive layer may define pads, traces, and plugs, through which electrical signals or voltages may be distributed horizontally and vertically across the redistribution structure. In some embodiments, the package substrate 610 may include a plurality of predefined substrate units arranged in a strip manner, and a single-unit cutting process may be performed in a subsequent step to cut individual packages from the package strip along a single-unit cutting channel.

[0049] refer to Figure 6B , electronic components 621 and 622 and at least one pre-formed conductive block 630 are mounted on the top surface of the package substrate 610 .

[0050] For example, the electronic components 621 and 622 may include discrete devices or other small components. The preformed conductive block 630 may include an insulating base 634 and a conductive column 632 extending through the insulating base 634. For example, the preformed conductive block 630 may include an electrical function column module or a molded interconnect substrate (MIS). The conductive block 630 may form a wall surrounding the electronic components 621 and 622. In some embodiments, a soldering material may be deposited on contact pads formed on the top surface of the package substrate 610, and the electronic components 621 and 622 and the preformed conductive block 630 may be placed on the top surface of the package substrate 610 and contacted with the soldering material. The soldering material may then be reflowed to mount the electronic components 621 and 622 and the preformed conductive block 630 on the top surface of the package substrate 610 via the soldering material, thereby forming an electrical connection therebetween.

[0051] refer to Figure 6C , electronic components 623 and 624 are mounted on the top surface of the package substrate 610. The electronic components 623 and 624 may include semiconductor chips, semiconductor dies, or semiconductor packages. Figure 6C In the example shown in FIG, electronic component 623 is higher than electronic components 621, 622, and 624 and is at the same level as conductive block 630. Therefore, the top surface of conductive block 630 is substantially flush with the top surface of electronic component 623, but higher than the top surfaces of electronic components 621, 622, and 624.

[0052] I understand. Figure 6B and 6C The operations shown in FIG are merely examples, and the present application is not limited thereto. In some other embodiments, the electronic components 621 and 622 , the preformed conductive block 630 , and the electronic components 623 and 624 may be mounted on the top surface of the package substrate 610 in a different order.

[0053] refer to Figure 6D, a sealant 640 is formed on the top surface of the package substrate 610 to seal the conductive blocks 630 and the electronic components 621, 622, 623, and 624. In some embodiments, a molding material may be formed on the top surface of the package substrate 610 to form the sealant 640. The molding material may include epoxy resin, epoxy resin with filler, epoxy acrylate with filler, or a polymer with a suitable filler, but the scope of the present application is not limited thereto. In some embodiments, the sealant 640 may be formed using compression molding, transfer molding, liquid sealant molding, or other suitable molding processes.

[0054] refer to Figure 6E , the sealant 640 is ground to expose the top surface of the conductive pillar 632 of the conductive block 630 and the top surface of the electronic component 623 .

[0055] In some embodiments, a grinder may be used to remove the upper portion of the encapsulant 640. In some embodiments, since the grinding process can flatten the top surface of the entire package, the upper portion of the conductive block 630 or the upper portion of the conductive block 630 may be removed at the same time to ensure that the top surface of the conductive block 630 and the top surface of the electronic component 623 are substantially flush or coplanar with each other.

[0056] I understand. Figure 6C and 6D The operations shown in the figure are merely examples, and the present application is not limited thereto. In some other embodiments, the sealant can be formed using a film-assisted molding (FAM) process. The FAM process allows the sealed package to be easily released from the mold groove because the molding material contacts the auxiliary film rather than the mold groove. In addition, the FAM process can directly form the sealant that exposes the top surface of the conductive pillar 632 of the conductive block 630 and the top surface of the electronic component 623, and does not require grinding the sealant.

[0057] refer to Figure 6F , an electromagnetic interference (EMI) shield 652 is formed on the top surface of the encapsulant 640. The EMI shield 652 is electrically coupled to the conductive posts 632 of the conductive block 630 and thermally coupled to the electronic components 623. In some embodiments, the EMI shield 652 can be formed of copper, aluminum, iron, or any other suitable material for EMI shielding. In some embodiments, the EMI shield 652 can be formed by sputtering, spraying, plating, or any other suitable metal deposition process.

[0058] refer to Figure 6GA thermal interface material (TIM) layer 656 is formed on the EMI shield 652. In some embodiments, the TIM layer 656 may include solder, indium, silver, an indium / silver alloy, or other suitable materials. In some embodiments, the TIM layer 656 may be formed by spraying, plating, sputtering, or any other suitable metal deposition process.

[0059] In some embodiments, when the package substrate 610 includes a plurality of predefined substrate units arranged in a strip manner, a single-unit cutting process may be performed to cut individual packages from the package strip along single-unit cutting channels after forming the TIM layer 656. For example, a saw blade may be used to cut the package strip into the individual packages.

[0060] refer to Figure 6H , the heat sink 654 is attached to the TIM layer 656. Therefore, the heat sink 654 is thermally coupled to the electronic component 623 through the TIM layer 656.

[0061] In some embodiments, the heat sink 654 can include a metal cap made of copper, aluminum, nickel-plated copper, nickel-plated aluminum, or other materials with high thermal conductivity. In some embodiments, the TIM layer 656 can be reflowed to solder the heat sink 654 and TIM layer 656 together and to solder the EMI shield 652 and TIM layer 656 together. Specifically, the TIM layer 656 can be heated above its melting point so that the TIM layer 656 and the heat sink 654 / EMI shield 652 can react and form an intermetallic compound (IMC). The IMC can enhance the adhesion between the TIM layer 656 and the heat sink 654 / EMI shield 652. Therefore, the heat sink 654 can be attached to the TIM layer 656 and thermally coupled to the electronic component 623 through the TIM layer 656 and the EMI shield 652 to dissipate heat generated by the electronic component 623 and other electronic components. However, the present invention is not limited to the above example. In some other embodiments, the heat spreader 654 may be formed on the TIM layer 656 by a deposition process, and the thickness of the heat spreader 654 may be accurately controlled by the deposition process.

[0062] In some embodiments, solder material may be printed or deposited onto the contact pads exposed from the bottom surface of the package substrate 610, and then the solder material may be reflowed by heating the material above its melting point to form the conductive bumps 660. In some other embodiments, the conductive bumps 660 may be compression bonded or thermocompression bonded to the contact pads exposed from the bottom surface of the package substrate 610. Figure 6H In the example shown in FIG, the conductive bump 660 is illustrated as a solder bump, but the scope of the present application is not limited thereto. In some other embodiments, the conductive bump 660 may include a conductive column, a copper ball, a microbump, etc.

[0063] In some embodiments, the singulation process is not performed immediately after forming the TIM layer 656, but is performed after attaching or depositing the heat spreader strip on the EMI shield 652. The heat spreader strip can be singulated together with the package substrate 610 to form individual semiconductor devices, thereby increasing productivity.

[0064] In reference Figures 6A to 6H In the above method, a heat dissipation cover 650 including an EMI shield 652, a TIM layer 656, and a heat sink 654 is connected to a preformed conductive block 630 to form a closed structure, and electronic components 621, 622, 623, and 624 are housed within the closed structure. The closed structure not only serves as an EMI shield for the electronic components 621, 622, 623, and 624, but also dissipates heat generated by the electronic components 621, 622, 623, and 624. Because the preformed conductive block 630 is generally less expensive than a conventional metal bar and can be easily attached to the package substrate 610 using surface mounting technology, the cost of forming a semiconductor device can be reduced.

[0065] refer to Figures 7A to 7H , according to another embodiment of the present application, various steps of a method for forming a semiconductor device are shown. The method can also be used to form Figure 1 The semiconductor device 100 shown in FIG. is different from the reference Figures 6A to 6H An embodiment is described in which an integrated conductive block is used and partitioned to form individual conductive blocks in different semiconductor devices.

[0066] refer to Figure 7A , providing a package substrate 710. The package substrate 710 may include a plurality of predefined substrate units arranged in a strip manner. The plurality of substrate units may be isolated from each other by individual cutting lanes 712. The individual cutting lanes may provide cutting areas for individually cutting the package substrate 710 into individual semiconductor devices.

[0067] Then, refer to Figure 7B , electronic components 721 and 722 (e.g., discrete devices) and at least one integrated conductive block 730 are mounted on the top surface of the package substrate 710. The integrated conductive block 730 is pre-formed and includes an insulating base 734 and at least two conductive pillars 732 extending through the insulating base 734. The integrated conductive block 730 can extend across the individual cutting channel 712, and the at least two conductive pillars 732 can be located on different sides of the individual cutting channel 712. Therefore, after the integrated conductive block 730 and the package substrate 710 are singulated, the conductive pillars 732 on different sides of the individual cutting channel 712 can form respective conductive blocks in different semiconductor devices.

[0068] Then, refer to Figure 7C , electronic components 723 and 724 (eg, semiconductor chips) are mounted on the top surface of the package substrate 710 .

[0069] Then, refer to Figure 7D , a sealant 740 is formed on the top surface of the package substrate 710 to seal the integrated conductive blocks 730 and the electronic components 721 , 722 , 723 and 724 .

[0070] Then, refer to Figure 7E , the sealant 740 is ground to expose the top surface of the conductive pillar 732 of the integrated conductive block 730 and the top surface of the electronic component 723 .

[0071] Then, refer to Figure 7F An electromagnetic interference (EMI) shield 752 is formed on the top surface of the encapsulant 740. The EMI shield 752 is electrically coupled to the conductive posts 732 of the integrated conductive block 730 and thermally coupled to the electronic components 723.

[0072] Then, refer to Figure 7G , the integrated conductive block 730 and the package substrate 710 can be cut into individual pieces via the individual cutting channels 712 using a saw blade 770. For example, Figure 7G As shown in FIG, the integrated conductive block 730 can be singulated into individual conductive blocks 730-1, 730-2, and 730-3 that can be used for various semiconductor devices. In some other embodiments, the integrated conductive block 730 and the package substrate 710 can be singulated using a laser cutting tool.

[0073] Then, refer to Figure 7H , a thermal interface material (TIM) layer 756 is formed on the EMI shield 752, and a heat sink 754 is attached to the TIM layer 756. Thus, the heat dissipation top cover 750 including the EMI shield 752, the TIM layer 756, and the heat sink 754 is connected to the conductive block 730-1 to form a closed structure, and the electronic components 721, 722, 723, and 724 are accommodated in the closed structure. In addition, as Figure 7H As shown in FIG, a plurality of conductive bumps 760 are formed on the bottom surface of the package substrate 710. The conductive bumps 760 can be used to electrically connect the semiconductor device to an external device or substrate.

[0074] refer to Figures 8A to 8D , according to another embodiment of the present application, various steps of a method for forming a semiconductor device are shown. The method can also be used to form Figure 4 The semiconductor device 400 is shown in FIG.

[0075] refer to Figure 8A, providing a semiconductor package 801. The semiconductor package 801 may include: a package substrate 810; at least one pre-formed conductive block 830 and a plurality of electronic components 821, 822, 823, and 824 mounted on the top surface of the package substrate 810; and a sealant 840 formed on the top surface of the package substrate 810. The pre-formed conductive block 830 may include an insulating base 834 and at least one conductive pillar 832 extending through the insulating base 834. The sealant 840 may expose the top surface of the conductive pillar 832 of the conductive block 830 and the top surface of the electronic component 823. For example, the package 801 may be made of a reference Figures 6A to 6E The method described is formed and will not be described in detail here.

[0076] Then, refer to Figure 8B An interconnect layer 858 is formed on the top surface of the conductive pillars 832 of the conductive block 830, and a thermal interface material (TIM) layer 856 is formed on the top surface of the electronic component 823. In some embodiments, the TIM layer 856 may include a material having a melting point close to room temperature, such as gallium, a gallium-indium alloy, a gallium-indium-tin alloy, etc. The interconnect layer 858 may surround the liquid TIM layer 851 and prevent it from leaking to the outside. In some embodiments, the TIM layer 856 may include solder, silver, an indium / silver alloy, or other suitable materials. The TIM layer 856 may be formed by spraying, plating, sputtering, or any other suitable metal deposition process. In some embodiments, the interconnect layer 858 may be made of a conductive material such as solder, conductive ink, conductive epoxy, or other suitable material, and may be formed by spraying, plating, sputtering, or any other suitable metal deposition process.

[0077] Then, refer to Figure 8C , a heat sink 854 can be attached to the interconnect layer 858 and the TIM layer 856. In some embodiments, the interconnect layer 858 and the TIM layer 856 can be reflowed to solder the heat sink 854 thereon. Thus, the heat sink 854 is electrically coupled to the conductive posts of the conductive block 830 through the interconnect layer 858 and thermally coupled to the electronic component 823 through the TIM layer 856.

[0078] Then, refer to Figure 8D , a plurality of conductive bumps 860 are formed on the bottom surface of the package substrate 810. The conductive bumps 860 can be used to electrically connect the semiconductor device to an external device or substrate.

[0079] Although combined Figures 6A to 6H 、 Figures 7A to 7H and Figures 8A to 8DDifferent processes for forming semiconductor devices are shown, but those skilled in the art will appreciate that modifications and adjustments can be made to the processes without departing from the scope of the present invention. For example, when preformed conductive blocks are formed between different electronic components of a semiconductor device, Figure 2 The semiconductor device 200 shown in FIG. Figure 5 The semiconductor device 500 shown in FIG. 5 can be respectively referred to as Figures 6A to 6H Similar processes described and references Figures 8A to 8D Furthermore, when the EMI shield is formed on the side surfaces of the package substrate and the sealant, Figure 3 The semiconductor device 300 shown in FIG. Figures 6A to 6H The similar process described is formed.

[0080] The discussion herein includes a number of illustrative figures that illustrate various portions of semiconductor devices and methods for fabricating semiconductor devices. For clarity, such figures do not illustrate all aspects of each example device. Any example device and / or method provided herein may share any or all features with any or all other devices and / or methods provided herein.

[0081] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and variations may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art by consideration of the specification and practice of one or more embodiments of the invention disclosed herein. Therefore, it is intended that the present application and the examples herein be considered merely exemplary, with the true scope and spirit of the invention being indicated by the list of the appended exemplary claims.

Claims

1. A method for forming a semiconductor device, characterized in that The method comprises: providing a packaging substrate; mounting at least one preformed conductive block and at least one electronic component on a top surface of the package substrate, wherein the preformed conductive block comprises an insulating base and at least one conductive post extending through the insulating base; forming a sealant on a top surface of the package substrate, wherein the sealant exposes top surfaces of the conductive pillars of the conductive blocks and a top surface of the electronic component; and A heat sink cap is formed on the encapsulant to electrically couple the heat sink cap to the conductive posts of the conductive block and thermally couple the heat sink cap to the electronic component.

2. The method according to claim 1, characterized in that Forming the sealant on the top surface of the package substrate includes: forming the sealant on a top surface of the package substrate to seal the conductive block and the electronic component; and The encapsulant is ground to expose top surfaces of the conductive posts of the conductive blocks and a top surface of the electronic component.

3. The method according to claim 1, characterized in that Forming the heat dissipation top cover on the sealant includes: forming an electromagnetic interference (EMI) shield on the encapsulant to be electrically coupled to the conductive posts of the conductive block and thermally coupled to the electronic component; and A heat sink is attached to the EMI shield to thermally couple to the EMI shield.

4. The method according to claim 3, characterized in that The method further comprises: Before attaching the heat sink to the EMI shield, a thermal interface material (TIM) layer is formed on the EMI shield.

5. The method according to claim 3, characterized in that The EMI shield covers side surfaces of the package substrate and side surfaces of the encapsulant.

6. The method according to claim 1, wherein Forming the heat dissipation top cover on the sealant includes: forming an interconnect layer on top surfaces of the conductive pillars of the conductive block; forming a thermal interface material (TIM) layer on a top surface of the electronic component; and A heat sink is attached to the interconnect layer and the TIM layer such that the heat sink is electrically coupled to the conductive pillars through the interconnect layer and thermally coupled to the electronic component through the TIM layer.

7. The method according to claim 1, characterized in that A top surface of the electronic component is substantially flush with a top surface of the conductive block.

8. The method according to claim 1, characterized in that The conductive block includes an electrical function column module.

9. The method according to claim 1, characterized in that The conductive block includes a molded interconnect substrate.

10. A method for forming a semiconductor device, characterized in that: The method comprises: providing a packaging substrate; mounting at least one preformed conductive bump and at least one electronic component on a top surface of the package substrate; forming a sealant on a top surface of the package substrate, wherein the sealant exposes a top surface of the conductive block; and A heat dissipation cover is formed on the sealant to connect with the conductive block, so that the conductive block and the heat dissipation cover form a closed structure to accommodate the electronic component.

11. The method according to claim 10, characterized in that The conductive block includes an electrical function column module.

12. The method according to claim 10, characterized in that The conductive block includes a molded interconnect substrate.

13. A semiconductor device, characterized in that: The semiconductor device comprises: packaging substrate; at least one preformed conductive block and at least one electronic component mounted on a top surface of the package substrate, wherein the preformed conductive block comprises an insulating base and at least one conductive post extending through the insulating base; a sealant formed on a top surface of the package substrate, wherein the sealant exposes top surfaces of the conductive pillars of the conductive blocks and a top surface of the electronic component; and A heat sink cap is formed on the encapsulant, wherein the heat sink cap is electrically coupled to the conductive posts of the conductive block and thermally coupled to the electronic component.

14. The semiconductor device according to claim 13, wherein: The heat dissipation top cover comprises: an electromagnetic interference (EMI) shield formed on the encapsulant, wherein the EMI shield is electrically coupled to the conductive posts of the conductive block and thermally coupled to the electronic component; and A heat sink is attached to the EMI shield, wherein the heat sink is thermally coupled to the EMI shield.

15. The semiconductor device according to claim 14, wherein: The heat dissipation top cover further comprises: A thermal interface material (TIM) layer is formed between the EMI shield and the heat sink.

16. The semiconductor device according to claim 14, wherein: The EMI shield covers side surfaces of the package substrate and side surfaces of the encapsulant.

17. The semiconductor device according to claim 13, wherein: The heat dissipation top cover comprises: an interconnect layer formed on top surfaces of the conductive pillars of the conductive block; a thermal interface material (TIM) layer formed on a top surface of the electronic component; and A heat sink is attached to the interconnect layer and the TIM layer, wherein the heat sink is electrically coupled to the conductive pillars through the interconnect layer and thermally coupled to the electronic component through the TIM layer.

18. The semiconductor device according to claim 13, wherein A top surface of the electronic component is substantially flush with a top surface of the conductive block.

19. The semiconductor device according to claim 13, wherein The conductive block includes an electrical function column module.

20. The semiconductor device according to claim 13, wherein The conductive block includes a molded interconnect substrate.

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