Zero-pressure low-temperature Cu-Cu bonding method based on atomic layer deposition technology

Abstract

The invention discloses a pressure-free low-temperature Cu-Cu bonding method based on an atomic layer deposition technology, and belongs to the technical field of three-dimensional electronic packaging. The method comprises the following steps: providing two core particles as a to-be-bonded substrate, preparing a patterned photoresist on a bonding surface, etching a Cu seed layer, a Ti adhesion layer and a SiO2 dielectric layer, and forming a groove in a to-be-bonded surface of the first core particle; and etching the Cu seed layer and the Ti adhesion layer, and depositing a SiO2 support column on the to-be-bonded surface of the second core grain. And removing the photoresist, preparing the high (111) orientation nano twin crystal Cu layer through direct current electroplating, combining the core particles through the grooves and the SiO2 support columns, and depositing an interconnection layer to realize Cu-Cu bonding. The nano twin crystal Cu layer has the advantages of high mechanical strength, electromigration resistance and the like, the interconnection layer is deposited in a high-vacuum cavity, external mechanical force is not needed, the interconnection layer is not prone to oxidation and has no bonding interface, and the requirements for flatness and cleanliness of a deposition substrate are low. Mechanical chemical polishing is not needed before deposition, annealing is not needed after deposition to eliminate a bonding interface, and the bonding process is simplified.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional electronic packaging, and in particular to a pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology. Background Art

[0002] With the continued slowdown of Moore's Law and the rapid development of artificial intelligence and communications technologies, three-dimensional electronic packaging faces significant challenges. Chip-level three-dimensional integration, by vertically stacking chips, shortens signal transmission distances, reduces transmission latency and power consumption, and increases bandwidth density, potentially extending the growth of Moore's Law. However, when using lead-free tin-based solders for flip-chip bonding or micro-bump bonding with interconnect pitches below 40 µm, short circuits due to melting of the bumps or the formation of intermetallic compounds with low electromigration and thermomigration resistance can significantly degrade the thermomechanical stability and electrical transmission performance of the bonded structure.

[0003] Cu-Cu bonding is a next-generation interconnect technology that eliminates the use of traditional solders such as tin-based alloys, resulting in a solderless structure. This prevents the formation of intermetallic compounds at the bonding interface, which can lead to brittle failure and Kirkendall voids. Cu-Cu bonding offers low resistivity, high thermal conductivity, and strong resistance to electromigration. In 2019, Sony Corporation used this technology to bond InGaAs cores to InP wafers.

[0004] Cu-Cu bonding is typically performed using a hot pressing process at temperatures ≥300°C and ≥20 MPa. High bonding temperatures significantly accelerate the oxidation of the Cu bonding surface and cause thermal damage to the chip. The mismatch in thermal expansion coefficients between the substrate, dielectric layer, and Cu bonding surface generates significant thermal stress, which, combined with high bonding pressure, leads to mechanical damage to the chip, severely restricting and reducing chip performance and service life. Self-assembled monolayer bonding, surface-activated bonding, and the preparation of various passivation layers on the Cu bonding surface are currently commonly used to reduce bonding temperature and pressure, as well as to prevent oxidation of the Cu bonding surface. Most of these methods rely on thermomechanical processes and have the disadvantages of requiring high flatness and cleanliness of the bonding surface, as well as significantly increasing the manufacturing process and cost.

[0005] The Chinese invention patent with publication number CN114899115A discloses a method and application of metal hot-compression bonding, which realizes metal hot-compression bonding in an air environment through the coordinated control of temperature and pressure. In the heating and high-pressure stage of this bonding method, the bonding temperature and pressure reach 200~400℃ and 20~35MPa respectively, and the bonding temperature reaches 200~400℃ in the low-pressure stage of heat preservation. The higher bonding temperature and pressure may cause damage such as cracking and warping of the bonded chip. In addition, this method requires mechanical polishing or chemical mechanical polishing of the wafer before hot-compression bonding. After polishing, the wafer needs to be cut into chips before bonding. The preparation process is complex, the cost is high, and it is difficult to bond multiple chips of different sizes at the same time.

[0006] The Chinese invention patent with publication number CN118248573A provides a Cu-Cu low-temperature bonding method, which introduces a layer of energetic compound that can decompose and release heat during bonding on the Cu bonding surface, and promotes the diffusion of Cu atoms through local thermal effects to promote bonding. The energetic compound releases N2 when decomposing, which may affect the uniformity of the Cu bonding surface and form bubbles at the bonding interface, resulting in a decrease in bonding quality and electrical signal transmission capability. The decomposition rate and temperature of the energetic compound cannot be precisely controlled, which may cause the temperature of the Cu bonding surface to be too high at a certain time during bonding, causing thermal damage to the chip as the bonding substrate. In addition, it is difficult to establish a clear relationship between the thickness of the energetic compound and the temperature distribution of the Cu bonding surface during bonding, as well as the bonding strength after bonding.

[0007] In summary, there is an urgent need to develop a new Cu-Cu bonding method that can prevent oxidation of the Cu bonding surface while ensuring low temperature and low pressure bonding, thereby reducing bonding costs and simplifying the process. Summary of the Invention

[0008] In view of the above-mentioned defects of the prior art, in a first aspect of the present invention, a pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology is provided, comprising the following steps: (1) Providing two core particles, including a first core particle as an upper mold to be bonded and a second core particle as a lower mold to be bonded; (2) forming a SiO2 dielectric layer, a Ti adhesion layer, and a Cu seed layer on the bonding surfaces of the two core particles in sequence; (3) Spin-coat photoresist on the bonding surfaces of the two core particles, expose through a mask, develop to form a groove pattern, and etch the Cu seed layer and Ti adhesion layer in the groove from the outside to the inside; (4) etching the SiO2 dielectric layer of the first core particle to prepare a groove, and depositing a patterned SiO2 support column on the surface of the SiO2 dielectric layer of the second core particle; (5) peeling off the photoresist on the bonding surfaces of the two core particles, and preparing a high (111) oriented nano-twinned Cu layer on the bonding surfaces of the two core particles by electroplating; (6) The first core particle and the second core particle are combined through the groove and the SiO2 support column, and the combination is deposited by atomic layer deposition to form an interconnection layer that fills the gap between the first core particle and the second core particle, thereby achieving pressure-free low-temperature Cu-Cu bonding.

[0009] Preferably, in step (2), the thickness of the SiO2 dielectric layer of the two core particles is 1-20 μm; the thickness of the Ti adhesion layer is 20-200 nm; and the thickness of the Cu seed layer is 50-500 nm.

[0010] Preferably, in step (2), the SiO2 dielectric layer is made of SiH4 and N2O as raw materials, using plasma enhanced chemical vapor deposition technology at an ambient temperature and pressure of 250-350°C and 50-300 Pa.

[0011] Preferably, in step (2), the Ti adhesion layer is made by magnetron sputtering technology, the sputtering target is a Ti target, the sputtering power is 200-400 W, the Ar gas flow rate is 20-30 sccm, and the substrate temperature is 100-200 °C.

[0012] Preferably, in step (2), the Cu seed layer is prepared by magnetron sputtering technology, the sputtering target is a Cu target, the sputtering power is 150-250 W, the Ar gas flow rate is 25-45 sccm, and the substrate temperature is 100-200 °C.

[0013] Preferably, in step (3), the Cu seed layer is removed by etching with a nitric acid-based solution or a FeCl3 solution; the Ti adhesion layer is removed by etching with a mixed gas of Cl2 and BCl3 with flow rates of 20-40 sccm and 10-20 sccm, respectively, with a radio frequency power of 200-400 W and a bias voltage of 50-150 V.

[0014] Preferably, in step (4), the SiO2 dielectric layer of the first core particle is removed by etching with a mixed gas of CF4 and CHF3 with a volume ratio of 1:1-3 and a total flow rate of 50-200 sccm; during etching, the RF power is 100-300 W, the chamber pressure is 20-80 mTorr, and the substrate temperature is 40-90 °C; the depth of the groove etched in the SiO2 dielectric layer is 1-10 µm.

[0015] Preferably, in step (4), the patterned SiO2 support columns on the surface of the SiO2 dielectric layer of the second core particle are made of SiH4 and N2O as raw materials, using plasma enhanced chemical vapor deposition technology at an ambient temperature and pressure of 250~350°C and 50~300 Pa; the shape of the SiO2 support columns matches the grooves in the SiO2 dielectric layer of the first core particle, and the height is 2~20 μm.

[0016] Preferably, in step (6), the material for preparing the interconnection layer that fills the gap between the first core particle and the second core particle in the assembly to complete the Cu-Cu bonding includes any one of Mo, Ru, Pt, Co, and Cu.

[0017] Preferably, in step (6), the specific steps of depositing the interconnection layer are as follows: S1, aligning a first core particle having a groove and a second core particle having a SiO2 support column, respectively, in a bonding machine, and mechanically interlocking the groove and the SiO2 support column to form an assembly; S2. Moving the assembly to an atomic layer deposition chamber, sequentially introducing a first precursor for providing metal atoms into the chamber with the assistance of a carrier gas, purging the chamber with an inert carrier gas, introducing a second precursor for performing a reducing effect into the chamber with the assistance of a carrier gas, and purging the chamber with an inert carrier gas; S3. Repeat step S2 to deposit the interconnect layer until the gap between the first core particle and the second core particle in the assembly is completely filled, thereby achieving pressure-free low-temperature Cu-Cu bonding.

[0018] More preferably, in step S2, the deposition temperature is 100-200°C.

[0019] The bonding method of the present invention has broad applicability. The two core particles can be of any shape, such as square, circular, diamond, or trapezoidal. They can be made of commonly used materials in the field, such as Si wafers, Sapphire wafers, GaN wafers, InP wafers, Ga2O3 wafers, GaAs wafers, and SiC wafers. Furthermore, the grooves etched in the SiO2 dielectric layer can be of any shape, such as square, circular, diamond, or trapezoidal. The shape of the SiO2 support pillars can match these shapes.

[0020] In a second aspect of the present invention, an application of the pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology of the first aspect of the present invention is provided, including the preparation of high-bandwidth memories in the field of three-dimensional integrated circuits, chiplet heterogeneous integration and through-silicon via interconnection, and the preparation of inertial sensors and pressure sensors in the field of micro-electromechanical systems.

[0021] Based on the above technical solutions, the design concept and principle of the present invention are as follows: The present invention prepares a high (111) oriented nano-twinned Cu layer by electroplating on the surface of two core particles, combines the core particles through grooves and SiO2 support columns, and uses atomic layer deposition technology to deposit an interconnection layer on the Cu layer substrate to fill the gap between the core particle assembly to achieve Cu-Cu bonding. High (111) oriented nano-twinned Cu has excellent electrical properties, mechanical properties, oxidation resistance and electromigration resistance. Atomic layer deposition technology can achieve submicron-level gap filling, and the deposition substrate does not need to have high flatness and cleanliness. In addition, the interconnection layer is deposited in a high vacuum deposition chamber at a low temperature and without involving external mechanical forces, which can effectively avoid oxidation of the interconnection layer and warping or cracking of the core particles due to large thermal stress and external pressure. The interconnection layer has no bonding interface, and there is no need for subsequent high-temperature annealing to promote atomic diffusion and grain growth to eliminate the bonding interface. The bonding process is simplified and production efficiency is improved.

[0022] Compared with the prior art, the present invention has the following advantages and beneficial effects: The present invention provides a pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology, which combines the advantages of high (111) oriented nano-twinned Cu with atomic layer deposition technology. The prepared bonding layer uses a high (111) oriented nano-twinned Cu layer with excellent electrical properties, mechanical properties, oxidation resistance and electromigration resistance as a substrate, and interconnects the substrates with an interconnection layer without a bonding interface. The formed bonding structure does not need to be subsequently annealed at a high temperature to eliminate the bonding interface; the interconnection layer is deposited in a high vacuum atomic deposition chamber, without the need for external mechanical force, the deposition temperature is low, the thermal stress is small, and oxidation of the interconnection layer and damage problems such as warping or cracking of the core particles are effectively prevented; when depositing the interconnection layer, the substrate does not need to have high flatness and cleanliness, and there is no need to perform chemical mechanical polishing on the substrate before deposition. The bonding process is simplified, which is conducive to improving production efficiency; in addition, the atomic layer deposition technology has a strong gap filling ability and can simultaneously deposit interconnection layers with multiple spacings and multiple areas on multiple assemblies, which is beneficial to the manufacture of ultra-large-scale three-dimensional integrated circuits.

[0023] The present invention provides an application of a pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology, which has good application prospects in the preparation of three-dimensional integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the process of the pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology provided in this application; Figure 2 A schematic cross-sectional view of the core particles to be bonded after a SiO2 dielectric layer, a Ti adhesion layer, and a Cu seed layer are sequentially formed on the bonding surfaces of the two core particles provided in the present application; Figure 3A schematic cross-sectional view of the core particles to be bonded after spin coating photoresist on the surfaces to be bonded of two core particles provided in the present application, exposing through a mask, developing to form a groove pattern, and etching the Cu seed layer and Ti adhesion layer in the groove from the outside to the inside; Figure 4 Schematic cross-sectional view of the core particles to be bonded after etching the SiO2 dielectric layer of the first core particle used as the upper bonding mold to form grooves and depositing patterned SiO2 support pillars on the surface of the SiO2 dielectric layer of the second core particle used as the lower bonding mold provided in the present application; Figure A shows the first core particle, and Figure B shows the second core particle; Figure 5 A schematic cross-sectional view of the core particles to be bonded after the photoresist on the bonding surfaces of the two core particles is stripped off and a high (111) oriented nano-twinned Cu layer is prepared on the bonding surfaces of the two core particles by electroplating; Figure A is the first core particle, and Figure B is the second core particle; Figure 6 A schematic cross-sectional view of the bonding structure after pressure-free low-temperature Cu-Cu bonding is achieved by mechanically interlocking the grooves and SiO2 support pillars to combine the first core particle and the second core particle, and preparing the interconnection layer filling the gap between the combination through atomic layer deposition technology; Figure 7 The electron backscatter diffraction pattern of the surface of the high (111) oriented nano-twinned Cu layer prepared on the bonding surface of the first core particle provided in this application; Figure A is a fringe contrast image, and Figure B is a fringe contrast + Z-direction reverse polarity emitter image corresponding to Figure A; Figure 8 The present application provides a cross-sectional view of the bonding structure after placing the assembly into an atomic layer deposition chamber to deposit an interconnection layer to fill the gap between the first core particle and the second core particle; Figure A is a scanning electron microscope image, and Figure B is the fringe contrast + Z-direction reverse polarity emitter image corresponding to Figure A.

[0025] In the above figure: A1 represents the first core particle; A2 represents the SiO2 dielectric layer of the first core particle; A3 represents the second core particle; A4 represents the SiO2 dielectric layer of the second core particle; A5 represents the Ti adhesion layer prepared on the bonding surfaces of the two core particles; A6 represents the Cu seed layer prepared on the bonding surfaces of the two core particles; A7 represents the photoresist processed by spin coating, exposure and development on the bonding surfaces of the two core particles; A8 represents the groove prepared in the SiO2 dielectric layer of the first core particle; A9 represents the patterned SiO2 support column prepared on the surface of the SiO2 dielectric layer of the second core particle; A10 represents the high (111) oriented nano-twinned Cu layer prepared by electroplating on the bonding surfaces of the two core particles; A11 represents the interconnection layer prepared by atomic layer deposition technology to fill the gap between the first core particle and the second core particle to achieve bonding. DETAILED DESCRIPTION

[0026] The present invention is further illustrated by way of examples below, but the present invention is not limited to the scope of the examples. Experimental methods in the following examples where specific conditions are not specified were performed according to conventional methods and conditions, or selected according to the product specifications.

[0027] This embodiment provides a low-temperature, pressure-free Cu-Cu bonding method based on atomic layer deposition technology, which will be described below in conjunction with the corresponding drawings. In the embodiments described below, the same or corresponding contents can be referenced to each other.

[0028] Example 1 Pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology, such as Figure 1 As shown, the steps are as follows: (1) Providing two core particles, including a first core particle as an upper mold to be bonded and a second core particle as a lower mold to be bonded; (2) forming a SiO2 dielectric layer, a Ti adhesion layer, and a Cu seed layer on the bonding surfaces of the two core particles in sequence; (3) Spin-coat photoresist on the bonding surfaces of the two core particles, expose through a mask, develop to form a groove pattern, and etch the Cu seed layer and Ti adhesion layer in the groove from the outside to the inside; (4) etching the SiO2 dielectric layer of the first core particle to prepare a groove, and depositing a patterned SiO2 support column on the surface of the SiO2 dielectric layer of the second core particle; (5) peeling off the photoresist on the bonding surfaces of the two core particles, and preparing a high (111) oriented nano-twinned Cu layer on the bonding surfaces of the two core particles by electroplating; (6) The first core particle and the second core particle are combined through the groove and the SiO2 support column, and the combination is deposited by atomic layer deposition to form an interconnection layer that fills the gap between the first core particle and the second core particle, thereby achieving pressure-free low-temperature Cu-Cu bonding.

[0029] In the above embodiment, the two core particles have a thickness of 600 μm, a surface of a square with a side length of 3 mm, and are made of Si wafers.

[0030] Figure 2The figure shows a cross-section of the two cores to be bonded, after sequentially forming a SiO2 dielectric layer, a Ti adhesion layer, and a Cu seed layer on the bonding surfaces of the two cores. The SiO2 dielectric layer, 10 µm thick, was deposited using plasma-enhanced technology using SiH4 and N2O at an ambient temperature and pressure of 300°C and 200 Pa, under a radio frequency power of 300 W. The Ti adhesion layer and Cu seed layer, 50 nm thick and 200 nm thick, were deposited using magnetron sputtering. The sputtering targets were 99.995% pure Ti and Cu, respectively. The sputtering powers were 350 W and 200 W, respectively, with Ar gas flows of 25 sccm and 35 sccm, respectively, and the substrate temperature was 150°C. After sputtering, the two cores were annealed at 250 °C in N2 atmosphere for 30 min to relieve stress and strengthen the Ti / Cu interface, and then immersed in 5 wt.% C6H8O7 solution for 30 s to remove the surface oxide of the Cu seed layer.

[0031] Figure 3 Schematic diagram of the cross-section of the cores to be bonded after spin-coating photoresist on the surfaces to be bonded, exposing through a mask, and developing to form a groove pattern. The Cu seed layer and Ti adhesion layer within the grooves are then etched inwards. SXAR-PC5000 / 82 positive photoresist was used, with a spin-coated thickness of 2.5 µm. Before exposure, it was baked at 100°C for 45 seconds to remove solvents and enhance adhesion. This type of photoresist is relatively stable even at 400°C and exhibits excellent plasma etching resistance. Exposure was performed using an i-line with a wavelength of 365 nm. The groove pattern in the mask was circular, 20 µm in diameter, with a 200 µm pitch. Development was performed using a TMAH solution for 45 seconds. After development, the two cores were rinsed with ultrapure water and high-purity nitrogen and then dried. The two cores were placed in a 10 wt.% FeCl₃ solution to etch the Cu seed layer. The reaction was then terminated in ultrapure water, followed by rinsing with ultrapure water and high-purity N₂, and then drying. The Ti adhesion layer was removed using a mixture of Cl₂ and BCl₃ at flow rates of 30 sccm and 15 sccm, respectively. The RF power and bias voltage were 250 W and 100 V, respectively, and the chamber pressure and substrate temperature were 15 mTorr and 75°C, respectively. Cl₂ reacts with Ti to form volatile TiCl₄; BCl₃ reacts with oxides such as TiO₂ to produce volatile TiCl₄ and B₂O₃.

[0032] Figure 4Schematic cross-section of the cores to be bonded, after etching the SiO2 dielectric layer of the first core (the upper bonding mold) to create grooves and depositing patterned SiO2 support pillars on the surface of the SiO2 dielectric layer of the second core (the lower bonding mold). Figure A shows the first core, and Figure B shows the second core. The SiO2 dielectric layer of the first core was removed using a CF4 and CHF3 gas mixture with a volume ratio of 1:3 and a total flow rate of 100 sccm. The RF power, chamber pressure, and substrate temperature were 250 W, 50 mTorr, and 75°C, respectively. The grooves etched in the SiO2 dielectric layer of the first core had a pitch of 200 µm, corresponding to the groove pattern in the mask. The grooves had a circular surface with a diameter of 20 µm and a depth of 5 µm. The patterned SiO2 support pillars on the SiO2 dielectric layer of the second core were deposited using plasma-enhanced chemical vapor deposition. The raw materials are SiH4 and N2O, the ambient temperature and pressure are 300°C and 200 Pa, respectively, and the RF power is 300 W. The SiO2 support pillars are cylindrical, distributed to match the grooves etched in the SiO2 dielectric layer of the first core particle, with a spacing of 200 µm and a diameter and height of 20 µm and 15 µm, respectively.

[0033] Figure 5 The present application provides a schematic cross-sectional view of the core particles to be bonded after the photoresist on the bonding surfaces of the two core particles is stripped and a high (111) oriented nano-twinned Cu layer is prepared on the bonding surfaces of the two core particles by electroplating. Figure A shows the first core particle and Figure B shows the second core particle. The two core particles are placed in Dynasolve 210 high-performance photoresist stripping solution and soaked for 20 minutes, and the photoresist swelling is accelerated by ultrasound. The photoresist is stripped by spraying, and the two core particles are rinsed with isopropyl alcohol and deionized water in turn, and blown dry with N2. The electroplating method is direct current electroplating, and the electroplating solution consists of 0.9 mol / L CuSO4·5H2O, 60 ppm HCl, 60 ppm Gelatin, 10 ml / L H2SO4, 15 ppm SH110, 15 ppm methylene blue and ultrapure water. The electroplating temperature and current density are 25 °C and 30 mA / cm, respectively. 2 The electromagnetic stirring rate was 1000 rpm to eliminate the concentration polarization of the plating solution and provide shear force to promote the formation of nanotwins in the Cu layer grains.

[0034] Figure 6This application provides a schematic cross-sectional view of the bonded structure after pressureless, low-temperature Cu-Cu bonding, using a mechanical interlocking groove and SiO2 support pillar to combine a first core particle and a second core particle. The interconnect layer, which fills the gap between the two core particles, is prepared using atomic layer deposition (ALD). The first and second core particles are vacuum-fixed in a bonding machine. Laser calibration is used to align the groove in the SiO2 dielectric layer of the first core particle with the SiO2 support pillar on the surface of the SiO2 dielectric layer of the second core particle. The core particles are then controlled to insert the SiO2 support pillar into the groove, creating a mechanical interlock and forming a composite. The interconnect layer is deposited at 150°C using Co(DAD)2 as the first precursor to provide Co atoms and (CH3)3CNH2 as the second precursor to provide a reducing agent. The deposition process is as follows: a Co(DAD)2 pulse of 5 s, an N2 purge of 10 s, a (CH3)3CNH2 pulse of 0.3 s, and an N2 purge of 10 s. Each deposition grows a Co interconnect layer with a thickness of 1.2 Å.

[0035] Figure 7 The electron backscatter diffraction pattern of the surface of the highly (111) oriented nano-twinned Cu layer prepared on the bonding surface of the first core particle provided in this application. Figure A is a fringe contrast image, and Figure B is a fringe contrast + Z-direction reverse polarity emitter image corresponding to Figure A. It can be seen that the (111) oriented grain area of ​​the nano-twinned Cu layer accounts for 98.2%, and the average size of the twins in the grains is 192.3 nm.

[0036] Figure 8 The present application provides a cross-sectional view of the bonding structure after placing the assembly into an atomic layer deposition chamber to deposit an interconnection layer to fill the gap between the first core particle and the second core particle. Figure A is a scanning electron microscope image, and Figure B is a fringe contrast + Z-direction reverse polarity emitter image corresponding to Figure A. It can be seen that the nano-twinned Cu layer prepared by electroplating on the bonding surfaces of the two core particles has a high (111) orientation and columnar growth tendency. The gap filling rate of the assembly exceeds 90%, and interconnection bonding has been achieved.

[0037] Example 2 In this example, the shear strength of the Cu-Cu bonded core particles prepared using atomic layer deposition (ALD) in Example 1 of the present invention was tested at 25°C in air to investigate their performance in applications. The shear strength results are compared with those reported in the literature for Cu-Cu bonding using different processes, as shown in Table 1.

[0038] Table 1: Shear strength comparison

[0039] As can be seen from Table 1, the shear strength of the Cu-Cu bond prepared in the embodiment of the present invention is 72 MPa, which is 106% higher than the Cu-Cu bond prepared in Reference 3, which has the second highest shear strength.

[0040] In summary, the present invention provides two core particles as substrates to be bonded, and a patterned photoresist is prepared on the bonding surfaces of the two core particles, a Cu seed layer and a Ti adhesion layer are etched, the SiO2 dielectric layer of the first core particle is etched to form a groove, and a SiO2 support column matching the groove is prepared on the surface of the SiO2 dielectric layer of the second core particle. The photoresist is removed, and a high (111) oriented nano-twinned Cu layer is electroplated on the bonding surfaces of the two core particles. The core particles are combined by the groove and the SiO2 support column, and the interconnection layer is deposited to achieve Cu-Cu bonding. The present invention has the following advantages: 1. The interconnection layer deposition substrate does not require chemical mechanical polishing, does not require high flatness and cleanliness, and the bonding process is greatly simplified; 2. Bonding does not require external mechanical force and the interconnection layer deposition temperature is low, so the core particles are not prone to warping or cracking; 3. The interconnection layer is deposited in a high vacuum chamber without oxidation, and the deposition is not limited by the bonding surface spacing and area.

[0041] The above describes in detail the preferred embodiments of the present invention. It should be understood that those skilled in the art can make numerous modifications and variations based on the concepts of the present invention without inventive effort. Therefore, any technical solutions that can be obtained by those skilled in the art based on the concepts of the present invention through logical analysis, reasoning, or limited experimentation based on the existing technology should be within the scope of protection defined by the claims.

Claims

1. A pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology, characterized in that: The steps include: (1) Providing two core particles, including a first core particle as an upper mold to be bonded and a second core particle as a lower mold to be bonded; (2) forming a SiO2 dielectric layer, a Ti adhesion layer, and a Cu seed layer on the bonding surfaces of the two core particles in sequence; (3) Spin-coat photoresist on the bonding surfaces of the two core particles, expose through a mask, develop to form a groove pattern, and etch the Cu seed layer and Ti adhesion layer in the groove from the outside to the inside; (4) etching the SiO2 dielectric layer of the first core particle to prepare a groove, and depositing a patterned SiO2 support column on the surface of the SiO2 dielectric layer of the second core particle; (5) peeling off the photoresist on the bonding surfaces of the two core particles, and preparing a high (111) oriented nano-twinned Cu layer on the bonding surfaces of the two core particles by electroplating; (6) The first core particle and the second core particle are combined through the groove and the SiO2 support column, and the combination is deposited by atomic layer deposition to form an interconnection layer that fills the gap between the first core particle and the second core particle, thereby achieving pressure-free low-temperature Cu-Cu bonding.

2. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In step (2), the thickness of the SiO2 dielectric layer of the two core particles is 1-20 μm; the thickness of the Ti adhesion layer is 20-200 nm; and the thickness of the Cu seed layer is 50-500 nm.

3. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In the step (2), the SiO2 dielectric layer is made of SiH4 and N2O as raw materials, and is prepared by plasma enhanced chemical vapor deposition technology at an ambient temperature and pressure of 250~350°C and 50~300 Pa; the Ti adhesion layer is prepared by magnetron sputtering technology, the sputtering target is a Ti target, the sputtering power is 200~400 W, the Ar gas flow rate is 20~30 sccm, and the substrate temperature is 100~200°C; the Cu seed layer is prepared by magnetron sputtering technology, the sputtering target is a Cu target, the sputtering power is 150~250 W, the Ar gas flow rate is 25~45 sccm, and the substrate temperature is 100~200°C.

4. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In step (3), the Cu seed layers of the two core particles are etched away using a nitric acid-based solution or a FeCl3 solution; the Ti adhesion layer is etched away using a mixed gas of Cl2 and BCl3 with flow rates of 20-40 sccm and 10-20 sccm, respectively, with a radio frequency power of 200-400 W and a bias voltage of 50-150 V.

5. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In the step (4), the SiO2 dielectric layer of the first core particle is removed by etching with a mixed gas of CF4 and CHF3 with a volume ratio of 1:1 to 3 and a total flow rate of 50 to 200 sccm; during the etching, the RF power is 100 to 300 W, the chamber pressure is 20 to 80 mTorr, and the substrate temperature is 40 to 90 °C; the depth of the groove etched in the SiO2 dielectric layer is 1 to 10 µm.

6. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In the step (4), the patterned SiO2 support column on the surface of the SiO2 dielectric layer of the second core particle is made of SiH4 and N2O as raw materials, using plasma enhanced chemical vapor deposition technology at an ambient temperature and pressure of 250~350°C and 50~300 Pa; the shape of the SiO2 support column matches the groove in the SiO2 dielectric layer of the first core particle, and the height is 2~20 μm.

7. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In the step (6), the material for preparing the interconnection layer for filling the gap between the first core particle and the second core particle in the assembly to complete the Cu-Cu bonding includes any one of Mo, Ru, Pt, Co, and Cu.

8. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 1, characterized in that: In step (6), the specific steps of depositing the interconnection layer are as follows: S1, aligning a first core particle having a groove and a second core particle having a SiO2 support column, respectively, in a bonding machine, and mechanically interlocking the groove and the SiO2 support column to form an assembly; S2. Moving the assembly to an atomic layer deposition chamber, sequentially introducing a first precursor for providing metal atoms into the chamber with the assistance of a carrier gas, purging the chamber with an inert carrier gas, introducing a second precursor for performing a reducing effect into the chamber with the assistance of a carrier gas, and purging the chamber with an inert carrier gas; S3. Repeat step S2 to deposit the interconnect layer until the gap between the first core particle and the second core particle in the assembly is completely filled, thereby achieving pressure-free low-temperature Cu-Cu bonding.

9. The pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to claim 8, characterized in that: In step S2, the deposition temperature is 100-200°C.

10. An application of the pressure-free low-temperature Cu-Cu bonding method based on atomic layer deposition technology according to any one of claims 1 to 9, characterized in that: include: It is used for the preparation of high-bandwidth memory, chiplet heterogeneous integration and through-silicon via interconnection in the field of three-dimensional integrated circuits, as well as the preparation of inertial sensors and pressure sensors in the field of micro-electromechanical systems.

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