Three-dimensional integrated radio frequency microsystem and manufacturing method thereof

Abstract

The invention discloses a three-dimensional integrated radio frequency microsystem and a manufacturing method thereof, and the manufacturing method comprises the steps: leading out a back electrode of each back grounding chip to be coplanar with a front electrode of the back grounding chip, and forming a coplanar two-dimensional structure; the coplanar end surface in the coplanar two-dimensional structure is the front surface of the coplanar two-dimensional structure; performing wafer reconstruction and rewiring on the plurality of coplanar two-dimensional structures and the plurality of TSV arrays to form an I-FO structure; and connecting an expansion device required by the radio frequency microsystem to the I-FO structure to form the three-dimensional integrated radio frequency microsystem. According to the invention, back electrode signals of the back grounding chip can be led out to the front by forming the coplanar two-dimensional structure, better heat dissipation can be realized, and the problems that three-dimensional integration cannot be realized due to the bottom leading-out and heat dissipation problems of the existing radio frequency microsystem, the integration level of the radio frequency microsystem cannot be improved, and the like are solved.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency system integration, and in particular relates to a three-dimensional integrated radio frequency microsystem and a manufacturing method thereof. Background Art

[0002] RF microsystems are subsystems that implement some of the functions of RF systems. Traditional RF microsystems are primarily based on discrete components, printed circuit boards, cavity circuits, and related connectors, assembled using microassembly processes. This technology is mature and stable, with a wide range of applications. However, as a critical component of wireless communications, the size, weight, and performance of RF microsystems have a significant impact. With the increasing demand for integrated, miniaturized, and multifunctional wireless communication systems, traditional RF microsystems are no longer able to meet the demands of microsystem development. With the shrinking feature size of transistors, Moore's Law, the principle that has driven the information technology revolution since the 1960s, is coming to an end. As a key tool for surpassing Moore's Law, three-dimensional integration technology has been widely and intensively researched and applied. Currently, the continuous maturity of advanced three-dimensional integration processes, represented by wafer-level packaging (WLP), fan-out packaging, through-silicon vias (TSV), flip-chip technology, and micro-bumping, has made the use of three-dimensional integrated RF microsystems possible.

[0003] In existing technology, the packaging process for RF chips requiring backside grounding still uses traditional planar integration processes. The device active layer only exists within tens of microns of the chip surface. This causes the device area to increase with increasing current capacity, seriously affecting the integration of the power system. At the same time, signal delay time and the proportion of interconnect power consumption will also increase. If the heat dissipation problem of the RF chip can be solved while leading the chip back electrode to the front, and using IN-FO technology to complete the interconnection with other chips, and finally vertically lead the signal through TSV, it can be fully applicable to the integration requirements of this type of RF microsystem. Summary of the Invention

[0004] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a three-dimensional integrated radio frequency microsystem and a manufacturing method thereof.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A method for manufacturing a three-dimensional integrated radio frequency microsystem comprises the following steps:

[0007] S100, leading the back electrodes of each back-grounded chip to be coplanar with its front electrodes to form a coplanar two-dimensional structure; the coplanar end surfaces of the coplanar two-dimensional structure are its front surfaces;

[0008] S200, forming an IN-FO structure by wafer reconstruction and rewiring of multiple coplanar two-dimensional structures and multiple TSV arrays;

[0009] S300: Connect the expansion devices required for the RF microsystem to the IN-FO structure to form a three-dimensional integrated RF microsystem.

[0010] Furthermore, the back ground chip includes a low noise amplifier chip, a high power RF chip, a first attenuator chip and a second attenuator chip; the expansion devices required for the RF microsystem include a first filter, a second filter and auxiliary circuit separation elements of each back ground chip.

[0011] Furthermore, the step S100 includes the following sub-steps:

[0012] S110, taking a metal interconnect bridge having an accommodation space; the metal interconnect bridge having a front side and a back side opposite to each other, the accommodation space being located on the front side of the metal interconnect bridge;

[0013] S120, applying solder paste in the accommodation space, and placing a back grounding chip into the accommodation space of the metal interconnection bridge, so that the back electrode of the back grounding chip contacts the solder paste at the bottom of the accommodation space;

[0014] S130, welding and fixing the back electrode of the back grounding chip to the bottom of the accommodation space through high-temperature sintering, and making the end surface of the front electrode of the back grounding chip coplanar with the front surface of the metal interconnection bridge.

[0015] Furthermore, the metal interconnection bridge is an L-shaped structure with a notch at one end, and the notch forms an accommodating space.

[0016] Furthermore, in the step S120, after the back grounding chip is placed in the accommodation space, the end face of the front electrode of the back grounding chip is adjusted to be coplanar with the front face of the metal interconnection bridge, and then high-temperature tape is used to stick on the front electrode of the back grounding chip and the front face of the metal interconnection bridge; the high-temperature tape is removed after the high-temperature sintering of the step S130 is completed.

[0017] Furthermore, the step S200 includes the following sub-steps:

[0018] S210, reconstructing each coplanar two-dimensional structure and each TSV array on a wafer by a face-down process, so that each coplanar two-dimensional structure and each TSV array are embedded in the reconstructed wafer; the wafer has a chip side and an anti-chip side opposite to the chip side;

[0019] S220, forming back-side interconnection lines and back-side pads on the chip side of the wafer, forming front-side interconnection lines and front-side pads on the chip side of the wafer, and making first solder balls on the back-side pads on the chip side of the wafer to form an IN-FO structure.

[0020] Furthermore, the step S210 includes the following sub-steps:

[0021] S211, taking a first carrier board, fixing each coplanar two-dimensional structure and each TSV array on the first carrier board with the front side facing downward;

[0022] S212. Reconstruct the wafer on the first carrier so that each coplanar two-dimensional structure and each TSV array are embedded in the reconstructed wafer; the wafer facing the first carrier is the chip side, and the side opposite to the chip side is the chip opposite side; the front side of each coplanar two-dimensional structure and the front side of each TSV array are flush with the end face of the chip side of the wafer, and the back side of each TSV array is flush with the end face of the chip opposite side of the wafer.

[0023] Furthermore, the step S220 includes the following sub-steps:

[0024] S221, performing RDL rewiring on the opposite side of the chip of the wafer to form backside interconnect lines and backside pads;

[0025] S222, debonding the first carrier connected to the chip side of the wafer, connecting a second carrier to the side opposite to the chip of the wafer, and flipping the wafer over via the second carrier so that the chip side of the wafer faces upward;

[0026] S223, performing RDL rewiring on the chip side of the wafer to form front-side interconnect lines and front-side pads;

[0027] S224, debonding the second carrier connected to the chip-opposite side of the wafer, connecting a third carrier to the chip-opposite side of the wafer, and flipping the wafer over via the third carrier so that the chip-opposite side of the wafer faces upward;

[0028] S225, forming a first solder ball on the backside pad on the opposite side of the chip of the wafer by reflow to form an IN-FO structure;

[0029] S226 , debonding the third carrier board connected to the chip side of the wafer.

[0030] Furthermore, in the step S300, the expansion components required by the radio frequency microsystem are mounted on the front pads on the IN-FO structure chip side through a flip-chip process, and the passive components are soldered and fixed to the corresponding front pads through reflow.

[0031] A three-dimensional integrated radio frequency microsystem is manufactured using any of the above-mentioned methods for manufacturing a three-dimensional integrated radio frequency microsystem.

[0032] The present invention utilizes a metal interconnect bridge to lead the back electrode signal of the back-grounded chip to the front, quickly transferring heat generated within the back-grounded chip to the surface of the metal interconnect bridge. Furthermore, other heat dissipation structures can be appropriately stacked based on the amount of heat generated to form a low-thermal-resistance path, ensuring timely and effective heat dissipation, thereby improving the thermal stability of the three-dimensional integrated RF system. This solves the increasingly significant technical issues of existing RF microsystems, which are hindered by bottom-out lead generation and heat dissipation issues, hindering the ability to achieve three-dimensional integration, thereby increasing the integration level of RF microsystems, and reducing signal delay time and interconnect power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0034] Figure 1 This is a flow chart of an embodiment of a three-dimensional integrated radio frequency microsystem and a manufacturing method thereof according to the present invention.

[0035] Figure 2 Schematic diagram of the structure of the back-side grounded chip and metal interconnection bridge.

[0036] Figure 3 Schematic diagram of the coplanar two-dimensional structure.

[0037] Figure 4 Schematic diagram of the wafer structure after reconstruction.

[0038] Figure 5 Schematic diagram after connecting the second carrier and flipping the wafer.

[0039] Figure 6 Schematic diagram after connecting the third carrier and flipping the wafer again.

[0040] Figure 7 Schematic diagram of the structure of the RF microsystem.

[0041] Figure 8 This is the principle block diagram of the RF microsystem.

[0042] The accompanying drawings in this specification are numeraled as follows:

[0043] Wafer 100, chip side 110, chip opposite side 120, first solder ball 121, back ground chip 200, front electrode 210, back electrode 220, metal interconnect bridge 300, gap 310, TSV array 400, extension device 500, second solder ball 501, first carrier 910, second carrier 920, and third carrier 930. DETAILED DESCRIPTION

[0044] The following describes the implementation of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other unless there is any conflict.

[0045] See also Figure 1 , Figure 1 This is a flow chart of an embodiment of a three-dimensional integrated radio frequency microsystem and a method for manufacturing the same according to the present invention. The three-dimensional integrated radio frequency microsystem and the method for manufacturing the same according to this embodiment include the following steps:

[0046] S100: Lead the back electrodes 220 of each back grounded chip 200 to the same plane as its front electrodes 210 to form a coplanar two-dimensional structure; the coplanar end faces of the coplanar two-dimensional structure are the front faces. The method for forming a coplanar two-dimensional structure may include the following sub-steps:

[0047] S110, please refer to Figure 2 , a metal interconnect bridge 300 with a receiving space is taken, and the thickness of the metal interconnect bridge 300 can be selected according to the heat dissipation requirements of the back ground chip 200. The material of the metal interconnect bridge 300 can be copper, of course, other materials with good conductivity and heat dissipation can also be used. The metal interconnect bridge 300 has a front and a back side arranged opposite to each other, and the receiving space is located on the front side of the metal interconnect bridge 300. In this embodiment, the metal interconnect bridge 300 is an L-shaped structure with a notch 310 at one end, and the notch 310 forms the receiving space. Of course, since the sizes of the back ground chips 200 are not necessarily the same, the sizes of the metal interconnect bridges 300 and the sizes of their notches 310 used to connect the back ground chips 200 may also be different. The depth of the notch 310 is slightly larger than the thickness of the corresponding back ground chip 200 to leave space for applying solder paste.

[0048] S120, please refer to Figure 3 , solder paste is applied in the accommodation space, and the back ground chip 200 is placed in the accommodation space of the metal interconnection bridge 300, so that the back electrode 220 of the back ground chip 200 contacts the solder paste at the bottom of the accommodation space.

[0049] S130: The back electrode 220 of the back ground chip 200 is welded and fixed to the bottom of the accommodation space through high-temperature sintering, and the end surface of the front electrode 210 of the back ground chip 200 is made coplanar with the front surface of the metal interconnect bridge 300. Since the metal interconnect bridge 300 is connected to the back electrode 220 of the back ground chip 200, that is, the entire metal interconnect bridge 300 has become the back electrode 220 of the back ground chip 200; therefore, after forming a coplanar two-dimensional structure, the front electrode 210 and the back electrode 220 of the back ground chip 200 are in the same plane.

[0050] To ensure that the end surface of the front electrode 210 of the back ground chip 200 is coplanar with the front surface of the metal interconnect bridge 300, in this embodiment, in step S120, after the back ground chip 200 is placed into the accommodation space, the end surface of the front electrode 210 of the back ground chip 200 is adjusted to be coplanar with the front surface of the metal interconnect bridge 300. Then, high-temperature tape (not shown) is attached to the front electrode 210 of the back ground chip 200 and the front surface of the metal interconnect bridge 300 to temporarily secure the back ground chip 200 during the high-temperature sintering process. Because the high-temperature tape does not deform in a high-temperature environment, it can ensure that the end surface of the front electrode 210 of the back ground chip 200 and the front surface of the metal interconnect bridge 300 remain coplanar during the high-temperature sintering process. The high-temperature tape is removed after the high-temperature sintering in step S130 is completed.

[0051] In this embodiment, the back ground chip 200 includes a low noise amplifier chip, a high power RF chip, a first attenuator chip and a second attenuator chip. Each of the back ground chips 200 is respectively made with a metal interconnection bridge 300 to form a coplanar two-dimensional structure.

[0052] S200: Reconstruct and rewire multiple coplanar two-dimensional structures and multiple TSV arrays 400 through the wafer 100 to form an IN-FO structure. This step may include the following sub-steps:

[0053] S210, please refer to Figure 4 , each coplanar two-dimensional structure and each TSV array 400 are reconstructed on the wafer 100 through the Face-Down process, so that each coplanar two-dimensional structure and each TSV array 400 are embedded in the reconstructed wafer 100. It should be noted that, Figure 4 This is merely a schematic diagram. The one coplanar two-dimensional structure and four TSV arrays 400 shown are merely illustrative of the structures in the wafer 100 of the coplanar two-dimensional structure and TSV arrays 400 and do not limit the number of coplanar two-dimensional structures and TSV arrays 400. The wafer 100 has a chip side 110 and a chip-opposite side 120 opposite to the chip side 110. The face-down process may include the following sub-steps:

[0054] S211. Take a first carrier plate 910 and fix each coplanar two-dimensional structure and each TSV array 400 on the first carrier plate 910 with the front surface facing downward. The first carrier plate 910 can be used to temporarily position each coplanar two-dimensional structure and each TSV array 400 to facilitate the reconstruction of the wafer 100. If necessary, a heat dissipation structure, such as a heat sink or heat dissipation fins, can be provided on the back surface of the metal interconnect bridge 300 of the coplanar two-dimensional structure to enhance the heat dissipation effect of the metal interconnect bridge 300.

[0055] S212: Reconstruct the wafer 100 on the first carrier 910 so that each coplanar two-dimensional structure and each TSV array 400 are embedded in the reconstructed wafer 100. The wafer 100 can be formed of a resin material. The side of the wafer 100 facing the first carrier 910 is the chip side 110, and the side opposite to the chip side 110 is the chip-opposite side 120. The front surface of each coplanar two-dimensional structure and the front surface of each TSV array 400 are flush with the end surface of the chip side 110 of the wafer 100, and the back surface of each TSV array 400 is flush with the end surface of the chip-opposite side 120 of the wafer 100.

[0056] S220: Form backside interconnects and backside pads on the chip-opposite side 120 of the wafer 100, form frontside interconnects and frontside pads on the chip-opposite side 110 of the wafer 100, and fabricate first solder balls 121 on the backside pads on the chip-opposite side 120 of the wafer 100 to form an IN-FO structure. This step may include the following sub-steps:

[0057] S221: Perform RDL rewiring on the opposite side 120 of the wafer 100 to form backside interconnects and backside pads. The backside pads are preferably Sn bump pads, which are used to connect the microsystem to the outside. Backside wiring can be used to interconnect the backside pads and the backside of the TSV array 400 as needed.

[0058] S222, please refer to Figure 5 The first carrier 910 connected to the chip side 110 of the wafer 100 is debonded to expose the chip side 110 of the wafer 100. A second carrier 920 is then connected to the opposite chip side 120 of the wafer 100. The wafer 100 is flipped using the second carrier 920 so that the chip side 110 of the wafer 100 faces upward. Because the wafer 100 is very thin and difficult to flip, the second carrier 920 ensures the stability of the wafer 100 during the flipping process.

[0059] S223, RDL rewiring is performed on the chip side 110 of the wafer 100 to form front interconnect lines and front pads. The front pads are Sn bump pads for connecting the passive components required by the microsystem. Through the front interconnect lines, the front pads, the front and back electrodes 210 and 220 of the grounded chip 200 can be interconnected as needed, so that the ports that the microsystem needs to connect to the outside world can be led out to the back pads of the wafer 100 through the TSV array 400.

[0060] S224, please refer to Figure 6 The second carrier 920 connected to the chip-opposite side 120 of the wafer 100 is debonded, and a third carrier 930 is connected to the chip-opposite side 110 of the wafer 100. The wafer 100 is flipped over using the third carrier 930 so that the chip-opposite side 120 of the wafer 100 faces upward. The third carrier 930 ensures the stability of the wafer 100 during this flipping process.

[0061] S225, please continue to read Figure 6 The first solder balls 121 are formed on the backside pads of the chip-opposite side 120 of the wafer 100 by reflow, forming an IN-FO structure. The first solder balls 121 are preferably Sn solder balls. The first solder balls 121 facilitate the connection of the microsystem to the outside.

[0062] S226 , debonding the third carrier 930 connected to the chip side 110 of the wafer 100 .

[0063] In this step, the IN-FO process is used to interconnect the TSV array 400 and the RF chip, solving technical problems of the existing integration process such as large wiring area, long interconnection lines, large interconnection line loss, inability to integrate in three dimensions, and long signal delay time.

[0064] S300, please refer to Figure 7 , connect the expansion device 500 required by the RF microsystem to the IN-FO structure to form a three-dimensional integrated RF microsystem. It should be noted that, Figure 7 This is a schematic diagram. The two expansion components 500 shown are merely illustrative of the mounting method of the expansion components 500 on the wafer 100 and do not limit the number of expansion components 500. In this embodiment, the expansion components 500 required by the RF microsystem are flip-chip mounted on the front pads of the IN-FO structure chip side 110, and the passive components are soldered to the corresponding front pads through reflow. The expansion components 500 are generally provided with a second solder ball 501 to facilitate reflow soldering.

[0065] The expansion device 500 required for the radio frequency microsystem is generally a passive device. In this embodiment, the passive device includes a first filter, a second filter and auxiliary circuit separation elements of each back-grounded chip 200, such as chip resistors, chip capacitors, inductors, transformers, etc.

[0066] By flip-chip mounting passive components such as chip resistors, chip capacitors, inductors, and filters on the IN-FO structure chip side 110 using a flip-chip process and connecting them together through reflow, a three-dimensional integrated RF microsystem with a back-grounded RF chip can be formed. Using the process of this embodiment, the passive components can also be expanded to larger-scale SOC chips. By integrating the SOC chip into the RF microsystem, higher performance and higher functional density can be achieved.

[0067] Please continue reading Figure 8 In a specific example of this embodiment, the high-power RF chip is connected to two RF channels (of course, it can also be connected to only one RF channel). Each RF channel includes a first filter, a first attenuator chip, a low-noise amplifier chip, a second filter, and a second attenuator chip connected in series. The second attenuator chip is electrically connected to the high-power RF chip. Of course, the above-mentioned chips are generally also connected to auxiliary circuits composed of passive components mounted in step S300. These auxiliary circuit structures are all existing technologies and are therefore not shown in the block diagram.

[0068] This embodiment proposes an integration method for a three-dimensional integrated radio frequency microsystem with a back-grounded chip 200, which improves the integration of the radio frequency microsystem and the performance of each functional module. By adopting an L-shaped metal interconnection bridge 300, the signal of the back electrode 220 of the back-grounded chip 200 can be led out to the front. By adjusting the thickness of the L-shaped metal interconnection bridge 300, the heat generated inside the back-grounded chip can be quickly transferred to the surface of the metal interconnection bridge 300. Other heat dissipation structures can also be reasonably superimposed on the back of the metal interconnection bridge 300 according to the heat generation to form a low thermal resistance path to ensure that the heat can be dissipated in a timely and effective manner, thereby solving the thermal stability of the three-dimensional integrated radio frequency system (such as a power system). Therefore, this embodiment solves the problem that the existing radio frequency microsystem cannot achieve three-dimensional integration due to the bottom lead-out and heat dissipation problems, thereby failing to improve the integration of the radio frequency microsystem, and will reduce the increasingly significant technical problems such as signal delay time and interconnection power consumption.

[0069] The present invention also discloses a three-dimensional integrated radio frequency microsystem, which is fabricated using the method for fabricating a three-dimensional integrated radio frequency microsystem according to any of the aforementioned embodiments. The three-dimensional integrated radio frequency microsystem of this embodiment achieves three-dimensional integration, high integration, low signal delay, and low interconnect power consumption, and has broad application prospects.

[0070] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for manufacturing a three-dimensional integrated radio frequency microsystem, characterized in that: The following steps are involved: S100, leading the back electrodes of each back-grounded chip to be coplanar with its front electrodes to form a coplanar two-dimensional structure; the coplanar end surfaces of the coplanar two-dimensional structure are its front surfaces; S200, forming an IN-FO structure by wafer reconstruction and rewiring of multiple coplanar two-dimensional structures and multiple TSV arrays; S300: Connect the expansion devices required for the RF microsystem to the IN-FO structure to form a three-dimensional integrated RF microsystem.

2. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 1, wherein: The back ground chip includes a low noise amplifier chip, a high-power RF chip, a first attenuator chip and a second attenuator chip; the expansion devices required for the RF microsystem include a first filter, a second filter and auxiliary circuit separation elements of each back ground chip.

3. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 1 or 2, wherein: The step S100 includes the following sub-steps: S110, taking a metal interconnect bridge having an accommodation space; the metal interconnect bridge having a front side and a back side opposite to each other, the accommodation space being located on the front side of the metal interconnect bridge; S120, applying solder paste in the accommodation space, and placing a back grounding chip into the accommodation space of the metal interconnection bridge, so that the back electrode of the back grounding chip contacts the solder paste at the bottom of the accommodation space; S130, welding and fixing the back electrode of the back grounding chip to the bottom of the accommodation space through high-temperature sintering, and making the end surface of the front electrode of the back grounding chip coplanar with the front surface of the metal interconnection bridge.

4. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 3, wherein: The metal interconnection bridge is an L-shaped structure with a notch at one end, and the notch forms an accommodating space.

5. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 3, wherein: In the step S120, after the back grounding chip is placed in the accommodation space, the end face of the front electrode of the back grounding chip is adjusted to be coplanar with the front face of the metal interconnection bridge, and then high-temperature tape is used to stick on the front electrode of the back grounding chip and the front face of the metal interconnection bridge; the high-temperature tape is removed after the high-temperature sintering of the step S130 is completed.

6. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 3, wherein: The step S200 includes the following sub-steps: S210, reconstructing each coplanar two-dimensional structure and each TSV array on a wafer by a face-down process, so that each coplanar two-dimensional structure and each TSV array are embedded in the reconstructed wafer; the wafer has a chip side and an anti-chip side opposite to the chip side; S220, forming back-side interconnection lines and back-side pads on the chip side of the wafer, forming front-side interconnection lines and front-side pads on the chip side of the wafer, and making first solder balls on the back-side pads on the chip side of the wafer to form an IN-FO structure.

7. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 6, wherein: The step S210 includes the following sub-steps: S211, taking a first carrier board, fixing each coplanar two-dimensional structure and each TSV array on the first carrier board with the front side facing downward; S212. Reconstruct the wafer on the first carrier so that each coplanar two-dimensional structure and each TSV array are embedded in the reconstructed wafer; the wafer facing the first carrier is the chip side, and the side opposite to the chip side is the chip opposite side; the front side of each coplanar two-dimensional structure and the front side of each TSV array are flush with the end face of the chip side of the wafer, and the back side of each TSV array is flush with the end face of the chip opposite side of the wafer.

8. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 7, wherein: The step S220 includes the following sub-steps: S221, performing RDL rewiring on the opposite side of the chip of the wafer to form backside interconnect lines and backside pads; S222, debonding the first carrier connected to the chip side of the wafer, connecting a second carrier to the side opposite to the chip of the wafer, and flipping the wafer over via the second carrier so that the chip side of the wafer faces upward; S223, performing RDL rewiring on the chip side of the wafer to form front-side interconnect lines and front-side pads; S224, debonding the second carrier connected to the chip-opposite side of the wafer, connecting a third carrier to the chip-opposite side of the wafer, and flipping the wafer over via the third carrier so that the chip-opposite side of the wafer faces upward; S225, forming a first solder ball on the backside pad on the opposite side of the chip of the wafer by reflow to form an IN-FO structure; S226 , debonding the third carrier board connected to the chip side of the wafer.

9. The method for manufacturing a three-dimensional integrated radio frequency microsystem according to claim 6, wherein: In the step S300, the expansion components required by the radio frequency microsystem are mounted on the front pads on the IN-FO structure chip side through a flip-chip process, and the passive components are soldered and fixed to the corresponding front pads through reflow.

10. A three-dimensional integrated radio frequency microsystem, characterized in that: The three-dimensional integrated radio frequency microsystem is manufactured using the manufacturing method of any one of claims 1 to 9.

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